1 /* 2 * hcd.c - DesignWare HS OTG Controller host-mode routines 3 * 4 * Copyright (C) 2004-2013 Synopsys, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The names of the above-listed copyright holders may not be used 16 * to endorse or promote products derived from this software without 17 * specific prior written permission. 18 * 19 * ALTERNATIVELY, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") as published by the Free Software 21 * Foundation; either version 2 of the License, or (at your option) any 22 * later version. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * This file contains the core HCD code, and implements the Linux hc_driver 39 * API 40 */ 41 #include <linux/kernel.h> 42 #include <linux/module.h> 43 #include <linux/spinlock.h> 44 #include <linux/interrupt.h> 45 #include <linux/dma-mapping.h> 46 #include <linux/delay.h> 47 #include <linux/io.h> 48 #include <linux/slab.h> 49 #include <linux/usb.h> 50 51 #include <linux/usb/hcd.h> 52 #include <linux/usb/ch11.h> 53 54 #include "core.h" 55 #include "hcd.h" 56 57 /* 58 * ========================================================================= 59 * Host Core Layer Functions 60 * ========================================================================= 61 */ 62 63 /** 64 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts, 65 * used in both device and host modes 66 * 67 * @hsotg: Programming view of the DWC_otg controller 68 */ 69 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg) 70 { 71 u32 intmsk; 72 73 /* Clear any pending OTG Interrupts */ 74 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); 75 76 /* Clear any pending interrupts */ 77 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 78 79 /* Enable the interrupts in the GINTMSK */ 80 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT; 81 82 if (hsotg->params.host_dma <= 0) 83 intmsk |= GINTSTS_RXFLVL; 84 if (hsotg->params.external_id_pin_ctl <= 0) 85 intmsk |= GINTSTS_CONIDSTSCHNG; 86 87 intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP | 88 GINTSTS_SESSREQINT; 89 90 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 91 } 92 93 /* 94 * Initializes the FSLSPClkSel field of the HCFG register depending on the 95 * PHY type 96 */ 97 static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg) 98 { 99 u32 hcfg, val; 100 101 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && 102 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && 103 hsotg->params.ulpi_fs_ls > 0) || 104 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { 105 /* Full speed PHY */ 106 val = HCFG_FSLSPCLKSEL_48_MHZ; 107 } else { 108 /* High speed PHY running at full speed or high speed */ 109 val = HCFG_FSLSPCLKSEL_30_60_MHZ; 110 } 111 112 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); 113 hcfg = dwc2_readl(hsotg->regs + HCFG); 114 hcfg &= ~HCFG_FSLSPCLKSEL_MASK; 115 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT; 116 dwc2_writel(hcfg, hsotg->regs + HCFG); 117 } 118 119 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 120 { 121 u32 usbcfg, i2cctl; 122 int retval = 0; 123 124 /* 125 * core_init() is now called on every switch so only call the 126 * following for the first time through 127 */ 128 if (select_phy) { 129 dev_dbg(hsotg->dev, "FS PHY selected\n"); 130 131 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 132 if (!(usbcfg & GUSBCFG_PHYSEL)) { 133 usbcfg |= GUSBCFG_PHYSEL; 134 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 135 136 /* Reset after a PHY select */ 137 retval = dwc2_core_reset_and_force_dr_mode(hsotg); 138 139 if (retval) { 140 dev_err(hsotg->dev, 141 "%s: Reset failed, aborting", __func__); 142 return retval; 143 } 144 } 145 } 146 147 /* 148 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also 149 * do this on HNP Dev/Host mode switches (done in dev_init and 150 * host_init). 151 */ 152 if (dwc2_is_host_mode(hsotg)) 153 dwc2_init_fs_ls_pclk_sel(hsotg); 154 155 if (hsotg->params.i2c_enable > 0) { 156 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n"); 157 158 /* Program GUSBCFG.OtgUtmiFsSel to I2C */ 159 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 160 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL; 161 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 162 163 /* Program GI2CCTL.I2CEn */ 164 i2cctl = dwc2_readl(hsotg->regs + GI2CCTL); 165 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK; 166 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT; 167 i2cctl &= ~GI2CCTL_I2CEN; 168 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL); 169 i2cctl |= GI2CCTL_I2CEN; 170 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL); 171 } 172 173 return retval; 174 } 175 176 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 177 { 178 u32 usbcfg, usbcfg_old; 179 int retval = 0; 180 181 if (!select_phy) 182 return 0; 183 184 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 185 usbcfg_old = usbcfg; 186 187 /* 188 * HS PHY parameters. These parameters are preserved during soft reset 189 * so only program the first time. Do a soft reset immediately after 190 * setting phyif. 191 */ 192 switch (hsotg->params.phy_type) { 193 case DWC2_PHY_TYPE_PARAM_ULPI: 194 /* ULPI interface */ 195 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n"); 196 usbcfg |= GUSBCFG_ULPI_UTMI_SEL; 197 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL); 198 if (hsotg->params.phy_ulpi_ddr > 0) 199 usbcfg |= GUSBCFG_DDRSEL; 200 break; 201 case DWC2_PHY_TYPE_PARAM_UTMI: 202 /* UTMI+ interface */ 203 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n"); 204 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16); 205 if (hsotg->params.phy_utmi_width == 16) 206 usbcfg |= GUSBCFG_PHYIF16; 207 break; 208 default: 209 dev_err(hsotg->dev, "FS PHY selected at HS!\n"); 210 break; 211 } 212 213 if (usbcfg != usbcfg_old) { 214 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 215 216 /* Reset after setting the PHY parameters */ 217 retval = dwc2_core_reset_and_force_dr_mode(hsotg); 218 if (retval) { 219 dev_err(hsotg->dev, 220 "%s: Reset failed, aborting", __func__); 221 return retval; 222 } 223 } 224 225 return retval; 226 } 227 228 static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 229 { 230 u32 usbcfg; 231 int retval = 0; 232 233 if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL || 234 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) && 235 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { 236 /* If FS/LS mode with FS/LS PHY */ 237 retval = dwc2_fs_phy_init(hsotg, select_phy); 238 if (retval) 239 return retval; 240 } else { 241 /* High speed PHY */ 242 retval = dwc2_hs_phy_init(hsotg, select_phy); 243 if (retval) 244 return retval; 245 } 246 247 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && 248 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && 249 hsotg->params.ulpi_fs_ls > 0) { 250 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n"); 251 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 252 usbcfg |= GUSBCFG_ULPI_FS_LS; 253 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M; 254 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 255 } else { 256 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 257 usbcfg &= ~GUSBCFG_ULPI_FS_LS; 258 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M; 259 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 260 } 261 262 return retval; 263 } 264 265 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) 266 { 267 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 268 269 switch (hsotg->hw_params.arch) { 270 case GHWCFG2_EXT_DMA_ARCH: 271 dev_err(hsotg->dev, "External DMA Mode not supported\n"); 272 return -EINVAL; 273 274 case GHWCFG2_INT_DMA_ARCH: 275 dev_dbg(hsotg->dev, "Internal DMA Mode\n"); 276 if (hsotg->params.ahbcfg != -1) { 277 ahbcfg &= GAHBCFG_CTRL_MASK; 278 ahbcfg |= hsotg->params.ahbcfg & 279 ~GAHBCFG_CTRL_MASK; 280 } 281 break; 282 283 case GHWCFG2_SLAVE_ONLY_ARCH: 284 default: 285 dev_dbg(hsotg->dev, "Slave Only Mode\n"); 286 break; 287 } 288 289 dev_dbg(hsotg->dev, "host_dma:%d dma_desc_enable:%d\n", 290 hsotg->params.host_dma, 291 hsotg->params.dma_desc_enable); 292 293 if (hsotg->params.host_dma > 0) { 294 if (hsotg->params.dma_desc_enable > 0) 295 dev_dbg(hsotg->dev, "Using Descriptor DMA mode\n"); 296 else 297 dev_dbg(hsotg->dev, "Using Buffer DMA mode\n"); 298 } else { 299 dev_dbg(hsotg->dev, "Using Slave mode\n"); 300 hsotg->params.dma_desc_enable = 0; 301 } 302 303 if (hsotg->params.host_dma > 0) 304 ahbcfg |= GAHBCFG_DMA_EN; 305 306 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 307 308 return 0; 309 } 310 311 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg) 312 { 313 u32 usbcfg; 314 315 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 316 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP); 317 318 switch (hsotg->hw_params.op_mode) { 319 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 320 if (hsotg->params.otg_cap == 321 DWC2_CAP_PARAM_HNP_SRP_CAPABLE) 322 usbcfg |= GUSBCFG_HNPCAP; 323 if (hsotg->params.otg_cap != 324 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE) 325 usbcfg |= GUSBCFG_SRPCAP; 326 break; 327 328 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 329 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 330 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 331 if (hsotg->params.otg_cap != 332 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE) 333 usbcfg |= GUSBCFG_SRPCAP; 334 break; 335 336 case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE: 337 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE: 338 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST: 339 default: 340 break; 341 } 342 343 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 344 } 345 346 /** 347 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts 348 * 349 * @hsotg: Programming view of DWC_otg controller 350 */ 351 static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg) 352 { 353 u32 intmsk; 354 355 dev_dbg(hsotg->dev, "%s()\n", __func__); 356 357 /* Disable all interrupts */ 358 dwc2_writel(0, hsotg->regs + GINTMSK); 359 dwc2_writel(0, hsotg->regs + HAINTMSK); 360 361 /* Enable the common interrupts */ 362 dwc2_enable_common_interrupts(hsotg); 363 364 /* Enable host mode interrupts without disturbing common interrupts */ 365 intmsk = dwc2_readl(hsotg->regs + GINTMSK); 366 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT; 367 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 368 } 369 370 /** 371 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts 372 * 373 * @hsotg: Programming view of DWC_otg controller 374 */ 375 static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg) 376 { 377 u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK); 378 379 /* Disable host mode interrupts without disturbing common interrupts */ 380 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT | 381 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT); 382 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 383 } 384 385 /* 386 * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size 387 * For system that have a total fifo depth that is smaller than the default 388 * RX + TX fifo size. 389 * 390 * @hsotg: Programming view of DWC_otg controller 391 */ 392 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg) 393 { 394 struct dwc2_core_params *params = &hsotg->params; 395 struct dwc2_hw_params *hw = &hsotg->hw_params; 396 u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size; 397 398 total_fifo_size = hw->total_fifo_size; 399 rxfsiz = params->host_rx_fifo_size; 400 nptxfsiz = params->host_nperio_tx_fifo_size; 401 ptxfsiz = params->host_perio_tx_fifo_size; 402 403 /* 404 * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth 405 * allocation with support for high bandwidth endpoints. Synopsys 406 * defines MPS(Max Packet size) for a periodic EP=1024, and for 407 * non-periodic as 512. 408 */ 409 if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) { 410 /* 411 * For Buffer DMA mode/Scatter Gather DMA mode 412 * 2 * ((Largest Packet size / 4) + 1 + 1) + n 413 * with n = number of host channel. 414 * 2 * ((1024/4) + 2) = 516 415 */ 416 rxfsiz = 516 + hw->host_channels; 417 418 /* 419 * min non-periodic tx fifo depth 420 * 2 * (largest non-periodic USB packet used / 4) 421 * 2 * (512/4) = 256 422 */ 423 nptxfsiz = 256; 424 425 /* 426 * min periodic tx fifo depth 427 * (largest packet size*MC)/4 428 * (1024 * 3)/4 = 768 429 */ 430 ptxfsiz = 768; 431 432 params->host_rx_fifo_size = rxfsiz; 433 params->host_nperio_tx_fifo_size = nptxfsiz; 434 params->host_perio_tx_fifo_size = ptxfsiz; 435 } 436 437 /* 438 * If the summation of RX, NPTX and PTX fifo sizes is still 439 * bigger than the total_fifo_size, then we have a problem. 440 * 441 * We won't be able to allocate as many endpoints. Right now, 442 * we're just printing an error message, but ideally this FIFO 443 * allocation algorithm would be improved in the future. 444 * 445 * FIXME improve this FIFO allocation algorithm. 446 */ 447 if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz))) 448 dev_err(hsotg->dev, "invalid fifo sizes\n"); 449 } 450 451 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg) 452 { 453 struct dwc2_core_params *params = &hsotg->params; 454 u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz; 455 456 if (!params->enable_dynamic_fifo) 457 return; 458 459 dwc2_calculate_dynamic_fifo(hsotg); 460 461 /* Rx FIFO */ 462 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); 463 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz); 464 grxfsiz &= ~GRXFSIZ_DEPTH_MASK; 465 grxfsiz |= params->host_rx_fifo_size << 466 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK; 467 dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ); 468 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", 469 dwc2_readl(hsotg->regs + GRXFSIZ)); 470 471 /* Non-periodic Tx FIFO */ 472 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n", 473 dwc2_readl(hsotg->regs + GNPTXFSIZ)); 474 nptxfsiz = params->host_nperio_tx_fifo_size << 475 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; 476 nptxfsiz |= params->host_rx_fifo_size << 477 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; 478 dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ); 479 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n", 480 dwc2_readl(hsotg->regs + GNPTXFSIZ)); 481 482 /* Periodic Tx FIFO */ 483 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n", 484 dwc2_readl(hsotg->regs + HPTXFSIZ)); 485 hptxfsiz = params->host_perio_tx_fifo_size << 486 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; 487 hptxfsiz |= (params->host_rx_fifo_size + 488 params->host_nperio_tx_fifo_size) << 489 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; 490 dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ); 491 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n", 492 dwc2_readl(hsotg->regs + HPTXFSIZ)); 493 494 if (hsotg->params.en_multiple_tx_fifo > 0 && 495 hsotg->hw_params.snpsid <= DWC2_CORE_REV_2_94a) { 496 /* 497 * Global DFIFOCFG calculation for Host mode - 498 * include RxFIFO, NPTXFIFO and HPTXFIFO 499 */ 500 dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG); 501 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK; 502 dfifocfg |= (params->host_rx_fifo_size + 503 params->host_nperio_tx_fifo_size + 504 params->host_perio_tx_fifo_size) << 505 GDFIFOCFG_EPINFOBASE_SHIFT & 506 GDFIFOCFG_EPINFOBASE_MASK; 507 dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG); 508 } 509 } 510 511 /** 512 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for 513 * the HFIR register according to PHY type and speed 514 * 515 * @hsotg: Programming view of DWC_otg controller 516 * 517 * NOTE: The caller can modify the value of the HFIR register only after the 518 * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort) 519 * has been set 520 */ 521 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg) 522 { 523 u32 usbcfg; 524 u32 hprt0; 525 int clock = 60; /* default value */ 526 527 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 528 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 529 530 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) && 531 !(usbcfg & GUSBCFG_PHYIF16)) 532 clock = 60; 533 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type == 534 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI) 535 clock = 48; 536 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 537 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) 538 clock = 30; 539 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 540 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16)) 541 clock = 60; 542 if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 543 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) 544 clock = 48; 545 if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) && 546 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI) 547 clock = 48; 548 if ((usbcfg & GUSBCFG_PHYSEL) && 549 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 550 clock = 48; 551 552 if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED) 553 /* High speed case */ 554 return 125 * clock - 1; 555 556 /* FS/LS case */ 557 return 1000 * clock - 1; 558 } 559 560 /** 561 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination 562 * buffer 563 * 564 * @core_if: Programming view of DWC_otg controller 565 * @dest: Destination buffer for the packet 566 * @bytes: Number of bytes to copy to the destination 567 */ 568 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes) 569 { 570 u32 __iomem *fifo = hsotg->regs + HCFIFO(0); 571 u32 *data_buf = (u32 *)dest; 572 int word_count = (bytes + 3) / 4; 573 int i; 574 575 /* 576 * Todo: Account for the case where dest is not dword aligned. This 577 * requires reading data from the FIFO into a u32 temp buffer, then 578 * moving it into the data buffer. 579 */ 580 581 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes); 582 583 for (i = 0; i < word_count; i++, data_buf++) 584 *data_buf = dwc2_readl(fifo); 585 } 586 587 /** 588 * dwc2_dump_channel_info() - Prints the state of a host channel 589 * 590 * @hsotg: Programming view of DWC_otg controller 591 * @chan: Pointer to the channel to dump 592 * 593 * Must be called with interrupt disabled and spinlock held 594 * 595 * NOTE: This function will be removed once the peripheral controller code 596 * is integrated and the driver is stable 597 */ 598 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg, 599 struct dwc2_host_chan *chan) 600 { 601 #ifdef VERBOSE_DEBUG 602 int num_channels = hsotg->params.host_channels; 603 struct dwc2_qh *qh; 604 u32 hcchar; 605 u32 hcsplt; 606 u32 hctsiz; 607 u32 hc_dma; 608 int i; 609 610 if (!chan) 611 return; 612 613 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 614 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); 615 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num)); 616 hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num)); 617 618 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); 619 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", 620 hcchar, hcsplt); 621 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", 622 hctsiz, hc_dma); 623 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 624 chan->dev_addr, chan->ep_num, chan->ep_is_in); 625 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 626 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 627 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start); 628 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started); 629 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 630 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 631 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 632 (unsigned long)chan->xfer_dma); 633 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 634 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 635 dev_dbg(hsotg->dev, " NP inactive sched:\n"); 636 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive, 637 qh_list_entry) 638 dev_dbg(hsotg->dev, " %p\n", qh); 639 dev_dbg(hsotg->dev, " NP active sched:\n"); 640 list_for_each_entry(qh, &hsotg->non_periodic_sched_active, 641 qh_list_entry) 642 dev_dbg(hsotg->dev, " %p\n", qh); 643 dev_dbg(hsotg->dev, " Channels:\n"); 644 for (i = 0; i < num_channels; i++) { 645 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 646 647 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan); 648 } 649 #endif /* VERBOSE_DEBUG */ 650 } 651 652 static int _dwc2_hcd_start(struct usb_hcd *hcd); 653 654 static void dwc2_host_start(struct dwc2_hsotg *hsotg) 655 { 656 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 657 658 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg); 659 _dwc2_hcd_start(hcd); 660 } 661 662 static void dwc2_host_disconnect(struct dwc2_hsotg *hsotg) 663 { 664 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 665 666 hcd->self.is_b_host = 0; 667 } 668 669 static void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, 670 int *hub_addr, int *hub_port) 671 { 672 struct urb *urb = context; 673 674 if (urb->dev->tt) 675 *hub_addr = urb->dev->tt->hub->devnum; 676 else 677 *hub_addr = 0; 678 *hub_port = urb->dev->ttport; 679 } 680 681 /* 682 * ========================================================================= 683 * Low Level Host Channel Access Functions 684 * ========================================================================= 685 */ 686 687 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg, 688 struct dwc2_host_chan *chan) 689 { 690 u32 hcintmsk = HCINTMSK_CHHLTD; 691 692 switch (chan->ep_type) { 693 case USB_ENDPOINT_XFER_CONTROL: 694 case USB_ENDPOINT_XFER_BULK: 695 dev_vdbg(hsotg->dev, "control/bulk\n"); 696 hcintmsk |= HCINTMSK_XFERCOMPL; 697 hcintmsk |= HCINTMSK_STALL; 698 hcintmsk |= HCINTMSK_XACTERR; 699 hcintmsk |= HCINTMSK_DATATGLERR; 700 if (chan->ep_is_in) { 701 hcintmsk |= HCINTMSK_BBLERR; 702 } else { 703 hcintmsk |= HCINTMSK_NAK; 704 hcintmsk |= HCINTMSK_NYET; 705 if (chan->do_ping) 706 hcintmsk |= HCINTMSK_ACK; 707 } 708 709 if (chan->do_split) { 710 hcintmsk |= HCINTMSK_NAK; 711 if (chan->complete_split) 712 hcintmsk |= HCINTMSK_NYET; 713 else 714 hcintmsk |= HCINTMSK_ACK; 715 } 716 717 if (chan->error_state) 718 hcintmsk |= HCINTMSK_ACK; 719 break; 720 721 case USB_ENDPOINT_XFER_INT: 722 if (dbg_perio()) 723 dev_vdbg(hsotg->dev, "intr\n"); 724 hcintmsk |= HCINTMSK_XFERCOMPL; 725 hcintmsk |= HCINTMSK_NAK; 726 hcintmsk |= HCINTMSK_STALL; 727 hcintmsk |= HCINTMSK_XACTERR; 728 hcintmsk |= HCINTMSK_DATATGLERR; 729 hcintmsk |= HCINTMSK_FRMOVRUN; 730 731 if (chan->ep_is_in) 732 hcintmsk |= HCINTMSK_BBLERR; 733 if (chan->error_state) 734 hcintmsk |= HCINTMSK_ACK; 735 if (chan->do_split) { 736 if (chan->complete_split) 737 hcintmsk |= HCINTMSK_NYET; 738 else 739 hcintmsk |= HCINTMSK_ACK; 740 } 741 break; 742 743 case USB_ENDPOINT_XFER_ISOC: 744 if (dbg_perio()) 745 dev_vdbg(hsotg->dev, "isoc\n"); 746 hcintmsk |= HCINTMSK_XFERCOMPL; 747 hcintmsk |= HCINTMSK_FRMOVRUN; 748 hcintmsk |= HCINTMSK_ACK; 749 750 if (chan->ep_is_in) { 751 hcintmsk |= HCINTMSK_XACTERR; 752 hcintmsk |= HCINTMSK_BBLERR; 753 } 754 break; 755 default: 756 dev_err(hsotg->dev, "## Unknown EP type ##\n"); 757 break; 758 } 759 760 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); 761 if (dbg_hc(chan)) 762 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); 763 } 764 765 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg, 766 struct dwc2_host_chan *chan) 767 { 768 u32 hcintmsk = HCINTMSK_CHHLTD; 769 770 /* 771 * For Descriptor DMA mode core halts the channel on AHB error. 772 * Interrupt is not required. 773 */ 774 if (hsotg->params.dma_desc_enable <= 0) { 775 if (dbg_hc(chan)) 776 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); 777 hcintmsk |= HCINTMSK_AHBERR; 778 } else { 779 if (dbg_hc(chan)) 780 dev_vdbg(hsotg->dev, "desc DMA enabled\n"); 781 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 782 hcintmsk |= HCINTMSK_XFERCOMPL; 783 } 784 785 if (chan->error_state && !chan->do_split && 786 chan->ep_type != USB_ENDPOINT_XFER_ISOC) { 787 if (dbg_hc(chan)) 788 dev_vdbg(hsotg->dev, "setting ACK\n"); 789 hcintmsk |= HCINTMSK_ACK; 790 if (chan->ep_is_in) { 791 hcintmsk |= HCINTMSK_DATATGLERR; 792 if (chan->ep_type != USB_ENDPOINT_XFER_INT) 793 hcintmsk |= HCINTMSK_NAK; 794 } 795 } 796 797 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); 798 if (dbg_hc(chan)) 799 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); 800 } 801 802 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg, 803 struct dwc2_host_chan *chan) 804 { 805 u32 intmsk; 806 807 if (hsotg->params.host_dma > 0) { 808 if (dbg_hc(chan)) 809 dev_vdbg(hsotg->dev, "DMA enabled\n"); 810 dwc2_hc_enable_dma_ints(hsotg, chan); 811 } else { 812 if (dbg_hc(chan)) 813 dev_vdbg(hsotg->dev, "DMA disabled\n"); 814 dwc2_hc_enable_slave_ints(hsotg, chan); 815 } 816 817 /* Enable the top level host channel interrupt */ 818 intmsk = dwc2_readl(hsotg->regs + HAINTMSK); 819 intmsk |= 1 << chan->hc_num; 820 dwc2_writel(intmsk, hsotg->regs + HAINTMSK); 821 if (dbg_hc(chan)) 822 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk); 823 824 /* Make sure host channel interrupts are enabled */ 825 intmsk = dwc2_readl(hsotg->regs + GINTMSK); 826 intmsk |= GINTSTS_HCHINT; 827 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 828 if (dbg_hc(chan)) 829 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk); 830 } 831 832 /** 833 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from 834 * a specific endpoint 835 * 836 * @hsotg: Programming view of DWC_otg controller 837 * @chan: Information needed to initialize the host channel 838 * 839 * The HCCHARn register is set up with the characteristics specified in chan. 840 * Host channel interrupts that may need to be serviced while this transfer is 841 * in progress are enabled. 842 */ 843 static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 844 { 845 u8 hc_num = chan->hc_num; 846 u32 hcintmsk; 847 u32 hcchar; 848 u32 hcsplt = 0; 849 850 if (dbg_hc(chan)) 851 dev_vdbg(hsotg->dev, "%s()\n", __func__); 852 853 /* Clear old interrupt conditions for this host channel */ 854 hcintmsk = 0xffffffff; 855 hcintmsk &= ~HCINTMSK_RESERVED14_31; 856 dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num)); 857 858 /* Enable channel interrupts required for this transfer */ 859 dwc2_hc_enable_ints(hsotg, chan); 860 861 /* 862 * Program the HCCHARn register with the endpoint characteristics for 863 * the current transfer 864 */ 865 hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK; 866 hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK; 867 if (chan->ep_is_in) 868 hcchar |= HCCHAR_EPDIR; 869 if (chan->speed == USB_SPEED_LOW) 870 hcchar |= HCCHAR_LSPDDEV; 871 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK; 872 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK; 873 dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num)); 874 if (dbg_hc(chan)) { 875 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n", 876 hc_num, hcchar); 877 878 dev_vdbg(hsotg->dev, "%s: Channel %d\n", 879 __func__, hc_num); 880 dev_vdbg(hsotg->dev, " Dev Addr: %d\n", 881 chan->dev_addr); 882 dev_vdbg(hsotg->dev, " Ep Num: %d\n", 883 chan->ep_num); 884 dev_vdbg(hsotg->dev, " Is In: %d\n", 885 chan->ep_is_in); 886 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n", 887 chan->speed == USB_SPEED_LOW); 888 dev_vdbg(hsotg->dev, " Ep Type: %d\n", 889 chan->ep_type); 890 dev_vdbg(hsotg->dev, " Max Pkt: %d\n", 891 chan->max_packet); 892 } 893 894 /* Program the HCSPLT register for SPLITs */ 895 if (chan->do_split) { 896 if (dbg_hc(chan)) 897 dev_vdbg(hsotg->dev, 898 "Programming HC %d with split --> %s\n", 899 hc_num, 900 chan->complete_split ? "CSPLIT" : "SSPLIT"); 901 if (chan->complete_split) 902 hcsplt |= HCSPLT_COMPSPLT; 903 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT & 904 HCSPLT_XACTPOS_MASK; 905 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT & 906 HCSPLT_HUBADDR_MASK; 907 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT & 908 HCSPLT_PRTADDR_MASK; 909 if (dbg_hc(chan)) { 910 dev_vdbg(hsotg->dev, " comp split %d\n", 911 chan->complete_split); 912 dev_vdbg(hsotg->dev, " xact pos %d\n", 913 chan->xact_pos); 914 dev_vdbg(hsotg->dev, " hub addr %d\n", 915 chan->hub_addr); 916 dev_vdbg(hsotg->dev, " hub port %d\n", 917 chan->hub_port); 918 dev_vdbg(hsotg->dev, " is_in %d\n", 919 chan->ep_is_in); 920 dev_vdbg(hsotg->dev, " Max Pkt %d\n", 921 chan->max_packet); 922 dev_vdbg(hsotg->dev, " xferlen %d\n", 923 chan->xfer_len); 924 } 925 } 926 927 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num)); 928 } 929 930 /** 931 * dwc2_hc_halt() - Attempts to halt a host channel 932 * 933 * @hsotg: Controller register interface 934 * @chan: Host channel to halt 935 * @halt_status: Reason for halting the channel 936 * 937 * This function should only be called in Slave mode or to abort a transfer in 938 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the 939 * controller halts the channel when the transfer is complete or a condition 940 * occurs that requires application intervention. 941 * 942 * In slave mode, checks for a free request queue entry, then sets the Channel 943 * Enable and Channel Disable bits of the Host Channel Characteristics 944 * register of the specified channel to intiate the halt. If there is no free 945 * request queue entry, sets only the Channel Disable bit of the HCCHARn 946 * register to flush requests for this channel. In the latter case, sets a 947 * flag to indicate that the host channel needs to be halted when a request 948 * queue slot is open. 949 * 950 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the 951 * HCCHARn register. The controller ensures there is space in the request 952 * queue before submitting the halt request. 953 * 954 * Some time may elapse before the core flushes any posted requests for this 955 * host channel and halts. The Channel Halted interrupt handler completes the 956 * deactivation of the host channel. 957 */ 958 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 959 enum dwc2_halt_status halt_status) 960 { 961 u32 nptxsts, hptxsts, hcchar; 962 963 if (dbg_hc(chan)) 964 dev_vdbg(hsotg->dev, "%s()\n", __func__); 965 if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS) 966 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status); 967 968 if (halt_status == DWC2_HC_XFER_URB_DEQUEUE || 969 halt_status == DWC2_HC_XFER_AHB_ERR) { 970 /* 971 * Disable all channel interrupts except Ch Halted. The QTD 972 * and QH state associated with this transfer has been cleared 973 * (in the case of URB_DEQUEUE), so the channel needs to be 974 * shut down carefully to prevent crashes. 975 */ 976 u32 hcintmsk = HCINTMSK_CHHLTD; 977 978 dev_vdbg(hsotg->dev, "dequeue/error\n"); 979 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); 980 981 /* 982 * Make sure no other interrupts besides halt are currently 983 * pending. Handling another interrupt could cause a crash due 984 * to the QTD and QH state. 985 */ 986 dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num)); 987 988 /* 989 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR 990 * even if the channel was already halted for some other 991 * reason 992 */ 993 chan->halt_status = halt_status; 994 995 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 996 if (!(hcchar & HCCHAR_CHENA)) { 997 /* 998 * The channel is either already halted or it hasn't 999 * started yet. In DMA mode, the transfer may halt if 1000 * it finishes normally or a condition occurs that 1001 * requires driver intervention. Don't want to halt 1002 * the channel again. In either Slave or DMA mode, 1003 * it's possible that the transfer has been assigned 1004 * to a channel, but not started yet when an URB is 1005 * dequeued. Don't want to halt a channel that hasn't 1006 * started yet. 1007 */ 1008 return; 1009 } 1010 } 1011 if (chan->halt_pending) { 1012 /* 1013 * A halt has already been issued for this channel. This might 1014 * happen when a transfer is aborted by a higher level in 1015 * the stack. 1016 */ 1017 dev_vdbg(hsotg->dev, 1018 "*** %s: Channel %d, chan->halt_pending already set ***\n", 1019 __func__, chan->hc_num); 1020 return; 1021 } 1022 1023 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1024 1025 /* No need to set the bit in DDMA for disabling the channel */ 1026 /* TODO check it everywhere channel is disabled */ 1027 if (hsotg->params.dma_desc_enable <= 0) { 1028 if (dbg_hc(chan)) 1029 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); 1030 hcchar |= HCCHAR_CHENA; 1031 } else { 1032 if (dbg_hc(chan)) 1033 dev_dbg(hsotg->dev, "desc DMA enabled\n"); 1034 } 1035 hcchar |= HCCHAR_CHDIS; 1036 1037 if (hsotg->params.host_dma <= 0) { 1038 if (dbg_hc(chan)) 1039 dev_vdbg(hsotg->dev, "DMA not enabled\n"); 1040 hcchar |= HCCHAR_CHENA; 1041 1042 /* Check for space in the request queue to issue the halt */ 1043 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || 1044 chan->ep_type == USB_ENDPOINT_XFER_BULK) { 1045 dev_vdbg(hsotg->dev, "control/bulk\n"); 1046 nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); 1047 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) { 1048 dev_vdbg(hsotg->dev, "Disabling channel\n"); 1049 hcchar &= ~HCCHAR_CHENA; 1050 } 1051 } else { 1052 if (dbg_perio()) 1053 dev_vdbg(hsotg->dev, "isoc/intr\n"); 1054 hptxsts = dwc2_readl(hsotg->regs + HPTXSTS); 1055 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 || 1056 hsotg->queuing_high_bandwidth) { 1057 if (dbg_perio()) 1058 dev_vdbg(hsotg->dev, "Disabling channel\n"); 1059 hcchar &= ~HCCHAR_CHENA; 1060 } 1061 } 1062 } else { 1063 if (dbg_hc(chan)) 1064 dev_vdbg(hsotg->dev, "DMA enabled\n"); 1065 } 1066 1067 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1068 chan->halt_status = halt_status; 1069 1070 if (hcchar & HCCHAR_CHENA) { 1071 if (dbg_hc(chan)) 1072 dev_vdbg(hsotg->dev, "Channel enabled\n"); 1073 chan->halt_pending = 1; 1074 chan->halt_on_queue = 0; 1075 } else { 1076 if (dbg_hc(chan)) 1077 dev_vdbg(hsotg->dev, "Channel disabled\n"); 1078 chan->halt_on_queue = 1; 1079 } 1080 1081 if (dbg_hc(chan)) { 1082 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1083 chan->hc_num); 1084 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n", 1085 hcchar); 1086 dev_vdbg(hsotg->dev, " halt_pending: %d\n", 1087 chan->halt_pending); 1088 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n", 1089 chan->halt_on_queue); 1090 dev_vdbg(hsotg->dev, " halt_status: %d\n", 1091 chan->halt_status); 1092 } 1093 } 1094 1095 /** 1096 * dwc2_hc_cleanup() - Clears the transfer state for a host channel 1097 * 1098 * @hsotg: Programming view of DWC_otg controller 1099 * @chan: Identifies the host channel to clean up 1100 * 1101 * This function is normally called after a transfer is done and the host 1102 * channel is being released 1103 */ 1104 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 1105 { 1106 u32 hcintmsk; 1107 1108 chan->xfer_started = 0; 1109 1110 list_del_init(&chan->split_order_list_entry); 1111 1112 /* 1113 * Clear channel interrupt enables and any unhandled channel interrupt 1114 * conditions 1115 */ 1116 dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num)); 1117 hcintmsk = 0xffffffff; 1118 hcintmsk &= ~HCINTMSK_RESERVED14_31; 1119 dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num)); 1120 } 1121 1122 /** 1123 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in 1124 * which frame a periodic transfer should occur 1125 * 1126 * @hsotg: Programming view of DWC_otg controller 1127 * @chan: Identifies the host channel to set up and its properties 1128 * @hcchar: Current value of the HCCHAR register for the specified host channel 1129 * 1130 * This function has no effect on non-periodic transfers 1131 */ 1132 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg, 1133 struct dwc2_host_chan *chan, u32 *hcchar) 1134 { 1135 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1136 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1137 int host_speed; 1138 int xfer_ns; 1139 int xfer_us; 1140 int bytes_in_fifo; 1141 u16 fifo_space; 1142 u16 frame_number; 1143 u16 wire_frame; 1144 1145 /* 1146 * Try to figure out if we're an even or odd frame. If we set 1147 * even and the current frame number is even the the transfer 1148 * will happen immediately. Similar if both are odd. If one is 1149 * even and the other is odd then the transfer will happen when 1150 * the frame number ticks. 1151 * 1152 * There's a bit of a balancing act to get this right. 1153 * Sometimes we may want to send data in the current frame (AK 1154 * right away). We might want to do this if the frame number 1155 * _just_ ticked, but we might also want to do this in order 1156 * to continue a split transaction that happened late in a 1157 * microframe (so we didn't know to queue the next transfer 1158 * until the frame number had ticked). The problem is that we 1159 * need a lot of knowledge to know if there's actually still 1160 * time to send things or if it would be better to wait until 1161 * the next frame. 1162 * 1163 * We can look at how much time is left in the current frame 1164 * and make a guess about whether we'll have time to transfer. 1165 * We'll do that. 1166 */ 1167 1168 /* Get speed host is running at */ 1169 host_speed = (chan->speed != USB_SPEED_HIGH && 1170 !chan->do_split) ? chan->speed : USB_SPEED_HIGH; 1171 1172 /* See how many bytes are in the periodic FIFO right now */ 1173 fifo_space = (dwc2_readl(hsotg->regs + HPTXSTS) & 1174 TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT; 1175 bytes_in_fifo = sizeof(u32) * 1176 (hsotg->params.host_perio_tx_fifo_size - 1177 fifo_space); 1178 1179 /* 1180 * Roughly estimate bus time for everything in the periodic 1181 * queue + our new transfer. This is "rough" because we're 1182 * using a function that makes takes into account IN/OUT 1183 * and INT/ISO and we're just slamming in one value for all 1184 * transfers. This should be an over-estimate and that should 1185 * be OK, but we can probably tighten it. 1186 */ 1187 xfer_ns = usb_calc_bus_time(host_speed, false, false, 1188 chan->xfer_len + bytes_in_fifo); 1189 xfer_us = NS_TO_US(xfer_ns); 1190 1191 /* See what frame number we'll be at by the time we finish */ 1192 frame_number = dwc2_hcd_get_future_frame_number(hsotg, xfer_us); 1193 1194 /* This is when we were scheduled to be on the wire */ 1195 wire_frame = dwc2_frame_num_inc(chan->qh->next_active_frame, 1); 1196 1197 /* 1198 * If we'd finish _after_ the frame we're scheduled in then 1199 * it's hopeless. Just schedule right away and hope for the 1200 * best. Note that it _might_ be wise to call back into the 1201 * scheduler to pick a better frame, but this is better than 1202 * nothing. 1203 */ 1204 if (dwc2_frame_num_gt(frame_number, wire_frame)) { 1205 dwc2_sch_vdbg(hsotg, 1206 "QH=%p EO MISS fr=%04x=>%04x (%+d)\n", 1207 chan->qh, wire_frame, frame_number, 1208 dwc2_frame_num_dec(frame_number, 1209 wire_frame)); 1210 wire_frame = frame_number; 1211 1212 /* 1213 * We picked a different frame number; communicate this 1214 * back to the scheduler so it doesn't try to schedule 1215 * another in the same frame. 1216 * 1217 * Remember that next_active_frame is 1 before the wire 1218 * frame. 1219 */ 1220 chan->qh->next_active_frame = 1221 dwc2_frame_num_dec(frame_number, 1); 1222 } 1223 1224 if (wire_frame & 1) 1225 *hcchar |= HCCHAR_ODDFRM; 1226 else 1227 *hcchar &= ~HCCHAR_ODDFRM; 1228 } 1229 } 1230 1231 static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan) 1232 { 1233 /* Set up the initial PID for the transfer */ 1234 if (chan->speed == USB_SPEED_HIGH) { 1235 if (chan->ep_is_in) { 1236 if (chan->multi_count == 1) 1237 chan->data_pid_start = DWC2_HC_PID_DATA0; 1238 else if (chan->multi_count == 2) 1239 chan->data_pid_start = DWC2_HC_PID_DATA1; 1240 else 1241 chan->data_pid_start = DWC2_HC_PID_DATA2; 1242 } else { 1243 if (chan->multi_count == 1) 1244 chan->data_pid_start = DWC2_HC_PID_DATA0; 1245 else 1246 chan->data_pid_start = DWC2_HC_PID_MDATA; 1247 } 1248 } else { 1249 chan->data_pid_start = DWC2_HC_PID_DATA0; 1250 } 1251 } 1252 1253 /** 1254 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with 1255 * the Host Channel 1256 * 1257 * @hsotg: Programming view of DWC_otg controller 1258 * @chan: Information needed to initialize the host channel 1259 * 1260 * This function should only be called in Slave mode. For a channel associated 1261 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel 1262 * associated with a periodic EP, the periodic Tx FIFO is written. 1263 * 1264 * Upon return the xfer_buf and xfer_count fields in chan are incremented by 1265 * the number of bytes written to the Tx FIFO. 1266 */ 1267 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg, 1268 struct dwc2_host_chan *chan) 1269 { 1270 u32 i; 1271 u32 remaining_count; 1272 u32 byte_count; 1273 u32 dword_count; 1274 u32 __iomem *data_fifo; 1275 u32 *data_buf = (u32 *)chan->xfer_buf; 1276 1277 if (dbg_hc(chan)) 1278 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1279 1280 data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num)); 1281 1282 remaining_count = chan->xfer_len - chan->xfer_count; 1283 if (remaining_count > chan->max_packet) 1284 byte_count = chan->max_packet; 1285 else 1286 byte_count = remaining_count; 1287 1288 dword_count = (byte_count + 3) / 4; 1289 1290 if (((unsigned long)data_buf & 0x3) == 0) { 1291 /* xfer_buf is DWORD aligned */ 1292 for (i = 0; i < dword_count; i++, data_buf++) 1293 dwc2_writel(*data_buf, data_fifo); 1294 } else { 1295 /* xfer_buf is not DWORD aligned */ 1296 for (i = 0; i < dword_count; i++, data_buf++) { 1297 u32 data = data_buf[0] | data_buf[1] << 8 | 1298 data_buf[2] << 16 | data_buf[3] << 24; 1299 dwc2_writel(data, data_fifo); 1300 } 1301 } 1302 1303 chan->xfer_count += byte_count; 1304 chan->xfer_buf += byte_count; 1305 } 1306 1307 /** 1308 * dwc2_hc_do_ping() - Starts a PING transfer 1309 * 1310 * @hsotg: Programming view of DWC_otg controller 1311 * @chan: Information needed to initialize the host channel 1312 * 1313 * This function should only be called in Slave mode. The Do Ping bit is set in 1314 * the HCTSIZ register, then the channel is enabled. 1315 */ 1316 static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, 1317 struct dwc2_host_chan *chan) 1318 { 1319 u32 hcchar; 1320 u32 hctsiz; 1321 1322 if (dbg_hc(chan)) 1323 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1324 chan->hc_num); 1325 1326 hctsiz = TSIZ_DOPNG; 1327 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT; 1328 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); 1329 1330 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1331 hcchar |= HCCHAR_CHENA; 1332 hcchar &= ~HCCHAR_CHDIS; 1333 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1334 } 1335 1336 /** 1337 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host 1338 * channel and starts the transfer 1339 * 1340 * @hsotg: Programming view of DWC_otg controller 1341 * @chan: Information needed to initialize the host channel. The xfer_len value 1342 * may be reduced to accommodate the max widths of the XferSize and 1343 * PktCnt fields in the HCTSIZn register. The multi_count value may be 1344 * changed to reflect the final xfer_len value. 1345 * 1346 * This function may be called in either Slave mode or DMA mode. In Slave mode, 1347 * the caller must ensure that there is sufficient space in the request queue 1348 * and Tx Data FIFO. 1349 * 1350 * For an OUT transfer in Slave mode, it loads a data packet into the 1351 * appropriate FIFO. If necessary, additional data packets are loaded in the 1352 * Host ISR. 1353 * 1354 * For an IN transfer in Slave mode, a data packet is requested. The data 1355 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary, 1356 * additional data packets are requested in the Host ISR. 1357 * 1358 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ 1359 * register along with a packet count of 1 and the channel is enabled. This 1360 * causes a single PING transaction to occur. Other fields in HCTSIZ are 1361 * simply set to 0 since no data transfer occurs in this case. 1362 * 1363 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with 1364 * all the information required to perform the subsequent data transfer. In 1365 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the 1366 * controller performs the entire PING protocol, then starts the data 1367 * transfer. 1368 */ 1369 static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 1370 struct dwc2_host_chan *chan) 1371 { 1372 u32 max_hc_xfer_size = hsotg->params.max_transfer_size; 1373 u16 max_hc_pkt_count = hsotg->params.max_packet_count; 1374 u32 hcchar; 1375 u32 hctsiz = 0; 1376 u16 num_packets; 1377 u32 ec_mc; 1378 1379 if (dbg_hc(chan)) 1380 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1381 1382 if (chan->do_ping) { 1383 if (hsotg->params.host_dma <= 0) { 1384 if (dbg_hc(chan)) 1385 dev_vdbg(hsotg->dev, "ping, no DMA\n"); 1386 dwc2_hc_do_ping(hsotg, chan); 1387 chan->xfer_started = 1; 1388 return; 1389 } 1390 1391 if (dbg_hc(chan)) 1392 dev_vdbg(hsotg->dev, "ping, DMA\n"); 1393 1394 hctsiz |= TSIZ_DOPNG; 1395 } 1396 1397 if (chan->do_split) { 1398 if (dbg_hc(chan)) 1399 dev_vdbg(hsotg->dev, "split\n"); 1400 num_packets = 1; 1401 1402 if (chan->complete_split && !chan->ep_is_in) 1403 /* 1404 * For CSPLIT OUT Transfer, set the size to 0 so the 1405 * core doesn't expect any data written to the FIFO 1406 */ 1407 chan->xfer_len = 0; 1408 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet) 1409 chan->xfer_len = chan->max_packet; 1410 else if (!chan->ep_is_in && chan->xfer_len > 188) 1411 chan->xfer_len = 188; 1412 1413 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & 1414 TSIZ_XFERSIZE_MASK; 1415 1416 /* For split set ec_mc for immediate retries */ 1417 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1418 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1419 ec_mc = 3; 1420 else 1421 ec_mc = 1; 1422 } else { 1423 if (dbg_hc(chan)) 1424 dev_vdbg(hsotg->dev, "no split\n"); 1425 /* 1426 * Ensure that the transfer length and packet count will fit 1427 * in the widths allocated for them in the HCTSIZn register 1428 */ 1429 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1430 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1431 /* 1432 * Make sure the transfer size is no larger than one 1433 * (micro)frame's worth of data. (A check was done 1434 * when the periodic transfer was accepted to ensure 1435 * that a (micro)frame's worth of data can be 1436 * programmed into a channel.) 1437 */ 1438 u32 max_periodic_len = 1439 chan->multi_count * chan->max_packet; 1440 1441 if (chan->xfer_len > max_periodic_len) 1442 chan->xfer_len = max_periodic_len; 1443 } else if (chan->xfer_len > max_hc_xfer_size) { 1444 /* 1445 * Make sure that xfer_len is a multiple of max packet 1446 * size 1447 */ 1448 chan->xfer_len = 1449 max_hc_xfer_size - chan->max_packet + 1; 1450 } 1451 1452 if (chan->xfer_len > 0) { 1453 num_packets = (chan->xfer_len + chan->max_packet - 1) / 1454 chan->max_packet; 1455 if (num_packets > max_hc_pkt_count) { 1456 num_packets = max_hc_pkt_count; 1457 chan->xfer_len = num_packets * chan->max_packet; 1458 } 1459 } else { 1460 /* Need 1 packet for transfer length of 0 */ 1461 num_packets = 1; 1462 } 1463 1464 if (chan->ep_is_in) 1465 /* 1466 * Always program an integral # of max packets for IN 1467 * transfers 1468 */ 1469 chan->xfer_len = num_packets * chan->max_packet; 1470 1471 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1472 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1473 /* 1474 * Make sure that the multi_count field matches the 1475 * actual transfer length 1476 */ 1477 chan->multi_count = num_packets; 1478 1479 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1480 dwc2_set_pid_isoc(chan); 1481 1482 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & 1483 TSIZ_XFERSIZE_MASK; 1484 1485 /* The ec_mc gets the multi_count for non-split */ 1486 ec_mc = chan->multi_count; 1487 } 1488 1489 chan->start_pkt_count = num_packets; 1490 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK; 1491 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & 1492 TSIZ_SC_MC_PID_MASK; 1493 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); 1494 if (dbg_hc(chan)) { 1495 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n", 1496 hctsiz, chan->hc_num); 1497 1498 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1499 chan->hc_num); 1500 dev_vdbg(hsotg->dev, " Xfer Size: %d\n", 1501 (hctsiz & TSIZ_XFERSIZE_MASK) >> 1502 TSIZ_XFERSIZE_SHIFT); 1503 dev_vdbg(hsotg->dev, " Num Pkts: %d\n", 1504 (hctsiz & TSIZ_PKTCNT_MASK) >> 1505 TSIZ_PKTCNT_SHIFT); 1506 dev_vdbg(hsotg->dev, " Start PID: %d\n", 1507 (hctsiz & TSIZ_SC_MC_PID_MASK) >> 1508 TSIZ_SC_MC_PID_SHIFT); 1509 } 1510 1511 if (hsotg->params.host_dma > 0) { 1512 dwc2_writel((u32)chan->xfer_dma, 1513 hsotg->regs + HCDMA(chan->hc_num)); 1514 if (dbg_hc(chan)) 1515 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n", 1516 (unsigned long)chan->xfer_dma, chan->hc_num); 1517 } 1518 1519 /* Start the split */ 1520 if (chan->do_split) { 1521 u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); 1522 1523 hcsplt |= HCSPLT_SPLTENA; 1524 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num)); 1525 } 1526 1527 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1528 hcchar &= ~HCCHAR_MULTICNT_MASK; 1529 hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK; 1530 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); 1531 1532 if (hcchar & HCCHAR_CHDIS) 1533 dev_warn(hsotg->dev, 1534 "%s: chdis set, channel %d, hcchar 0x%08x\n", 1535 __func__, chan->hc_num, hcchar); 1536 1537 /* Set host channel enable after all other setup is complete */ 1538 hcchar |= HCCHAR_CHENA; 1539 hcchar &= ~HCCHAR_CHDIS; 1540 1541 if (dbg_hc(chan)) 1542 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", 1543 (hcchar & HCCHAR_MULTICNT_MASK) >> 1544 HCCHAR_MULTICNT_SHIFT); 1545 1546 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1547 if (dbg_hc(chan)) 1548 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, 1549 chan->hc_num); 1550 1551 chan->xfer_started = 1; 1552 chan->requests++; 1553 1554 if (hsotg->params.host_dma <= 0 && 1555 !chan->ep_is_in && chan->xfer_len > 0) 1556 /* Load OUT packet into the appropriate Tx FIFO */ 1557 dwc2_hc_write_packet(hsotg, chan); 1558 } 1559 1560 /** 1561 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a 1562 * host channel and starts the transfer in Descriptor DMA mode 1563 * 1564 * @hsotg: Programming view of DWC_otg controller 1565 * @chan: Information needed to initialize the host channel 1566 * 1567 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set. 1568 * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field 1569 * with micro-frame bitmap. 1570 * 1571 * Initializes HCDMA register with descriptor list address and CTD value then 1572 * starts the transfer via enabling the channel. 1573 */ 1574 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 1575 struct dwc2_host_chan *chan) 1576 { 1577 u32 hcchar; 1578 u32 hctsiz = 0; 1579 1580 if (chan->do_ping) 1581 hctsiz |= TSIZ_DOPNG; 1582 1583 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1584 dwc2_set_pid_isoc(chan); 1585 1586 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */ 1587 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & 1588 TSIZ_SC_MC_PID_MASK; 1589 1590 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */ 1591 hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK; 1592 1593 /* Non-zero only for high-speed interrupt endpoints */ 1594 hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK; 1595 1596 if (dbg_hc(chan)) { 1597 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1598 chan->hc_num); 1599 dev_vdbg(hsotg->dev, " Start PID: %d\n", 1600 chan->data_pid_start); 1601 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1); 1602 } 1603 1604 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); 1605 1606 dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr, 1607 chan->desc_list_sz, DMA_TO_DEVICE); 1608 1609 dwc2_writel(chan->desc_list_addr, hsotg->regs + HCDMA(chan->hc_num)); 1610 1611 if (dbg_hc(chan)) 1612 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n", 1613 &chan->desc_list_addr, chan->hc_num); 1614 1615 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1616 hcchar &= ~HCCHAR_MULTICNT_MASK; 1617 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT & 1618 HCCHAR_MULTICNT_MASK; 1619 1620 if (hcchar & HCCHAR_CHDIS) 1621 dev_warn(hsotg->dev, 1622 "%s: chdis set, channel %d, hcchar 0x%08x\n", 1623 __func__, chan->hc_num, hcchar); 1624 1625 /* Set host channel enable after all other setup is complete */ 1626 hcchar |= HCCHAR_CHENA; 1627 hcchar &= ~HCCHAR_CHDIS; 1628 1629 if (dbg_hc(chan)) 1630 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", 1631 (hcchar & HCCHAR_MULTICNT_MASK) >> 1632 HCCHAR_MULTICNT_SHIFT); 1633 1634 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1635 if (dbg_hc(chan)) 1636 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, 1637 chan->hc_num); 1638 1639 chan->xfer_started = 1; 1640 chan->requests++; 1641 } 1642 1643 /** 1644 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by 1645 * a previous call to dwc2_hc_start_transfer() 1646 * 1647 * @hsotg: Programming view of DWC_otg controller 1648 * @chan: Information needed to initialize the host channel 1649 * 1650 * The caller must ensure there is sufficient space in the request queue and Tx 1651 * Data FIFO. This function should only be called in Slave mode. In DMA mode, 1652 * the controller acts autonomously to complete transfers programmed to a host 1653 * channel. 1654 * 1655 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO 1656 * if there is any data remaining to be queued. For an IN transfer, another 1657 * data packet is always requested. For the SETUP phase of a control transfer, 1658 * this function does nothing. 1659 * 1660 * Return: 1 if a new request is queued, 0 if no more requests are required 1661 * for this transfer 1662 */ 1663 static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 1664 struct dwc2_host_chan *chan) 1665 { 1666 if (dbg_hc(chan)) 1667 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1668 chan->hc_num); 1669 1670 if (chan->do_split) 1671 /* SPLITs always queue just once per channel */ 1672 return 0; 1673 1674 if (chan->data_pid_start == DWC2_HC_PID_SETUP) 1675 /* SETUPs are queued only once since they can't be NAK'd */ 1676 return 0; 1677 1678 if (chan->ep_is_in) { 1679 /* 1680 * Always queue another request for other IN transfers. If 1681 * back-to-back INs are issued and NAKs are received for both, 1682 * the driver may still be processing the first NAK when the 1683 * second NAK is received. When the interrupt handler clears 1684 * the NAK interrupt for the first NAK, the second NAK will 1685 * not be seen. So we can't depend on the NAK interrupt 1686 * handler to requeue a NAK'd request. Instead, IN requests 1687 * are issued each time this function is called. When the 1688 * transfer completes, the extra requests for the channel will 1689 * be flushed. 1690 */ 1691 u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1692 1693 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); 1694 hcchar |= HCCHAR_CHENA; 1695 hcchar &= ~HCCHAR_CHDIS; 1696 if (dbg_hc(chan)) 1697 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n", 1698 hcchar); 1699 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1700 chan->requests++; 1701 return 1; 1702 } 1703 1704 /* OUT transfers */ 1705 1706 if (chan->xfer_count < chan->xfer_len) { 1707 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1708 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1709 u32 hcchar = dwc2_readl(hsotg->regs + 1710 HCCHAR(chan->hc_num)); 1711 1712 dwc2_hc_set_even_odd_frame(hsotg, chan, 1713 &hcchar); 1714 } 1715 1716 /* Load OUT packet into the appropriate Tx FIFO */ 1717 dwc2_hc_write_packet(hsotg, chan); 1718 chan->requests++; 1719 return 1; 1720 } 1721 1722 return 0; 1723 } 1724 1725 /* 1726 * ========================================================================= 1727 * HCD 1728 * ========================================================================= 1729 */ 1730 1731 /* 1732 * Processes all the URBs in a single list of QHs. Completes them with 1733 * -ETIMEDOUT and frees the QTD. 1734 * 1735 * Must be called with interrupt disabled and spinlock held 1736 */ 1737 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg, 1738 struct list_head *qh_list) 1739 { 1740 struct dwc2_qh *qh, *qh_tmp; 1741 struct dwc2_qtd *qtd, *qtd_tmp; 1742 1743 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 1744 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 1745 qtd_list_entry) { 1746 dwc2_host_complete(hsotg, qtd, -ECONNRESET); 1747 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 1748 } 1749 } 1750 } 1751 1752 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg, 1753 struct list_head *qh_list) 1754 { 1755 struct dwc2_qtd *qtd, *qtd_tmp; 1756 struct dwc2_qh *qh, *qh_tmp; 1757 unsigned long flags; 1758 1759 if (!qh_list->next) 1760 /* The list hasn't been initialized yet */ 1761 return; 1762 1763 spin_lock_irqsave(&hsotg->lock, flags); 1764 1765 /* Ensure there are no QTDs or URBs left */ 1766 dwc2_kill_urbs_in_qh_list(hsotg, qh_list); 1767 1768 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 1769 dwc2_hcd_qh_unlink(hsotg, qh); 1770 1771 /* Free each QTD in the QH's QTD list */ 1772 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 1773 qtd_list_entry) 1774 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 1775 1776 if (qh->channel && qh->channel->qh == qh) 1777 qh->channel->qh = NULL; 1778 1779 spin_unlock_irqrestore(&hsotg->lock, flags); 1780 dwc2_hcd_qh_free(hsotg, qh); 1781 spin_lock_irqsave(&hsotg->lock, flags); 1782 } 1783 1784 spin_unlock_irqrestore(&hsotg->lock, flags); 1785 } 1786 1787 /* 1788 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic 1789 * and periodic schedules. The QTD associated with each URB is removed from 1790 * the schedule and freed. This function may be called when a disconnect is 1791 * detected or when the HCD is being stopped. 1792 * 1793 * Must be called with interrupt disabled and spinlock held 1794 */ 1795 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg) 1796 { 1797 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive); 1798 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active); 1799 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive); 1800 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready); 1801 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned); 1802 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued); 1803 } 1804 1805 /** 1806 * dwc2_hcd_start() - Starts the HCD when switching to Host mode 1807 * 1808 * @hsotg: Pointer to struct dwc2_hsotg 1809 */ 1810 void dwc2_hcd_start(struct dwc2_hsotg *hsotg) 1811 { 1812 u32 hprt0; 1813 1814 if (hsotg->op_state == OTG_STATE_B_HOST) { 1815 /* 1816 * Reset the port. During a HNP mode switch the reset 1817 * needs to occur within 1ms and have a duration of at 1818 * least 50ms. 1819 */ 1820 hprt0 = dwc2_read_hprt0(hsotg); 1821 hprt0 |= HPRT0_RST; 1822 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1823 } 1824 1825 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, 1826 msecs_to_jiffies(50)); 1827 } 1828 1829 /* Must be called with interrupt disabled and spinlock held */ 1830 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) 1831 { 1832 int num_channels = hsotg->params.host_channels; 1833 struct dwc2_host_chan *channel; 1834 u32 hcchar; 1835 int i; 1836 1837 if (hsotg->params.host_dma <= 0) { 1838 /* Flush out any channel requests in slave mode */ 1839 for (i = 0; i < num_channels; i++) { 1840 channel = hsotg->hc_ptr_array[i]; 1841 if (!list_empty(&channel->hc_list_entry)) 1842 continue; 1843 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 1844 if (hcchar & HCCHAR_CHENA) { 1845 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); 1846 hcchar |= HCCHAR_CHDIS; 1847 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 1848 } 1849 } 1850 } 1851 1852 for (i = 0; i < num_channels; i++) { 1853 channel = hsotg->hc_ptr_array[i]; 1854 if (!list_empty(&channel->hc_list_entry)) 1855 continue; 1856 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 1857 if (hcchar & HCCHAR_CHENA) { 1858 /* Halt the channel */ 1859 hcchar |= HCCHAR_CHDIS; 1860 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 1861 } 1862 1863 dwc2_hc_cleanup(hsotg, channel); 1864 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list); 1865 /* 1866 * Added for Descriptor DMA to prevent channel double cleanup in 1867 * release_channel_ddma(), which is called from ep_disable when 1868 * device disconnects 1869 */ 1870 channel->qh = NULL; 1871 } 1872 /* All channels have been freed, mark them available */ 1873 if (hsotg->params.uframe_sched > 0) { 1874 hsotg->available_host_channels = 1875 hsotg->params.host_channels; 1876 } else { 1877 hsotg->non_periodic_channels = 0; 1878 hsotg->periodic_channels = 0; 1879 } 1880 } 1881 1882 /** 1883 * dwc2_hcd_connect() - Handles connect of the HCD 1884 * 1885 * @hsotg: Pointer to struct dwc2_hsotg 1886 * 1887 * Must be called with interrupt disabled and spinlock held 1888 */ 1889 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) 1890 { 1891 if (hsotg->lx_state != DWC2_L0) 1892 usb_hcd_resume_root_hub(hsotg->priv); 1893 1894 hsotg->flags.b.port_connect_status_change = 1; 1895 hsotg->flags.b.port_connect_status = 1; 1896 } 1897 1898 /** 1899 * dwc2_hcd_disconnect() - Handles disconnect of the HCD 1900 * 1901 * @hsotg: Pointer to struct dwc2_hsotg 1902 * @force: If true, we won't try to reconnect even if we see device connected. 1903 * 1904 * Must be called with interrupt disabled and spinlock held 1905 */ 1906 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) 1907 { 1908 u32 intr; 1909 u32 hprt0; 1910 1911 /* Set status flags for the hub driver */ 1912 hsotg->flags.b.port_connect_status_change = 1; 1913 hsotg->flags.b.port_connect_status = 0; 1914 1915 /* 1916 * Shutdown any transfers in process by clearing the Tx FIFO Empty 1917 * interrupt mask and status bits and disabling subsequent host 1918 * channel interrupts. 1919 */ 1920 intr = dwc2_readl(hsotg->regs + GINTMSK); 1921 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); 1922 dwc2_writel(intr, hsotg->regs + GINTMSK); 1923 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; 1924 dwc2_writel(intr, hsotg->regs + GINTSTS); 1925 1926 /* 1927 * Turn off the vbus power only if the core has transitioned to device 1928 * mode. If still in host mode, need to keep power on to detect a 1929 * reconnection. 1930 */ 1931 if (dwc2_is_device_mode(hsotg)) { 1932 if (hsotg->op_state != OTG_STATE_A_SUSPEND) { 1933 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); 1934 dwc2_writel(0, hsotg->regs + HPRT0); 1935 } 1936 1937 dwc2_disable_host_interrupts(hsotg); 1938 } 1939 1940 /* Respond with an error status to all URBs in the schedule */ 1941 dwc2_kill_all_urbs(hsotg); 1942 1943 if (dwc2_is_host_mode(hsotg)) 1944 /* Clean up any host channels that were in use */ 1945 dwc2_hcd_cleanup_channels(hsotg); 1946 1947 dwc2_host_disconnect(hsotg); 1948 1949 /* 1950 * Add an extra check here to see if we're actually connected but 1951 * we don't have a detection interrupt pending. This can happen if: 1952 * 1. hardware sees connect 1953 * 2. hardware sees disconnect 1954 * 3. hardware sees connect 1955 * 4. dwc2_port_intr() - clears connect interrupt 1956 * 5. dwc2_handle_common_intr() - calls here 1957 * 1958 * Without the extra check here we will end calling disconnect 1959 * and won't get any future interrupts to handle the connect. 1960 */ 1961 if (!force) { 1962 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 1963 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS)) 1964 dwc2_hcd_connect(hsotg); 1965 } 1966 } 1967 1968 /** 1969 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup 1970 * 1971 * @hsotg: Pointer to struct dwc2_hsotg 1972 */ 1973 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg) 1974 { 1975 if (hsotg->bus_suspended) { 1976 hsotg->flags.b.port_suspend_change = 1; 1977 usb_hcd_resume_root_hub(hsotg->priv); 1978 } 1979 1980 if (hsotg->lx_state == DWC2_L1) 1981 hsotg->flags.b.port_l1_change = 1; 1982 } 1983 1984 /** 1985 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner 1986 * 1987 * @hsotg: Pointer to struct dwc2_hsotg 1988 * 1989 * Must be called with interrupt disabled and spinlock held 1990 */ 1991 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg) 1992 { 1993 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n"); 1994 1995 /* 1996 * The root hub should be disconnected before this function is called. 1997 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) 1998 * and the QH lists (via ..._hcd_endpoint_disable). 1999 */ 2000 2001 /* Turn off all host-specific interrupts */ 2002 dwc2_disable_host_interrupts(hsotg); 2003 2004 /* Turn off the vbus power */ 2005 dev_dbg(hsotg->dev, "PortPower off\n"); 2006 dwc2_writel(0, hsotg->regs + HPRT0); 2007 } 2008 2009 /* Caller must hold driver lock */ 2010 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, 2011 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh, 2012 struct dwc2_qtd *qtd) 2013 { 2014 u32 intr_mask; 2015 int retval; 2016 int dev_speed; 2017 2018 if (!hsotg->flags.b.port_connect_status) { 2019 /* No longer connected */ 2020 dev_err(hsotg->dev, "Not connected\n"); 2021 return -ENODEV; 2022 } 2023 2024 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 2025 2026 /* Some configurations cannot support LS traffic on a FS root port */ 2027 if ((dev_speed == USB_SPEED_LOW) && 2028 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && 2029 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { 2030 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 2031 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 2032 2033 if (prtspd == HPRT0_SPD_FULL_SPEED) 2034 return -ENODEV; 2035 } 2036 2037 if (!qtd) 2038 return -EINVAL; 2039 2040 dwc2_hcd_qtd_init(qtd, urb); 2041 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh); 2042 if (retval) { 2043 dev_err(hsotg->dev, 2044 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n", 2045 retval); 2046 return retval; 2047 } 2048 2049 intr_mask = dwc2_readl(hsotg->regs + GINTMSK); 2050 if (!(intr_mask & GINTSTS_SOF)) { 2051 enum dwc2_transaction_type tr_type; 2052 2053 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK && 2054 !(qtd->urb->flags & URB_GIVEBACK_ASAP)) 2055 /* 2056 * Do not schedule SG transactions until qtd has 2057 * URB_GIVEBACK_ASAP set 2058 */ 2059 return 0; 2060 2061 tr_type = dwc2_hcd_select_transactions(hsotg); 2062 if (tr_type != DWC2_TRANSACTION_NONE) 2063 dwc2_hcd_queue_transactions(hsotg, tr_type); 2064 } 2065 2066 return 0; 2067 } 2068 2069 /* Must be called with interrupt disabled and spinlock held */ 2070 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg, 2071 struct dwc2_hcd_urb *urb) 2072 { 2073 struct dwc2_qh *qh; 2074 struct dwc2_qtd *urb_qtd; 2075 2076 urb_qtd = urb->qtd; 2077 if (!urb_qtd) { 2078 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n"); 2079 return -EINVAL; 2080 } 2081 2082 qh = urb_qtd->qh; 2083 if (!qh) { 2084 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n"); 2085 return -EINVAL; 2086 } 2087 2088 urb->priv = NULL; 2089 2090 if (urb_qtd->in_process && qh->channel) { 2091 dwc2_dump_channel_info(hsotg, qh->channel); 2092 2093 /* The QTD is in process (it has been assigned to a channel) */ 2094 if (hsotg->flags.b.port_connect_status) 2095 /* 2096 * If still connected (i.e. in host mode), halt the 2097 * channel so it can be used for other transfers. If 2098 * no longer connected, the host registers can't be 2099 * written to halt the channel since the core is in 2100 * device mode. 2101 */ 2102 dwc2_hc_halt(hsotg, qh->channel, 2103 DWC2_HC_XFER_URB_DEQUEUE); 2104 } 2105 2106 /* 2107 * Free the QTD and clean up the associated QH. Leave the QH in the 2108 * schedule if it has any remaining QTDs. 2109 */ 2110 if (hsotg->params.dma_desc_enable <= 0) { 2111 u8 in_process = urb_qtd->in_process; 2112 2113 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 2114 if (in_process) { 2115 dwc2_hcd_qh_deactivate(hsotg, qh, 0); 2116 qh->channel = NULL; 2117 } else if (list_empty(&qh->qtd_list)) { 2118 dwc2_hcd_qh_unlink(hsotg, qh); 2119 } 2120 } else { 2121 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 2122 } 2123 2124 return 0; 2125 } 2126 2127 /* Must NOT be called with interrupt disabled or spinlock held */ 2128 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg, 2129 struct usb_host_endpoint *ep, int retry) 2130 { 2131 struct dwc2_qtd *qtd, *qtd_tmp; 2132 struct dwc2_qh *qh; 2133 unsigned long flags; 2134 int rc; 2135 2136 spin_lock_irqsave(&hsotg->lock, flags); 2137 2138 qh = ep->hcpriv; 2139 if (!qh) { 2140 rc = -EINVAL; 2141 goto err; 2142 } 2143 2144 while (!list_empty(&qh->qtd_list) && retry--) { 2145 if (retry == 0) { 2146 dev_err(hsotg->dev, 2147 "## timeout in dwc2_hcd_endpoint_disable() ##\n"); 2148 rc = -EBUSY; 2149 goto err; 2150 } 2151 2152 spin_unlock_irqrestore(&hsotg->lock, flags); 2153 msleep(20); 2154 spin_lock_irqsave(&hsotg->lock, flags); 2155 qh = ep->hcpriv; 2156 if (!qh) { 2157 rc = -EINVAL; 2158 goto err; 2159 } 2160 } 2161 2162 dwc2_hcd_qh_unlink(hsotg, qh); 2163 2164 /* Free each QTD in the QH's QTD list */ 2165 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) 2166 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 2167 2168 ep->hcpriv = NULL; 2169 2170 if (qh->channel && qh->channel->qh == qh) 2171 qh->channel->qh = NULL; 2172 2173 spin_unlock_irqrestore(&hsotg->lock, flags); 2174 2175 dwc2_hcd_qh_free(hsotg, qh); 2176 2177 return 0; 2178 2179 err: 2180 ep->hcpriv = NULL; 2181 spin_unlock_irqrestore(&hsotg->lock, flags); 2182 2183 return rc; 2184 } 2185 2186 /* Must be called with interrupt disabled and spinlock held */ 2187 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg, 2188 struct usb_host_endpoint *ep) 2189 { 2190 struct dwc2_qh *qh = ep->hcpriv; 2191 2192 if (!qh) 2193 return -EINVAL; 2194 2195 qh->data_toggle = DWC2_HC_PID_DATA0; 2196 2197 return 0; 2198 } 2199 2200 /** 2201 * dwc2_core_init() - Initializes the DWC_otg controller registers and 2202 * prepares the core for device mode or host mode operation 2203 * 2204 * @hsotg: Programming view of the DWC_otg controller 2205 * @initial_setup: If true then this is the first init for this instance. 2206 */ 2207 static int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) 2208 { 2209 u32 usbcfg, otgctl; 2210 int retval; 2211 2212 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 2213 2214 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 2215 2216 /* Set ULPI External VBUS bit if needed */ 2217 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV; 2218 if (hsotg->params.phy_ulpi_ext_vbus == 2219 DWC2_PHY_ULPI_EXTERNAL_VBUS) 2220 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV; 2221 2222 /* Set external TS Dline pulsing bit if needed */ 2223 usbcfg &= ~GUSBCFG_TERMSELDLPULSE; 2224 if (hsotg->params.ts_dline > 0) 2225 usbcfg |= GUSBCFG_TERMSELDLPULSE; 2226 2227 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 2228 2229 /* 2230 * Reset the Controller 2231 * 2232 * We only need to reset the controller if this is a re-init. 2233 * For the first init we know for sure that earlier code reset us (it 2234 * needed to in order to properly detect various parameters). 2235 */ 2236 if (!initial_setup) { 2237 retval = dwc2_core_reset_and_force_dr_mode(hsotg); 2238 if (retval) { 2239 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n", 2240 __func__); 2241 return retval; 2242 } 2243 } 2244 2245 /* 2246 * This needs to happen in FS mode before any other programming occurs 2247 */ 2248 retval = dwc2_phy_init(hsotg, initial_setup); 2249 if (retval) 2250 return retval; 2251 2252 /* Program the GAHBCFG Register */ 2253 retval = dwc2_gahbcfg_init(hsotg); 2254 if (retval) 2255 return retval; 2256 2257 /* Program the GUSBCFG register */ 2258 dwc2_gusbcfg_init(hsotg); 2259 2260 /* Program the GOTGCTL register */ 2261 otgctl = dwc2_readl(hsotg->regs + GOTGCTL); 2262 otgctl &= ~GOTGCTL_OTGVER; 2263 if (hsotg->params.otg_ver > 0) 2264 otgctl |= GOTGCTL_OTGVER; 2265 dwc2_writel(otgctl, hsotg->regs + GOTGCTL); 2266 dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->params.otg_ver); 2267 2268 /* Clear the SRP success bit for FS-I2c */ 2269 hsotg->srp_success = 0; 2270 2271 /* Enable common interrupts */ 2272 dwc2_enable_common_interrupts(hsotg); 2273 2274 /* 2275 * Do device or host initialization based on mode during PCD and 2276 * HCD initialization 2277 */ 2278 if (dwc2_is_host_mode(hsotg)) { 2279 dev_dbg(hsotg->dev, "Host Mode\n"); 2280 hsotg->op_state = OTG_STATE_A_HOST; 2281 } else { 2282 dev_dbg(hsotg->dev, "Device Mode\n"); 2283 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 2284 } 2285 2286 return 0; 2287 } 2288 2289 /** 2290 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for 2291 * Host mode 2292 * 2293 * @hsotg: Programming view of DWC_otg controller 2294 * 2295 * This function flushes the Tx and Rx FIFOs and flushes any entries in the 2296 * request queues. Host channels are reset to ensure that they are ready for 2297 * performing transfers. 2298 */ 2299 static void dwc2_core_host_init(struct dwc2_hsotg *hsotg) 2300 { 2301 u32 hcfg, hfir, otgctl; 2302 2303 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 2304 2305 /* Restart the Phy Clock */ 2306 dwc2_writel(0, hsotg->regs + PCGCTL); 2307 2308 /* Initialize Host Configuration Register */ 2309 dwc2_init_fs_ls_pclk_sel(hsotg); 2310 if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL || 2311 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) { 2312 hcfg = dwc2_readl(hsotg->regs + HCFG); 2313 hcfg |= HCFG_FSLSSUPP; 2314 dwc2_writel(hcfg, hsotg->regs + HCFG); 2315 } 2316 2317 /* 2318 * This bit allows dynamic reloading of the HFIR register during 2319 * runtime. This bit needs to be programmed during initial configuration 2320 * and its value must not be changed during runtime. 2321 */ 2322 if (hsotg->params.reload_ctl > 0) { 2323 hfir = dwc2_readl(hsotg->regs + HFIR); 2324 hfir |= HFIR_RLDCTRL; 2325 dwc2_writel(hfir, hsotg->regs + HFIR); 2326 } 2327 2328 if (hsotg->params.dma_desc_enable > 0) { 2329 u32 op_mode = hsotg->hw_params.op_mode; 2330 2331 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a || 2332 !hsotg->hw_params.dma_desc_enable || 2333 op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE || 2334 op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE || 2335 op_mode == GHWCFG2_OP_MODE_UNDEFINED) { 2336 dev_err(hsotg->dev, 2337 "Hardware does not support descriptor DMA mode -\n"); 2338 dev_err(hsotg->dev, 2339 "falling back to buffer DMA mode.\n"); 2340 hsotg->params.dma_desc_enable = 0; 2341 } else { 2342 hcfg = dwc2_readl(hsotg->regs + HCFG); 2343 hcfg |= HCFG_DESCDMA; 2344 dwc2_writel(hcfg, hsotg->regs + HCFG); 2345 } 2346 } 2347 2348 /* Configure data FIFO sizes */ 2349 dwc2_config_fifos(hsotg); 2350 2351 /* TODO - check this */ 2352 /* Clear Host Set HNP Enable in the OTG Control Register */ 2353 otgctl = dwc2_readl(hsotg->regs + GOTGCTL); 2354 otgctl &= ~GOTGCTL_HSTSETHNPEN; 2355 dwc2_writel(otgctl, hsotg->regs + GOTGCTL); 2356 2357 /* Make sure the FIFOs are flushed */ 2358 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */); 2359 dwc2_flush_rx_fifo(hsotg); 2360 2361 /* Clear Host Set HNP Enable in the OTG Control Register */ 2362 otgctl = dwc2_readl(hsotg->regs + GOTGCTL); 2363 otgctl &= ~GOTGCTL_HSTSETHNPEN; 2364 dwc2_writel(otgctl, hsotg->regs + GOTGCTL); 2365 2366 if (hsotg->params.dma_desc_enable <= 0) { 2367 int num_channels, i; 2368 u32 hcchar; 2369 2370 /* Flush out any leftover queued requests */ 2371 num_channels = hsotg->params.host_channels; 2372 for (i = 0; i < num_channels; i++) { 2373 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 2374 hcchar &= ~HCCHAR_CHENA; 2375 hcchar |= HCCHAR_CHDIS; 2376 hcchar &= ~HCCHAR_EPDIR; 2377 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 2378 } 2379 2380 /* Halt all channels to put them into a known state */ 2381 for (i = 0; i < num_channels; i++) { 2382 int count = 0; 2383 2384 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 2385 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS; 2386 hcchar &= ~HCCHAR_EPDIR; 2387 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 2388 dev_dbg(hsotg->dev, "%s: Halt channel %d\n", 2389 __func__, i); 2390 do { 2391 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 2392 if (++count > 1000) { 2393 dev_err(hsotg->dev, 2394 "Unable to clear enable on channel %d\n", 2395 i); 2396 break; 2397 } 2398 udelay(1); 2399 } while (hcchar & HCCHAR_CHENA); 2400 } 2401 } 2402 2403 /* Turn on the vbus power */ 2404 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state); 2405 if (hsotg->op_state == OTG_STATE_A_HOST) { 2406 u32 hprt0 = dwc2_read_hprt0(hsotg); 2407 2408 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n", 2409 !!(hprt0 & HPRT0_PWR)); 2410 if (!(hprt0 & HPRT0_PWR)) { 2411 hprt0 |= HPRT0_PWR; 2412 dwc2_writel(hprt0, hsotg->regs + HPRT0); 2413 } 2414 } 2415 2416 dwc2_enable_host_interrupts(hsotg); 2417 } 2418 2419 /* 2420 * Initializes dynamic portions of the DWC_otg HCD state 2421 * 2422 * Must be called with interrupt disabled and spinlock held 2423 */ 2424 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg) 2425 { 2426 struct dwc2_host_chan *chan, *chan_tmp; 2427 int num_channels; 2428 int i; 2429 2430 hsotg->flags.d32 = 0; 2431 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active; 2432 2433 if (hsotg->params.uframe_sched > 0) { 2434 hsotg->available_host_channels = 2435 hsotg->params.host_channels; 2436 } else { 2437 hsotg->non_periodic_channels = 0; 2438 hsotg->periodic_channels = 0; 2439 } 2440 2441 /* 2442 * Put all channels in the free channel list and clean up channel 2443 * states 2444 */ 2445 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list, 2446 hc_list_entry) 2447 list_del_init(&chan->hc_list_entry); 2448 2449 num_channels = hsotg->params.host_channels; 2450 for (i = 0; i < num_channels; i++) { 2451 chan = hsotg->hc_ptr_array[i]; 2452 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); 2453 dwc2_hc_cleanup(hsotg, chan); 2454 } 2455 2456 /* Initialize the DWC core for host mode operation */ 2457 dwc2_core_host_init(hsotg); 2458 } 2459 2460 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg, 2461 struct dwc2_host_chan *chan, 2462 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 2463 { 2464 int hub_addr, hub_port; 2465 2466 chan->do_split = 1; 2467 chan->xact_pos = qtd->isoc_split_pos; 2468 chan->complete_split = qtd->complete_split; 2469 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 2470 chan->hub_addr = (u8)hub_addr; 2471 chan->hub_port = (u8)hub_port; 2472 } 2473 2474 static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg, 2475 struct dwc2_host_chan *chan, 2476 struct dwc2_qtd *qtd) 2477 { 2478 struct dwc2_hcd_urb *urb = qtd->urb; 2479 struct dwc2_hcd_iso_packet_desc *frame_desc; 2480 2481 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { 2482 case USB_ENDPOINT_XFER_CONTROL: 2483 chan->ep_type = USB_ENDPOINT_XFER_CONTROL; 2484 2485 switch (qtd->control_phase) { 2486 case DWC2_CONTROL_SETUP: 2487 dev_vdbg(hsotg->dev, " Control setup transaction\n"); 2488 chan->do_ping = 0; 2489 chan->ep_is_in = 0; 2490 chan->data_pid_start = DWC2_HC_PID_SETUP; 2491 if (hsotg->params.host_dma > 0) 2492 chan->xfer_dma = urb->setup_dma; 2493 else 2494 chan->xfer_buf = urb->setup_packet; 2495 chan->xfer_len = 8; 2496 break; 2497 2498 case DWC2_CONTROL_DATA: 2499 dev_vdbg(hsotg->dev, " Control data transaction\n"); 2500 chan->data_pid_start = qtd->data_toggle; 2501 break; 2502 2503 case DWC2_CONTROL_STATUS: 2504 /* 2505 * Direction is opposite of data direction or IN if no 2506 * data 2507 */ 2508 dev_vdbg(hsotg->dev, " Control status transaction\n"); 2509 if (urb->length == 0) 2510 chan->ep_is_in = 1; 2511 else 2512 chan->ep_is_in = 2513 dwc2_hcd_is_pipe_out(&urb->pipe_info); 2514 if (chan->ep_is_in) 2515 chan->do_ping = 0; 2516 chan->data_pid_start = DWC2_HC_PID_DATA1; 2517 chan->xfer_len = 0; 2518 if (hsotg->params.host_dma > 0) 2519 chan->xfer_dma = hsotg->status_buf_dma; 2520 else 2521 chan->xfer_buf = hsotg->status_buf; 2522 break; 2523 } 2524 break; 2525 2526 case USB_ENDPOINT_XFER_BULK: 2527 chan->ep_type = USB_ENDPOINT_XFER_BULK; 2528 break; 2529 2530 case USB_ENDPOINT_XFER_INT: 2531 chan->ep_type = USB_ENDPOINT_XFER_INT; 2532 break; 2533 2534 case USB_ENDPOINT_XFER_ISOC: 2535 chan->ep_type = USB_ENDPOINT_XFER_ISOC; 2536 if (hsotg->params.dma_desc_enable > 0) 2537 break; 2538 2539 frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; 2540 frame_desc->status = 0; 2541 2542 if (hsotg->params.host_dma > 0) { 2543 chan->xfer_dma = urb->dma; 2544 chan->xfer_dma += frame_desc->offset + 2545 qtd->isoc_split_offset; 2546 } else { 2547 chan->xfer_buf = urb->buf; 2548 chan->xfer_buf += frame_desc->offset + 2549 qtd->isoc_split_offset; 2550 } 2551 2552 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset; 2553 2554 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) { 2555 if (chan->xfer_len <= 188) 2556 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL; 2557 else 2558 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN; 2559 } 2560 break; 2561 } 2562 } 2563 2564 #define DWC2_USB_DMA_ALIGN 4 2565 2566 struct dma_aligned_buffer { 2567 void *kmalloc_ptr; 2568 void *old_xfer_buffer; 2569 u8 data[0]; 2570 }; 2571 2572 static void dwc2_free_dma_aligned_buffer(struct urb *urb) 2573 { 2574 struct dma_aligned_buffer *temp; 2575 2576 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) 2577 return; 2578 2579 temp = container_of(urb->transfer_buffer, 2580 struct dma_aligned_buffer, data); 2581 2582 if (usb_urb_dir_in(urb)) 2583 memcpy(temp->old_xfer_buffer, temp->data, 2584 urb->transfer_buffer_length); 2585 urb->transfer_buffer = temp->old_xfer_buffer; 2586 kfree(temp->kmalloc_ptr); 2587 2588 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; 2589 } 2590 2591 static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags) 2592 { 2593 struct dma_aligned_buffer *temp, *kmalloc_ptr; 2594 size_t kmalloc_size; 2595 2596 if (urb->num_sgs || urb->sg || 2597 urb->transfer_buffer_length == 0 || 2598 !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1))) 2599 return 0; 2600 2601 /* Allocate a buffer with enough padding for alignment */ 2602 kmalloc_size = urb->transfer_buffer_length + 2603 sizeof(struct dma_aligned_buffer) + DWC2_USB_DMA_ALIGN - 1; 2604 2605 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags); 2606 if (!kmalloc_ptr) 2607 return -ENOMEM; 2608 2609 /* Position our struct dma_aligned_buffer such that data is aligned */ 2610 temp = PTR_ALIGN(kmalloc_ptr + 1, DWC2_USB_DMA_ALIGN) - 1; 2611 temp->kmalloc_ptr = kmalloc_ptr; 2612 temp->old_xfer_buffer = urb->transfer_buffer; 2613 if (usb_urb_dir_out(urb)) 2614 memcpy(temp->data, urb->transfer_buffer, 2615 urb->transfer_buffer_length); 2616 urb->transfer_buffer = temp->data; 2617 2618 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; 2619 2620 return 0; 2621 } 2622 2623 static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, 2624 gfp_t mem_flags) 2625 { 2626 int ret; 2627 2628 /* We assume setup_dma is always aligned; warn if not */ 2629 WARN_ON_ONCE(urb->setup_dma && 2630 (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1))); 2631 2632 ret = dwc2_alloc_dma_aligned_buffer(urb, mem_flags); 2633 if (ret) 2634 return ret; 2635 2636 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); 2637 if (ret) 2638 dwc2_free_dma_aligned_buffer(urb); 2639 2640 return ret; 2641 } 2642 2643 static void dwc2_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) 2644 { 2645 usb_hcd_unmap_urb_for_dma(hcd, urb); 2646 dwc2_free_dma_aligned_buffer(urb); 2647 } 2648 2649 /** 2650 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host 2651 * channel and initializes the host channel to perform the transactions. The 2652 * host channel is removed from the free list. 2653 * 2654 * @hsotg: The HCD state structure 2655 * @qh: Transactions from the first QTD for this QH are selected and assigned 2656 * to a free host channel 2657 */ 2658 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 2659 { 2660 struct dwc2_host_chan *chan; 2661 struct dwc2_hcd_urb *urb; 2662 struct dwc2_qtd *qtd; 2663 2664 if (dbg_qh(qh)) 2665 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh); 2666 2667 if (list_empty(&qh->qtd_list)) { 2668 dev_dbg(hsotg->dev, "No QTDs in QH list\n"); 2669 return -ENOMEM; 2670 } 2671 2672 if (list_empty(&hsotg->free_hc_list)) { 2673 dev_dbg(hsotg->dev, "No free channel to assign\n"); 2674 return -ENOMEM; 2675 } 2676 2677 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan, 2678 hc_list_entry); 2679 2680 /* Remove host channel from free list */ 2681 list_del_init(&chan->hc_list_entry); 2682 2683 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry); 2684 urb = qtd->urb; 2685 qh->channel = chan; 2686 qtd->in_process = 1; 2687 2688 /* 2689 * Use usb_pipedevice to determine device address. This address is 2690 * 0 before the SET_ADDRESS command and the correct address afterward. 2691 */ 2692 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info); 2693 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info); 2694 chan->speed = qh->dev_speed; 2695 chan->max_packet = dwc2_max_packet(qh->maxp); 2696 2697 chan->xfer_started = 0; 2698 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; 2699 chan->error_state = (qtd->error_count > 0); 2700 chan->halt_on_queue = 0; 2701 chan->halt_pending = 0; 2702 chan->requests = 0; 2703 2704 /* 2705 * The following values may be modified in the transfer type section 2706 * below. The xfer_len value may be reduced when the transfer is 2707 * started to accommodate the max widths of the XferSize and PktCnt 2708 * fields in the HCTSIZn register. 2709 */ 2710 2711 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0); 2712 if (chan->ep_is_in) 2713 chan->do_ping = 0; 2714 else 2715 chan->do_ping = qh->ping_state; 2716 2717 chan->data_pid_start = qh->data_toggle; 2718 chan->multi_count = 1; 2719 2720 if (urb->actual_length > urb->length && 2721 !dwc2_hcd_is_pipe_in(&urb->pipe_info)) 2722 urb->actual_length = urb->length; 2723 2724 if (hsotg->params.host_dma > 0) 2725 chan->xfer_dma = urb->dma + urb->actual_length; 2726 else 2727 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length; 2728 2729 chan->xfer_len = urb->length - urb->actual_length; 2730 chan->xfer_count = 0; 2731 2732 /* Set the split attributes if required */ 2733 if (qh->do_split) 2734 dwc2_hc_init_split(hsotg, chan, qtd, urb); 2735 else 2736 chan->do_split = 0; 2737 2738 /* Set the transfer attributes */ 2739 dwc2_hc_init_xfer(hsotg, chan, qtd); 2740 2741 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 2742 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 2743 /* 2744 * This value may be modified when the transfer is started 2745 * to reflect the actual transfer length 2746 */ 2747 chan->multi_count = dwc2_hb_mult(qh->maxp); 2748 2749 if (hsotg->params.dma_desc_enable > 0) { 2750 chan->desc_list_addr = qh->desc_list_dma; 2751 chan->desc_list_sz = qh->desc_list_sz; 2752 } 2753 2754 dwc2_hc_init(hsotg, chan); 2755 chan->qh = qh; 2756 2757 return 0; 2758 } 2759 2760 /** 2761 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer 2762 * schedule and assigns them to available host channels. Called from the HCD 2763 * interrupt handler functions. 2764 * 2765 * @hsotg: The HCD state structure 2766 * 2767 * Return: The types of new transactions that were assigned to host channels 2768 */ 2769 enum dwc2_transaction_type dwc2_hcd_select_transactions( 2770 struct dwc2_hsotg *hsotg) 2771 { 2772 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE; 2773 struct list_head *qh_ptr; 2774 struct dwc2_qh *qh; 2775 int num_channels; 2776 2777 #ifdef DWC2_DEBUG_SOF 2778 dev_vdbg(hsotg->dev, " Select Transactions\n"); 2779 #endif 2780 2781 /* Process entries in the periodic ready list */ 2782 qh_ptr = hsotg->periodic_sched_ready.next; 2783 while (qh_ptr != &hsotg->periodic_sched_ready) { 2784 if (list_empty(&hsotg->free_hc_list)) 2785 break; 2786 if (hsotg->params.uframe_sched > 0) { 2787 if (hsotg->available_host_channels <= 1) 2788 break; 2789 hsotg->available_host_channels--; 2790 } 2791 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 2792 if (dwc2_assign_and_init_hc(hsotg, qh)) 2793 break; 2794 2795 /* 2796 * Move the QH from the periodic ready schedule to the 2797 * periodic assigned schedule 2798 */ 2799 qh_ptr = qh_ptr->next; 2800 list_move_tail(&qh->qh_list_entry, 2801 &hsotg->periodic_sched_assigned); 2802 ret_val = DWC2_TRANSACTION_PERIODIC; 2803 } 2804 2805 /* 2806 * Process entries in the inactive portion of the non-periodic 2807 * schedule. Some free host channels may not be used if they are 2808 * reserved for periodic transfers. 2809 */ 2810 num_channels = hsotg->params.host_channels; 2811 qh_ptr = hsotg->non_periodic_sched_inactive.next; 2812 while (qh_ptr != &hsotg->non_periodic_sched_inactive) { 2813 if (hsotg->params.uframe_sched <= 0 && 2814 hsotg->non_periodic_channels >= num_channels - 2815 hsotg->periodic_channels) 2816 break; 2817 if (list_empty(&hsotg->free_hc_list)) 2818 break; 2819 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 2820 if (hsotg->params.uframe_sched > 0) { 2821 if (hsotg->available_host_channels < 1) 2822 break; 2823 hsotg->available_host_channels--; 2824 } 2825 2826 if (dwc2_assign_and_init_hc(hsotg, qh)) 2827 break; 2828 2829 /* 2830 * Move the QH from the non-periodic inactive schedule to the 2831 * non-periodic active schedule 2832 */ 2833 qh_ptr = qh_ptr->next; 2834 list_move_tail(&qh->qh_list_entry, 2835 &hsotg->non_periodic_sched_active); 2836 2837 if (ret_val == DWC2_TRANSACTION_NONE) 2838 ret_val = DWC2_TRANSACTION_NON_PERIODIC; 2839 else 2840 ret_val = DWC2_TRANSACTION_ALL; 2841 2842 if (hsotg->params.uframe_sched <= 0) 2843 hsotg->non_periodic_channels++; 2844 } 2845 2846 return ret_val; 2847 } 2848 2849 /** 2850 * dwc2_queue_transaction() - Attempts to queue a single transaction request for 2851 * a host channel associated with either a periodic or non-periodic transfer 2852 * 2853 * @hsotg: The HCD state structure 2854 * @chan: Host channel descriptor associated with either a periodic or 2855 * non-periodic transfer 2856 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO 2857 * for periodic transfers or the non-periodic Tx FIFO 2858 * for non-periodic transfers 2859 * 2860 * Return: 1 if a request is queued and more requests may be needed to 2861 * complete the transfer, 0 if no more requests are required for this 2862 * transfer, -1 if there is insufficient space in the Tx FIFO 2863 * 2864 * This function assumes that there is space available in the appropriate 2865 * request queue. For an OUT transfer or SETUP transaction in Slave mode, 2866 * it checks whether space is available in the appropriate Tx FIFO. 2867 * 2868 * Must be called with interrupt disabled and spinlock held 2869 */ 2870 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg, 2871 struct dwc2_host_chan *chan, 2872 u16 fifo_dwords_avail) 2873 { 2874 int retval = 0; 2875 2876 if (chan->do_split) 2877 /* Put ourselves on the list to keep order straight */ 2878 list_move_tail(&chan->split_order_list_entry, 2879 &hsotg->split_order); 2880 2881 if (hsotg->params.host_dma > 0) { 2882 if (hsotg->params.dma_desc_enable > 0) { 2883 if (!chan->xfer_started || 2884 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 2885 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh); 2886 chan->qh->ping_state = 0; 2887 } 2888 } else if (!chan->xfer_started) { 2889 dwc2_hc_start_transfer(hsotg, chan); 2890 chan->qh->ping_state = 0; 2891 } 2892 } else if (chan->halt_pending) { 2893 /* Don't queue a request if the channel has been halted */ 2894 } else if (chan->halt_on_queue) { 2895 dwc2_hc_halt(hsotg, chan, chan->halt_status); 2896 } else if (chan->do_ping) { 2897 if (!chan->xfer_started) 2898 dwc2_hc_start_transfer(hsotg, chan); 2899 } else if (!chan->ep_is_in || 2900 chan->data_pid_start == DWC2_HC_PID_SETUP) { 2901 if ((fifo_dwords_avail * 4) >= chan->max_packet) { 2902 if (!chan->xfer_started) { 2903 dwc2_hc_start_transfer(hsotg, chan); 2904 retval = 1; 2905 } else { 2906 retval = dwc2_hc_continue_transfer(hsotg, chan); 2907 } 2908 } else { 2909 retval = -1; 2910 } 2911 } else { 2912 if (!chan->xfer_started) { 2913 dwc2_hc_start_transfer(hsotg, chan); 2914 retval = 1; 2915 } else { 2916 retval = dwc2_hc_continue_transfer(hsotg, chan); 2917 } 2918 } 2919 2920 return retval; 2921 } 2922 2923 /* 2924 * Processes periodic channels for the next frame and queues transactions for 2925 * these channels to the DWC_otg controller. After queueing transactions, the 2926 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions 2927 * to queue as Periodic Tx FIFO or request queue space becomes available. 2928 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. 2929 * 2930 * Must be called with interrupt disabled and spinlock held 2931 */ 2932 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) 2933 { 2934 struct list_head *qh_ptr; 2935 struct dwc2_qh *qh; 2936 u32 tx_status; 2937 u32 fspcavail; 2938 u32 gintmsk; 2939 int status; 2940 bool no_queue_space = false; 2941 bool no_fifo_space = false; 2942 u32 qspcavail; 2943 2944 /* If empty list then just adjust interrupt enables */ 2945 if (list_empty(&hsotg->periodic_sched_assigned)) 2946 goto exit; 2947 2948 if (dbg_perio()) 2949 dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); 2950 2951 tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 2952 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 2953 TXSTS_QSPCAVAIL_SHIFT; 2954 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 2955 TXSTS_FSPCAVAIL_SHIFT; 2956 2957 if (dbg_perio()) { 2958 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n", 2959 qspcavail); 2960 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n", 2961 fspcavail); 2962 } 2963 2964 qh_ptr = hsotg->periodic_sched_assigned.next; 2965 while (qh_ptr != &hsotg->periodic_sched_assigned) { 2966 tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 2967 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 2968 TXSTS_QSPCAVAIL_SHIFT; 2969 if (qspcavail == 0) { 2970 no_queue_space = 1; 2971 break; 2972 } 2973 2974 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 2975 if (!qh->channel) { 2976 qh_ptr = qh_ptr->next; 2977 continue; 2978 } 2979 2980 /* Make sure EP's TT buffer is clean before queueing qtds */ 2981 if (qh->tt_buffer_dirty) { 2982 qh_ptr = qh_ptr->next; 2983 continue; 2984 } 2985 2986 /* 2987 * Set a flag if we're queuing high-bandwidth in slave mode. 2988 * The flag prevents any halts to get into the request queue in 2989 * the middle of multiple high-bandwidth packets getting queued. 2990 */ 2991 if (hsotg->params.host_dma <= 0 && 2992 qh->channel->multi_count > 1) 2993 hsotg->queuing_high_bandwidth = 1; 2994 2995 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 2996 TXSTS_FSPCAVAIL_SHIFT; 2997 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 2998 if (status < 0) { 2999 no_fifo_space = 1; 3000 break; 3001 } 3002 3003 /* 3004 * In Slave mode, stay on the current transfer until there is 3005 * nothing more to do or the high-bandwidth request count is 3006 * reached. In DMA mode, only need to queue one request. The 3007 * controller automatically handles multiple packets for 3008 * high-bandwidth transfers. 3009 */ 3010 if (hsotg->params.host_dma > 0 || status == 0 || 3011 qh->channel->requests == qh->channel->multi_count) { 3012 qh_ptr = qh_ptr->next; 3013 /* 3014 * Move the QH from the periodic assigned schedule to 3015 * the periodic queued schedule 3016 */ 3017 list_move_tail(&qh->qh_list_entry, 3018 &hsotg->periodic_sched_queued); 3019 3020 /* done queuing high bandwidth */ 3021 hsotg->queuing_high_bandwidth = 0; 3022 } 3023 } 3024 3025 exit: 3026 if (no_queue_space || no_fifo_space || 3027 (hsotg->params.host_dma <= 0 && 3028 !list_empty(&hsotg->periodic_sched_assigned))) { 3029 /* 3030 * May need to queue more transactions as the request 3031 * queue or Tx FIFO empties. Enable the periodic Tx 3032 * FIFO empty interrupt. (Always use the half-empty 3033 * level to ensure that new requests are loaded as 3034 * soon as possible.) 3035 */ 3036 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3037 if (!(gintmsk & GINTSTS_PTXFEMP)) { 3038 gintmsk |= GINTSTS_PTXFEMP; 3039 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3040 } 3041 } else { 3042 /* 3043 * Disable the Tx FIFO empty interrupt since there are 3044 * no more transactions that need to be queued right 3045 * now. This function is called from interrupt 3046 * handlers to queue more transactions as transfer 3047 * states change. 3048 */ 3049 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3050 if (gintmsk & GINTSTS_PTXFEMP) { 3051 gintmsk &= ~GINTSTS_PTXFEMP; 3052 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3053 } 3054 } 3055 } 3056 3057 /* 3058 * Processes active non-periodic channels and queues transactions for these 3059 * channels to the DWC_otg controller. After queueing transactions, the NP Tx 3060 * FIFO Empty interrupt is enabled if there are more transactions to queue as 3061 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx 3062 * FIFO Empty interrupt is disabled. 3063 * 3064 * Must be called with interrupt disabled and spinlock held 3065 */ 3066 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) 3067 { 3068 struct list_head *orig_qh_ptr; 3069 struct dwc2_qh *qh; 3070 u32 tx_status; 3071 u32 qspcavail; 3072 u32 fspcavail; 3073 u32 gintmsk; 3074 int status; 3075 int no_queue_space = 0; 3076 int no_fifo_space = 0; 3077 int more_to_do = 0; 3078 3079 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); 3080 3081 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3082 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3083 TXSTS_QSPCAVAIL_SHIFT; 3084 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3085 TXSTS_FSPCAVAIL_SHIFT; 3086 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n", 3087 qspcavail); 3088 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n", 3089 fspcavail); 3090 3091 /* 3092 * Keep track of the starting point. Skip over the start-of-list 3093 * entry. 3094 */ 3095 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active) 3096 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 3097 orig_qh_ptr = hsotg->non_periodic_qh_ptr; 3098 3099 /* 3100 * Process once through the active list or until no more space is 3101 * available in the request queue or the Tx FIFO 3102 */ 3103 do { 3104 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3105 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3106 TXSTS_QSPCAVAIL_SHIFT; 3107 if (hsotg->params.host_dma <= 0 && qspcavail == 0) { 3108 no_queue_space = 1; 3109 break; 3110 } 3111 3112 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh, 3113 qh_list_entry); 3114 if (!qh->channel) 3115 goto next; 3116 3117 /* Make sure EP's TT buffer is clean before queueing qtds */ 3118 if (qh->tt_buffer_dirty) 3119 goto next; 3120 3121 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3122 TXSTS_FSPCAVAIL_SHIFT; 3123 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 3124 3125 if (status > 0) { 3126 more_to_do = 1; 3127 } else if (status < 0) { 3128 no_fifo_space = 1; 3129 break; 3130 } 3131 next: 3132 /* Advance to next QH, skipping start-of-list entry */ 3133 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 3134 if (hsotg->non_periodic_qh_ptr == 3135 &hsotg->non_periodic_sched_active) 3136 hsotg->non_periodic_qh_ptr = 3137 hsotg->non_periodic_qh_ptr->next; 3138 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); 3139 3140 if (hsotg->params.host_dma <= 0) { 3141 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3142 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3143 TXSTS_QSPCAVAIL_SHIFT; 3144 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3145 TXSTS_FSPCAVAIL_SHIFT; 3146 dev_vdbg(hsotg->dev, 3147 " NP Tx Req Queue Space Avail (after queue): %d\n", 3148 qspcavail); 3149 dev_vdbg(hsotg->dev, 3150 " NP Tx FIFO Space Avail (after queue): %d\n", 3151 fspcavail); 3152 3153 if (more_to_do || no_queue_space || no_fifo_space) { 3154 /* 3155 * May need to queue more transactions as the request 3156 * queue or Tx FIFO empties. Enable the non-periodic 3157 * Tx FIFO empty interrupt. (Always use the half-empty 3158 * level to ensure that new requests are loaded as 3159 * soon as possible.) 3160 */ 3161 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3162 gintmsk |= GINTSTS_NPTXFEMP; 3163 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3164 } else { 3165 /* 3166 * Disable the Tx FIFO empty interrupt since there are 3167 * no more transactions that need to be queued right 3168 * now. This function is called from interrupt 3169 * handlers to queue more transactions as transfer 3170 * states change. 3171 */ 3172 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3173 gintmsk &= ~GINTSTS_NPTXFEMP; 3174 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3175 } 3176 } 3177 } 3178 3179 /** 3180 * dwc2_hcd_queue_transactions() - Processes the currently active host channels 3181 * and queues transactions for these channels to the DWC_otg controller. Called 3182 * from the HCD interrupt handler functions. 3183 * 3184 * @hsotg: The HCD state structure 3185 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic, 3186 * or both) 3187 * 3188 * Must be called with interrupt disabled and spinlock held 3189 */ 3190 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 3191 enum dwc2_transaction_type tr_type) 3192 { 3193 #ifdef DWC2_DEBUG_SOF 3194 dev_vdbg(hsotg->dev, "Queue Transactions\n"); 3195 #endif 3196 /* Process host channels associated with periodic transfers */ 3197 if (tr_type == DWC2_TRANSACTION_PERIODIC || 3198 tr_type == DWC2_TRANSACTION_ALL) 3199 dwc2_process_periodic_channels(hsotg); 3200 3201 /* Process host channels associated with non-periodic transfers */ 3202 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC || 3203 tr_type == DWC2_TRANSACTION_ALL) { 3204 if (!list_empty(&hsotg->non_periodic_sched_active)) { 3205 dwc2_process_non_periodic_channels(hsotg); 3206 } else { 3207 /* 3208 * Ensure NP Tx FIFO empty interrupt is disabled when 3209 * there are no non-periodic transfers to process 3210 */ 3211 u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3212 3213 gintmsk &= ~GINTSTS_NPTXFEMP; 3214 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3215 } 3216 } 3217 } 3218 3219 static void dwc2_conn_id_status_change(struct work_struct *work) 3220 { 3221 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 3222 wf_otg); 3223 u32 count = 0; 3224 u32 gotgctl; 3225 unsigned long flags; 3226 3227 dev_dbg(hsotg->dev, "%s()\n", __func__); 3228 3229 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 3230 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); 3231 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", 3232 !!(gotgctl & GOTGCTL_CONID_B)); 3233 3234 /* B-Device connector (Device Mode) */ 3235 if (gotgctl & GOTGCTL_CONID_B) { 3236 /* Wait for switch to device mode */ 3237 dev_dbg(hsotg->dev, "connId B\n"); 3238 while (!dwc2_is_device_mode(hsotg)) { 3239 dev_info(hsotg->dev, 3240 "Waiting for Peripheral Mode, Mode=%s\n", 3241 dwc2_is_host_mode(hsotg) ? "Host" : 3242 "Peripheral"); 3243 msleep(20); 3244 if (++count > 250) 3245 break; 3246 } 3247 if (count > 250) 3248 dev_err(hsotg->dev, 3249 "Connection id status change timed out\n"); 3250 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 3251 dwc2_core_init(hsotg, false); 3252 dwc2_enable_global_interrupts(hsotg); 3253 spin_lock_irqsave(&hsotg->lock, flags); 3254 dwc2_hsotg_core_init_disconnected(hsotg, false); 3255 spin_unlock_irqrestore(&hsotg->lock, flags); 3256 dwc2_hsotg_core_connect(hsotg); 3257 } else { 3258 /* A-Device connector (Host Mode) */ 3259 dev_dbg(hsotg->dev, "connId A\n"); 3260 while (!dwc2_is_host_mode(hsotg)) { 3261 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n", 3262 dwc2_is_host_mode(hsotg) ? 3263 "Host" : "Peripheral"); 3264 msleep(20); 3265 if (++count > 250) 3266 break; 3267 } 3268 if (count > 250) 3269 dev_err(hsotg->dev, 3270 "Connection id status change timed out\n"); 3271 hsotg->op_state = OTG_STATE_A_HOST; 3272 3273 /* Initialize the Core for Host mode */ 3274 dwc2_core_init(hsotg, false); 3275 dwc2_enable_global_interrupts(hsotg); 3276 dwc2_hcd_start(hsotg); 3277 } 3278 } 3279 3280 static void dwc2_wakeup_detected(unsigned long data) 3281 { 3282 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data; 3283 u32 hprt0; 3284 3285 dev_dbg(hsotg->dev, "%s()\n", __func__); 3286 3287 /* 3288 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms 3289 * so that OPT tests pass with all PHYs.) 3290 */ 3291 hprt0 = dwc2_read_hprt0(hsotg); 3292 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); 3293 hprt0 &= ~HPRT0_RES; 3294 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3295 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", 3296 dwc2_readl(hsotg->regs + HPRT0)); 3297 3298 dwc2_hcd_rem_wakeup(hsotg); 3299 hsotg->bus_suspended = 0; 3300 3301 /* Change to L0 state */ 3302 hsotg->lx_state = DWC2_L0; 3303 } 3304 3305 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg) 3306 { 3307 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 3308 3309 return hcd->self.b_hnp_enable; 3310 } 3311 3312 /* Must NOT be called with interrupt disabled or spinlock held */ 3313 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 3314 { 3315 unsigned long flags; 3316 u32 hprt0; 3317 u32 pcgctl; 3318 u32 gotgctl; 3319 3320 dev_dbg(hsotg->dev, "%s()\n", __func__); 3321 3322 spin_lock_irqsave(&hsotg->lock, flags); 3323 3324 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { 3325 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 3326 gotgctl |= GOTGCTL_HSTSETHNPEN; 3327 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); 3328 hsotg->op_state = OTG_STATE_A_SUSPEND; 3329 } 3330 3331 hprt0 = dwc2_read_hprt0(hsotg); 3332 hprt0 |= HPRT0_SUSP; 3333 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3334 3335 hsotg->bus_suspended = 1; 3336 3337 /* 3338 * If hibernation is supported, Phy clock will be suspended 3339 * after registers are backuped. 3340 */ 3341 if (!hsotg->params.hibernation) { 3342 /* Suspend the Phy Clock */ 3343 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3344 pcgctl |= PCGCTL_STOPPCLK; 3345 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3346 udelay(10); 3347 } 3348 3349 /* For HNP the bus must be suspended for at least 200ms */ 3350 if (dwc2_host_is_b_hnp_enabled(hsotg)) { 3351 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3352 pcgctl &= ~PCGCTL_STOPPCLK; 3353 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3354 3355 spin_unlock_irqrestore(&hsotg->lock, flags); 3356 3357 msleep(200); 3358 } else { 3359 spin_unlock_irqrestore(&hsotg->lock, flags); 3360 } 3361 } 3362 3363 /* Must NOT be called with interrupt disabled or spinlock held */ 3364 static void dwc2_port_resume(struct dwc2_hsotg *hsotg) 3365 { 3366 unsigned long flags; 3367 u32 hprt0; 3368 u32 pcgctl; 3369 3370 spin_lock_irqsave(&hsotg->lock, flags); 3371 3372 /* 3373 * If hibernation is supported, Phy clock is already resumed 3374 * after registers restore. 3375 */ 3376 if (!hsotg->params.hibernation) { 3377 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3378 pcgctl &= ~PCGCTL_STOPPCLK; 3379 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3380 spin_unlock_irqrestore(&hsotg->lock, flags); 3381 msleep(20); 3382 spin_lock_irqsave(&hsotg->lock, flags); 3383 } 3384 3385 hprt0 = dwc2_read_hprt0(hsotg); 3386 hprt0 |= HPRT0_RES; 3387 hprt0 &= ~HPRT0_SUSP; 3388 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3389 spin_unlock_irqrestore(&hsotg->lock, flags); 3390 3391 msleep(USB_RESUME_TIMEOUT); 3392 3393 spin_lock_irqsave(&hsotg->lock, flags); 3394 hprt0 = dwc2_read_hprt0(hsotg); 3395 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP); 3396 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3397 hsotg->bus_suspended = 0; 3398 spin_unlock_irqrestore(&hsotg->lock, flags); 3399 } 3400 3401 /* Handles hub class-specific requests */ 3402 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, 3403 u16 wvalue, u16 windex, char *buf, u16 wlength) 3404 { 3405 struct usb_hub_descriptor *hub_desc; 3406 int retval = 0; 3407 u32 hprt0; 3408 u32 port_status; 3409 u32 speed; 3410 u32 pcgctl; 3411 3412 switch (typereq) { 3413 case ClearHubFeature: 3414 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue); 3415 3416 switch (wvalue) { 3417 case C_HUB_LOCAL_POWER: 3418 case C_HUB_OVER_CURRENT: 3419 /* Nothing required here */ 3420 break; 3421 3422 default: 3423 retval = -EINVAL; 3424 dev_err(hsotg->dev, 3425 "ClearHubFeature request %1xh unknown\n", 3426 wvalue); 3427 } 3428 break; 3429 3430 case ClearPortFeature: 3431 if (wvalue != USB_PORT_FEAT_L1) 3432 if (!windex || windex > 1) 3433 goto error; 3434 switch (wvalue) { 3435 case USB_PORT_FEAT_ENABLE: 3436 dev_dbg(hsotg->dev, 3437 "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); 3438 hprt0 = dwc2_read_hprt0(hsotg); 3439 hprt0 |= HPRT0_ENA; 3440 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3441 break; 3442 3443 case USB_PORT_FEAT_SUSPEND: 3444 dev_dbg(hsotg->dev, 3445 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); 3446 3447 if (hsotg->bus_suspended) 3448 dwc2_port_resume(hsotg); 3449 break; 3450 3451 case USB_PORT_FEAT_POWER: 3452 dev_dbg(hsotg->dev, 3453 "ClearPortFeature USB_PORT_FEAT_POWER\n"); 3454 hprt0 = dwc2_read_hprt0(hsotg); 3455 hprt0 &= ~HPRT0_PWR; 3456 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3457 break; 3458 3459 case USB_PORT_FEAT_INDICATOR: 3460 dev_dbg(hsotg->dev, 3461 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); 3462 /* Port indicator not supported */ 3463 break; 3464 3465 case USB_PORT_FEAT_C_CONNECTION: 3466 /* 3467 * Clears driver's internal Connect Status Change flag 3468 */ 3469 dev_dbg(hsotg->dev, 3470 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); 3471 hsotg->flags.b.port_connect_status_change = 0; 3472 break; 3473 3474 case USB_PORT_FEAT_C_RESET: 3475 /* Clears driver's internal Port Reset Change flag */ 3476 dev_dbg(hsotg->dev, 3477 "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); 3478 hsotg->flags.b.port_reset_change = 0; 3479 break; 3480 3481 case USB_PORT_FEAT_C_ENABLE: 3482 /* 3483 * Clears the driver's internal Port Enable/Disable 3484 * Change flag 3485 */ 3486 dev_dbg(hsotg->dev, 3487 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); 3488 hsotg->flags.b.port_enable_change = 0; 3489 break; 3490 3491 case USB_PORT_FEAT_C_SUSPEND: 3492 /* 3493 * Clears the driver's internal Port Suspend Change 3494 * flag, which is set when resume signaling on the host 3495 * port is complete 3496 */ 3497 dev_dbg(hsotg->dev, 3498 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); 3499 hsotg->flags.b.port_suspend_change = 0; 3500 break; 3501 3502 case USB_PORT_FEAT_C_PORT_L1: 3503 dev_dbg(hsotg->dev, 3504 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n"); 3505 hsotg->flags.b.port_l1_change = 0; 3506 break; 3507 3508 case USB_PORT_FEAT_C_OVER_CURRENT: 3509 dev_dbg(hsotg->dev, 3510 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); 3511 hsotg->flags.b.port_over_current_change = 0; 3512 break; 3513 3514 default: 3515 retval = -EINVAL; 3516 dev_err(hsotg->dev, 3517 "ClearPortFeature request %1xh unknown or unsupported\n", 3518 wvalue); 3519 } 3520 break; 3521 3522 case GetHubDescriptor: 3523 dev_dbg(hsotg->dev, "GetHubDescriptor\n"); 3524 hub_desc = (struct usb_hub_descriptor *)buf; 3525 hub_desc->bDescLength = 9; 3526 hub_desc->bDescriptorType = USB_DT_HUB; 3527 hub_desc->bNbrPorts = 1; 3528 hub_desc->wHubCharacteristics = 3529 cpu_to_le16(HUB_CHAR_COMMON_LPSM | 3530 HUB_CHAR_INDV_PORT_OCPM); 3531 hub_desc->bPwrOn2PwrGood = 1; 3532 hub_desc->bHubContrCurrent = 0; 3533 hub_desc->u.hs.DeviceRemovable[0] = 0; 3534 hub_desc->u.hs.DeviceRemovable[1] = 0xff; 3535 break; 3536 3537 case GetHubStatus: 3538 dev_dbg(hsotg->dev, "GetHubStatus\n"); 3539 memset(buf, 0, 4); 3540 break; 3541 3542 case GetPortStatus: 3543 dev_vdbg(hsotg->dev, 3544 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex, 3545 hsotg->flags.d32); 3546 if (!windex || windex > 1) 3547 goto error; 3548 3549 port_status = 0; 3550 if (hsotg->flags.b.port_connect_status_change) 3551 port_status |= USB_PORT_STAT_C_CONNECTION << 16; 3552 if (hsotg->flags.b.port_enable_change) 3553 port_status |= USB_PORT_STAT_C_ENABLE << 16; 3554 if (hsotg->flags.b.port_suspend_change) 3555 port_status |= USB_PORT_STAT_C_SUSPEND << 16; 3556 if (hsotg->flags.b.port_l1_change) 3557 port_status |= USB_PORT_STAT_C_L1 << 16; 3558 if (hsotg->flags.b.port_reset_change) 3559 port_status |= USB_PORT_STAT_C_RESET << 16; 3560 if (hsotg->flags.b.port_over_current_change) { 3561 dev_warn(hsotg->dev, "Overcurrent change detected\n"); 3562 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16; 3563 } 3564 3565 if (!hsotg->flags.b.port_connect_status) { 3566 /* 3567 * The port is disconnected, which means the core is 3568 * either in device mode or it soon will be. Just 3569 * return 0's for the remainder of the port status 3570 * since the port register can't be read if the core 3571 * is in device mode. 3572 */ 3573 *(__le32 *)buf = cpu_to_le32(port_status); 3574 break; 3575 } 3576 3577 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 3578 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); 3579 3580 if (hprt0 & HPRT0_CONNSTS) 3581 port_status |= USB_PORT_STAT_CONNECTION; 3582 if (hprt0 & HPRT0_ENA) 3583 port_status |= USB_PORT_STAT_ENABLE; 3584 if (hprt0 & HPRT0_SUSP) 3585 port_status |= USB_PORT_STAT_SUSPEND; 3586 if (hprt0 & HPRT0_OVRCURRACT) 3587 port_status |= USB_PORT_STAT_OVERCURRENT; 3588 if (hprt0 & HPRT0_RST) 3589 port_status |= USB_PORT_STAT_RESET; 3590 if (hprt0 & HPRT0_PWR) 3591 port_status |= USB_PORT_STAT_POWER; 3592 3593 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 3594 if (speed == HPRT0_SPD_HIGH_SPEED) 3595 port_status |= USB_PORT_STAT_HIGH_SPEED; 3596 else if (speed == HPRT0_SPD_LOW_SPEED) 3597 port_status |= USB_PORT_STAT_LOW_SPEED; 3598 3599 if (hprt0 & HPRT0_TSTCTL_MASK) 3600 port_status |= USB_PORT_STAT_TEST; 3601 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ 3602 3603 if (hsotg->params.dma_desc_fs_enable) { 3604 /* 3605 * Enable descriptor DMA only if a full speed 3606 * device is connected. 3607 */ 3608 if (hsotg->new_connection && 3609 ((port_status & 3610 (USB_PORT_STAT_CONNECTION | 3611 USB_PORT_STAT_HIGH_SPEED | 3612 USB_PORT_STAT_LOW_SPEED)) == 3613 USB_PORT_STAT_CONNECTION)) { 3614 u32 hcfg; 3615 3616 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n"); 3617 hsotg->params.dma_desc_enable = 1; 3618 hcfg = dwc2_readl(hsotg->regs + HCFG); 3619 hcfg |= HCFG_DESCDMA; 3620 dwc2_writel(hcfg, hsotg->regs + HCFG); 3621 hsotg->new_connection = false; 3622 } 3623 } 3624 3625 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status); 3626 *(__le32 *)buf = cpu_to_le32(port_status); 3627 break; 3628 3629 case SetHubFeature: 3630 dev_dbg(hsotg->dev, "SetHubFeature\n"); 3631 /* No HUB features supported */ 3632 break; 3633 3634 case SetPortFeature: 3635 dev_dbg(hsotg->dev, "SetPortFeature\n"); 3636 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1)) 3637 goto error; 3638 3639 if (!hsotg->flags.b.port_connect_status) { 3640 /* 3641 * The port is disconnected, which means the core is 3642 * either in device mode or it soon will be. Just 3643 * return without doing anything since the port 3644 * register can't be written if the core is in device 3645 * mode. 3646 */ 3647 break; 3648 } 3649 3650 switch (wvalue) { 3651 case USB_PORT_FEAT_SUSPEND: 3652 dev_dbg(hsotg->dev, 3653 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); 3654 if (windex != hsotg->otg_port) 3655 goto error; 3656 dwc2_port_suspend(hsotg, windex); 3657 break; 3658 3659 case USB_PORT_FEAT_POWER: 3660 dev_dbg(hsotg->dev, 3661 "SetPortFeature - USB_PORT_FEAT_POWER\n"); 3662 hprt0 = dwc2_read_hprt0(hsotg); 3663 hprt0 |= HPRT0_PWR; 3664 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3665 break; 3666 3667 case USB_PORT_FEAT_RESET: 3668 hprt0 = dwc2_read_hprt0(hsotg); 3669 dev_dbg(hsotg->dev, 3670 "SetPortFeature - USB_PORT_FEAT_RESET\n"); 3671 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3672 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); 3673 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3674 /* ??? Original driver does this */ 3675 dwc2_writel(0, hsotg->regs + PCGCTL); 3676 3677 hprt0 = dwc2_read_hprt0(hsotg); 3678 /* Clear suspend bit if resetting from suspend state */ 3679 hprt0 &= ~HPRT0_SUSP; 3680 3681 /* 3682 * When B-Host the Port reset bit is set in the Start 3683 * HCD Callback function, so that the reset is started 3684 * within 1ms of the HNP success interrupt 3685 */ 3686 if (!dwc2_hcd_is_b_host(hsotg)) { 3687 hprt0 |= HPRT0_PWR | HPRT0_RST; 3688 dev_dbg(hsotg->dev, 3689 "In host mode, hprt0=%08x\n", hprt0); 3690 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3691 } 3692 3693 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ 3694 msleep(50); 3695 hprt0 &= ~HPRT0_RST; 3696 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3697 hsotg->lx_state = DWC2_L0; /* Now back to On state */ 3698 break; 3699 3700 case USB_PORT_FEAT_INDICATOR: 3701 dev_dbg(hsotg->dev, 3702 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); 3703 /* Not supported */ 3704 break; 3705 3706 case USB_PORT_FEAT_TEST: 3707 hprt0 = dwc2_read_hprt0(hsotg); 3708 dev_dbg(hsotg->dev, 3709 "SetPortFeature - USB_PORT_FEAT_TEST\n"); 3710 hprt0 &= ~HPRT0_TSTCTL_MASK; 3711 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT; 3712 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3713 break; 3714 3715 default: 3716 retval = -EINVAL; 3717 dev_err(hsotg->dev, 3718 "SetPortFeature %1xh unknown or unsupported\n", 3719 wvalue); 3720 break; 3721 } 3722 break; 3723 3724 default: 3725 error: 3726 retval = -EINVAL; 3727 dev_dbg(hsotg->dev, 3728 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n", 3729 typereq, windex, wvalue); 3730 break; 3731 } 3732 3733 return retval; 3734 } 3735 3736 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port) 3737 { 3738 int retval; 3739 3740 if (port != 1) 3741 return -EINVAL; 3742 3743 retval = (hsotg->flags.b.port_connect_status_change || 3744 hsotg->flags.b.port_reset_change || 3745 hsotg->flags.b.port_enable_change || 3746 hsotg->flags.b.port_suspend_change || 3747 hsotg->flags.b.port_over_current_change); 3748 3749 if (retval) { 3750 dev_dbg(hsotg->dev, 3751 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n"); 3752 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n", 3753 hsotg->flags.b.port_connect_status_change); 3754 dev_dbg(hsotg->dev, " port_reset_change: %d\n", 3755 hsotg->flags.b.port_reset_change); 3756 dev_dbg(hsotg->dev, " port_enable_change: %d\n", 3757 hsotg->flags.b.port_enable_change); 3758 dev_dbg(hsotg->dev, " port_suspend_change: %d\n", 3759 hsotg->flags.b.port_suspend_change); 3760 dev_dbg(hsotg->dev, " port_over_current_change: %d\n", 3761 hsotg->flags.b.port_over_current_change); 3762 } 3763 3764 return retval; 3765 } 3766 3767 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 3768 { 3769 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); 3770 3771 #ifdef DWC2_DEBUG_SOF 3772 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", 3773 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT); 3774 #endif 3775 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 3776 } 3777 3778 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us) 3779 { 3780 u32 hprt = dwc2_readl(hsotg->regs + HPRT0); 3781 u32 hfir = dwc2_readl(hsotg->regs + HFIR); 3782 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); 3783 unsigned int us_per_frame; 3784 unsigned int frame_number; 3785 unsigned int remaining; 3786 unsigned int interval; 3787 unsigned int phy_clks; 3788 3789 /* High speed has 125 us per (micro) frame; others are 1 ms per */ 3790 us_per_frame = (hprt & HPRT0_SPD_MASK) ? 1000 : 125; 3791 3792 /* Extract fields */ 3793 frame_number = (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 3794 remaining = (hfnum & HFNUM_FRREM_MASK) >> HFNUM_FRREM_SHIFT; 3795 interval = (hfir & HFIR_FRINT_MASK) >> HFIR_FRINT_SHIFT; 3796 3797 /* 3798 * Number of phy clocks since the last tick of the frame number after 3799 * "us" has passed. 3800 */ 3801 phy_clks = (interval - remaining) + 3802 DIV_ROUND_UP(interval * us, us_per_frame); 3803 3804 return dwc2_frame_num_inc(frame_number, phy_clks / interval); 3805 } 3806 3807 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg) 3808 { 3809 return hsotg->op_state == OTG_STATE_B_HOST; 3810 } 3811 3812 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg, 3813 int iso_desc_count, 3814 gfp_t mem_flags) 3815 { 3816 struct dwc2_hcd_urb *urb; 3817 u32 size = sizeof(*urb) + iso_desc_count * 3818 sizeof(struct dwc2_hcd_iso_packet_desc); 3819 3820 urb = kzalloc(size, mem_flags); 3821 if (urb) 3822 urb->packet_count = iso_desc_count; 3823 return urb; 3824 } 3825 3826 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg, 3827 struct dwc2_hcd_urb *urb, u8 dev_addr, 3828 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps) 3829 { 3830 if (dbg_perio() || 3831 ep_type == USB_ENDPOINT_XFER_BULK || 3832 ep_type == USB_ENDPOINT_XFER_CONTROL) 3833 dev_vdbg(hsotg->dev, 3834 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n", 3835 dev_addr, ep_num, ep_dir, ep_type, mps); 3836 urb->pipe_info.dev_addr = dev_addr; 3837 urb->pipe_info.ep_num = ep_num; 3838 urb->pipe_info.pipe_type = ep_type; 3839 urb->pipe_info.pipe_dir = ep_dir; 3840 urb->pipe_info.mps = mps; 3841 } 3842 3843 /* 3844 * NOTE: This function will be removed once the peripheral controller code 3845 * is integrated and the driver is stable 3846 */ 3847 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg) 3848 { 3849 #ifdef DEBUG 3850 struct dwc2_host_chan *chan; 3851 struct dwc2_hcd_urb *urb; 3852 struct dwc2_qtd *qtd; 3853 int num_channels; 3854 u32 np_tx_status; 3855 u32 p_tx_status; 3856 int i; 3857 3858 num_channels = hsotg->params.host_channels; 3859 dev_dbg(hsotg->dev, "\n"); 3860 dev_dbg(hsotg->dev, 3861 "************************************************************\n"); 3862 dev_dbg(hsotg->dev, "HCD State:\n"); 3863 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels); 3864 3865 for (i = 0; i < num_channels; i++) { 3866 chan = hsotg->hc_ptr_array[i]; 3867 dev_dbg(hsotg->dev, " Channel %d:\n", i); 3868 dev_dbg(hsotg->dev, 3869 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 3870 chan->dev_addr, chan->ep_num, chan->ep_is_in); 3871 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed); 3872 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 3873 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 3874 dev_dbg(hsotg->dev, " data_pid_start: %d\n", 3875 chan->data_pid_start); 3876 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count); 3877 dev_dbg(hsotg->dev, " xfer_started: %d\n", 3878 chan->xfer_started); 3879 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 3880 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 3881 (unsigned long)chan->xfer_dma); 3882 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 3883 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count); 3884 dev_dbg(hsotg->dev, " halt_on_queue: %d\n", 3885 chan->halt_on_queue); 3886 dev_dbg(hsotg->dev, " halt_pending: %d\n", 3887 chan->halt_pending); 3888 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 3889 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split); 3890 dev_dbg(hsotg->dev, " complete_split: %d\n", 3891 chan->complete_split); 3892 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr); 3893 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port); 3894 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos); 3895 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests); 3896 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 3897 3898 if (chan->xfer_started) { 3899 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk; 3900 3901 hfnum = dwc2_readl(hsotg->regs + HFNUM); 3902 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 3903 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i)); 3904 hcint = dwc2_readl(hsotg->regs + HCINT(i)); 3905 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i)); 3906 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum); 3907 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar); 3908 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz); 3909 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint); 3910 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk); 3911 } 3912 3913 if (!(chan->xfer_started && chan->qh)) 3914 continue; 3915 3916 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) { 3917 if (!qtd->in_process) 3918 break; 3919 urb = qtd->urb; 3920 dev_dbg(hsotg->dev, " URB Info:\n"); 3921 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n", 3922 qtd, urb); 3923 if (urb) { 3924 dev_dbg(hsotg->dev, 3925 " Dev: %d, EP: %d %s\n", 3926 dwc2_hcd_get_dev_addr(&urb->pipe_info), 3927 dwc2_hcd_get_ep_num(&urb->pipe_info), 3928 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 3929 "IN" : "OUT"); 3930 dev_dbg(hsotg->dev, 3931 " Max packet size: %d\n", 3932 dwc2_hcd_get_mps(&urb->pipe_info)); 3933 dev_dbg(hsotg->dev, 3934 " transfer_buffer: %p\n", 3935 urb->buf); 3936 dev_dbg(hsotg->dev, 3937 " transfer_dma: %08lx\n", 3938 (unsigned long)urb->dma); 3939 dev_dbg(hsotg->dev, 3940 " transfer_buffer_length: %d\n", 3941 urb->length); 3942 dev_dbg(hsotg->dev, " actual_length: %d\n", 3943 urb->actual_length); 3944 } 3945 } 3946 } 3947 3948 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n", 3949 hsotg->non_periodic_channels); 3950 dev_dbg(hsotg->dev, " periodic_channels: %d\n", 3951 hsotg->periodic_channels); 3952 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); 3953 np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3954 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", 3955 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 3956 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", 3957 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 3958 p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 3959 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", 3960 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 3961 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", 3962 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 3963 dwc2_hcd_dump_frrem(hsotg); 3964 dwc2_dump_global_registers(hsotg); 3965 dwc2_dump_host_registers(hsotg); 3966 dev_dbg(hsotg->dev, 3967 "************************************************************\n"); 3968 dev_dbg(hsotg->dev, "\n"); 3969 #endif 3970 } 3971 3972 /* 3973 * NOTE: This function will be removed once the peripheral controller code 3974 * is integrated and the driver is stable 3975 */ 3976 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg) 3977 { 3978 #ifdef DWC2_DUMP_FRREM 3979 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n"); 3980 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 3981 hsotg->frrem_samples, hsotg->frrem_accum, 3982 hsotg->frrem_samples > 0 ? 3983 hsotg->frrem_accum / hsotg->frrem_samples : 0); 3984 dev_dbg(hsotg->dev, "\n"); 3985 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n"); 3986 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 3987 hsotg->hfnum_7_samples, 3988 hsotg->hfnum_7_frrem_accum, 3989 hsotg->hfnum_7_samples > 0 ? 3990 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0); 3991 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n"); 3992 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 3993 hsotg->hfnum_0_samples, 3994 hsotg->hfnum_0_frrem_accum, 3995 hsotg->hfnum_0_samples > 0 ? 3996 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0); 3997 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n"); 3998 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 3999 hsotg->hfnum_other_samples, 4000 hsotg->hfnum_other_frrem_accum, 4001 hsotg->hfnum_other_samples > 0 ? 4002 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples : 4003 0); 4004 dev_dbg(hsotg->dev, "\n"); 4005 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n"); 4006 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4007 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a, 4008 hsotg->hfnum_7_samples_a > 0 ? 4009 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0); 4010 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n"); 4011 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4012 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a, 4013 hsotg->hfnum_0_samples_a > 0 ? 4014 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0); 4015 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n"); 4016 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4017 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a, 4018 hsotg->hfnum_other_samples_a > 0 ? 4019 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a 4020 : 0); 4021 dev_dbg(hsotg->dev, "\n"); 4022 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n"); 4023 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4024 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b, 4025 hsotg->hfnum_7_samples_b > 0 ? 4026 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0); 4027 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n"); 4028 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4029 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b, 4030 (hsotg->hfnum_0_samples_b > 0) ? 4031 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0); 4032 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n"); 4033 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4034 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b, 4035 (hsotg->hfnum_other_samples_b > 0) ? 4036 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b 4037 : 0); 4038 #endif 4039 } 4040 4041 struct wrapper_priv_data { 4042 struct dwc2_hsotg *hsotg; 4043 }; 4044 4045 /* Gets the dwc2_hsotg from a usb_hcd */ 4046 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd) 4047 { 4048 struct wrapper_priv_data *p; 4049 4050 p = (struct wrapper_priv_data *) &hcd->hcd_priv; 4051 return p->hsotg; 4052 } 4053 4054 /** 4055 * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context 4056 * 4057 * This will get the dwc2_tt structure (and ttport) associated with the given 4058 * context (which is really just a struct urb pointer). 4059 * 4060 * The first time this is called for a given TT we allocate memory for our 4061 * structure. When everyone is done and has called dwc2_host_put_tt_info() 4062 * then the refcount for the structure will go to 0 and we'll free it. 4063 * 4064 * @hsotg: The HCD state structure for the DWC OTG controller. 4065 * @qh: The QH structure. 4066 * @context: The priv pointer from a struct dwc2_hcd_urb. 4067 * @mem_flags: Flags for allocating memory. 4068 * @ttport: We'll return this device's port number here. That's used to 4069 * reference into the bitmap if we're on a multi_tt hub. 4070 * 4071 * Return: a pointer to a struct dwc2_tt. Don't forget to call 4072 * dwc2_host_put_tt_info()! Returns NULL upon memory alloc failure. 4073 */ 4074 4075 struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context, 4076 gfp_t mem_flags, int *ttport) 4077 { 4078 struct urb *urb = context; 4079 struct dwc2_tt *dwc_tt = NULL; 4080 4081 if (urb->dev->tt) { 4082 *ttport = urb->dev->ttport; 4083 4084 dwc_tt = urb->dev->tt->hcpriv; 4085 if (dwc_tt == NULL) { 4086 size_t bitmap_size; 4087 4088 /* 4089 * For single_tt we need one schedule. For multi_tt 4090 * we need one per port. 4091 */ 4092 bitmap_size = DWC2_ELEMENTS_PER_LS_BITMAP * 4093 sizeof(dwc_tt->periodic_bitmaps[0]); 4094 if (urb->dev->tt->multi) 4095 bitmap_size *= urb->dev->tt->hub->maxchild; 4096 4097 dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size, 4098 mem_flags); 4099 if (dwc_tt == NULL) 4100 return NULL; 4101 4102 dwc_tt->usb_tt = urb->dev->tt; 4103 dwc_tt->usb_tt->hcpriv = dwc_tt; 4104 } 4105 4106 dwc_tt->refcount++; 4107 } 4108 4109 return dwc_tt; 4110 } 4111 4112 /** 4113 * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info() 4114 * 4115 * Frees resources allocated by dwc2_host_get_tt_info() if all current holders 4116 * of the structure are done. 4117 * 4118 * It's OK to call this with NULL. 4119 * 4120 * @hsotg: The HCD state structure for the DWC OTG controller. 4121 * @dwc_tt: The pointer returned by dwc2_host_get_tt_info. 4122 */ 4123 void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt) 4124 { 4125 /* Model kfree and make put of NULL a no-op */ 4126 if (dwc_tt == NULL) 4127 return; 4128 4129 WARN_ON(dwc_tt->refcount < 1); 4130 4131 dwc_tt->refcount--; 4132 if (!dwc_tt->refcount) { 4133 dwc_tt->usb_tt->hcpriv = NULL; 4134 kfree(dwc_tt); 4135 } 4136 } 4137 4138 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context) 4139 { 4140 struct urb *urb = context; 4141 4142 return urb->dev->speed; 4143 } 4144 4145 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 4146 struct urb *urb) 4147 { 4148 struct usb_bus *bus = hcd_to_bus(hcd); 4149 4150 if (urb->interval) 4151 bus->bandwidth_allocated += bw / urb->interval; 4152 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 4153 bus->bandwidth_isoc_reqs++; 4154 else 4155 bus->bandwidth_int_reqs++; 4156 } 4157 4158 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 4159 struct urb *urb) 4160 { 4161 struct usb_bus *bus = hcd_to_bus(hcd); 4162 4163 if (urb->interval) 4164 bus->bandwidth_allocated -= bw / urb->interval; 4165 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 4166 bus->bandwidth_isoc_reqs--; 4167 else 4168 bus->bandwidth_int_reqs--; 4169 } 4170 4171 /* 4172 * Sets the final status of an URB and returns it to the upper layer. Any 4173 * required cleanup of the URB is performed. 4174 * 4175 * Must be called with interrupt disabled and spinlock held 4176 */ 4177 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 4178 int status) 4179 { 4180 struct urb *urb; 4181 int i; 4182 4183 if (!qtd) { 4184 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__); 4185 return; 4186 } 4187 4188 if (!qtd->urb) { 4189 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__); 4190 return; 4191 } 4192 4193 urb = qtd->urb->priv; 4194 if (!urb) { 4195 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__); 4196 return; 4197 } 4198 4199 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb); 4200 4201 if (dbg_urb(urb)) 4202 dev_vdbg(hsotg->dev, 4203 "%s: urb %p device %d ep %d-%s status %d actual %d\n", 4204 __func__, urb, usb_pipedevice(urb->pipe), 4205 usb_pipeendpoint(urb->pipe), 4206 usb_pipein(urb->pipe) ? "IN" : "OUT", status, 4207 urb->actual_length); 4208 4209 4210 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 4211 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb); 4212 for (i = 0; i < urb->number_of_packets; ++i) { 4213 urb->iso_frame_desc[i].actual_length = 4214 dwc2_hcd_urb_get_iso_desc_actual_length( 4215 qtd->urb, i); 4216 urb->iso_frame_desc[i].status = 4217 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i); 4218 } 4219 } 4220 4221 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) { 4222 for (i = 0; i < urb->number_of_packets; i++) 4223 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n", 4224 i, urb->iso_frame_desc[i].status); 4225 } 4226 4227 urb->status = status; 4228 if (!status) { 4229 if ((urb->transfer_flags & URB_SHORT_NOT_OK) && 4230 urb->actual_length < urb->transfer_buffer_length) 4231 urb->status = -EREMOTEIO; 4232 } 4233 4234 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 4235 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 4236 struct usb_host_endpoint *ep = urb->ep; 4237 4238 if (ep) 4239 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg), 4240 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 4241 urb); 4242 } 4243 4244 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb); 4245 urb->hcpriv = NULL; 4246 kfree(qtd->urb); 4247 qtd->urb = NULL; 4248 4249 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status); 4250 } 4251 4252 /* 4253 * Work queue function for starting the HCD when A-Cable is connected 4254 */ 4255 static void dwc2_hcd_start_func(struct work_struct *work) 4256 { 4257 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 4258 start_work.work); 4259 4260 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg); 4261 dwc2_host_start(hsotg); 4262 } 4263 4264 /* 4265 * Reset work queue function 4266 */ 4267 static void dwc2_hcd_reset_func(struct work_struct *work) 4268 { 4269 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 4270 reset_work.work); 4271 unsigned long flags; 4272 u32 hprt0; 4273 4274 dev_dbg(hsotg->dev, "USB RESET function called\n"); 4275 4276 spin_lock_irqsave(&hsotg->lock, flags); 4277 4278 hprt0 = dwc2_read_hprt0(hsotg); 4279 hprt0 &= ~HPRT0_RST; 4280 dwc2_writel(hprt0, hsotg->regs + HPRT0); 4281 hsotg->flags.b.port_reset_change = 1; 4282 4283 spin_unlock_irqrestore(&hsotg->lock, flags); 4284 } 4285 4286 /* 4287 * ========================================================================= 4288 * Linux HC Driver Functions 4289 * ========================================================================= 4290 */ 4291 4292 /* 4293 * Initializes the DWC_otg controller and its root hub and prepares it for host 4294 * mode operation. Activates the root port. Returns 0 on success and a negative 4295 * error code on failure. 4296 */ 4297 static int _dwc2_hcd_start(struct usb_hcd *hcd) 4298 { 4299 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4300 struct usb_bus *bus = hcd_to_bus(hcd); 4301 unsigned long flags; 4302 4303 dev_dbg(hsotg->dev, "DWC OTG HCD START\n"); 4304 4305 spin_lock_irqsave(&hsotg->lock, flags); 4306 hsotg->lx_state = DWC2_L0; 4307 hcd->state = HC_STATE_RUNNING; 4308 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4309 4310 if (dwc2_is_device_mode(hsotg)) { 4311 spin_unlock_irqrestore(&hsotg->lock, flags); 4312 return 0; /* why 0 ?? */ 4313 } 4314 4315 dwc2_hcd_reinit(hsotg); 4316 4317 /* Initialize and connect root hub if one is not already attached */ 4318 if (bus->root_hub) { 4319 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n"); 4320 /* Inform the HUB driver to resume */ 4321 usb_hcd_resume_root_hub(hcd); 4322 } 4323 4324 spin_unlock_irqrestore(&hsotg->lock, flags); 4325 return 0; 4326 } 4327 4328 /* 4329 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are 4330 * stopped. 4331 */ 4332 static void _dwc2_hcd_stop(struct usb_hcd *hcd) 4333 { 4334 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4335 unsigned long flags; 4336 4337 /* Turn off all host-specific interrupts */ 4338 dwc2_disable_host_interrupts(hsotg); 4339 4340 /* Wait for interrupt processing to finish */ 4341 synchronize_irq(hcd->irq); 4342 4343 spin_lock_irqsave(&hsotg->lock, flags); 4344 /* Ensure hcd is disconnected */ 4345 dwc2_hcd_disconnect(hsotg, true); 4346 dwc2_hcd_stop(hsotg); 4347 hsotg->lx_state = DWC2_L3; 4348 hcd->state = HC_STATE_HALT; 4349 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4350 spin_unlock_irqrestore(&hsotg->lock, flags); 4351 4352 usleep_range(1000, 3000); 4353 } 4354 4355 static int _dwc2_hcd_suspend(struct usb_hcd *hcd) 4356 { 4357 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4358 unsigned long flags; 4359 int ret = 0; 4360 u32 hprt0; 4361 4362 spin_lock_irqsave(&hsotg->lock, flags); 4363 4364 if (hsotg->lx_state != DWC2_L0) 4365 goto unlock; 4366 4367 if (!HCD_HW_ACCESSIBLE(hcd)) 4368 goto unlock; 4369 4370 if (!hsotg->params.hibernation) 4371 goto skip_power_saving; 4372 4373 /* 4374 * Drive USB suspend and disable port Power 4375 * if usb bus is not suspended. 4376 */ 4377 if (!hsotg->bus_suspended) { 4378 hprt0 = dwc2_read_hprt0(hsotg); 4379 hprt0 |= HPRT0_SUSP; 4380 hprt0 &= ~HPRT0_PWR; 4381 dwc2_writel(hprt0, hsotg->regs + HPRT0); 4382 } 4383 4384 /* Enter hibernation */ 4385 ret = dwc2_enter_hibernation(hsotg); 4386 if (ret) { 4387 if (ret != -ENOTSUPP) 4388 dev_err(hsotg->dev, 4389 "enter hibernation failed\n"); 4390 goto skip_power_saving; 4391 } 4392 4393 /* Ask phy to be suspended */ 4394 if (!IS_ERR_OR_NULL(hsotg->uphy)) { 4395 spin_unlock_irqrestore(&hsotg->lock, flags); 4396 usb_phy_set_suspend(hsotg->uphy, true); 4397 spin_lock_irqsave(&hsotg->lock, flags); 4398 } 4399 4400 /* After entering hibernation, hardware is no more accessible */ 4401 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4402 4403 skip_power_saving: 4404 hsotg->lx_state = DWC2_L2; 4405 unlock: 4406 spin_unlock_irqrestore(&hsotg->lock, flags); 4407 4408 return ret; 4409 } 4410 4411 static int _dwc2_hcd_resume(struct usb_hcd *hcd) 4412 { 4413 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4414 unsigned long flags; 4415 int ret = 0; 4416 4417 spin_lock_irqsave(&hsotg->lock, flags); 4418 4419 if (hsotg->lx_state != DWC2_L2) 4420 goto unlock; 4421 4422 if (!hsotg->params.hibernation) { 4423 hsotg->lx_state = DWC2_L0; 4424 goto unlock; 4425 } 4426 4427 /* 4428 * Set HW accessible bit before powering on the controller 4429 * since an interrupt may rise. 4430 */ 4431 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4432 4433 /* 4434 * Enable power if not already done. 4435 * This must not be spinlocked since duration 4436 * of this call is unknown. 4437 */ 4438 if (!IS_ERR_OR_NULL(hsotg->uphy)) { 4439 spin_unlock_irqrestore(&hsotg->lock, flags); 4440 usb_phy_set_suspend(hsotg->uphy, false); 4441 spin_lock_irqsave(&hsotg->lock, flags); 4442 } 4443 4444 /* Exit hibernation */ 4445 ret = dwc2_exit_hibernation(hsotg, true); 4446 if (ret && (ret != -ENOTSUPP)) 4447 dev_err(hsotg->dev, "exit hibernation failed\n"); 4448 4449 hsotg->lx_state = DWC2_L0; 4450 4451 spin_unlock_irqrestore(&hsotg->lock, flags); 4452 4453 if (hsotg->bus_suspended) { 4454 spin_lock_irqsave(&hsotg->lock, flags); 4455 hsotg->flags.b.port_suspend_change = 1; 4456 spin_unlock_irqrestore(&hsotg->lock, flags); 4457 dwc2_port_resume(hsotg); 4458 } else { 4459 /* Wait for controller to correctly update D+/D- level */ 4460 usleep_range(3000, 5000); 4461 4462 /* 4463 * Clear Port Enable and Port Status changes. 4464 * Enable Port Power. 4465 */ 4466 dwc2_writel(HPRT0_PWR | HPRT0_CONNDET | 4467 HPRT0_ENACHG, hsotg->regs + HPRT0); 4468 /* Wait for controller to detect Port Connect */ 4469 usleep_range(5000, 7000); 4470 } 4471 4472 return ret; 4473 unlock: 4474 spin_unlock_irqrestore(&hsotg->lock, flags); 4475 4476 return ret; 4477 } 4478 4479 /* Returns the current frame number */ 4480 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd) 4481 { 4482 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4483 4484 return dwc2_hcd_get_frame_number(hsotg); 4485 } 4486 4487 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb, 4488 char *fn_name) 4489 { 4490 #ifdef VERBOSE_DEBUG 4491 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4492 char *pipetype; 4493 char *speed; 4494 4495 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb); 4496 dev_vdbg(hsotg->dev, " Device address: %d\n", 4497 usb_pipedevice(urb->pipe)); 4498 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n", 4499 usb_pipeendpoint(urb->pipe), 4500 usb_pipein(urb->pipe) ? "IN" : "OUT"); 4501 4502 switch (usb_pipetype(urb->pipe)) { 4503 case PIPE_CONTROL: 4504 pipetype = "CONTROL"; 4505 break; 4506 case PIPE_BULK: 4507 pipetype = "BULK"; 4508 break; 4509 case PIPE_INTERRUPT: 4510 pipetype = "INTERRUPT"; 4511 break; 4512 case PIPE_ISOCHRONOUS: 4513 pipetype = "ISOCHRONOUS"; 4514 break; 4515 } 4516 4517 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype, 4518 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ? 4519 "IN" : "OUT"); 4520 4521 switch (urb->dev->speed) { 4522 case USB_SPEED_HIGH: 4523 speed = "HIGH"; 4524 break; 4525 case USB_SPEED_FULL: 4526 speed = "FULL"; 4527 break; 4528 case USB_SPEED_LOW: 4529 speed = "LOW"; 4530 break; 4531 default: 4532 speed = "UNKNOWN"; 4533 break; 4534 } 4535 4536 dev_vdbg(hsotg->dev, " Speed: %s\n", speed); 4537 dev_vdbg(hsotg->dev, " Max packet size: %d\n", 4538 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); 4539 dev_vdbg(hsotg->dev, " Data buffer length: %d\n", 4540 urb->transfer_buffer_length); 4541 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n", 4542 urb->transfer_buffer, (unsigned long)urb->transfer_dma); 4543 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n", 4544 urb->setup_packet, (unsigned long)urb->setup_dma); 4545 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval); 4546 4547 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 4548 int i; 4549 4550 for (i = 0; i < urb->number_of_packets; i++) { 4551 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i); 4552 dev_vdbg(hsotg->dev, " offset: %d, length %d\n", 4553 urb->iso_frame_desc[i].offset, 4554 urb->iso_frame_desc[i].length); 4555 } 4556 } 4557 #endif 4558 } 4559 4560 /* 4561 * Starts processing a USB transfer request specified by a USB Request Block 4562 * (URB). mem_flags indicates the type of memory allocation to use while 4563 * processing this URB. 4564 */ 4565 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, 4566 gfp_t mem_flags) 4567 { 4568 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4569 struct usb_host_endpoint *ep = urb->ep; 4570 struct dwc2_hcd_urb *dwc2_urb; 4571 int i; 4572 int retval; 4573 int alloc_bandwidth = 0; 4574 u8 ep_type = 0; 4575 u32 tflags = 0; 4576 void *buf; 4577 unsigned long flags; 4578 struct dwc2_qh *qh; 4579 bool qh_allocated = false; 4580 struct dwc2_qtd *qtd; 4581 4582 if (dbg_urb(urb)) { 4583 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n"); 4584 dwc2_dump_urb_info(hcd, urb, "urb_enqueue"); 4585 } 4586 4587 if (ep == NULL) 4588 return -EINVAL; 4589 4590 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 4591 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 4592 spin_lock_irqsave(&hsotg->lock, flags); 4593 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep)) 4594 alloc_bandwidth = 1; 4595 spin_unlock_irqrestore(&hsotg->lock, flags); 4596 } 4597 4598 switch (usb_pipetype(urb->pipe)) { 4599 case PIPE_CONTROL: 4600 ep_type = USB_ENDPOINT_XFER_CONTROL; 4601 break; 4602 case PIPE_ISOCHRONOUS: 4603 ep_type = USB_ENDPOINT_XFER_ISOC; 4604 break; 4605 case PIPE_BULK: 4606 ep_type = USB_ENDPOINT_XFER_BULK; 4607 break; 4608 case PIPE_INTERRUPT: 4609 ep_type = USB_ENDPOINT_XFER_INT; 4610 break; 4611 } 4612 4613 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets, 4614 mem_flags); 4615 if (!dwc2_urb) 4616 return -ENOMEM; 4617 4618 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe), 4619 usb_pipeendpoint(urb->pipe), ep_type, 4620 usb_pipein(urb->pipe), 4621 usb_maxpacket(urb->dev, urb->pipe, 4622 !(usb_pipein(urb->pipe)))); 4623 4624 buf = urb->transfer_buffer; 4625 4626 if (hcd->self.uses_dma) { 4627 if (!buf && (urb->transfer_dma & 3)) { 4628 dev_err(hsotg->dev, 4629 "%s: unaligned transfer with no transfer_buffer", 4630 __func__); 4631 retval = -EINVAL; 4632 goto fail0; 4633 } 4634 } 4635 4636 if (!(urb->transfer_flags & URB_NO_INTERRUPT)) 4637 tflags |= URB_GIVEBACK_ASAP; 4638 if (urb->transfer_flags & URB_ZERO_PACKET) 4639 tflags |= URB_SEND_ZERO_PACKET; 4640 4641 dwc2_urb->priv = urb; 4642 dwc2_urb->buf = buf; 4643 dwc2_urb->dma = urb->transfer_dma; 4644 dwc2_urb->length = urb->transfer_buffer_length; 4645 dwc2_urb->setup_packet = urb->setup_packet; 4646 dwc2_urb->setup_dma = urb->setup_dma; 4647 dwc2_urb->flags = tflags; 4648 dwc2_urb->interval = urb->interval; 4649 dwc2_urb->status = -EINPROGRESS; 4650 4651 for (i = 0; i < urb->number_of_packets; ++i) 4652 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, 4653 urb->iso_frame_desc[i].offset, 4654 urb->iso_frame_desc[i].length); 4655 4656 urb->hcpriv = dwc2_urb; 4657 qh = (struct dwc2_qh *) ep->hcpriv; 4658 /* Create QH for the endpoint if it doesn't exist */ 4659 if (!qh) { 4660 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags); 4661 if (!qh) { 4662 retval = -ENOMEM; 4663 goto fail0; 4664 } 4665 ep->hcpriv = qh; 4666 qh_allocated = true; 4667 } 4668 4669 qtd = kzalloc(sizeof(*qtd), mem_flags); 4670 if (!qtd) { 4671 retval = -ENOMEM; 4672 goto fail1; 4673 } 4674 4675 spin_lock_irqsave(&hsotg->lock, flags); 4676 retval = usb_hcd_link_urb_to_ep(hcd, urb); 4677 if (retval) 4678 goto fail2; 4679 4680 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd); 4681 if (retval) 4682 goto fail3; 4683 4684 if (alloc_bandwidth) { 4685 dwc2_allocate_bus_bandwidth(hcd, 4686 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 4687 urb); 4688 } 4689 4690 spin_unlock_irqrestore(&hsotg->lock, flags); 4691 4692 return 0; 4693 4694 fail3: 4695 dwc2_urb->priv = NULL; 4696 usb_hcd_unlink_urb_from_ep(hcd, urb); 4697 if (qh_allocated && qh->channel && qh->channel->qh == qh) 4698 qh->channel->qh = NULL; 4699 fail2: 4700 spin_unlock_irqrestore(&hsotg->lock, flags); 4701 urb->hcpriv = NULL; 4702 kfree(qtd); 4703 qtd = NULL; 4704 fail1: 4705 if (qh_allocated) { 4706 struct dwc2_qtd *qtd2, *qtd2_tmp; 4707 4708 ep->hcpriv = NULL; 4709 dwc2_hcd_qh_unlink(hsotg, qh); 4710 /* Free each QTD in the QH's QTD list */ 4711 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list, 4712 qtd_list_entry) 4713 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh); 4714 dwc2_hcd_qh_free(hsotg, qh); 4715 } 4716 fail0: 4717 kfree(dwc2_urb); 4718 4719 return retval; 4720 } 4721 4722 /* 4723 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success. 4724 */ 4725 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, 4726 int status) 4727 { 4728 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4729 int rc; 4730 unsigned long flags; 4731 4732 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n"); 4733 dwc2_dump_urb_info(hcd, urb, "urb_dequeue"); 4734 4735 spin_lock_irqsave(&hsotg->lock, flags); 4736 4737 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 4738 if (rc) 4739 goto out; 4740 4741 if (!urb->hcpriv) { 4742 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n"); 4743 goto out; 4744 } 4745 4746 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv); 4747 4748 usb_hcd_unlink_urb_from_ep(hcd, urb); 4749 4750 kfree(urb->hcpriv); 4751 urb->hcpriv = NULL; 4752 4753 /* Higher layer software sets URB status */ 4754 spin_unlock(&hsotg->lock); 4755 usb_hcd_giveback_urb(hcd, urb, status); 4756 spin_lock(&hsotg->lock); 4757 4758 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n"); 4759 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status); 4760 out: 4761 spin_unlock_irqrestore(&hsotg->lock, flags); 4762 4763 return rc; 4764 } 4765 4766 /* 4767 * Frees resources in the DWC_otg controller related to a given endpoint. Also 4768 * clears state in the HCD related to the endpoint. Any URBs for the endpoint 4769 * must already be dequeued. 4770 */ 4771 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd, 4772 struct usb_host_endpoint *ep) 4773 { 4774 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4775 4776 dev_dbg(hsotg->dev, 4777 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n", 4778 ep->desc.bEndpointAddress, ep->hcpriv); 4779 dwc2_hcd_endpoint_disable(hsotg, ep, 250); 4780 } 4781 4782 /* 4783 * Resets endpoint specific parameter values, in current version used to reset 4784 * the data toggle (as a WA). This function can be called from usb_clear_halt 4785 * routine. 4786 */ 4787 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd, 4788 struct usb_host_endpoint *ep) 4789 { 4790 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4791 unsigned long flags; 4792 4793 dev_dbg(hsotg->dev, 4794 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n", 4795 ep->desc.bEndpointAddress); 4796 4797 spin_lock_irqsave(&hsotg->lock, flags); 4798 dwc2_hcd_endpoint_reset(hsotg, ep); 4799 spin_unlock_irqrestore(&hsotg->lock, flags); 4800 } 4801 4802 /* 4803 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if 4804 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid 4805 * interrupt. 4806 * 4807 * This function is called by the USB core when an interrupt occurs 4808 */ 4809 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd) 4810 { 4811 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4812 4813 return dwc2_handle_hcd_intr(hsotg); 4814 } 4815 4816 /* 4817 * Creates Status Change bitmap for the root hub and root port. The bitmap is 4818 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 4819 * is the status change indicator for the single root port. Returns 1 if either 4820 * change indicator is 1, otherwise returns 0. 4821 */ 4822 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf) 4823 { 4824 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4825 4826 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1; 4827 return buf[0] != 0; 4828 } 4829 4830 /* Handles hub class-specific requests */ 4831 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue, 4832 u16 windex, char *buf, u16 wlength) 4833 { 4834 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq, 4835 wvalue, windex, buf, wlength); 4836 return retval; 4837 } 4838 4839 /* Handles hub TT buffer clear completions */ 4840 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd, 4841 struct usb_host_endpoint *ep) 4842 { 4843 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4844 struct dwc2_qh *qh; 4845 unsigned long flags; 4846 4847 qh = ep->hcpriv; 4848 if (!qh) 4849 return; 4850 4851 spin_lock_irqsave(&hsotg->lock, flags); 4852 qh->tt_buffer_dirty = 0; 4853 4854 if (hsotg->flags.b.port_connect_status) 4855 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL); 4856 4857 spin_unlock_irqrestore(&hsotg->lock, flags); 4858 } 4859 4860 static struct hc_driver dwc2_hc_driver = { 4861 .description = "dwc2_hsotg", 4862 .product_desc = "DWC OTG Controller", 4863 .hcd_priv_size = sizeof(struct wrapper_priv_data), 4864 4865 .irq = _dwc2_hcd_irq, 4866 .flags = HCD_MEMORY | HCD_USB2 | HCD_BH, 4867 4868 .start = _dwc2_hcd_start, 4869 .stop = _dwc2_hcd_stop, 4870 .urb_enqueue = _dwc2_hcd_urb_enqueue, 4871 .urb_dequeue = _dwc2_hcd_urb_dequeue, 4872 .endpoint_disable = _dwc2_hcd_endpoint_disable, 4873 .endpoint_reset = _dwc2_hcd_endpoint_reset, 4874 .get_frame_number = _dwc2_hcd_get_frame_number, 4875 4876 .hub_status_data = _dwc2_hcd_hub_status_data, 4877 .hub_control = _dwc2_hcd_hub_control, 4878 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete, 4879 4880 .bus_suspend = _dwc2_hcd_suspend, 4881 .bus_resume = _dwc2_hcd_resume, 4882 4883 .map_urb_for_dma = dwc2_map_urb_for_dma, 4884 .unmap_urb_for_dma = dwc2_unmap_urb_for_dma, 4885 }; 4886 4887 /* 4888 * Frees secondary storage associated with the dwc2_hsotg structure contained 4889 * in the struct usb_hcd field 4890 */ 4891 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg) 4892 { 4893 u32 ahbcfg; 4894 u32 dctl; 4895 int i; 4896 4897 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n"); 4898 4899 /* Free memory for QH/QTD lists */ 4900 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive); 4901 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active); 4902 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive); 4903 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready); 4904 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned); 4905 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued); 4906 4907 /* Free memory for the host channels */ 4908 for (i = 0; i < MAX_EPS_CHANNELS; i++) { 4909 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 4910 4911 if (chan != NULL) { 4912 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n", 4913 i, chan); 4914 hsotg->hc_ptr_array[i] = NULL; 4915 kfree(chan); 4916 } 4917 } 4918 4919 if (hsotg->params.host_dma > 0) { 4920 if (hsotg->status_buf) { 4921 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE, 4922 hsotg->status_buf, 4923 hsotg->status_buf_dma); 4924 hsotg->status_buf = NULL; 4925 } 4926 } else { 4927 kfree(hsotg->status_buf); 4928 hsotg->status_buf = NULL; 4929 } 4930 4931 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 4932 4933 /* Disable all interrupts */ 4934 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 4935 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 4936 dwc2_writel(0, hsotg->regs + GINTMSK); 4937 4938 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { 4939 dctl = dwc2_readl(hsotg->regs + DCTL); 4940 dctl |= DCTL_SFTDISCON; 4941 dwc2_writel(dctl, hsotg->regs + DCTL); 4942 } 4943 4944 if (hsotg->wq_otg) { 4945 if (!cancel_work_sync(&hsotg->wf_otg)) 4946 flush_workqueue(hsotg->wq_otg); 4947 destroy_workqueue(hsotg->wq_otg); 4948 } 4949 4950 del_timer(&hsotg->wkp_timer); 4951 } 4952 4953 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg) 4954 { 4955 /* Turn off all host-specific interrupts */ 4956 dwc2_disable_host_interrupts(hsotg); 4957 4958 dwc2_hcd_free(hsotg); 4959 } 4960 4961 /* 4962 * Initializes the HCD. This function allocates memory for and initializes the 4963 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the 4964 * USB bus with the core and calls the hc_driver->start() function. It returns 4965 * a negative error on failure. 4966 */ 4967 int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) 4968 { 4969 struct usb_hcd *hcd; 4970 struct dwc2_host_chan *channel; 4971 u32 hcfg; 4972 int i, num_channels; 4973 int retval; 4974 4975 if (usb_disabled()) 4976 return -ENODEV; 4977 4978 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n"); 4979 4980 retval = -ENOMEM; 4981 4982 hcfg = dwc2_readl(hsotg->regs + HCFG); 4983 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg); 4984 4985 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 4986 hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) * 4987 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL); 4988 if (!hsotg->frame_num_array) 4989 goto error1; 4990 hsotg->last_frame_num_array = kzalloc( 4991 sizeof(*hsotg->last_frame_num_array) * 4992 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL); 4993 if (!hsotg->last_frame_num_array) 4994 goto error1; 4995 #endif 4996 hsotg->last_frame_num = HFNUM_MAX_FRNUM; 4997 4998 /* Check if the bus driver or platform code has setup a dma_mask */ 4999 if (hsotg->params.host_dma > 0 && 5000 hsotg->dev->dma_mask == NULL) { 5001 dev_warn(hsotg->dev, 5002 "dma_mask not set, disabling DMA\n"); 5003 hsotg->params.host_dma = 0; 5004 hsotg->params.dma_desc_enable = 0; 5005 } 5006 5007 /* Set device flags indicating whether the HCD supports DMA */ 5008 if (hsotg->params.host_dma > 0) { 5009 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 5010 dev_warn(hsotg->dev, "can't set DMA mask\n"); 5011 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 5012 dev_warn(hsotg->dev, "can't set coherent DMA mask\n"); 5013 } 5014 5015 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev)); 5016 if (!hcd) 5017 goto error1; 5018 5019 if (hsotg->params.host_dma <= 0) 5020 hcd->self.uses_dma = 0; 5021 5022 hcd->has_tt = 1; 5023 5024 ((struct wrapper_priv_data *) &hcd->hcd_priv)->hsotg = hsotg; 5025 hsotg->priv = hcd; 5026 5027 /* 5028 * Disable the global interrupt until all the interrupt handlers are 5029 * installed 5030 */ 5031 dwc2_disable_global_interrupts(hsotg); 5032 5033 /* Initialize the DWC_otg core, and select the Phy type */ 5034 retval = dwc2_core_init(hsotg, true); 5035 if (retval) 5036 goto error2; 5037 5038 /* Create new workqueue and init work */ 5039 retval = -ENOMEM; 5040 hsotg->wq_otg = alloc_ordered_workqueue("dwc2", 0); 5041 if (!hsotg->wq_otg) { 5042 dev_err(hsotg->dev, "Failed to create workqueue\n"); 5043 goto error2; 5044 } 5045 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change); 5046 5047 setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected, 5048 (unsigned long)hsotg); 5049 5050 /* Initialize the non-periodic schedule */ 5051 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive); 5052 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active); 5053 5054 /* Initialize the periodic schedule */ 5055 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive); 5056 INIT_LIST_HEAD(&hsotg->periodic_sched_ready); 5057 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned); 5058 INIT_LIST_HEAD(&hsotg->periodic_sched_queued); 5059 5060 INIT_LIST_HEAD(&hsotg->split_order); 5061 5062 /* 5063 * Create a host channel descriptor for each host channel implemented 5064 * in the controller. Initialize the channel descriptor array. 5065 */ 5066 INIT_LIST_HEAD(&hsotg->free_hc_list); 5067 num_channels = hsotg->params.host_channels; 5068 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array)); 5069 5070 for (i = 0; i < num_channels; i++) { 5071 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 5072 if (channel == NULL) 5073 goto error3; 5074 channel->hc_num = i; 5075 INIT_LIST_HEAD(&channel->split_order_list_entry); 5076 hsotg->hc_ptr_array[i] = channel; 5077 } 5078 5079 /* Initialize hsotg start work */ 5080 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func); 5081 5082 /* Initialize port reset work */ 5083 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func); 5084 5085 /* 5086 * Allocate space for storing data on status transactions. Normally no 5087 * data is sent, but this space acts as a bit bucket. This must be 5088 * done after usb_add_hcd since that function allocates the DMA buffer 5089 * pool. 5090 */ 5091 if (hsotg->params.host_dma > 0) 5092 hsotg->status_buf = dma_alloc_coherent(hsotg->dev, 5093 DWC2_HCD_STATUS_BUF_SIZE, 5094 &hsotg->status_buf_dma, GFP_KERNEL); 5095 else 5096 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE, 5097 GFP_KERNEL); 5098 5099 if (!hsotg->status_buf) 5100 goto error3; 5101 5102 /* 5103 * Create kmem caches to handle descriptor buffers in descriptor 5104 * DMA mode. 5105 * Alignment must be set to 512 bytes. 5106 */ 5107 if (hsotg->params.dma_desc_enable || 5108 hsotg->params.dma_desc_fs_enable) { 5109 hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc", 5110 sizeof(struct dwc2_dma_desc) * 5111 MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA, 5112 NULL); 5113 if (!hsotg->desc_gen_cache) { 5114 dev_err(hsotg->dev, 5115 "unable to create dwc2 generic desc cache\n"); 5116 5117 /* 5118 * Disable descriptor dma mode since it will not be 5119 * usable. 5120 */ 5121 hsotg->params.dma_desc_enable = 0; 5122 hsotg->params.dma_desc_fs_enable = 0; 5123 } 5124 5125 hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc", 5126 sizeof(struct dwc2_dma_desc) * 5127 MAX_DMA_DESC_NUM_HS_ISOC, 512, 0, NULL); 5128 if (!hsotg->desc_hsisoc_cache) { 5129 dev_err(hsotg->dev, 5130 "unable to create dwc2 hs isoc desc cache\n"); 5131 5132 kmem_cache_destroy(hsotg->desc_gen_cache); 5133 5134 /* 5135 * Disable descriptor dma mode since it will not be 5136 * usable. 5137 */ 5138 hsotg->params.dma_desc_enable = 0; 5139 hsotg->params.dma_desc_fs_enable = 0; 5140 } 5141 } 5142 5143 hsotg->otg_port = 1; 5144 hsotg->frame_list = NULL; 5145 hsotg->frame_list_dma = 0; 5146 hsotg->periodic_qh_count = 0; 5147 5148 /* Initiate lx_state to L3 disconnected state */ 5149 hsotg->lx_state = DWC2_L3; 5150 5151 hcd->self.otg_port = hsotg->otg_port; 5152 5153 /* Don't support SG list at this point */ 5154 hcd->self.sg_tablesize = 0; 5155 5156 if (!IS_ERR_OR_NULL(hsotg->uphy)) 5157 otg_set_host(hsotg->uphy->otg, &hcd->self); 5158 5159 /* 5160 * Finish generic HCD initialization and start the HCD. This function 5161 * allocates the DMA buffer pool, registers the USB bus, requests the 5162 * IRQ line, and calls hcd_start method. 5163 */ 5164 retval = usb_add_hcd(hcd, irq, IRQF_SHARED); 5165 if (retval < 0) 5166 goto error4; 5167 5168 device_wakeup_enable(hcd->self.controller); 5169 5170 dwc2_hcd_dump_state(hsotg); 5171 5172 dwc2_enable_global_interrupts(hsotg); 5173 5174 return 0; 5175 5176 error4: 5177 kmem_cache_destroy(hsotg->desc_gen_cache); 5178 kmem_cache_destroy(hsotg->desc_hsisoc_cache); 5179 error3: 5180 dwc2_hcd_release(hsotg); 5181 error2: 5182 usb_put_hcd(hcd); 5183 error1: 5184 5185 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 5186 kfree(hsotg->last_frame_num_array); 5187 kfree(hsotg->frame_num_array); 5188 #endif 5189 5190 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval); 5191 return retval; 5192 } 5193 5194 /* 5195 * Removes the HCD. 5196 * Frees memory and resources associated with the HCD and deregisters the bus. 5197 */ 5198 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) 5199 { 5200 struct usb_hcd *hcd; 5201 5202 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n"); 5203 5204 hcd = dwc2_hsotg_to_hcd(hsotg); 5205 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd); 5206 5207 if (!hcd) { 5208 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n", 5209 __func__); 5210 return; 5211 } 5212 5213 if (!IS_ERR_OR_NULL(hsotg->uphy)) 5214 otg_set_host(hsotg->uphy->otg, NULL); 5215 5216 usb_remove_hcd(hcd); 5217 hsotg->priv = NULL; 5218 5219 kmem_cache_destroy(hsotg->desc_gen_cache); 5220 kmem_cache_destroy(hsotg->desc_hsisoc_cache); 5221 5222 dwc2_hcd_release(hsotg); 5223 usb_put_hcd(hcd); 5224 5225 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 5226 kfree(hsotg->last_frame_num_array); 5227 kfree(hsotg->frame_num_array); 5228 #endif 5229 } 5230 5231 /** 5232 * dwc2_backup_host_registers() - Backup controller host registers. 5233 * When suspending usb bus, registers needs to be backuped 5234 * if controller power is disabled once suspended. 5235 * 5236 * @hsotg: Programming view of the DWC_otg controller 5237 */ 5238 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 5239 { 5240 struct dwc2_hregs_backup *hr; 5241 int i; 5242 5243 dev_dbg(hsotg->dev, "%s\n", __func__); 5244 5245 /* Backup Host regs */ 5246 hr = &hsotg->hr_backup; 5247 hr->hcfg = dwc2_readl(hsotg->regs + HCFG); 5248 hr->haintmsk = dwc2_readl(hsotg->regs + HAINTMSK); 5249 for (i = 0; i < hsotg->params.host_channels; ++i) 5250 hr->hcintmsk[i] = dwc2_readl(hsotg->regs + HCINTMSK(i)); 5251 5252 hr->hprt0 = dwc2_read_hprt0(hsotg); 5253 hr->hfir = dwc2_readl(hsotg->regs + HFIR); 5254 hr->valid = true; 5255 5256 return 0; 5257 } 5258 5259 /** 5260 * dwc2_restore_host_registers() - Restore controller host registers. 5261 * When resuming usb bus, device registers needs to be restored 5262 * if controller power were disabled. 5263 * 5264 * @hsotg: Programming view of the DWC_otg controller 5265 */ 5266 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 5267 { 5268 struct dwc2_hregs_backup *hr; 5269 int i; 5270 5271 dev_dbg(hsotg->dev, "%s\n", __func__); 5272 5273 /* Restore host regs */ 5274 hr = &hsotg->hr_backup; 5275 if (!hr->valid) { 5276 dev_err(hsotg->dev, "%s: no host registers to restore\n", 5277 __func__); 5278 return -EINVAL; 5279 } 5280 hr->valid = false; 5281 5282 dwc2_writel(hr->hcfg, hsotg->regs + HCFG); 5283 dwc2_writel(hr->haintmsk, hsotg->regs + HAINTMSK); 5284 5285 for (i = 0; i < hsotg->params.host_channels; ++i) 5286 dwc2_writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i)); 5287 5288 dwc2_writel(hr->hprt0, hsotg->regs + HPRT0); 5289 dwc2_writel(hr->hfir, hsotg->regs + HFIR); 5290 hsotg->frame_number = 0; 5291 5292 return 0; 5293 } 5294