1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 4 * http://www.samsung.com 5 * 6 * Copyright 2008 Openmoko, Inc. 7 * Copyright 2008 Simtec Electronics 8 * Ben Dooks <ben@simtec.co.uk> 9 * http://armlinux.simtec.co.uk/ 10 * 11 * S3C USB2.0 High-speed / OtG driver 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/spinlock.h> 17 #include <linux/interrupt.h> 18 #include <linux/platform_device.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/mutex.h> 21 #include <linux/seq_file.h> 22 #include <linux/delay.h> 23 #include <linux/io.h> 24 #include <linux/slab.h> 25 #include <linux/of_platform.h> 26 27 #include <linux/usb/ch9.h> 28 #include <linux/usb/gadget.h> 29 #include <linux/usb/phy.h> 30 31 #include "core.h" 32 #include "hw.h" 33 34 /* conversion functions */ 35 static inline struct dwc2_hsotg_req *our_req(struct usb_request *req) 36 { 37 return container_of(req, struct dwc2_hsotg_req, req); 38 } 39 40 static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep) 41 { 42 return container_of(ep, struct dwc2_hsotg_ep, ep); 43 } 44 45 static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget) 46 { 47 return container_of(gadget, struct dwc2_hsotg, gadget); 48 } 49 50 static inline void dwc2_set_bit(void __iomem *ptr, u32 val) 51 { 52 dwc2_writel(dwc2_readl(ptr) | val, ptr); 53 } 54 55 static inline void dwc2_clear_bit(void __iomem *ptr, u32 val) 56 { 57 dwc2_writel(dwc2_readl(ptr) & ~val, ptr); 58 } 59 60 static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg, 61 u32 ep_index, u32 dir_in) 62 { 63 if (dir_in) 64 return hsotg->eps_in[ep_index]; 65 else 66 return hsotg->eps_out[ep_index]; 67 } 68 69 /* forward declaration of functions */ 70 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg); 71 72 /** 73 * using_dma - return the DMA status of the driver. 74 * @hsotg: The driver state. 75 * 76 * Return true if we're using DMA. 77 * 78 * Currently, we have the DMA support code worked into everywhere 79 * that needs it, but the AMBA DMA implementation in the hardware can 80 * only DMA from 32bit aligned addresses. This means that gadgets such 81 * as the CDC Ethernet cannot work as they often pass packets which are 82 * not 32bit aligned. 83 * 84 * Unfortunately the choice to use DMA or not is global to the controller 85 * and seems to be only settable when the controller is being put through 86 * a core reset. This means we either need to fix the gadgets to take 87 * account of DMA alignment, or add bounce buffers (yuerk). 88 * 89 * g_using_dma is set depending on dts flag. 90 */ 91 static inline bool using_dma(struct dwc2_hsotg *hsotg) 92 { 93 return hsotg->params.g_dma; 94 } 95 96 /* 97 * using_desc_dma - return the descriptor DMA status of the driver. 98 * @hsotg: The driver state. 99 * 100 * Return true if we're using descriptor DMA. 101 */ 102 static inline bool using_desc_dma(struct dwc2_hsotg *hsotg) 103 { 104 return hsotg->params.g_dma_desc; 105 } 106 107 /** 108 * dwc2_gadget_incr_frame_num - Increments the targeted frame number. 109 * @hs_ep: The endpoint 110 * 111 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT. 112 * If an overrun occurs it will wrap the value and set the frame_overrun flag. 113 */ 114 static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep) 115 { 116 hs_ep->target_frame += hs_ep->interval; 117 if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) { 118 hs_ep->frame_overrun = true; 119 hs_ep->target_frame &= DSTS_SOFFN_LIMIT; 120 } else { 121 hs_ep->frame_overrun = false; 122 } 123 } 124 125 /** 126 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt 127 * @hsotg: The device state 128 * @ints: A bitmask of the interrupts to enable 129 */ 130 static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints) 131 { 132 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); 133 u32 new_gsintmsk; 134 135 new_gsintmsk = gsintmsk | ints; 136 137 if (new_gsintmsk != gsintmsk) { 138 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); 139 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); 140 } 141 } 142 143 /** 144 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt 145 * @hsotg: The device state 146 * @ints: A bitmask of the interrupts to enable 147 */ 148 static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints) 149 { 150 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); 151 u32 new_gsintmsk; 152 153 new_gsintmsk = gsintmsk & ~ints; 154 155 if (new_gsintmsk != gsintmsk) 156 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); 157 } 158 159 /** 160 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq 161 * @hsotg: The device state 162 * @ep: The endpoint index 163 * @dir_in: True if direction is in. 164 * @en: The enable value, true to enable 165 * 166 * Set or clear the mask for an individual endpoint's interrupt 167 * request. 168 */ 169 static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg, 170 unsigned int ep, unsigned int dir_in, 171 unsigned int en) 172 { 173 unsigned long flags; 174 u32 bit = 1 << ep; 175 u32 daint; 176 177 if (!dir_in) 178 bit <<= 16; 179 180 local_irq_save(flags); 181 daint = dwc2_readl(hsotg->regs + DAINTMSK); 182 if (en) 183 daint |= bit; 184 else 185 daint &= ~bit; 186 dwc2_writel(daint, hsotg->regs + DAINTMSK); 187 local_irq_restore(flags); 188 } 189 190 /** 191 * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode 192 * 193 * @hsotg: Programming view of the DWC_otg controller 194 */ 195 int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg) 196 { 197 if (hsotg->hw_params.en_multiple_tx_fifo) 198 /* In dedicated FIFO mode we need count of IN EPs */ 199 return hsotg->hw_params.num_dev_in_eps; 200 else 201 /* In shared FIFO mode we need count of Periodic IN EPs */ 202 return hsotg->hw_params.num_dev_perio_in_ep; 203 } 204 205 /** 206 * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for 207 * device mode TX FIFOs 208 * 209 * @hsotg: Programming view of the DWC_otg controller 210 */ 211 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) 212 { 213 int addr; 214 int tx_addr_max; 215 u32 np_tx_fifo_size; 216 217 np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size, 218 hsotg->params.g_np_tx_fifo_size); 219 220 /* Get Endpoint Info Control block size in DWORDs. */ 221 tx_addr_max = hsotg->hw_params.total_fifo_size; 222 223 addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size; 224 if (tx_addr_max <= addr) 225 return 0; 226 227 return tx_addr_max - addr; 228 } 229 230 /** 231 * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode 232 * TX FIFOs 233 * 234 * @hsotg: Programming view of the DWC_otg controller 235 */ 236 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg) 237 { 238 int tx_fifo_count; 239 int tx_fifo_depth; 240 241 tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg); 242 243 tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 244 245 if (!tx_fifo_count) 246 return tx_fifo_depth; 247 else 248 return tx_fifo_depth / tx_fifo_count; 249 } 250 251 /** 252 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs 253 * @hsotg: The device instance. 254 */ 255 static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg) 256 { 257 unsigned int ep; 258 unsigned int addr; 259 int timeout; 260 261 u32 val; 262 u32 *txfsz = hsotg->params.g_tx_fifo_size; 263 264 /* Reset fifo map if not correctly cleared during previous session */ 265 WARN_ON(hsotg->fifo_map); 266 hsotg->fifo_map = 0; 267 268 /* set RX/NPTX FIFO sizes */ 269 dwc2_writel(hsotg->params.g_rx_fifo_size, hsotg->regs + GRXFSIZ); 270 dwc2_writel((hsotg->params.g_rx_fifo_size << FIFOSIZE_STARTADDR_SHIFT) | 271 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT), 272 hsotg->regs + GNPTXFSIZ); 273 274 /* 275 * arange all the rest of the TX FIFOs, as some versions of this 276 * block have overlapping default addresses. This also ensures 277 * that if the settings have been changed, then they are set to 278 * known values. 279 */ 280 281 /* start at the end of the GNPTXFSIZ, rounded up */ 282 addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size; 283 284 /* 285 * Configure fifos sizes from provided configuration and assign 286 * them to endpoints dynamically according to maxpacket size value of 287 * given endpoint. 288 */ 289 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) { 290 if (!txfsz[ep]) 291 continue; 292 val = addr; 293 val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT; 294 WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem, 295 "insufficient fifo memory"); 296 addr += txfsz[ep]; 297 298 dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep)); 299 val = dwc2_readl(hsotg->regs + DPTXFSIZN(ep)); 300 } 301 302 dwc2_writel(hsotg->hw_params.total_fifo_size | 303 addr << GDFIFOCFG_EPINFOBASE_SHIFT, 304 hsotg->regs + GDFIFOCFG); 305 /* 306 * according to p428 of the design guide, we need to ensure that 307 * all fifos are flushed before continuing 308 */ 309 310 dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | 311 GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL); 312 313 /* wait until the fifos are both flushed */ 314 timeout = 100; 315 while (1) { 316 val = dwc2_readl(hsotg->regs + GRSTCTL); 317 318 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) 319 break; 320 321 if (--timeout == 0) { 322 dev_err(hsotg->dev, 323 "%s: timeout flushing fifos (GRSTCTL=%08x)\n", 324 __func__, val); 325 break; 326 } 327 328 udelay(1); 329 } 330 331 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout); 332 } 333 334 /** 335 * dwc2_hsotg_ep_alloc_request - allocate USB rerequest structure 336 * @ep: USB endpoint to allocate request for. 337 * @flags: Allocation flags 338 * 339 * Allocate a new USB request structure appropriate for the specified endpoint 340 */ 341 static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep, 342 gfp_t flags) 343 { 344 struct dwc2_hsotg_req *req; 345 346 req = kzalloc(sizeof(*req), flags); 347 if (!req) 348 return NULL; 349 350 INIT_LIST_HEAD(&req->queue); 351 352 return &req->req; 353 } 354 355 /** 356 * is_ep_periodic - return true if the endpoint is in periodic mode. 357 * @hs_ep: The endpoint to query. 358 * 359 * Returns true if the endpoint is in periodic mode, meaning it is being 360 * used for an Interrupt or ISO transfer. 361 */ 362 static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep) 363 { 364 return hs_ep->periodic; 365 } 366 367 /** 368 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request 369 * @hsotg: The device state. 370 * @hs_ep: The endpoint for the request 371 * @hs_req: The request being processed. 372 * 373 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion 374 * of a request to ensure the buffer is ready for access by the caller. 375 */ 376 static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg, 377 struct dwc2_hsotg_ep *hs_ep, 378 struct dwc2_hsotg_req *hs_req) 379 { 380 struct usb_request *req = &hs_req->req; 381 382 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in); 383 } 384 385 /* 386 * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains 387 * for Control endpoint 388 * @hsotg: The device state. 389 * 390 * This function will allocate 4 descriptor chains for EP 0: 2 for 391 * Setup stage, per one for IN and OUT data/status transactions. 392 */ 393 static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg) 394 { 395 hsotg->setup_desc[0] = 396 dmam_alloc_coherent(hsotg->dev, 397 sizeof(struct dwc2_dma_desc), 398 &hsotg->setup_desc_dma[0], 399 GFP_KERNEL); 400 if (!hsotg->setup_desc[0]) 401 goto fail; 402 403 hsotg->setup_desc[1] = 404 dmam_alloc_coherent(hsotg->dev, 405 sizeof(struct dwc2_dma_desc), 406 &hsotg->setup_desc_dma[1], 407 GFP_KERNEL); 408 if (!hsotg->setup_desc[1]) 409 goto fail; 410 411 hsotg->ctrl_in_desc = 412 dmam_alloc_coherent(hsotg->dev, 413 sizeof(struct dwc2_dma_desc), 414 &hsotg->ctrl_in_desc_dma, 415 GFP_KERNEL); 416 if (!hsotg->ctrl_in_desc) 417 goto fail; 418 419 hsotg->ctrl_out_desc = 420 dmam_alloc_coherent(hsotg->dev, 421 sizeof(struct dwc2_dma_desc), 422 &hsotg->ctrl_out_desc_dma, 423 GFP_KERNEL); 424 if (!hsotg->ctrl_out_desc) 425 goto fail; 426 427 return 0; 428 429 fail: 430 return -ENOMEM; 431 } 432 433 /** 434 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO 435 * @hsotg: The controller state. 436 * @hs_ep: The endpoint we're going to write for. 437 * @hs_req: The request to write data for. 438 * 439 * This is called when the TxFIFO has some space in it to hold a new 440 * transmission and we have something to give it. The actual setup of 441 * the data size is done elsewhere, so all we have to do is to actually 442 * write the data. 443 * 444 * The return value is zero if there is more space (or nothing was done) 445 * otherwise -ENOSPC is returned if the FIFO space was used up. 446 * 447 * This routine is only needed for PIO 448 */ 449 static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg, 450 struct dwc2_hsotg_ep *hs_ep, 451 struct dwc2_hsotg_req *hs_req) 452 { 453 bool periodic = is_ep_periodic(hs_ep); 454 u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); 455 int buf_pos = hs_req->req.actual; 456 int to_write = hs_ep->size_loaded; 457 void *data; 458 int can_write; 459 int pkt_round; 460 int max_transfer; 461 462 to_write -= (buf_pos - hs_ep->last_load); 463 464 /* if there's nothing to write, get out early */ 465 if (to_write == 0) 466 return 0; 467 468 if (periodic && !hsotg->dedicated_fifos) { 469 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); 470 int size_left; 471 int size_done; 472 473 /* 474 * work out how much data was loaded so we can calculate 475 * how much data is left in the fifo. 476 */ 477 478 size_left = DXEPTSIZ_XFERSIZE_GET(epsize); 479 480 /* 481 * if shared fifo, we cannot write anything until the 482 * previous data has been completely sent. 483 */ 484 if (hs_ep->fifo_load != 0) { 485 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); 486 return -ENOSPC; 487 } 488 489 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n", 490 __func__, size_left, 491 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size); 492 493 /* how much of the data has moved */ 494 size_done = hs_ep->size_loaded - size_left; 495 496 /* how much data is left in the fifo */ 497 can_write = hs_ep->fifo_load - size_done; 498 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n", 499 __func__, can_write); 500 501 can_write = hs_ep->fifo_size - can_write; 502 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n", 503 __func__, can_write); 504 505 if (can_write <= 0) { 506 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); 507 return -ENOSPC; 508 } 509 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { 510 can_write = dwc2_readl(hsotg->regs + 511 DTXFSTS(hs_ep->fifo_index)); 512 513 can_write &= 0xffff; 514 can_write *= 4; 515 } else { 516 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) { 517 dev_dbg(hsotg->dev, 518 "%s: no queue slots available (0x%08x)\n", 519 __func__, gnptxsts); 520 521 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP); 522 return -ENOSPC; 523 } 524 525 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts); 526 can_write *= 4; /* fifo size is in 32bit quantities. */ 527 } 528 529 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc; 530 531 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n", 532 __func__, gnptxsts, can_write, to_write, max_transfer); 533 534 /* 535 * limit to 512 bytes of data, it seems at least on the non-periodic 536 * FIFO, requests of >512 cause the endpoint to get stuck with a 537 * fragment of the end of the transfer in it. 538 */ 539 if (can_write > 512 && !periodic) 540 can_write = 512; 541 542 /* 543 * limit the write to one max-packet size worth of data, but allow 544 * the transfer to return that it did not run out of fifo space 545 * doing it. 546 */ 547 if (to_write > max_transfer) { 548 to_write = max_transfer; 549 550 /* it's needed only when we do not use dedicated fifos */ 551 if (!hsotg->dedicated_fifos) 552 dwc2_hsotg_en_gsint(hsotg, 553 periodic ? GINTSTS_PTXFEMP : 554 GINTSTS_NPTXFEMP); 555 } 556 557 /* see if we can write data */ 558 559 if (to_write > can_write) { 560 to_write = can_write; 561 pkt_round = to_write % max_transfer; 562 563 /* 564 * Round the write down to an 565 * exact number of packets. 566 * 567 * Note, we do not currently check to see if we can ever 568 * write a full packet or not to the FIFO. 569 */ 570 571 if (pkt_round) 572 to_write -= pkt_round; 573 574 /* 575 * enable correct FIFO interrupt to alert us when there 576 * is more room left. 577 */ 578 579 /* it's needed only when we do not use dedicated fifos */ 580 if (!hsotg->dedicated_fifos) 581 dwc2_hsotg_en_gsint(hsotg, 582 periodic ? GINTSTS_PTXFEMP : 583 GINTSTS_NPTXFEMP); 584 } 585 586 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n", 587 to_write, hs_req->req.length, can_write, buf_pos); 588 589 if (to_write <= 0) 590 return -ENOSPC; 591 592 hs_req->req.actual = buf_pos + to_write; 593 hs_ep->total_data += to_write; 594 595 if (periodic) 596 hs_ep->fifo_load += to_write; 597 598 to_write = DIV_ROUND_UP(to_write, 4); 599 data = hs_req->req.buf + buf_pos; 600 601 iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write); 602 603 return (to_write >= can_write) ? -ENOSPC : 0; 604 } 605 606 /** 607 * get_ep_limit - get the maximum data legnth for this endpoint 608 * @hs_ep: The endpoint 609 * 610 * Return the maximum data that can be queued in one go on a given endpoint 611 * so that transfers that are too long can be split. 612 */ 613 static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep) 614 { 615 int index = hs_ep->index; 616 unsigned int maxsize; 617 unsigned int maxpkt; 618 619 if (index != 0) { 620 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1; 621 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1; 622 } else { 623 maxsize = 64 + 64; 624 if (hs_ep->dir_in) 625 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1; 626 else 627 maxpkt = 2; 628 } 629 630 /* we made the constant loading easier above by using +1 */ 631 maxpkt--; 632 maxsize--; 633 634 /* 635 * constrain by packet count if maxpkts*pktsize is greater 636 * than the length register size. 637 */ 638 639 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize) 640 maxsize = maxpkt * hs_ep->ep.maxpacket; 641 642 return maxsize; 643 } 644 645 /** 646 * dwc2_hsotg_read_frameno - read current frame number 647 * @hsotg: The device instance 648 * 649 * Return the current frame number 650 */ 651 static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg) 652 { 653 u32 dsts; 654 655 dsts = dwc2_readl(hsotg->regs + DSTS); 656 dsts &= DSTS_SOFFN_MASK; 657 dsts >>= DSTS_SOFFN_SHIFT; 658 659 return dsts; 660 } 661 662 /** 663 * dwc2_gadget_get_chain_limit - get the maximum data payload value of the 664 * DMA descriptor chain prepared for specific endpoint 665 * @hs_ep: The endpoint 666 * 667 * Return the maximum data that can be queued in one go on a given endpoint 668 * depending on its descriptor chain capacity so that transfers that 669 * are too long can be split. 670 */ 671 static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep) 672 { 673 int is_isoc = hs_ep->isochronous; 674 unsigned int maxsize; 675 676 if (is_isoc) 677 maxsize = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT : 678 DEV_DMA_ISOC_RX_NBYTES_LIMIT; 679 else 680 maxsize = DEV_DMA_NBYTES_LIMIT; 681 682 /* Above size of one descriptor was chosen, multiple it */ 683 maxsize *= MAX_DMA_DESC_NUM_GENERIC; 684 685 return maxsize; 686 } 687 688 /* 689 * dwc2_gadget_get_desc_params - get DMA descriptor parameters. 690 * @hs_ep: The endpoint 691 * @mask: RX/TX bytes mask to be defined 692 * 693 * Returns maximum data payload for one descriptor after analyzing endpoint 694 * characteristics. 695 * DMA descriptor transfer bytes limit depends on EP type: 696 * Control out - MPS, 697 * Isochronous - descriptor rx/tx bytes bitfield limit, 698 * Control In/Bulk/Interrupt - multiple of mps. This will allow to not 699 * have concatenations from various descriptors within one packet. 700 * 701 * Selects corresponding mask for RX/TX bytes as well. 702 */ 703 static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask) 704 { 705 u32 mps = hs_ep->ep.maxpacket; 706 int dir_in = hs_ep->dir_in; 707 u32 desc_size = 0; 708 709 if (!hs_ep->index && !dir_in) { 710 desc_size = mps; 711 *mask = DEV_DMA_NBYTES_MASK; 712 } else if (hs_ep->isochronous) { 713 if (dir_in) { 714 desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT; 715 *mask = DEV_DMA_ISOC_TX_NBYTES_MASK; 716 } else { 717 desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT; 718 *mask = DEV_DMA_ISOC_RX_NBYTES_MASK; 719 } 720 } else { 721 desc_size = DEV_DMA_NBYTES_LIMIT; 722 *mask = DEV_DMA_NBYTES_MASK; 723 724 /* Round down desc_size to be mps multiple */ 725 desc_size -= desc_size % mps; 726 } 727 728 return desc_size; 729 } 730 731 /* 732 * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain. 733 * @hs_ep: The endpoint 734 * @dma_buff: DMA address to use 735 * @len: Length of the transfer 736 * 737 * This function will iterate over descriptor chain and fill its entries 738 * with corresponding information based on transfer data. 739 */ 740 static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep, 741 dma_addr_t dma_buff, 742 unsigned int len) 743 { 744 struct dwc2_hsotg *hsotg = hs_ep->parent; 745 int dir_in = hs_ep->dir_in; 746 struct dwc2_dma_desc *desc = hs_ep->desc_list; 747 u32 mps = hs_ep->ep.maxpacket; 748 u32 maxsize = 0; 749 u32 offset = 0; 750 u32 mask = 0; 751 int i; 752 753 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); 754 755 hs_ep->desc_count = (len / maxsize) + 756 ((len % maxsize) ? 1 : 0); 757 if (len == 0) 758 hs_ep->desc_count = 1; 759 760 for (i = 0; i < hs_ep->desc_count; ++i) { 761 desc->status = 0; 762 desc->status |= (DEV_DMA_BUFF_STS_HBUSY 763 << DEV_DMA_BUFF_STS_SHIFT); 764 765 if (len > maxsize) { 766 if (!hs_ep->index && !dir_in) 767 desc->status |= (DEV_DMA_L | DEV_DMA_IOC); 768 769 desc->status |= (maxsize << 770 DEV_DMA_NBYTES_SHIFT & mask); 771 desc->buf = dma_buff + offset; 772 773 len -= maxsize; 774 offset += maxsize; 775 } else { 776 desc->status |= (DEV_DMA_L | DEV_DMA_IOC); 777 778 if (dir_in) 779 desc->status |= (len % mps) ? DEV_DMA_SHORT : 780 ((hs_ep->send_zlp) ? DEV_DMA_SHORT : 0); 781 if (len > maxsize) 782 dev_err(hsotg->dev, "wrong len %d\n", len); 783 784 desc->status |= 785 len << DEV_DMA_NBYTES_SHIFT & mask; 786 desc->buf = dma_buff + offset; 787 } 788 789 desc->status &= ~DEV_DMA_BUFF_STS_MASK; 790 desc->status |= (DEV_DMA_BUFF_STS_HREADY 791 << DEV_DMA_BUFF_STS_SHIFT); 792 desc++; 793 } 794 } 795 796 /* 797 * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain. 798 * @hs_ep: The isochronous endpoint. 799 * @dma_buff: usb requests dma buffer. 800 * @len: usb request transfer length. 801 * 802 * Fills next free descriptor with the data of the arrived usb request, 803 * frame info, sets Last and IOC bits increments next_desc. If filled 804 * descriptor is not the first one, removes L bit from the previous descriptor 805 * status. 806 */ 807 static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep, 808 dma_addr_t dma_buff, unsigned int len) 809 { 810 struct dwc2_dma_desc *desc; 811 struct dwc2_hsotg *hsotg = hs_ep->parent; 812 u32 index; 813 u32 maxsize = 0; 814 u32 mask = 0; 815 816 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); 817 818 index = hs_ep->next_desc; 819 desc = &hs_ep->desc_list[index]; 820 821 /* Check if descriptor chain full */ 822 if ((desc->status >> DEV_DMA_BUFF_STS_SHIFT) == 823 DEV_DMA_BUFF_STS_HREADY) { 824 dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__); 825 return 1; 826 } 827 828 /* Clear L bit of previous desc if more than one entries in the chain */ 829 if (hs_ep->next_desc) 830 hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L; 831 832 dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n", 833 __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index); 834 835 desc->status = 0; 836 desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT); 837 838 desc->buf = dma_buff; 839 desc->status |= (DEV_DMA_L | DEV_DMA_IOC | 840 ((len << DEV_DMA_NBYTES_SHIFT) & mask)); 841 842 if (hs_ep->dir_in) { 843 desc->status |= ((hs_ep->mc << DEV_DMA_ISOC_PID_SHIFT) & 844 DEV_DMA_ISOC_PID_MASK) | 845 ((len % hs_ep->ep.maxpacket) ? 846 DEV_DMA_SHORT : 0) | 847 ((hs_ep->target_frame << 848 DEV_DMA_ISOC_FRNUM_SHIFT) & 849 DEV_DMA_ISOC_FRNUM_MASK); 850 } 851 852 desc->status &= ~DEV_DMA_BUFF_STS_MASK; 853 desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT); 854 855 /* Increment frame number by interval for IN */ 856 if (hs_ep->dir_in) 857 dwc2_gadget_incr_frame_num(hs_ep); 858 859 /* Update index of last configured entry in the chain */ 860 hs_ep->next_desc++; 861 if (hs_ep->next_desc >= MAX_DMA_DESC_NUM_GENERIC) 862 hs_ep->next_desc = 0; 863 864 return 0; 865 } 866 867 /* 868 * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA 869 * @hs_ep: The isochronous endpoint. 870 * 871 * Prepare descriptor chain for isochronous endpoints. Afterwards 872 * write DMA address to HW and enable the endpoint. 873 */ 874 static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep) 875 { 876 struct dwc2_hsotg *hsotg = hs_ep->parent; 877 struct dwc2_hsotg_req *hs_req, *treq; 878 int index = hs_ep->index; 879 int ret; 880 int i; 881 u32 dma_reg; 882 u32 depctl; 883 u32 ctrl; 884 struct dwc2_dma_desc *desc; 885 886 if (list_empty(&hs_ep->queue)) { 887 dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__); 888 return; 889 } 890 891 /* Initialize descriptor chain by Host Busy status */ 892 for (i = 0; i < MAX_DMA_DESC_NUM_GENERIC; i++) { 893 desc = &hs_ep->desc_list[i]; 894 desc->status = 0; 895 desc->status |= (DEV_DMA_BUFF_STS_HBUSY 896 << DEV_DMA_BUFF_STS_SHIFT); 897 } 898 899 hs_ep->next_desc = 0; 900 list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) { 901 ret = dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma, 902 hs_req->req.length); 903 if (ret) 904 break; 905 } 906 907 hs_ep->compl_desc = 0; 908 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); 909 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index); 910 911 /* write descriptor chain address to control register */ 912 dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg); 913 914 ctrl = dwc2_readl(hsotg->regs + depctl); 915 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK; 916 dwc2_writel(ctrl, hsotg->regs + depctl); 917 } 918 919 /** 920 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue 921 * @hsotg: The controller state. 922 * @hs_ep: The endpoint to process a request for 923 * @hs_req: The request to start. 924 * @continuing: True if we are doing more for the current request. 925 * 926 * Start the given request running by setting the endpoint registers 927 * appropriately, and writing any data to the FIFOs. 928 */ 929 static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, 930 struct dwc2_hsotg_ep *hs_ep, 931 struct dwc2_hsotg_req *hs_req, 932 bool continuing) 933 { 934 struct usb_request *ureq = &hs_req->req; 935 int index = hs_ep->index; 936 int dir_in = hs_ep->dir_in; 937 u32 epctrl_reg; 938 u32 epsize_reg; 939 u32 epsize; 940 u32 ctrl; 941 unsigned int length; 942 unsigned int packets; 943 unsigned int maxreq; 944 unsigned int dma_reg; 945 946 if (index != 0) { 947 if (hs_ep->req && !continuing) { 948 dev_err(hsotg->dev, "%s: active request\n", __func__); 949 WARN_ON(1); 950 return; 951 } else if (hs_ep->req != hs_req && continuing) { 952 dev_err(hsotg->dev, 953 "%s: continue different req\n", __func__); 954 WARN_ON(1); 955 return; 956 } 957 } 958 959 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index); 960 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); 961 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); 962 963 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", 964 __func__, dwc2_readl(hsotg->regs + epctrl_reg), index, 965 hs_ep->dir_in ? "in" : "out"); 966 967 /* If endpoint is stalled, we will restart request later */ 968 ctrl = dwc2_readl(hsotg->regs + epctrl_reg); 969 970 if (index && ctrl & DXEPCTL_STALL) { 971 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); 972 return; 973 } 974 975 length = ureq->length - ureq->actual; 976 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n", 977 ureq->length, ureq->actual); 978 979 if (!using_desc_dma(hsotg)) 980 maxreq = get_ep_limit(hs_ep); 981 else 982 maxreq = dwc2_gadget_get_chain_limit(hs_ep); 983 984 if (length > maxreq) { 985 int round = maxreq % hs_ep->ep.maxpacket; 986 987 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n", 988 __func__, length, maxreq, round); 989 990 /* round down to multiple of packets */ 991 if (round) 992 maxreq -= round; 993 994 length = maxreq; 995 } 996 997 if (length) 998 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket); 999 else 1000 packets = 1; /* send one packet if length is zero. */ 1001 1002 if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) { 1003 dev_err(hsotg->dev, "req length > maxpacket*mc\n"); 1004 return; 1005 } 1006 1007 if (dir_in && index != 0) 1008 if (hs_ep->isochronous) 1009 epsize = DXEPTSIZ_MC(packets); 1010 else 1011 epsize = DXEPTSIZ_MC(1); 1012 else 1013 epsize = 0; 1014 1015 /* 1016 * zero length packet should be programmed on its own and should not 1017 * be counted in DIEPTSIZ.PktCnt with other packets. 1018 */ 1019 if (dir_in && ureq->zero && !continuing) { 1020 /* Test if zlp is actually required. */ 1021 if ((ureq->length >= hs_ep->ep.maxpacket) && 1022 !(ureq->length % hs_ep->ep.maxpacket)) 1023 hs_ep->send_zlp = 1; 1024 } 1025 1026 epsize |= DXEPTSIZ_PKTCNT(packets); 1027 epsize |= DXEPTSIZ_XFERSIZE(length); 1028 1029 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n", 1030 __func__, packets, length, ureq->length, epsize, epsize_reg); 1031 1032 /* store the request as the current one we're doing */ 1033 hs_ep->req = hs_req; 1034 1035 if (using_desc_dma(hsotg)) { 1036 u32 offset = 0; 1037 u32 mps = hs_ep->ep.maxpacket; 1038 1039 /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */ 1040 if (!dir_in) { 1041 if (!index) 1042 length = mps; 1043 else if (length % mps) 1044 length += (mps - (length % mps)); 1045 } 1046 1047 /* 1048 * If more data to send, adjust DMA for EP0 out data stage. 1049 * ureq->dma stays unchanged, hence increment it by already 1050 * passed passed data count before starting new transaction. 1051 */ 1052 if (!index && hsotg->ep0_state == DWC2_EP0_DATA_OUT && 1053 continuing) 1054 offset = ureq->actual; 1055 1056 /* Fill DDMA chain entries */ 1057 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset, 1058 length); 1059 1060 /* write descriptor chain address to control register */ 1061 dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg); 1062 1063 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n", 1064 __func__, (u32)hs_ep->desc_list_dma, dma_reg); 1065 } else { 1066 /* write size / packets */ 1067 dwc2_writel(epsize, hsotg->regs + epsize_reg); 1068 1069 if (using_dma(hsotg) && !continuing && (length != 0)) { 1070 /* 1071 * write DMA address to control register, buffer 1072 * already synced by dwc2_hsotg_ep_queue(). 1073 */ 1074 1075 dwc2_writel(ureq->dma, hsotg->regs + dma_reg); 1076 1077 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n", 1078 __func__, &ureq->dma, dma_reg); 1079 } 1080 } 1081 1082 if (hs_ep->isochronous && hs_ep->interval == 1) { 1083 hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg); 1084 dwc2_gadget_incr_frame_num(hs_ep); 1085 1086 if (hs_ep->target_frame & 0x1) 1087 ctrl |= DXEPCTL_SETODDFR; 1088 else 1089 ctrl |= DXEPCTL_SETEVENFR; 1090 } 1091 1092 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ 1093 1094 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state); 1095 1096 /* For Setup request do not clear NAK */ 1097 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP)) 1098 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ 1099 1100 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); 1101 dwc2_writel(ctrl, hsotg->regs + epctrl_reg); 1102 1103 /* 1104 * set these, it seems that DMA support increments past the end 1105 * of the packet buffer so we need to calculate the length from 1106 * this information. 1107 */ 1108 hs_ep->size_loaded = length; 1109 hs_ep->last_load = ureq->actual; 1110 1111 if (dir_in && !using_dma(hsotg)) { 1112 /* set these anyway, we may need them for non-periodic in */ 1113 hs_ep->fifo_load = 0; 1114 1115 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); 1116 } 1117 1118 /* 1119 * Note, trying to clear the NAK here causes problems with transmit 1120 * on the S3C6400 ending up with the TXFIFO becoming full. 1121 */ 1122 1123 /* check ep is enabled */ 1124 if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA)) 1125 dev_dbg(hsotg->dev, 1126 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", 1127 index, dwc2_readl(hsotg->regs + epctrl_reg)); 1128 1129 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", 1130 __func__, dwc2_readl(hsotg->regs + epctrl_reg)); 1131 1132 /* enable ep interrupts */ 1133 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1); 1134 } 1135 1136 /** 1137 * dwc2_hsotg_map_dma - map the DMA memory being used for the request 1138 * @hsotg: The device state. 1139 * @hs_ep: The endpoint the request is on. 1140 * @req: The request being processed. 1141 * 1142 * We've been asked to queue a request, so ensure that the memory buffer 1143 * is correctly setup for DMA. If we've been passed an extant DMA address 1144 * then ensure the buffer has been synced to memory. If our buffer has no 1145 * DMA memory, then we map the memory and mark our request to allow us to 1146 * cleanup on completion. 1147 */ 1148 static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg, 1149 struct dwc2_hsotg_ep *hs_ep, 1150 struct usb_request *req) 1151 { 1152 int ret; 1153 1154 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in); 1155 if (ret) 1156 goto dma_error; 1157 1158 return 0; 1159 1160 dma_error: 1161 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n", 1162 __func__, req->buf, req->length); 1163 1164 return -EIO; 1165 } 1166 1167 static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg, 1168 struct dwc2_hsotg_ep *hs_ep, 1169 struct dwc2_hsotg_req *hs_req) 1170 { 1171 void *req_buf = hs_req->req.buf; 1172 1173 /* If dma is not being used or buffer is aligned */ 1174 if (!using_dma(hsotg) || !((long)req_buf & 3)) 1175 return 0; 1176 1177 WARN_ON(hs_req->saved_req_buf); 1178 1179 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__, 1180 hs_ep->ep.name, req_buf, hs_req->req.length); 1181 1182 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC); 1183 if (!hs_req->req.buf) { 1184 hs_req->req.buf = req_buf; 1185 dev_err(hsotg->dev, 1186 "%s: unable to allocate memory for bounce buffer\n", 1187 __func__); 1188 return -ENOMEM; 1189 } 1190 1191 /* Save actual buffer */ 1192 hs_req->saved_req_buf = req_buf; 1193 1194 if (hs_ep->dir_in) 1195 memcpy(hs_req->req.buf, req_buf, hs_req->req.length); 1196 return 0; 1197 } 1198 1199 static void 1200 dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg, 1201 struct dwc2_hsotg_ep *hs_ep, 1202 struct dwc2_hsotg_req *hs_req) 1203 { 1204 /* If dma is not being used or buffer was aligned */ 1205 if (!using_dma(hsotg) || !hs_req->saved_req_buf) 1206 return; 1207 1208 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__, 1209 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual); 1210 1211 /* Copy data from bounce buffer on successful out transfer */ 1212 if (!hs_ep->dir_in && !hs_req->req.status) 1213 memcpy(hs_req->saved_req_buf, hs_req->req.buf, 1214 hs_req->req.actual); 1215 1216 /* Free bounce buffer */ 1217 kfree(hs_req->req.buf); 1218 1219 hs_req->req.buf = hs_req->saved_req_buf; 1220 hs_req->saved_req_buf = NULL; 1221 } 1222 1223 /** 1224 * dwc2_gadget_target_frame_elapsed - Checks target frame 1225 * @hs_ep: The driver endpoint to check 1226 * 1227 * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop 1228 * corresponding transfer. 1229 */ 1230 static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep) 1231 { 1232 struct dwc2_hsotg *hsotg = hs_ep->parent; 1233 u32 target_frame = hs_ep->target_frame; 1234 u32 current_frame = hsotg->frame_number; 1235 bool frame_overrun = hs_ep->frame_overrun; 1236 1237 if (!frame_overrun && current_frame >= target_frame) 1238 return true; 1239 1240 if (frame_overrun && current_frame >= target_frame && 1241 ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2)) 1242 return true; 1243 1244 return false; 1245 } 1246 1247 /* 1248 * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers 1249 * @hsotg: The driver state 1250 * @hs_ep: the ep descriptor chain is for 1251 * 1252 * Called to update EP0 structure's pointers depend on stage of 1253 * control transfer. 1254 */ 1255 static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg, 1256 struct dwc2_hsotg_ep *hs_ep) 1257 { 1258 switch (hsotg->ep0_state) { 1259 case DWC2_EP0_SETUP: 1260 case DWC2_EP0_STATUS_OUT: 1261 hs_ep->desc_list = hsotg->setup_desc[0]; 1262 hs_ep->desc_list_dma = hsotg->setup_desc_dma[0]; 1263 break; 1264 case DWC2_EP0_DATA_IN: 1265 case DWC2_EP0_STATUS_IN: 1266 hs_ep->desc_list = hsotg->ctrl_in_desc; 1267 hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma; 1268 break; 1269 case DWC2_EP0_DATA_OUT: 1270 hs_ep->desc_list = hsotg->ctrl_out_desc; 1271 hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma; 1272 break; 1273 default: 1274 dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n", 1275 hsotg->ep0_state); 1276 return -EINVAL; 1277 } 1278 1279 return 0; 1280 } 1281 1282 static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, 1283 gfp_t gfp_flags) 1284 { 1285 struct dwc2_hsotg_req *hs_req = our_req(req); 1286 struct dwc2_hsotg_ep *hs_ep = our_ep(ep); 1287 struct dwc2_hsotg *hs = hs_ep->parent; 1288 bool first; 1289 int ret; 1290 u32 maxsize = 0; 1291 u32 mask = 0; 1292 1293 1294 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n", 1295 ep->name, req, req->length, req->buf, req->no_interrupt, 1296 req->zero, req->short_not_ok); 1297 1298 /* Prevent new request submission when controller is suspended */ 1299 if (hs->lx_state != DWC2_L0) { 1300 dev_dbg(hs->dev, "%s: submit request only in active state\n", 1301 __func__); 1302 return -EAGAIN; 1303 } 1304 1305 /* initialise status of the request */ 1306 INIT_LIST_HEAD(&hs_req->queue); 1307 req->actual = 0; 1308 req->status = -EINPROGRESS; 1309 1310 /* In DDMA mode for ISOC's don't queue request if length greater 1311 * than descriptor limits. 1312 */ 1313 if (using_desc_dma(hs) && hs_ep->isochronous) { 1314 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); 1315 if (hs_ep->dir_in && req->length > maxsize) { 1316 dev_err(hs->dev, "wrong length %d (maxsize=%d)\n", 1317 req->length, maxsize); 1318 return -EINVAL; 1319 } 1320 1321 if (!hs_ep->dir_in && req->length > hs_ep->ep.maxpacket) { 1322 dev_err(hs->dev, "ISOC OUT: wrong length %d (mps=%d)\n", 1323 req->length, hs_ep->ep.maxpacket); 1324 return -EINVAL; 1325 } 1326 } 1327 1328 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req); 1329 if (ret) 1330 return ret; 1331 1332 /* if we're using DMA, sync the buffers as necessary */ 1333 if (using_dma(hs)) { 1334 ret = dwc2_hsotg_map_dma(hs, hs_ep, req); 1335 if (ret) 1336 return ret; 1337 } 1338 /* If using descriptor DMA configure EP0 descriptor chain pointers */ 1339 if (using_desc_dma(hs) && !hs_ep->index) { 1340 ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep); 1341 if (ret) 1342 return ret; 1343 } 1344 1345 first = list_empty(&hs_ep->queue); 1346 list_add_tail(&hs_req->queue, &hs_ep->queue); 1347 1348 /* 1349 * Handle DDMA isochronous transfers separately - just add new entry 1350 * to the descriptor chain. 1351 * Transfer will be started once SW gets either one of NAK or 1352 * OutTknEpDis interrupts. 1353 */ 1354 if (using_desc_dma(hs) && hs_ep->isochronous) { 1355 if (hs_ep->target_frame != TARGET_FRAME_INITIAL) { 1356 dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma, 1357 hs_req->req.length); 1358 } 1359 return 0; 1360 } 1361 1362 if (first) { 1363 if (!hs_ep->isochronous) { 1364 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); 1365 return 0; 1366 } 1367 1368 /* Update current frame number value. */ 1369 hs->frame_number = dwc2_hsotg_read_frameno(hs); 1370 while (dwc2_gadget_target_frame_elapsed(hs_ep)) { 1371 dwc2_gadget_incr_frame_num(hs_ep); 1372 /* Update current frame number value once more as it 1373 * changes here. 1374 */ 1375 hs->frame_number = dwc2_hsotg_read_frameno(hs); 1376 } 1377 1378 if (hs_ep->target_frame != TARGET_FRAME_INITIAL) 1379 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); 1380 } 1381 return 0; 1382 } 1383 1384 static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req, 1385 gfp_t gfp_flags) 1386 { 1387 struct dwc2_hsotg_ep *hs_ep = our_ep(ep); 1388 struct dwc2_hsotg *hs = hs_ep->parent; 1389 unsigned long flags = 0; 1390 int ret = 0; 1391 1392 spin_lock_irqsave(&hs->lock, flags); 1393 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags); 1394 spin_unlock_irqrestore(&hs->lock, flags); 1395 1396 return ret; 1397 } 1398 1399 static void dwc2_hsotg_ep_free_request(struct usb_ep *ep, 1400 struct usb_request *req) 1401 { 1402 struct dwc2_hsotg_req *hs_req = our_req(req); 1403 1404 kfree(hs_req); 1405 } 1406 1407 /** 1408 * dwc2_hsotg_complete_oursetup - setup completion callback 1409 * @ep: The endpoint the request was on. 1410 * @req: The request completed. 1411 * 1412 * Called on completion of any requests the driver itself 1413 * submitted that need cleaning up. 1414 */ 1415 static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep, 1416 struct usb_request *req) 1417 { 1418 struct dwc2_hsotg_ep *hs_ep = our_ep(ep); 1419 struct dwc2_hsotg *hsotg = hs_ep->parent; 1420 1421 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req); 1422 1423 dwc2_hsotg_ep_free_request(ep, req); 1424 } 1425 1426 /** 1427 * ep_from_windex - convert control wIndex value to endpoint 1428 * @hsotg: The driver state. 1429 * @windex: The control request wIndex field (in host order). 1430 * 1431 * Convert the given wIndex into a pointer to an driver endpoint 1432 * structure, or return NULL if it is not a valid endpoint. 1433 */ 1434 static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg, 1435 u32 windex) 1436 { 1437 struct dwc2_hsotg_ep *ep; 1438 int dir = (windex & USB_DIR_IN) ? 1 : 0; 1439 int idx = windex & 0x7F; 1440 1441 if (windex >= 0x100) 1442 return NULL; 1443 1444 if (idx > hsotg->num_of_eps) 1445 return NULL; 1446 1447 ep = index_to_ep(hsotg, idx, dir); 1448 1449 if (idx && ep->dir_in != dir) 1450 return NULL; 1451 1452 return ep; 1453 } 1454 1455 /** 1456 * dwc2_hsotg_set_test_mode - Enable usb Test Modes 1457 * @hsotg: The driver state. 1458 * @testmode: requested usb test mode 1459 * Enable usb Test Mode requested by the Host. 1460 */ 1461 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode) 1462 { 1463 int dctl = dwc2_readl(hsotg->regs + DCTL); 1464 1465 dctl &= ~DCTL_TSTCTL_MASK; 1466 switch (testmode) { 1467 case TEST_J: 1468 case TEST_K: 1469 case TEST_SE0_NAK: 1470 case TEST_PACKET: 1471 case TEST_FORCE_EN: 1472 dctl |= testmode << DCTL_TSTCTL_SHIFT; 1473 break; 1474 default: 1475 return -EINVAL; 1476 } 1477 dwc2_writel(dctl, hsotg->regs + DCTL); 1478 return 0; 1479 } 1480 1481 /** 1482 * dwc2_hsotg_send_reply - send reply to control request 1483 * @hsotg: The device state 1484 * @ep: Endpoint 0 1485 * @buff: Buffer for request 1486 * @length: Length of reply. 1487 * 1488 * Create a request and queue it on the given endpoint. This is useful as 1489 * an internal method of sending replies to certain control requests, etc. 1490 */ 1491 static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg, 1492 struct dwc2_hsotg_ep *ep, 1493 void *buff, 1494 int length) 1495 { 1496 struct usb_request *req; 1497 int ret; 1498 1499 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length); 1500 1501 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC); 1502 hsotg->ep0_reply = req; 1503 if (!req) { 1504 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__); 1505 return -ENOMEM; 1506 } 1507 1508 req->buf = hsotg->ep0_buff; 1509 req->length = length; 1510 /* 1511 * zero flag is for sending zlp in DATA IN stage. It has no impact on 1512 * STATUS stage. 1513 */ 1514 req->zero = 0; 1515 req->complete = dwc2_hsotg_complete_oursetup; 1516 1517 if (length) 1518 memcpy(req->buf, buff, length); 1519 1520 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC); 1521 if (ret) { 1522 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__); 1523 return ret; 1524 } 1525 1526 return 0; 1527 } 1528 1529 /** 1530 * dwc2_hsotg_process_req_status - process request GET_STATUS 1531 * @hsotg: The device state 1532 * @ctrl: USB control request 1533 */ 1534 static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg, 1535 struct usb_ctrlrequest *ctrl) 1536 { 1537 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; 1538 struct dwc2_hsotg_ep *ep; 1539 __le16 reply; 1540 int ret; 1541 1542 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__); 1543 1544 if (!ep0->dir_in) { 1545 dev_warn(hsotg->dev, "%s: direction out?\n", __func__); 1546 return -EINVAL; 1547 } 1548 1549 switch (ctrl->bRequestType & USB_RECIP_MASK) { 1550 case USB_RECIP_DEVICE: 1551 /* 1552 * bit 0 => self powered 1553 * bit 1 => remote wakeup 1554 */ 1555 reply = cpu_to_le16(0); 1556 break; 1557 1558 case USB_RECIP_INTERFACE: 1559 /* currently, the data result should be zero */ 1560 reply = cpu_to_le16(0); 1561 break; 1562 1563 case USB_RECIP_ENDPOINT: 1564 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex)); 1565 if (!ep) 1566 return -ENOENT; 1567 1568 reply = cpu_to_le16(ep->halted ? 1 : 0); 1569 break; 1570 1571 default: 1572 return 0; 1573 } 1574 1575 if (le16_to_cpu(ctrl->wLength) != 2) 1576 return -EINVAL; 1577 1578 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2); 1579 if (ret) { 1580 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__); 1581 return ret; 1582 } 1583 1584 return 1; 1585 } 1586 1587 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now); 1588 1589 /** 1590 * get_ep_head - return the first request on the endpoint 1591 * @hs_ep: The controller endpoint to get 1592 * 1593 * Get the first request on the endpoint. 1594 */ 1595 static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep) 1596 { 1597 return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req, 1598 queue); 1599 } 1600 1601 /** 1602 * dwc2_gadget_start_next_request - Starts next request from ep queue 1603 * @hs_ep: Endpoint structure 1604 * 1605 * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked 1606 * in its handler. Hence we need to unmask it here to be able to do 1607 * resynchronization. 1608 */ 1609 static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep) 1610 { 1611 u32 mask; 1612 struct dwc2_hsotg *hsotg = hs_ep->parent; 1613 int dir_in = hs_ep->dir_in; 1614 struct dwc2_hsotg_req *hs_req; 1615 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK; 1616 1617 if (!list_empty(&hs_ep->queue)) { 1618 hs_req = get_ep_head(hs_ep); 1619 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false); 1620 return; 1621 } 1622 if (!hs_ep->isochronous) 1623 return; 1624 1625 if (dir_in) { 1626 dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n", 1627 __func__); 1628 } else { 1629 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n", 1630 __func__); 1631 mask = dwc2_readl(hsotg->regs + epmsk_reg); 1632 mask |= DOEPMSK_OUTTKNEPDISMSK; 1633 dwc2_writel(mask, hsotg->regs + epmsk_reg); 1634 } 1635 } 1636 1637 /** 1638 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE 1639 * @hsotg: The device state 1640 * @ctrl: USB control request 1641 */ 1642 static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg, 1643 struct usb_ctrlrequest *ctrl) 1644 { 1645 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; 1646 struct dwc2_hsotg_req *hs_req; 1647 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE); 1648 struct dwc2_hsotg_ep *ep; 1649 int ret; 1650 bool halted; 1651 u32 recip; 1652 u32 wValue; 1653 u32 wIndex; 1654 1655 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n", 1656 __func__, set ? "SET" : "CLEAR"); 1657 1658 wValue = le16_to_cpu(ctrl->wValue); 1659 wIndex = le16_to_cpu(ctrl->wIndex); 1660 recip = ctrl->bRequestType & USB_RECIP_MASK; 1661 1662 switch (recip) { 1663 case USB_RECIP_DEVICE: 1664 switch (wValue) { 1665 case USB_DEVICE_REMOTE_WAKEUP: 1666 hsotg->remote_wakeup_allowed = 1; 1667 break; 1668 1669 case USB_DEVICE_TEST_MODE: 1670 if ((wIndex & 0xff) != 0) 1671 return -EINVAL; 1672 if (!set) 1673 return -EINVAL; 1674 1675 hsotg->test_mode = wIndex >> 8; 1676 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); 1677 if (ret) { 1678 dev_err(hsotg->dev, 1679 "%s: failed to send reply\n", __func__); 1680 return ret; 1681 } 1682 break; 1683 default: 1684 return -ENOENT; 1685 } 1686 break; 1687 1688 case USB_RECIP_ENDPOINT: 1689 ep = ep_from_windex(hsotg, wIndex); 1690 if (!ep) { 1691 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n", 1692 __func__, wIndex); 1693 return -ENOENT; 1694 } 1695 1696 switch (wValue) { 1697 case USB_ENDPOINT_HALT: 1698 halted = ep->halted; 1699 1700 dwc2_hsotg_ep_sethalt(&ep->ep, set, true); 1701 1702 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); 1703 if (ret) { 1704 dev_err(hsotg->dev, 1705 "%s: failed to send reply\n", __func__); 1706 return ret; 1707 } 1708 1709 /* 1710 * we have to complete all requests for ep if it was 1711 * halted, and the halt was cleared by CLEAR_FEATURE 1712 */ 1713 1714 if (!set && halted) { 1715 /* 1716 * If we have request in progress, 1717 * then complete it 1718 */ 1719 if (ep->req) { 1720 hs_req = ep->req; 1721 ep->req = NULL; 1722 list_del_init(&hs_req->queue); 1723 if (hs_req->req.complete) { 1724 spin_unlock(&hsotg->lock); 1725 usb_gadget_giveback_request( 1726 &ep->ep, &hs_req->req); 1727 spin_lock(&hsotg->lock); 1728 } 1729 } 1730 1731 /* If we have pending request, then start it */ 1732 if (!ep->req) 1733 dwc2_gadget_start_next_request(ep); 1734 } 1735 1736 break; 1737 1738 default: 1739 return -ENOENT; 1740 } 1741 break; 1742 default: 1743 return -ENOENT; 1744 } 1745 return 1; 1746 } 1747 1748 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg); 1749 1750 /** 1751 * dwc2_hsotg_stall_ep0 - stall ep0 1752 * @hsotg: The device state 1753 * 1754 * Set stall for ep0 as response for setup request. 1755 */ 1756 static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg) 1757 { 1758 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; 1759 u32 reg; 1760 u32 ctrl; 1761 1762 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in); 1763 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0; 1764 1765 /* 1766 * DxEPCTL_Stall will be cleared by EP once it has 1767 * taken effect, so no need to clear later. 1768 */ 1769 1770 ctrl = dwc2_readl(hsotg->regs + reg); 1771 ctrl |= DXEPCTL_STALL; 1772 ctrl |= DXEPCTL_CNAK; 1773 dwc2_writel(ctrl, hsotg->regs + reg); 1774 1775 dev_dbg(hsotg->dev, 1776 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n", 1777 ctrl, reg, dwc2_readl(hsotg->regs + reg)); 1778 1779 /* 1780 * complete won't be called, so we enqueue 1781 * setup request here 1782 */ 1783 dwc2_hsotg_enqueue_setup(hsotg); 1784 } 1785 1786 /** 1787 * dwc2_hsotg_process_control - process a control request 1788 * @hsotg: The device state 1789 * @ctrl: The control request received 1790 * 1791 * The controller has received the SETUP phase of a control request, and 1792 * needs to work out what to do next (and whether to pass it on to the 1793 * gadget driver). 1794 */ 1795 static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg, 1796 struct usb_ctrlrequest *ctrl) 1797 { 1798 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; 1799 int ret = 0; 1800 u32 dcfg; 1801 1802 dev_dbg(hsotg->dev, 1803 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n", 1804 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue, 1805 ctrl->wIndex, ctrl->wLength); 1806 1807 if (ctrl->wLength == 0) { 1808 ep0->dir_in = 1; 1809 hsotg->ep0_state = DWC2_EP0_STATUS_IN; 1810 } else if (ctrl->bRequestType & USB_DIR_IN) { 1811 ep0->dir_in = 1; 1812 hsotg->ep0_state = DWC2_EP0_DATA_IN; 1813 } else { 1814 ep0->dir_in = 0; 1815 hsotg->ep0_state = DWC2_EP0_DATA_OUT; 1816 } 1817 1818 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { 1819 switch (ctrl->bRequest) { 1820 case USB_REQ_SET_ADDRESS: 1821 hsotg->connected = 1; 1822 dcfg = dwc2_readl(hsotg->regs + DCFG); 1823 dcfg &= ~DCFG_DEVADDR_MASK; 1824 dcfg |= (le16_to_cpu(ctrl->wValue) << 1825 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK; 1826 dwc2_writel(dcfg, hsotg->regs + DCFG); 1827 1828 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); 1829 1830 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); 1831 return; 1832 1833 case USB_REQ_GET_STATUS: 1834 ret = dwc2_hsotg_process_req_status(hsotg, ctrl); 1835 break; 1836 1837 case USB_REQ_CLEAR_FEATURE: 1838 case USB_REQ_SET_FEATURE: 1839 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl); 1840 break; 1841 } 1842 } 1843 1844 /* as a fallback, try delivering it to the driver to deal with */ 1845 1846 if (ret == 0 && hsotg->driver) { 1847 spin_unlock(&hsotg->lock); 1848 ret = hsotg->driver->setup(&hsotg->gadget, ctrl); 1849 spin_lock(&hsotg->lock); 1850 if (ret < 0) 1851 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret); 1852 } 1853 1854 /* 1855 * the request is either unhandlable, or is not formatted correctly 1856 * so respond with a STALL for the status stage to indicate failure. 1857 */ 1858 1859 if (ret < 0) 1860 dwc2_hsotg_stall_ep0(hsotg); 1861 } 1862 1863 /** 1864 * dwc2_hsotg_complete_setup - completion of a setup transfer 1865 * @ep: The endpoint the request was on. 1866 * @req: The request completed. 1867 * 1868 * Called on completion of any requests the driver itself submitted for 1869 * EP0 setup packets 1870 */ 1871 static void dwc2_hsotg_complete_setup(struct usb_ep *ep, 1872 struct usb_request *req) 1873 { 1874 struct dwc2_hsotg_ep *hs_ep = our_ep(ep); 1875 struct dwc2_hsotg *hsotg = hs_ep->parent; 1876 1877 if (req->status < 0) { 1878 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status); 1879 return; 1880 } 1881 1882 spin_lock(&hsotg->lock); 1883 if (req->actual == 0) 1884 dwc2_hsotg_enqueue_setup(hsotg); 1885 else 1886 dwc2_hsotg_process_control(hsotg, req->buf); 1887 spin_unlock(&hsotg->lock); 1888 } 1889 1890 /** 1891 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets 1892 * @hsotg: The device state. 1893 * 1894 * Enqueue a request on EP0 if necessary to received any SETUP packets 1895 * received from the host. 1896 */ 1897 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg) 1898 { 1899 struct usb_request *req = hsotg->ctrl_req; 1900 struct dwc2_hsotg_req *hs_req = our_req(req); 1901 int ret; 1902 1903 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__); 1904 1905 req->zero = 0; 1906 req->length = 8; 1907 req->buf = hsotg->ctrl_buff; 1908 req->complete = dwc2_hsotg_complete_setup; 1909 1910 if (!list_empty(&hs_req->queue)) { 1911 dev_dbg(hsotg->dev, "%s already queued???\n", __func__); 1912 return; 1913 } 1914 1915 hsotg->eps_out[0]->dir_in = 0; 1916 hsotg->eps_out[0]->send_zlp = 0; 1917 hsotg->ep0_state = DWC2_EP0_SETUP; 1918 1919 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC); 1920 if (ret < 0) { 1921 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret); 1922 /* 1923 * Don't think there's much we can do other than watch the 1924 * driver fail. 1925 */ 1926 } 1927 } 1928 1929 static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg, 1930 struct dwc2_hsotg_ep *hs_ep) 1931 { 1932 u32 ctrl; 1933 u8 index = hs_ep->index; 1934 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); 1935 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); 1936 1937 if (hs_ep->dir_in) 1938 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n", 1939 index); 1940 else 1941 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n", 1942 index); 1943 if (using_desc_dma(hsotg)) { 1944 /* Not specific buffer needed for ep0 ZLP */ 1945 dma_addr_t dma = hs_ep->desc_list_dma; 1946 1947 if (!index) 1948 dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep); 1949 1950 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0); 1951 } else { 1952 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | 1953 DXEPTSIZ_XFERSIZE(0), hsotg->regs + 1954 epsiz_reg); 1955 } 1956 1957 ctrl = dwc2_readl(hsotg->regs + epctl_reg); 1958 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ 1959 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ 1960 ctrl |= DXEPCTL_USBACTEP; 1961 dwc2_writel(ctrl, hsotg->regs + epctl_reg); 1962 } 1963 1964 /** 1965 * dwc2_hsotg_complete_request - complete a request given to us 1966 * @hsotg: The device state. 1967 * @hs_ep: The endpoint the request was on. 1968 * @hs_req: The request to complete. 1969 * @result: The result code (0 => Ok, otherwise errno) 1970 * 1971 * The given request has finished, so call the necessary completion 1972 * if it has one and then look to see if we can start a new request 1973 * on the endpoint. 1974 * 1975 * Note, expects the ep to already be locked as appropriate. 1976 */ 1977 static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg, 1978 struct dwc2_hsotg_ep *hs_ep, 1979 struct dwc2_hsotg_req *hs_req, 1980 int result) 1981 { 1982 if (!hs_req) { 1983 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__); 1984 return; 1985 } 1986 1987 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n", 1988 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete); 1989 1990 /* 1991 * only replace the status if we've not already set an error 1992 * from a previous transaction 1993 */ 1994 1995 if (hs_req->req.status == -EINPROGRESS) 1996 hs_req->req.status = result; 1997 1998 if (using_dma(hsotg)) 1999 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req); 2000 2001 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req); 2002 2003 hs_ep->req = NULL; 2004 list_del_init(&hs_req->queue); 2005 2006 /* 2007 * call the complete request with the locks off, just in case the 2008 * request tries to queue more work for this endpoint. 2009 */ 2010 2011 if (hs_req->req.complete) { 2012 spin_unlock(&hsotg->lock); 2013 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req); 2014 spin_lock(&hsotg->lock); 2015 } 2016 2017 /* In DDMA don't need to proceed to starting of next ISOC request */ 2018 if (using_desc_dma(hsotg) && hs_ep->isochronous) 2019 return; 2020 2021 /* 2022 * Look to see if there is anything else to do. Note, the completion 2023 * of the previous request may have caused a new request to be started 2024 * so be careful when doing this. 2025 */ 2026 2027 if (!hs_ep->req && result >= 0) 2028 dwc2_gadget_start_next_request(hs_ep); 2029 } 2030 2031 /* 2032 * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA 2033 * @hs_ep: The endpoint the request was on. 2034 * 2035 * Get first request from the ep queue, determine descriptor on which complete 2036 * happened. SW discovers which descriptor currently in use by HW, adjusts 2037 * dma_address and calculates index of completed descriptor based on the value 2038 * of DEPDMA register. Update actual length of request, giveback to gadget. 2039 */ 2040 static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep) 2041 { 2042 struct dwc2_hsotg *hsotg = hs_ep->parent; 2043 struct dwc2_hsotg_req *hs_req; 2044 struct usb_request *ureq; 2045 u32 desc_sts; 2046 u32 mask; 2047 2048 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status; 2049 2050 /* Process only descriptors with buffer status set to DMA done */ 2051 while ((desc_sts & DEV_DMA_BUFF_STS_MASK) >> 2052 DEV_DMA_BUFF_STS_SHIFT == DEV_DMA_BUFF_STS_DMADONE) { 2053 2054 hs_req = get_ep_head(hs_ep); 2055 if (!hs_req) { 2056 dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__); 2057 return; 2058 } 2059 ureq = &hs_req->req; 2060 2061 /* Check completion status */ 2062 if ((desc_sts & DEV_DMA_STS_MASK) >> DEV_DMA_STS_SHIFT == 2063 DEV_DMA_STS_SUCC) { 2064 mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK : 2065 DEV_DMA_ISOC_RX_NBYTES_MASK; 2066 ureq->actual = ureq->length - ((desc_sts & mask) >> 2067 DEV_DMA_ISOC_NBYTES_SHIFT); 2068 2069 /* Adjust actual len for ISOC Out if len is 2070 * not align of 4 2071 */ 2072 if (!hs_ep->dir_in && ureq->length & 0x3) 2073 ureq->actual += 4 - (ureq->length & 0x3); 2074 } 2075 2076 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); 2077 2078 hs_ep->compl_desc++; 2079 if (hs_ep->compl_desc > (MAX_DMA_DESC_NUM_GENERIC - 1)) 2080 hs_ep->compl_desc = 0; 2081 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status; 2082 } 2083 } 2084 2085 /* 2086 * dwc2_gadget_handle_isoc_bna - handle BNA interrupt for ISOC. 2087 * @hs_ep: The isochronous endpoint. 2088 * 2089 * If EP ISOC OUT then need to flush RX FIFO to remove source of BNA 2090 * interrupt. Reset target frame and next_desc to allow to start 2091 * ISOC's on NAK interrupt for IN direction or on OUTTKNEPDIS 2092 * interrupt for OUT direction. 2093 */ 2094 static void dwc2_gadget_handle_isoc_bna(struct dwc2_hsotg_ep *hs_ep) 2095 { 2096 struct dwc2_hsotg *hsotg = hs_ep->parent; 2097 2098 if (!hs_ep->dir_in) 2099 dwc2_flush_rx_fifo(hsotg); 2100 dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0); 2101 2102 hs_ep->target_frame = TARGET_FRAME_INITIAL; 2103 hs_ep->next_desc = 0; 2104 hs_ep->compl_desc = 0; 2105 } 2106 2107 /** 2108 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint 2109 * @hsotg: The device state. 2110 * @ep_idx: The endpoint index for the data 2111 * @size: The size of data in the fifo, in bytes 2112 * 2113 * The FIFO status shows there is data to read from the FIFO for a given 2114 * endpoint, so sort out whether we need to read the data into a request 2115 * that has been made for that endpoint. 2116 */ 2117 static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size) 2118 { 2119 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx]; 2120 struct dwc2_hsotg_req *hs_req = hs_ep->req; 2121 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx); 2122 int to_read; 2123 int max_req; 2124 int read_ptr; 2125 2126 if (!hs_req) { 2127 u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx)); 2128 int ptr; 2129 2130 dev_dbg(hsotg->dev, 2131 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n", 2132 __func__, size, ep_idx, epctl); 2133 2134 /* dump the data from the FIFO, we've nothing we can do */ 2135 for (ptr = 0; ptr < size; ptr += 4) 2136 (void)dwc2_readl(fifo); 2137 2138 return; 2139 } 2140 2141 to_read = size; 2142 read_ptr = hs_req->req.actual; 2143 max_req = hs_req->req.length - read_ptr; 2144 2145 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n", 2146 __func__, to_read, max_req, read_ptr, hs_req->req.length); 2147 2148 if (to_read > max_req) { 2149 /* 2150 * more data appeared than we where willing 2151 * to deal with in this request. 2152 */ 2153 2154 /* currently we don't deal this */ 2155 WARN_ON_ONCE(1); 2156 } 2157 2158 hs_ep->total_data += to_read; 2159 hs_req->req.actual += to_read; 2160 to_read = DIV_ROUND_UP(to_read, 4); 2161 2162 /* 2163 * note, we might over-write the buffer end by 3 bytes depending on 2164 * alignment of the data. 2165 */ 2166 ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read); 2167 } 2168 2169 /** 2170 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint 2171 * @hsotg: The device instance 2172 * @dir_in: If IN zlp 2173 * 2174 * Generate a zero-length IN packet request for terminating a SETUP 2175 * transaction. 2176 * 2177 * Note, since we don't write any data to the TxFIFO, then it is 2178 * currently believed that we do not need to wait for any space in 2179 * the TxFIFO. 2180 */ 2181 static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in) 2182 { 2183 /* eps_out[0] is used in both directions */ 2184 hsotg->eps_out[0]->dir_in = dir_in; 2185 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT; 2186 2187 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]); 2188 } 2189 2190 static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg, 2191 u32 epctl_reg) 2192 { 2193 u32 ctrl; 2194 2195 ctrl = dwc2_readl(hsotg->regs + epctl_reg); 2196 if (ctrl & DXEPCTL_EOFRNUM) 2197 ctrl |= DXEPCTL_SETEVENFR; 2198 else 2199 ctrl |= DXEPCTL_SETODDFR; 2200 dwc2_writel(ctrl, hsotg->regs + epctl_reg); 2201 } 2202 2203 /* 2204 * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc 2205 * @hs_ep - The endpoint on which transfer went 2206 * 2207 * Iterate over endpoints descriptor chain and get info on bytes remained 2208 * in DMA descriptors after transfer has completed. Used for non isoc EPs. 2209 */ 2210 static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep) 2211 { 2212 struct dwc2_hsotg *hsotg = hs_ep->parent; 2213 unsigned int bytes_rem = 0; 2214 struct dwc2_dma_desc *desc = hs_ep->desc_list; 2215 int i; 2216 u32 status; 2217 2218 if (!desc) 2219 return -EINVAL; 2220 2221 for (i = 0; i < hs_ep->desc_count; ++i) { 2222 status = desc->status; 2223 bytes_rem += status & DEV_DMA_NBYTES_MASK; 2224 2225 if (status & DEV_DMA_STS_MASK) 2226 dev_err(hsotg->dev, "descriptor %d closed with %x\n", 2227 i, status & DEV_DMA_STS_MASK); 2228 } 2229 2230 return bytes_rem; 2231 } 2232 2233 /** 2234 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO 2235 * @hsotg: The device instance 2236 * @epnum: The endpoint received from 2237 * 2238 * The RXFIFO has delivered an OutDone event, which means that the data 2239 * transfer for an OUT endpoint has been completed, either by a short 2240 * packet or by the finish of a transfer. 2241 */ 2242 static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) 2243 { 2244 u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum)); 2245 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum]; 2246 struct dwc2_hsotg_req *hs_req = hs_ep->req; 2247 struct usb_request *req = &hs_req->req; 2248 unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize); 2249 int result = 0; 2250 2251 if (!hs_req) { 2252 dev_dbg(hsotg->dev, "%s: no request active\n", __func__); 2253 return; 2254 } 2255 2256 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) { 2257 dev_dbg(hsotg->dev, "zlp packet received\n"); 2258 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); 2259 dwc2_hsotg_enqueue_setup(hsotg); 2260 return; 2261 } 2262 2263 if (using_desc_dma(hsotg)) 2264 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep); 2265 2266 if (using_dma(hsotg)) { 2267 unsigned int size_done; 2268 2269 /* 2270 * Calculate the size of the transfer by checking how much 2271 * is left in the endpoint size register and then working it 2272 * out from the amount we loaded for the transfer. 2273 * 2274 * We need to do this as DMA pointers are always 32bit aligned 2275 * so may overshoot/undershoot the transfer. 2276 */ 2277 2278 size_done = hs_ep->size_loaded - size_left; 2279 size_done += hs_ep->last_load; 2280 2281 req->actual = size_done; 2282 } 2283 2284 /* if there is more request to do, schedule new transfer */ 2285 if (req->actual < req->length && size_left == 0) { 2286 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); 2287 return; 2288 } 2289 2290 if (req->actual < req->length && req->short_not_ok) { 2291 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n", 2292 __func__, req->actual, req->length); 2293 2294 /* 2295 * todo - what should we return here? there's no one else 2296 * even bothering to check the status. 2297 */ 2298 } 2299 2300 /* DDMA IN status phase will start from StsPhseRcvd interrupt */ 2301 if (!using_desc_dma(hsotg) && epnum == 0 && 2302 hsotg->ep0_state == DWC2_EP0_DATA_OUT) { 2303 /* Move to STATUS IN */ 2304 dwc2_hsotg_ep0_zlp(hsotg, true); 2305 return; 2306 } 2307 2308 /* 2309 * Slave mode OUT transfers do not go through XferComplete so 2310 * adjust the ISOC parity here. 2311 */ 2312 if (!using_dma(hsotg)) { 2313 if (hs_ep->isochronous && hs_ep->interval == 1) 2314 dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum)); 2315 else if (hs_ep->isochronous && hs_ep->interval > 1) 2316 dwc2_gadget_incr_frame_num(hs_ep); 2317 } 2318 2319 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result); 2320 } 2321 2322 /** 2323 * dwc2_hsotg_handle_rx - RX FIFO has data 2324 * @hsotg: The device instance 2325 * 2326 * The IRQ handler has detected that the RX FIFO has some data in it 2327 * that requires processing, so find out what is in there and do the 2328 * appropriate read. 2329 * 2330 * The RXFIFO is a true FIFO, the packets coming out are still in packet 2331 * chunks, so if you have x packets received on an endpoint you'll get x 2332 * FIFO events delivered, each with a packet's worth of data in it. 2333 * 2334 * When using DMA, we should not be processing events from the RXFIFO 2335 * as the actual data should be sent to the memory directly and we turn 2336 * on the completion interrupts to get notifications of transfer completion. 2337 */ 2338 static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg) 2339 { 2340 u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP); 2341 u32 epnum, status, size; 2342 2343 WARN_ON(using_dma(hsotg)); 2344 2345 epnum = grxstsr & GRXSTS_EPNUM_MASK; 2346 status = grxstsr & GRXSTS_PKTSTS_MASK; 2347 2348 size = grxstsr & GRXSTS_BYTECNT_MASK; 2349 size >>= GRXSTS_BYTECNT_SHIFT; 2350 2351 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n", 2352 __func__, grxstsr, size, epnum); 2353 2354 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) { 2355 case GRXSTS_PKTSTS_GLOBALOUTNAK: 2356 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n"); 2357 break; 2358 2359 case GRXSTS_PKTSTS_OUTDONE: 2360 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n", 2361 dwc2_hsotg_read_frameno(hsotg)); 2362 2363 if (!using_dma(hsotg)) 2364 dwc2_hsotg_handle_outdone(hsotg, epnum); 2365 break; 2366 2367 case GRXSTS_PKTSTS_SETUPDONE: 2368 dev_dbg(hsotg->dev, 2369 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", 2370 dwc2_hsotg_read_frameno(hsotg), 2371 dwc2_readl(hsotg->regs + DOEPCTL(0))); 2372 /* 2373 * Call dwc2_hsotg_handle_outdone here if it was not called from 2374 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't 2375 * generate GRXSTS_PKTSTS_OUTDONE for setup packet. 2376 */ 2377 if (hsotg->ep0_state == DWC2_EP0_SETUP) 2378 dwc2_hsotg_handle_outdone(hsotg, epnum); 2379 break; 2380 2381 case GRXSTS_PKTSTS_OUTRX: 2382 dwc2_hsotg_rx_data(hsotg, epnum, size); 2383 break; 2384 2385 case GRXSTS_PKTSTS_SETUPRX: 2386 dev_dbg(hsotg->dev, 2387 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", 2388 dwc2_hsotg_read_frameno(hsotg), 2389 dwc2_readl(hsotg->regs + DOEPCTL(0))); 2390 2391 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP); 2392 2393 dwc2_hsotg_rx_data(hsotg, epnum, size); 2394 break; 2395 2396 default: 2397 dev_warn(hsotg->dev, "%s: unknown status %08x\n", 2398 __func__, grxstsr); 2399 2400 dwc2_hsotg_dump(hsotg); 2401 break; 2402 } 2403 } 2404 2405 /** 2406 * dwc2_hsotg_ep0_mps - turn max packet size into register setting 2407 * @mps: The maximum packet size in bytes. 2408 */ 2409 static u32 dwc2_hsotg_ep0_mps(unsigned int mps) 2410 { 2411 switch (mps) { 2412 case 64: 2413 return D0EPCTL_MPS_64; 2414 case 32: 2415 return D0EPCTL_MPS_32; 2416 case 16: 2417 return D0EPCTL_MPS_16; 2418 case 8: 2419 return D0EPCTL_MPS_8; 2420 } 2421 2422 /* bad max packet size, warn and return invalid result */ 2423 WARN_ON(1); 2424 return (u32)-1; 2425 } 2426 2427 /** 2428 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field 2429 * @hsotg: The driver state. 2430 * @ep: The index number of the endpoint 2431 * @mps: The maximum packet size in bytes 2432 * @mc: The multicount value 2433 * @dir_in: True if direction is in. 2434 * 2435 * Configure the maximum packet size for the given endpoint, updating 2436 * the hardware control registers to reflect this. 2437 */ 2438 static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg, 2439 unsigned int ep, unsigned int mps, 2440 unsigned int mc, unsigned int dir_in) 2441 { 2442 struct dwc2_hsotg_ep *hs_ep; 2443 void __iomem *regs = hsotg->regs; 2444 u32 reg; 2445 2446 hs_ep = index_to_ep(hsotg, ep, dir_in); 2447 if (!hs_ep) 2448 return; 2449 2450 if (ep == 0) { 2451 u32 mps_bytes = mps; 2452 2453 /* EP0 is a special case */ 2454 mps = dwc2_hsotg_ep0_mps(mps_bytes); 2455 if (mps > 3) 2456 goto bad_mps; 2457 hs_ep->ep.maxpacket = mps_bytes; 2458 hs_ep->mc = 1; 2459 } else { 2460 if (mps > 1024) 2461 goto bad_mps; 2462 hs_ep->mc = mc; 2463 if (mc > 3) 2464 goto bad_mps; 2465 hs_ep->ep.maxpacket = mps; 2466 } 2467 2468 if (dir_in) { 2469 reg = dwc2_readl(regs + DIEPCTL(ep)); 2470 reg &= ~DXEPCTL_MPS_MASK; 2471 reg |= mps; 2472 dwc2_writel(reg, regs + DIEPCTL(ep)); 2473 } else { 2474 reg = dwc2_readl(regs + DOEPCTL(ep)); 2475 reg &= ~DXEPCTL_MPS_MASK; 2476 reg |= mps; 2477 dwc2_writel(reg, regs + DOEPCTL(ep)); 2478 } 2479 2480 return; 2481 2482 bad_mps: 2483 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps); 2484 } 2485 2486 /** 2487 * dwc2_hsotg_txfifo_flush - flush Tx FIFO 2488 * @hsotg: The driver state 2489 * @idx: The index for the endpoint (0..15) 2490 */ 2491 static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx) 2492 { 2493 dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, 2494 hsotg->regs + GRSTCTL); 2495 2496 /* wait until the fifo is flushed */ 2497 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100)) 2498 dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n", 2499 __func__); 2500 } 2501 2502 /** 2503 * dwc2_hsotg_trytx - check to see if anything needs transmitting 2504 * @hsotg: The driver state 2505 * @hs_ep: The driver endpoint to check. 2506 * 2507 * Check to see if there is a request that has data to send, and if so 2508 * make an attempt to write data into the FIFO. 2509 */ 2510 static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg, 2511 struct dwc2_hsotg_ep *hs_ep) 2512 { 2513 struct dwc2_hsotg_req *hs_req = hs_ep->req; 2514 2515 if (!hs_ep->dir_in || !hs_req) { 2516 /** 2517 * if request is not enqueued, we disable interrupts 2518 * for endpoints, excepting ep0 2519 */ 2520 if (hs_ep->index != 0) 2521 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, 2522 hs_ep->dir_in, 0); 2523 return 0; 2524 } 2525 2526 if (hs_req->req.actual < hs_req->req.length) { 2527 dev_dbg(hsotg->dev, "trying to write more for ep%d\n", 2528 hs_ep->index); 2529 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); 2530 } 2531 2532 return 0; 2533 } 2534 2535 /** 2536 * dwc2_hsotg_complete_in - complete IN transfer 2537 * @hsotg: The device state. 2538 * @hs_ep: The endpoint that has just completed. 2539 * 2540 * An IN transfer has been completed, update the transfer's state and then 2541 * call the relevant completion routines. 2542 */ 2543 static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg, 2544 struct dwc2_hsotg_ep *hs_ep) 2545 { 2546 struct dwc2_hsotg_req *hs_req = hs_ep->req; 2547 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); 2548 int size_left, size_done; 2549 2550 if (!hs_req) { 2551 dev_dbg(hsotg->dev, "XferCompl but no req\n"); 2552 return; 2553 } 2554 2555 /* Finish ZLP handling for IN EP0 transactions */ 2556 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) { 2557 dev_dbg(hsotg->dev, "zlp packet sent\n"); 2558 2559 /* 2560 * While send zlp for DWC2_EP0_STATUS_IN EP direction was 2561 * changed to IN. Change back to complete OUT transfer request 2562 */ 2563 hs_ep->dir_in = 0; 2564 2565 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); 2566 if (hsotg->test_mode) { 2567 int ret; 2568 2569 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode); 2570 if (ret < 0) { 2571 dev_dbg(hsotg->dev, "Invalid Test #%d\n", 2572 hsotg->test_mode); 2573 dwc2_hsotg_stall_ep0(hsotg); 2574 return; 2575 } 2576 } 2577 dwc2_hsotg_enqueue_setup(hsotg); 2578 return; 2579 } 2580 2581 /* 2582 * Calculate the size of the transfer by checking how much is left 2583 * in the endpoint size register and then working it out from 2584 * the amount we loaded for the transfer. 2585 * 2586 * We do this even for DMA, as the transfer may have incremented 2587 * past the end of the buffer (DMA transfers are always 32bit 2588 * aligned). 2589 */ 2590 if (using_desc_dma(hsotg)) { 2591 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep); 2592 if (size_left < 0) 2593 dev_err(hsotg->dev, "error parsing DDMA results %d\n", 2594 size_left); 2595 } else { 2596 size_left = DXEPTSIZ_XFERSIZE_GET(epsize); 2597 } 2598 2599 size_done = hs_ep->size_loaded - size_left; 2600 size_done += hs_ep->last_load; 2601 2602 if (hs_req->req.actual != size_done) 2603 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n", 2604 __func__, hs_req->req.actual, size_done); 2605 2606 hs_req->req.actual = size_done; 2607 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n", 2608 hs_req->req.length, hs_req->req.actual, hs_req->req.zero); 2609 2610 if (!size_left && hs_req->req.actual < hs_req->req.length) { 2611 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__); 2612 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); 2613 return; 2614 } 2615 2616 /* Zlp for all endpoints, for ep0 only in DATA IN stage */ 2617 if (hs_ep->send_zlp) { 2618 dwc2_hsotg_program_zlp(hsotg, hs_ep); 2619 hs_ep->send_zlp = 0; 2620 /* transfer will be completed on next complete interrupt */ 2621 return; 2622 } 2623 2624 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) { 2625 /* Move to STATUS OUT */ 2626 dwc2_hsotg_ep0_zlp(hsotg, false); 2627 return; 2628 } 2629 2630 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); 2631 } 2632 2633 /** 2634 * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep 2635 * @hsotg: The device state. 2636 * @idx: Index of ep. 2637 * @dir_in: Endpoint direction 1-in 0-out. 2638 * 2639 * Reads for endpoint with given index and direction, by masking 2640 * epint_reg with coresponding mask. 2641 */ 2642 static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg, 2643 unsigned int idx, int dir_in) 2644 { 2645 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK; 2646 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); 2647 u32 ints; 2648 u32 mask; 2649 u32 diepempmsk; 2650 2651 mask = dwc2_readl(hsotg->regs + epmsk_reg); 2652 diepempmsk = dwc2_readl(hsotg->regs + DIEPEMPMSK); 2653 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0; 2654 mask |= DXEPINT_SETUP_RCVD; 2655 2656 ints = dwc2_readl(hsotg->regs + epint_reg); 2657 ints &= mask; 2658 return ints; 2659 } 2660 2661 /** 2662 * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD 2663 * @hs_ep: The endpoint on which interrupt is asserted. 2664 * 2665 * This interrupt indicates that the endpoint has been disabled per the 2666 * application's request. 2667 * 2668 * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK, 2669 * in case of ISOC completes current request. 2670 * 2671 * For ISOC-OUT endpoints completes expired requests. If there is remaining 2672 * request starts it. 2673 */ 2674 static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep) 2675 { 2676 struct dwc2_hsotg *hsotg = hs_ep->parent; 2677 struct dwc2_hsotg_req *hs_req; 2678 unsigned char idx = hs_ep->index; 2679 int dir_in = hs_ep->dir_in; 2680 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); 2681 int dctl = dwc2_readl(hsotg->regs + DCTL); 2682 2683 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); 2684 2685 if (dir_in) { 2686 int epctl = dwc2_readl(hsotg->regs + epctl_reg); 2687 2688 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index); 2689 2690 if (hs_ep->isochronous) { 2691 dwc2_hsotg_complete_in(hsotg, hs_ep); 2692 return; 2693 } 2694 2695 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) { 2696 int dctl = dwc2_readl(hsotg->regs + DCTL); 2697 2698 dctl |= DCTL_CGNPINNAK; 2699 dwc2_writel(dctl, hsotg->regs + DCTL); 2700 } 2701 return; 2702 } 2703 2704 if (dctl & DCTL_GOUTNAKSTS) { 2705 dctl |= DCTL_CGOUTNAK; 2706 dwc2_writel(dctl, hsotg->regs + DCTL); 2707 } 2708 2709 if (!hs_ep->isochronous) 2710 return; 2711 2712 if (list_empty(&hs_ep->queue)) { 2713 dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n", 2714 __func__, hs_ep); 2715 return; 2716 } 2717 2718 do { 2719 hs_req = get_ep_head(hs_ep); 2720 if (hs_req) 2721 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 2722 -ENODATA); 2723 dwc2_gadget_incr_frame_num(hs_ep); 2724 /* Update current frame number value. */ 2725 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg); 2726 } while (dwc2_gadget_target_frame_elapsed(hs_ep)); 2727 2728 dwc2_gadget_start_next_request(hs_ep); 2729 } 2730 2731 /** 2732 * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS 2733 * @ep: The endpoint on which interrupt is asserted. 2734 * 2735 * This is starting point for ISOC-OUT transfer, synchronization done with 2736 * first out token received from host while corresponding EP is disabled. 2737 * 2738 * Device does not know initial frame in which out token will come. For this 2739 * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon 2740 * getting this interrupt SW starts calculation for next transfer frame. 2741 */ 2742 static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep) 2743 { 2744 struct dwc2_hsotg *hsotg = ep->parent; 2745 int dir_in = ep->dir_in; 2746 u32 doepmsk; 2747 u32 tmp; 2748 2749 if (dir_in || !ep->isochronous) 2750 return; 2751 2752 /* 2753 * Store frame in which irq was asserted here, as 2754 * it can change while completing request below. 2755 */ 2756 tmp = dwc2_hsotg_read_frameno(hsotg); 2757 2758 dwc2_hsotg_complete_request(hsotg, ep, get_ep_head(ep), 0); 2759 2760 if (using_desc_dma(hsotg)) { 2761 if (ep->target_frame == TARGET_FRAME_INITIAL) { 2762 /* Start first ISO Out */ 2763 ep->target_frame = tmp; 2764 dwc2_gadget_start_isoc_ddma(ep); 2765 } 2766 return; 2767 } 2768 2769 if (ep->interval > 1 && 2770 ep->target_frame == TARGET_FRAME_INITIAL) { 2771 u32 dsts; 2772 u32 ctrl; 2773 2774 dsts = dwc2_readl(hsotg->regs + DSTS); 2775 ep->target_frame = dwc2_hsotg_read_frameno(hsotg); 2776 dwc2_gadget_incr_frame_num(ep); 2777 2778 ctrl = dwc2_readl(hsotg->regs + DOEPCTL(ep->index)); 2779 if (ep->target_frame & 0x1) 2780 ctrl |= DXEPCTL_SETODDFR; 2781 else 2782 ctrl |= DXEPCTL_SETEVENFR; 2783 2784 dwc2_writel(ctrl, hsotg->regs + DOEPCTL(ep->index)); 2785 } 2786 2787 dwc2_gadget_start_next_request(ep); 2788 doepmsk = dwc2_readl(hsotg->regs + DOEPMSK); 2789 doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK; 2790 dwc2_writel(doepmsk, hsotg->regs + DOEPMSK); 2791 } 2792 2793 /** 2794 * dwc2_gadget_handle_nak - handle NAK interrupt 2795 * @hs_ep: The endpoint on which interrupt is asserted. 2796 * 2797 * This is starting point for ISOC-IN transfer, synchronization done with 2798 * first IN token received from host while corresponding EP is disabled. 2799 * 2800 * Device does not know when first one token will arrive from host. On first 2801 * token arrival HW generates 2 interrupts: 'in token received while FIFO empty' 2802 * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was 2803 * sent in response to that as there was no data in FIFO. SW is basing on this 2804 * interrupt to obtain frame in which token has come and then based on the 2805 * interval calculates next frame for transfer. 2806 */ 2807 static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep) 2808 { 2809 struct dwc2_hsotg *hsotg = hs_ep->parent; 2810 int dir_in = hs_ep->dir_in; 2811 u32 tmp; 2812 2813 if (!dir_in || !hs_ep->isochronous) 2814 return; 2815 2816 if (hs_ep->target_frame == TARGET_FRAME_INITIAL) { 2817 2818 tmp = dwc2_hsotg_read_frameno(hsotg); 2819 if (using_desc_dma(hsotg)) { 2820 dwc2_hsotg_complete_request(hsotg, hs_ep, 2821 get_ep_head(hs_ep), 0); 2822 2823 hs_ep->target_frame = tmp; 2824 dwc2_gadget_incr_frame_num(hs_ep); 2825 dwc2_gadget_start_isoc_ddma(hs_ep); 2826 return; 2827 } 2828 2829 hs_ep->target_frame = tmp; 2830 if (hs_ep->interval > 1) { 2831 u32 ctrl = dwc2_readl(hsotg->regs + 2832 DIEPCTL(hs_ep->index)); 2833 if (hs_ep->target_frame & 0x1) 2834 ctrl |= DXEPCTL_SETODDFR; 2835 else 2836 ctrl |= DXEPCTL_SETEVENFR; 2837 2838 dwc2_writel(ctrl, hsotg->regs + DIEPCTL(hs_ep->index)); 2839 } 2840 2841 dwc2_hsotg_complete_request(hsotg, hs_ep, 2842 get_ep_head(hs_ep), 0); 2843 } 2844 2845 if (!using_desc_dma(hsotg)) 2846 dwc2_gadget_incr_frame_num(hs_ep); 2847 } 2848 2849 /** 2850 * dwc2_hsotg_epint - handle an in/out endpoint interrupt 2851 * @hsotg: The driver state 2852 * @idx: The index for the endpoint (0..15) 2853 * @dir_in: Set if this is an IN endpoint 2854 * 2855 * Process and clear any interrupt pending for an individual endpoint 2856 */ 2857 static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, 2858 int dir_in) 2859 { 2860 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in); 2861 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); 2862 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); 2863 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx); 2864 u32 ints; 2865 u32 ctrl; 2866 2867 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in); 2868 ctrl = dwc2_readl(hsotg->regs + epctl_reg); 2869 2870 /* Clear endpoint interrupts */ 2871 dwc2_writel(ints, hsotg->regs + epint_reg); 2872 2873 if (!hs_ep) { 2874 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n", 2875 __func__, idx, dir_in ? "in" : "out"); 2876 return; 2877 } 2878 2879 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n", 2880 __func__, idx, dir_in ? "in" : "out", ints); 2881 2882 /* Don't process XferCompl interrupt if it is a setup packet */ 2883 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD))) 2884 ints &= ~DXEPINT_XFERCOMPL; 2885 2886 /* 2887 * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP 2888 * stage and xfercomplete was generated without SETUP phase done 2889 * interrupt. SW should parse received setup packet only after host's 2890 * exit from setup phase of control transfer. 2891 */ 2892 if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in && 2893 hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP)) 2894 ints &= ~DXEPINT_XFERCOMPL; 2895 2896 if (ints & DXEPINT_XFERCOMPL) { 2897 dev_dbg(hsotg->dev, 2898 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n", 2899 __func__, dwc2_readl(hsotg->regs + epctl_reg), 2900 dwc2_readl(hsotg->regs + epsiz_reg)); 2901 2902 /* In DDMA handle isochronous requests separately */ 2903 if (using_desc_dma(hsotg) && hs_ep->isochronous) { 2904 /* XferCompl set along with BNA */ 2905 if (!(ints & DXEPINT_BNAINTR)) 2906 dwc2_gadget_complete_isoc_request_ddma(hs_ep); 2907 } else if (dir_in) { 2908 /* 2909 * We get OutDone from the FIFO, so we only 2910 * need to look at completing IN requests here 2911 * if operating slave mode 2912 */ 2913 if (hs_ep->isochronous && hs_ep->interval > 1) 2914 dwc2_gadget_incr_frame_num(hs_ep); 2915 2916 dwc2_hsotg_complete_in(hsotg, hs_ep); 2917 if (ints & DXEPINT_NAKINTRPT) 2918 ints &= ~DXEPINT_NAKINTRPT; 2919 2920 if (idx == 0 && !hs_ep->req) 2921 dwc2_hsotg_enqueue_setup(hsotg); 2922 } else if (using_dma(hsotg)) { 2923 /* 2924 * We're using DMA, we need to fire an OutDone here 2925 * as we ignore the RXFIFO. 2926 */ 2927 if (hs_ep->isochronous && hs_ep->interval > 1) 2928 dwc2_gadget_incr_frame_num(hs_ep); 2929 2930 dwc2_hsotg_handle_outdone(hsotg, idx); 2931 } 2932 } 2933 2934 if (ints & DXEPINT_EPDISBLD) 2935 dwc2_gadget_handle_ep_disabled(hs_ep); 2936 2937 if (ints & DXEPINT_OUTTKNEPDIS) 2938 dwc2_gadget_handle_out_token_ep_disabled(hs_ep); 2939 2940 if (ints & DXEPINT_NAKINTRPT) 2941 dwc2_gadget_handle_nak(hs_ep); 2942 2943 if (ints & DXEPINT_AHBERR) 2944 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__); 2945 2946 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */ 2947 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__); 2948 2949 if (using_dma(hsotg) && idx == 0) { 2950 /* 2951 * this is the notification we've received a 2952 * setup packet. In non-DMA mode we'd get this 2953 * from the RXFIFO, instead we need to process 2954 * the setup here. 2955 */ 2956 2957 if (dir_in) 2958 WARN_ON_ONCE(1); 2959 else 2960 dwc2_hsotg_handle_outdone(hsotg, 0); 2961 } 2962 } 2963 2964 if (ints & DXEPINT_STSPHSERCVD) { 2965 dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__); 2966 2967 /* Safety check EP0 state when STSPHSERCVD asserted */ 2968 if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) { 2969 /* Move to STATUS IN for DDMA */ 2970 if (using_desc_dma(hsotg)) 2971 dwc2_hsotg_ep0_zlp(hsotg, true); 2972 } 2973 2974 } 2975 2976 if (ints & DXEPINT_BACK2BACKSETUP) 2977 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__); 2978 2979 if (ints & DXEPINT_BNAINTR) { 2980 dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__); 2981 if (hs_ep->isochronous) 2982 dwc2_gadget_handle_isoc_bna(hs_ep); 2983 } 2984 2985 if (dir_in && !hs_ep->isochronous) { 2986 /* not sure if this is important, but we'll clear it anyway */ 2987 if (ints & DXEPINT_INTKNTXFEMP) { 2988 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n", 2989 __func__, idx); 2990 } 2991 2992 /* this probably means something bad is happening */ 2993 if (ints & DXEPINT_INTKNEPMIS) { 2994 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n", 2995 __func__, idx); 2996 } 2997 2998 /* FIFO has space or is empty (see GAHBCFG) */ 2999 if (hsotg->dedicated_fifos && 3000 ints & DXEPINT_TXFEMP) { 3001 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n", 3002 __func__, idx); 3003 if (!using_dma(hsotg)) 3004 dwc2_hsotg_trytx(hsotg, hs_ep); 3005 } 3006 } 3007 } 3008 3009 /** 3010 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done) 3011 * @hsotg: The device state. 3012 * 3013 * Handle updating the device settings after the enumeration phase has 3014 * been completed. 3015 */ 3016 static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg) 3017 { 3018 u32 dsts = dwc2_readl(hsotg->regs + DSTS); 3019 int ep0_mps = 0, ep_mps = 8; 3020 3021 /* 3022 * This should signal the finish of the enumeration phase 3023 * of the USB handshaking, so we should now know what rate 3024 * we connected at. 3025 */ 3026 3027 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts); 3028 3029 /* 3030 * note, since we're limited by the size of transfer on EP0, and 3031 * it seems IN transfers must be a even number of packets we do 3032 * not advertise a 64byte MPS on EP0. 3033 */ 3034 3035 /* catch both EnumSpd_FS and EnumSpd_FS48 */ 3036 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) { 3037 case DSTS_ENUMSPD_FS: 3038 case DSTS_ENUMSPD_FS48: 3039 hsotg->gadget.speed = USB_SPEED_FULL; 3040 ep0_mps = EP0_MPS_LIMIT; 3041 ep_mps = 1023; 3042 break; 3043 3044 case DSTS_ENUMSPD_HS: 3045 hsotg->gadget.speed = USB_SPEED_HIGH; 3046 ep0_mps = EP0_MPS_LIMIT; 3047 ep_mps = 1024; 3048 break; 3049 3050 case DSTS_ENUMSPD_LS: 3051 hsotg->gadget.speed = USB_SPEED_LOW; 3052 ep0_mps = 8; 3053 ep_mps = 8; 3054 /* 3055 * note, we don't actually support LS in this driver at the 3056 * moment, and the documentation seems to imply that it isn't 3057 * supported by the PHYs on some of the devices. 3058 */ 3059 break; 3060 } 3061 dev_info(hsotg->dev, "new device is %s\n", 3062 usb_speed_string(hsotg->gadget.speed)); 3063 3064 /* 3065 * we should now know the maximum packet size for an 3066 * endpoint, so set the endpoints to a default value. 3067 */ 3068 3069 if (ep0_mps) { 3070 int i; 3071 /* Initialize ep0 for both in and out directions */ 3072 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1); 3073 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0); 3074 for (i = 1; i < hsotg->num_of_eps; i++) { 3075 if (hsotg->eps_in[i]) 3076 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 3077 0, 1); 3078 if (hsotg->eps_out[i]) 3079 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 3080 0, 0); 3081 } 3082 } 3083 3084 /* ensure after enumeration our EP0 is active */ 3085 3086 dwc2_hsotg_enqueue_setup(hsotg); 3087 3088 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", 3089 dwc2_readl(hsotg->regs + DIEPCTL0), 3090 dwc2_readl(hsotg->regs + DOEPCTL0)); 3091 } 3092 3093 /** 3094 * kill_all_requests - remove all requests from the endpoint's queue 3095 * @hsotg: The device state. 3096 * @ep: The endpoint the requests may be on. 3097 * @result: The result code to use. 3098 * 3099 * Go through the requests on the given endpoint and mark them 3100 * completed with the given result code. 3101 */ 3102 static void kill_all_requests(struct dwc2_hsotg *hsotg, 3103 struct dwc2_hsotg_ep *ep, 3104 int result) 3105 { 3106 struct dwc2_hsotg_req *req, *treq; 3107 unsigned int size; 3108 3109 ep->req = NULL; 3110 3111 list_for_each_entry_safe(req, treq, &ep->queue, queue) 3112 dwc2_hsotg_complete_request(hsotg, ep, req, 3113 result); 3114 3115 if (!hsotg->dedicated_fifos) 3116 return; 3117 size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->fifo_index)) & 0xffff) * 4; 3118 if (size < ep->fifo_size) 3119 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index); 3120 } 3121 3122 /** 3123 * dwc2_hsotg_disconnect - disconnect service 3124 * @hsotg: The device state. 3125 * 3126 * The device has been disconnected. Remove all current 3127 * transactions and signal the gadget driver that this 3128 * has happened. 3129 */ 3130 void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg) 3131 { 3132 unsigned int ep; 3133 3134 if (!hsotg->connected) 3135 return; 3136 3137 hsotg->connected = 0; 3138 hsotg->test_mode = 0; 3139 3140 for (ep = 0; ep < hsotg->num_of_eps; ep++) { 3141 if (hsotg->eps_in[ep]) 3142 kill_all_requests(hsotg, hsotg->eps_in[ep], 3143 -ESHUTDOWN); 3144 if (hsotg->eps_out[ep]) 3145 kill_all_requests(hsotg, hsotg->eps_out[ep], 3146 -ESHUTDOWN); 3147 } 3148 3149 call_gadget(hsotg, disconnect); 3150 hsotg->lx_state = DWC2_L3; 3151 3152 usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED); 3153 } 3154 3155 /** 3156 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler 3157 * @hsotg: The device state: 3158 * @periodic: True if this is a periodic FIFO interrupt 3159 */ 3160 static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic) 3161 { 3162 struct dwc2_hsotg_ep *ep; 3163 int epno, ret; 3164 3165 /* look through for any more data to transmit */ 3166 for (epno = 0; epno < hsotg->num_of_eps; epno++) { 3167 ep = index_to_ep(hsotg, epno, 1); 3168 3169 if (!ep) 3170 continue; 3171 3172 if (!ep->dir_in) 3173 continue; 3174 3175 if ((periodic && !ep->periodic) || 3176 (!periodic && ep->periodic)) 3177 continue; 3178 3179 ret = dwc2_hsotg_trytx(hsotg, ep); 3180 if (ret < 0) 3181 break; 3182 } 3183 } 3184 3185 /* IRQ flags which will trigger a retry around the IRQ loop */ 3186 #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \ 3187 GINTSTS_PTXFEMP | \ 3188 GINTSTS_RXFLVL) 3189 3190 /** 3191 * dwc2_hsotg_core_init - issue softreset to the core 3192 * @hsotg: The device state 3193 * @is_usb_reset: Usb resetting flag 3194 * 3195 * Issue a soft reset to the core, and await the core finishing it. 3196 */ 3197 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, 3198 bool is_usb_reset) 3199 { 3200 u32 intmsk; 3201 u32 val; 3202 u32 usbcfg; 3203 u32 dcfg = 0; 3204 3205 /* Kill any ep0 requests as controller will be reinitialized */ 3206 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET); 3207 3208 if (!is_usb_reset) 3209 if (dwc2_core_reset(hsotg, true)) 3210 return; 3211 3212 /* 3213 * we must now enable ep0 ready for host detection and then 3214 * set configuration. 3215 */ 3216 3217 /* keep other bits untouched (so e.g. forced modes are not lost) */ 3218 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 3219 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP | 3220 GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK); 3221 3222 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS && 3223 (hsotg->params.speed == DWC2_SPEED_PARAM_FULL || 3224 hsotg->params.speed == DWC2_SPEED_PARAM_LOW)) { 3225 /* FS/LS Dedicated Transceiver Interface */ 3226 usbcfg |= GUSBCFG_PHYSEL; 3227 } else { 3228 /* set the PLL on, remove the HNP/SRP and set the PHY */ 3229 val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; 3230 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) | 3231 (val << GUSBCFG_USBTRDTIM_SHIFT); 3232 } 3233 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 3234 3235 dwc2_hsotg_init_fifo(hsotg); 3236 3237 if (!is_usb_reset) 3238 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SFTDISCON); 3239 3240 dcfg |= DCFG_EPMISCNT(1); 3241 3242 switch (hsotg->params.speed) { 3243 case DWC2_SPEED_PARAM_LOW: 3244 dcfg |= DCFG_DEVSPD_LS; 3245 break; 3246 case DWC2_SPEED_PARAM_FULL: 3247 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) 3248 dcfg |= DCFG_DEVSPD_FS48; 3249 else 3250 dcfg |= DCFG_DEVSPD_FS; 3251 break; 3252 default: 3253 dcfg |= DCFG_DEVSPD_HS; 3254 } 3255 3256 if (hsotg->params.ipg_isoc_en) 3257 dcfg |= DCFG_IPG_ISOC_SUPPORDED; 3258 3259 dwc2_writel(dcfg, hsotg->regs + DCFG); 3260 3261 /* Clear any pending OTG interrupts */ 3262 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); 3263 3264 /* Clear any pending interrupts */ 3265 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 3266 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | 3267 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF | 3268 GINTSTS_USBRST | GINTSTS_RESETDET | 3269 GINTSTS_ENUMDONE | GINTSTS_OTGINT | 3270 GINTSTS_USBSUSP | GINTSTS_WKUPINT | 3271 GINTSTS_LPMTRANRCVD; 3272 3273 if (!using_desc_dma(hsotg)) 3274 intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT; 3275 3276 if (!hsotg->params.external_id_pin_ctl) 3277 intmsk |= GINTSTS_CONIDSTSCHNG; 3278 3279 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 3280 3281 if (using_dma(hsotg)) { 3282 dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | 3283 hsotg->params.ahbcfg, 3284 hsotg->regs + GAHBCFG); 3285 3286 /* Set DDMA mode support in the core if needed */ 3287 if (using_desc_dma(hsotg)) 3288 dwc2_set_bit(hsotg->regs + DCFG, DCFG_DESCDMA_EN); 3289 3290 } else { 3291 dwc2_writel(((hsotg->dedicated_fifos) ? 3292 (GAHBCFG_NP_TXF_EMP_LVL | 3293 GAHBCFG_P_TXF_EMP_LVL) : 0) | 3294 GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG); 3295 } 3296 3297 /* 3298 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts 3299 * when we have no data to transfer. Otherwise we get being flooded by 3300 * interrupts. 3301 */ 3302 3303 dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ? 3304 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) | 3305 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK | 3306 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK, 3307 hsotg->regs + DIEPMSK); 3308 3309 /* 3310 * don't need XferCompl, we get that from RXFIFO in slave mode. In 3311 * DMA mode we may need this and StsPhseRcvd. 3312 */ 3313 dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | 3314 DOEPMSK_STSPHSERCVDMSK) : 0) | 3315 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK | 3316 DOEPMSK_SETUPMSK, 3317 hsotg->regs + DOEPMSK); 3318 3319 /* Enable BNA interrupt for DDMA */ 3320 if (using_desc_dma(hsotg)) { 3321 dwc2_set_bit(hsotg->regs + DOEPMSK, DOEPMSK_BNAMSK); 3322 dwc2_set_bit(hsotg->regs + DIEPMSK, DIEPMSK_BNAININTRMSK); 3323 } 3324 3325 dwc2_writel(0, hsotg->regs + DAINTMSK); 3326 3327 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", 3328 dwc2_readl(hsotg->regs + DIEPCTL0), 3329 dwc2_readl(hsotg->regs + DOEPCTL0)); 3330 3331 /* enable in and out endpoint interrupts */ 3332 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT); 3333 3334 /* 3335 * Enable the RXFIFO when in slave mode, as this is how we collect 3336 * the data. In DMA mode, we get events from the FIFO but also 3337 * things we cannot process, so do not use it. 3338 */ 3339 if (!using_dma(hsotg)) 3340 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL); 3341 3342 /* Enable interrupts for EP0 in and out */ 3343 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1); 3344 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1); 3345 3346 if (!is_usb_reset) { 3347 dwc2_set_bit(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); 3348 udelay(10); /* see openiboot */ 3349 dwc2_clear_bit(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); 3350 } 3351 3352 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL)); 3353 3354 /* 3355 * DxEPCTL_USBActEp says RO in manual, but seems to be set by 3356 * writing to the EPCTL register.. 3357 */ 3358 3359 /* set to read 1 8byte packet */ 3360 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | 3361 DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0); 3362 3363 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | 3364 DXEPCTL_CNAK | DXEPCTL_EPENA | 3365 DXEPCTL_USBACTEP, 3366 hsotg->regs + DOEPCTL0); 3367 3368 /* enable, but don't activate EP0in */ 3369 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | 3370 DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0); 3371 3372 /* clear global NAKs */ 3373 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK; 3374 if (!is_usb_reset) 3375 val |= DCTL_SFTDISCON; 3376 dwc2_set_bit(hsotg->regs + DCTL, val); 3377 3378 /* configure the core to support LPM */ 3379 dwc2_gadget_init_lpm(hsotg); 3380 3381 /* must be at-least 3ms to allow bus to see disconnect */ 3382 mdelay(3); 3383 3384 hsotg->lx_state = DWC2_L0; 3385 3386 dwc2_hsotg_enqueue_setup(hsotg); 3387 3388 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", 3389 dwc2_readl(hsotg->regs + DIEPCTL0), 3390 dwc2_readl(hsotg->regs + DOEPCTL0)); 3391 } 3392 3393 static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) 3394 { 3395 /* set the soft-disconnect bit */ 3396 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SFTDISCON); 3397 } 3398 3399 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) 3400 { 3401 /* remove the soft-disconnect and let's go */ 3402 dwc2_clear_bit(hsotg->regs + DCTL, DCTL_SFTDISCON); 3403 } 3404 3405 /** 3406 * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt. 3407 * @hsotg: The device state: 3408 * 3409 * This interrupt indicates one of the following conditions occurred while 3410 * transmitting an ISOC transaction. 3411 * - Corrupted IN Token for ISOC EP. 3412 * - Packet not complete in FIFO. 3413 * 3414 * The following actions will be taken: 3415 * - Determine the EP 3416 * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO 3417 */ 3418 static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg) 3419 { 3420 struct dwc2_hsotg_ep *hs_ep; 3421 u32 epctrl; 3422 u32 daintmsk; 3423 u32 idx; 3424 3425 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n"); 3426 3427 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); 3428 3429 for (idx = 1; idx < hsotg->num_of_eps; idx++) { 3430 hs_ep = hsotg->eps_in[idx]; 3431 /* Proceed only unmasked ISOC EPs */ 3432 if (!hs_ep->isochronous || (BIT(idx) & ~daintmsk)) 3433 continue; 3434 3435 epctrl = dwc2_readl(hsotg->regs + DIEPCTL(idx)); 3436 if ((epctrl & DXEPCTL_EPENA) && 3437 dwc2_gadget_target_frame_elapsed(hs_ep)) { 3438 epctrl |= DXEPCTL_SNAK; 3439 epctrl |= DXEPCTL_EPDIS; 3440 dwc2_writel(epctrl, hsotg->regs + DIEPCTL(idx)); 3441 } 3442 } 3443 3444 /* Clear interrupt */ 3445 dwc2_writel(GINTSTS_INCOMPL_SOIN, hsotg->regs + GINTSTS); 3446 } 3447 3448 /** 3449 * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt 3450 * @hsotg: The device state: 3451 * 3452 * This interrupt indicates one of the following conditions occurred while 3453 * transmitting an ISOC transaction. 3454 * - Corrupted OUT Token for ISOC EP. 3455 * - Packet not complete in FIFO. 3456 * 3457 * The following actions will be taken: 3458 * - Determine the EP 3459 * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed. 3460 */ 3461 static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg) 3462 { 3463 u32 gintsts; 3464 u32 gintmsk; 3465 u32 daintmsk; 3466 u32 epctrl; 3467 struct dwc2_hsotg_ep *hs_ep; 3468 int idx; 3469 3470 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__); 3471 3472 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); 3473 daintmsk >>= DAINT_OUTEP_SHIFT; 3474 3475 for (idx = 1; idx < hsotg->num_of_eps; idx++) { 3476 hs_ep = hsotg->eps_out[idx]; 3477 /* Proceed only unmasked ISOC EPs */ 3478 if (!hs_ep->isochronous || (BIT(idx) & ~daintmsk)) 3479 continue; 3480 3481 epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx)); 3482 if ((epctrl & DXEPCTL_EPENA) && 3483 dwc2_gadget_target_frame_elapsed(hs_ep)) { 3484 /* Unmask GOUTNAKEFF interrupt */ 3485 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3486 gintmsk |= GINTSTS_GOUTNAKEFF; 3487 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3488 3489 gintsts = dwc2_readl(hsotg->regs + GINTSTS); 3490 if (!(gintsts & GINTSTS_GOUTNAKEFF)) { 3491 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SGOUTNAK); 3492 break; 3493 } 3494 } 3495 } 3496 3497 /* Clear interrupt */ 3498 dwc2_writel(GINTSTS_INCOMPL_SOOUT, hsotg->regs + GINTSTS); 3499 } 3500 3501 /** 3502 * dwc2_hsotg_irq - handle device interrupt 3503 * @irq: The IRQ number triggered 3504 * @pw: The pw value when registered the handler. 3505 */ 3506 static irqreturn_t dwc2_hsotg_irq(int irq, void *pw) 3507 { 3508 struct dwc2_hsotg *hsotg = pw; 3509 int retry_count = 8; 3510 u32 gintsts; 3511 u32 gintmsk; 3512 3513 if (!dwc2_is_device_mode(hsotg)) 3514 return IRQ_NONE; 3515 3516 spin_lock(&hsotg->lock); 3517 irq_retry: 3518 gintsts = dwc2_readl(hsotg->regs + GINTSTS); 3519 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3520 3521 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", 3522 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); 3523 3524 gintsts &= gintmsk; 3525 3526 if (gintsts & GINTSTS_RESETDET) { 3527 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__); 3528 3529 dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS); 3530 3531 /* This event must be used only if controller is suspended */ 3532 if (hsotg->lx_state == DWC2_L2) { 3533 dwc2_exit_partial_power_down(hsotg, true); 3534 hsotg->lx_state = DWC2_L0; 3535 } 3536 } 3537 3538 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) { 3539 u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL); 3540 u32 connected = hsotg->connected; 3541 3542 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__); 3543 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", 3544 dwc2_readl(hsotg->regs + GNPTXSTS)); 3545 3546 dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS); 3547 3548 /* Report disconnection if it is not already done. */ 3549 dwc2_hsotg_disconnect(hsotg); 3550 3551 /* Reset device address to zero */ 3552 dwc2_clear_bit(hsotg->regs + DCFG, DCFG_DEVADDR_MASK); 3553 3554 if (usb_status & GOTGCTL_BSESVLD && connected) 3555 dwc2_hsotg_core_init_disconnected(hsotg, true); 3556 } 3557 3558 if (gintsts & GINTSTS_ENUMDONE) { 3559 dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS); 3560 3561 dwc2_hsotg_irq_enumdone(hsotg); 3562 } 3563 3564 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) { 3565 u32 daint = dwc2_readl(hsotg->regs + DAINT); 3566 u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); 3567 u32 daint_out, daint_in; 3568 int ep; 3569 3570 daint &= daintmsk; 3571 daint_out = daint >> DAINT_OUTEP_SHIFT; 3572 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT); 3573 3574 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint); 3575 3576 for (ep = 0; ep < hsotg->num_of_eps && daint_out; 3577 ep++, daint_out >>= 1) { 3578 if (daint_out & 1) 3579 dwc2_hsotg_epint(hsotg, ep, 0); 3580 } 3581 3582 for (ep = 0; ep < hsotg->num_of_eps && daint_in; 3583 ep++, daint_in >>= 1) { 3584 if (daint_in & 1) 3585 dwc2_hsotg_epint(hsotg, ep, 1); 3586 } 3587 } 3588 3589 /* check both FIFOs */ 3590 3591 if (gintsts & GINTSTS_NPTXFEMP) { 3592 dev_dbg(hsotg->dev, "NPTxFEmp\n"); 3593 3594 /* 3595 * Disable the interrupt to stop it happening again 3596 * unless one of these endpoint routines decides that 3597 * it needs re-enabling 3598 */ 3599 3600 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP); 3601 dwc2_hsotg_irq_fifoempty(hsotg, false); 3602 } 3603 3604 if (gintsts & GINTSTS_PTXFEMP) { 3605 dev_dbg(hsotg->dev, "PTxFEmp\n"); 3606 3607 /* See note in GINTSTS_NPTxFEmp */ 3608 3609 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP); 3610 dwc2_hsotg_irq_fifoempty(hsotg, true); 3611 } 3612 3613 if (gintsts & GINTSTS_RXFLVL) { 3614 /* 3615 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty, 3616 * we need to retry dwc2_hsotg_handle_rx if this is still 3617 * set. 3618 */ 3619 3620 dwc2_hsotg_handle_rx(hsotg); 3621 } 3622 3623 if (gintsts & GINTSTS_ERLYSUSP) { 3624 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); 3625 dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS); 3626 } 3627 3628 /* 3629 * these next two seem to crop-up occasionally causing the core 3630 * to shutdown the USB transfer, so try clearing them and logging 3631 * the occurrence. 3632 */ 3633 3634 if (gintsts & GINTSTS_GOUTNAKEFF) { 3635 u8 idx; 3636 u32 epctrl; 3637 u32 gintmsk; 3638 u32 daintmsk; 3639 struct dwc2_hsotg_ep *hs_ep; 3640 3641 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); 3642 daintmsk >>= DAINT_OUTEP_SHIFT; 3643 /* Mask this interrupt */ 3644 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3645 gintmsk &= ~GINTSTS_GOUTNAKEFF; 3646 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3647 3648 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n"); 3649 for (idx = 1; idx < hsotg->num_of_eps; idx++) { 3650 hs_ep = hsotg->eps_out[idx]; 3651 /* Proceed only unmasked ISOC EPs */ 3652 if (!hs_ep->isochronous || (BIT(idx) & ~daintmsk)) 3653 continue; 3654 3655 epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx)); 3656 3657 if (epctrl & DXEPCTL_EPENA) { 3658 epctrl |= DXEPCTL_SNAK; 3659 epctrl |= DXEPCTL_EPDIS; 3660 dwc2_writel(epctrl, hsotg->regs + DOEPCTL(idx)); 3661 } 3662 } 3663 3664 /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */ 3665 } 3666 3667 if (gintsts & GINTSTS_GINNAKEFF) { 3668 dev_info(hsotg->dev, "GINNakEff triggered\n"); 3669 3670 dwc2_set_bit(hsotg->regs + DCTL, DCTL_CGNPINNAK); 3671 3672 dwc2_hsotg_dump(hsotg); 3673 } 3674 3675 if (gintsts & GINTSTS_INCOMPL_SOIN) 3676 dwc2_gadget_handle_incomplete_isoc_in(hsotg); 3677 3678 if (gintsts & GINTSTS_INCOMPL_SOOUT) 3679 dwc2_gadget_handle_incomplete_isoc_out(hsotg); 3680 3681 /* 3682 * if we've had fifo events, we should try and go around the 3683 * loop again to see if there's any point in returning yet. 3684 */ 3685 3686 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0) 3687 goto irq_retry; 3688 3689 spin_unlock(&hsotg->lock); 3690 3691 return IRQ_HANDLED; 3692 } 3693 3694 static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg, 3695 struct dwc2_hsotg_ep *hs_ep) 3696 { 3697 u32 epctrl_reg; 3698 u32 epint_reg; 3699 3700 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) : 3701 DOEPCTL(hs_ep->index); 3702 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) : 3703 DOEPINT(hs_ep->index); 3704 3705 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__, 3706 hs_ep->name); 3707 3708 if (hs_ep->dir_in) { 3709 if (hsotg->dedicated_fifos || hs_ep->periodic) { 3710 dwc2_set_bit(hsotg->regs + epctrl_reg, DXEPCTL_SNAK); 3711 /* Wait for Nak effect */ 3712 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, 3713 DXEPINT_INEPNAKEFF, 100)) 3714 dev_warn(hsotg->dev, 3715 "%s: timeout DIEPINT.NAKEFF\n", 3716 __func__); 3717 } else { 3718 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SGNPINNAK); 3719 /* Wait for Nak effect */ 3720 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, 3721 GINTSTS_GINNAKEFF, 100)) 3722 dev_warn(hsotg->dev, 3723 "%s: timeout GINTSTS.GINNAKEFF\n", 3724 __func__); 3725 } 3726 } else { 3727 if (!(dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_GOUTNAKEFF)) 3728 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SGOUTNAK); 3729 3730 /* Wait for global nak to take effect */ 3731 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, 3732 GINTSTS_GOUTNAKEFF, 100)) 3733 dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n", 3734 __func__); 3735 } 3736 3737 /* Disable ep */ 3738 dwc2_set_bit(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK); 3739 3740 /* Wait for ep to be disabled */ 3741 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100)) 3742 dev_warn(hsotg->dev, 3743 "%s: timeout DOEPCTL.EPDisable\n", __func__); 3744 3745 /* Clear EPDISBLD interrupt */ 3746 dwc2_set_bit(hsotg->regs + epint_reg, DXEPINT_EPDISBLD); 3747 3748 if (hs_ep->dir_in) { 3749 unsigned short fifo_index; 3750 3751 if (hsotg->dedicated_fifos || hs_ep->periodic) 3752 fifo_index = hs_ep->fifo_index; 3753 else 3754 fifo_index = 0; 3755 3756 /* Flush TX FIFO */ 3757 dwc2_flush_tx_fifo(hsotg, fifo_index); 3758 3759 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */ 3760 if (!hsotg->dedicated_fifos && !hs_ep->periodic) 3761 dwc2_set_bit(hsotg->regs + DCTL, DCTL_CGNPINNAK); 3762 3763 } else { 3764 /* Remove global NAKs */ 3765 dwc2_set_bit(hsotg->regs + DCTL, DCTL_CGOUTNAK); 3766 } 3767 } 3768 3769 /** 3770 * dwc2_hsotg_ep_enable - enable the given endpoint 3771 * @ep: The USB endpint to configure 3772 * @desc: The USB endpoint descriptor to configure with. 3773 * 3774 * This is called from the USB gadget code's usb_ep_enable(). 3775 */ 3776 static int dwc2_hsotg_ep_enable(struct usb_ep *ep, 3777 const struct usb_endpoint_descriptor *desc) 3778 { 3779 struct dwc2_hsotg_ep *hs_ep = our_ep(ep); 3780 struct dwc2_hsotg *hsotg = hs_ep->parent; 3781 unsigned long flags; 3782 unsigned int index = hs_ep->index; 3783 u32 epctrl_reg; 3784 u32 epctrl; 3785 u32 mps; 3786 u32 mc; 3787 u32 mask; 3788 unsigned int dir_in; 3789 unsigned int i, val, size; 3790 int ret = 0; 3791 unsigned char ep_type; 3792 3793 dev_dbg(hsotg->dev, 3794 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n", 3795 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes, 3796 desc->wMaxPacketSize, desc->bInterval); 3797 3798 /* not to be called for EP0 */ 3799 if (index == 0) { 3800 dev_err(hsotg->dev, "%s: called for EP 0\n", __func__); 3801 return -EINVAL; 3802 } 3803 3804 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0; 3805 if (dir_in != hs_ep->dir_in) { 3806 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__); 3807 return -EINVAL; 3808 } 3809 3810 ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; 3811 mps = usb_endpoint_maxp(desc); 3812 mc = usb_endpoint_maxp_mult(desc); 3813 3814 /* ISOC IN in DDMA supported bInterval up to 10 */ 3815 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC && 3816 dir_in && desc->bInterval > 10) { 3817 dev_err(hsotg->dev, 3818 "%s: ISOC IN, DDMA: bInterval>10 not supported!\n", __func__); 3819 return -EINVAL; 3820 } 3821 3822 /* High bandwidth ISOC OUT in DDMA not supported */ 3823 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC && 3824 !dir_in && mc > 1) { 3825 dev_err(hsotg->dev, 3826 "%s: ISOC OUT, DDMA: HB not supported!\n", __func__); 3827 return -EINVAL; 3828 } 3829 3830 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */ 3831 3832 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); 3833 epctrl = dwc2_readl(hsotg->regs + epctrl_reg); 3834 3835 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", 3836 __func__, epctrl, epctrl_reg); 3837 3838 /* Allocate DMA descriptor chain for non-ctrl endpoints */ 3839 if (using_desc_dma(hsotg) && !hs_ep->desc_list) { 3840 hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev, 3841 MAX_DMA_DESC_NUM_GENERIC * 3842 sizeof(struct dwc2_dma_desc), 3843 &hs_ep->desc_list_dma, GFP_ATOMIC); 3844 if (!hs_ep->desc_list) { 3845 ret = -ENOMEM; 3846 goto error2; 3847 } 3848 } 3849 3850 spin_lock_irqsave(&hsotg->lock, flags); 3851 3852 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK); 3853 epctrl |= DXEPCTL_MPS(mps); 3854 3855 /* 3856 * mark the endpoint as active, otherwise the core may ignore 3857 * transactions entirely for this endpoint 3858 */ 3859 epctrl |= DXEPCTL_USBACTEP; 3860 3861 /* update the endpoint state */ 3862 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in); 3863 3864 /* default, set to non-periodic */ 3865 hs_ep->isochronous = 0; 3866 hs_ep->periodic = 0; 3867 hs_ep->halted = 0; 3868 hs_ep->interval = desc->bInterval; 3869 3870 switch (ep_type) { 3871 case USB_ENDPOINT_XFER_ISOC: 3872 epctrl |= DXEPCTL_EPTYPE_ISO; 3873 epctrl |= DXEPCTL_SETEVENFR; 3874 hs_ep->isochronous = 1; 3875 hs_ep->interval = 1 << (desc->bInterval - 1); 3876 hs_ep->target_frame = TARGET_FRAME_INITIAL; 3877 hs_ep->next_desc = 0; 3878 hs_ep->compl_desc = 0; 3879 if (dir_in) { 3880 hs_ep->periodic = 1; 3881 mask = dwc2_readl(hsotg->regs + DIEPMSK); 3882 mask |= DIEPMSK_NAKMSK; 3883 dwc2_writel(mask, hsotg->regs + DIEPMSK); 3884 } else { 3885 mask = dwc2_readl(hsotg->regs + DOEPMSK); 3886 mask |= DOEPMSK_OUTTKNEPDISMSK; 3887 dwc2_writel(mask, hsotg->regs + DOEPMSK); 3888 } 3889 break; 3890 3891 case USB_ENDPOINT_XFER_BULK: 3892 epctrl |= DXEPCTL_EPTYPE_BULK; 3893 break; 3894 3895 case USB_ENDPOINT_XFER_INT: 3896 if (dir_in) 3897 hs_ep->periodic = 1; 3898 3899 if (hsotg->gadget.speed == USB_SPEED_HIGH) 3900 hs_ep->interval = 1 << (desc->bInterval - 1); 3901 3902 epctrl |= DXEPCTL_EPTYPE_INTERRUPT; 3903 break; 3904 3905 case USB_ENDPOINT_XFER_CONTROL: 3906 epctrl |= DXEPCTL_EPTYPE_CONTROL; 3907 break; 3908 } 3909 3910 /* 3911 * if the hardware has dedicated fifos, we must give each IN EP 3912 * a unique tx-fifo even if it is non-periodic. 3913 */ 3914 if (dir_in && hsotg->dedicated_fifos) { 3915 u32 fifo_index = 0; 3916 u32 fifo_size = UINT_MAX; 3917 3918 size = hs_ep->ep.maxpacket * hs_ep->mc; 3919 for (i = 1; i < hsotg->num_of_eps; ++i) { 3920 if (hsotg->fifo_map & (1 << i)) 3921 continue; 3922 val = dwc2_readl(hsotg->regs + DPTXFSIZN(i)); 3923 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4; 3924 if (val < size) 3925 continue; 3926 /* Search for smallest acceptable fifo */ 3927 if (val < fifo_size) { 3928 fifo_size = val; 3929 fifo_index = i; 3930 } 3931 } 3932 if (!fifo_index) { 3933 dev_err(hsotg->dev, 3934 "%s: No suitable fifo found\n", __func__); 3935 ret = -ENOMEM; 3936 goto error1; 3937 } 3938 hsotg->fifo_map |= 1 << fifo_index; 3939 epctrl |= DXEPCTL_TXFNUM(fifo_index); 3940 hs_ep->fifo_index = fifo_index; 3941 hs_ep->fifo_size = fifo_size; 3942 } 3943 3944 /* for non control endpoints, set PID to D0 */ 3945 if (index && !hs_ep->isochronous) 3946 epctrl |= DXEPCTL_SETD0PID; 3947 3948 /* WA for Full speed ISOC IN in DDMA mode. 3949 * By Clear NAK status of EP, core will send ZLP 3950 * to IN token and assert NAK interrupt relying 3951 * on TxFIFO status only 3952 */ 3953 3954 if (hsotg->gadget.speed == USB_SPEED_FULL && 3955 hs_ep->isochronous && dir_in) { 3956 /* The WA applies only to core versions from 2.72a 3957 * to 4.00a (including both). Also for FS_IOT_1.00a 3958 * and HS_IOT_1.00a. 3959 */ 3960 u32 gsnpsid = dwc2_readl(hsotg->regs + GSNPSID); 3961 3962 if ((gsnpsid >= DWC2_CORE_REV_2_72a && 3963 gsnpsid <= DWC2_CORE_REV_4_00a) || 3964 gsnpsid == DWC2_FS_IOT_REV_1_00a || 3965 gsnpsid == DWC2_HS_IOT_REV_1_00a) 3966 epctrl |= DXEPCTL_CNAK; 3967 } 3968 3969 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", 3970 __func__, epctrl); 3971 3972 dwc2_writel(epctrl, hsotg->regs + epctrl_reg); 3973 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", 3974 __func__, dwc2_readl(hsotg->regs + epctrl_reg)); 3975 3976 /* enable the endpoint interrupt */ 3977 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1); 3978 3979 error1: 3980 spin_unlock_irqrestore(&hsotg->lock, flags); 3981 3982 error2: 3983 if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) { 3984 dmam_free_coherent(hsotg->dev, MAX_DMA_DESC_NUM_GENERIC * 3985 sizeof(struct dwc2_dma_desc), 3986 hs_ep->desc_list, hs_ep->desc_list_dma); 3987 hs_ep->desc_list = NULL; 3988 } 3989 3990 return ret; 3991 } 3992 3993 /** 3994 * dwc2_hsotg_ep_disable - disable given endpoint 3995 * @ep: The endpoint to disable. 3996 */ 3997 static int dwc2_hsotg_ep_disable(struct usb_ep *ep) 3998 { 3999 struct dwc2_hsotg_ep *hs_ep = our_ep(ep); 4000 struct dwc2_hsotg *hsotg = hs_ep->parent; 4001 int dir_in = hs_ep->dir_in; 4002 int index = hs_ep->index; 4003 unsigned long flags; 4004 u32 epctrl_reg; 4005 u32 ctrl; 4006 4007 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep); 4008 4009 if (ep == &hsotg->eps_out[0]->ep) { 4010 dev_err(hsotg->dev, "%s: called for ep0\n", __func__); 4011 return -EINVAL; 4012 } 4013 4014 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { 4015 dev_err(hsotg->dev, "%s: called in host mode?\n", __func__); 4016 return -EINVAL; 4017 } 4018 4019 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); 4020 4021 spin_lock_irqsave(&hsotg->lock, flags); 4022 4023 ctrl = dwc2_readl(hsotg->regs + epctrl_reg); 4024 4025 if (ctrl & DXEPCTL_EPENA) 4026 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep); 4027 4028 ctrl &= ~DXEPCTL_EPENA; 4029 ctrl &= ~DXEPCTL_USBACTEP; 4030 ctrl |= DXEPCTL_SNAK; 4031 4032 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); 4033 dwc2_writel(ctrl, hsotg->regs + epctrl_reg); 4034 4035 /* disable endpoint interrupts */ 4036 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); 4037 4038 /* terminate all requests with shutdown */ 4039 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN); 4040 4041 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index); 4042 hs_ep->fifo_index = 0; 4043 hs_ep->fifo_size = 0; 4044 4045 spin_unlock_irqrestore(&hsotg->lock, flags); 4046 return 0; 4047 } 4048 4049 /** 4050 * on_list - check request is on the given endpoint 4051 * @ep: The endpoint to check. 4052 * @test: The request to test if it is on the endpoint. 4053 */ 4054 static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test) 4055 { 4056 struct dwc2_hsotg_req *req, *treq; 4057 4058 list_for_each_entry_safe(req, treq, &ep->queue, queue) { 4059 if (req == test) 4060 return true; 4061 } 4062 4063 return false; 4064 } 4065 4066 /** 4067 * dwc2_hsotg_ep_dequeue - dequeue given endpoint 4068 * @ep: The endpoint to dequeue. 4069 * @req: The request to be removed from a queue. 4070 */ 4071 static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req) 4072 { 4073 struct dwc2_hsotg_req *hs_req = our_req(req); 4074 struct dwc2_hsotg_ep *hs_ep = our_ep(ep); 4075 struct dwc2_hsotg *hs = hs_ep->parent; 4076 unsigned long flags; 4077 4078 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req); 4079 4080 spin_lock_irqsave(&hs->lock, flags); 4081 4082 if (!on_list(hs_ep, hs_req)) { 4083 spin_unlock_irqrestore(&hs->lock, flags); 4084 return -EINVAL; 4085 } 4086 4087 /* Dequeue already started request */ 4088 if (req == &hs_ep->req->req) 4089 dwc2_hsotg_ep_stop_xfr(hs, hs_ep); 4090 4091 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET); 4092 spin_unlock_irqrestore(&hs->lock, flags); 4093 4094 return 0; 4095 } 4096 4097 /** 4098 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint 4099 * @ep: The endpoint to set halt. 4100 * @value: Set or unset the halt. 4101 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if 4102 * the endpoint is busy processing requests. 4103 * 4104 * We need to stall the endpoint immediately if request comes from set_feature 4105 * protocol command handler. 4106 */ 4107 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now) 4108 { 4109 struct dwc2_hsotg_ep *hs_ep = our_ep(ep); 4110 struct dwc2_hsotg *hs = hs_ep->parent; 4111 int index = hs_ep->index; 4112 u32 epreg; 4113 u32 epctl; 4114 u32 xfertype; 4115 4116 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value); 4117 4118 if (index == 0) { 4119 if (value) 4120 dwc2_hsotg_stall_ep0(hs); 4121 else 4122 dev_warn(hs->dev, 4123 "%s: can't clear halt on ep0\n", __func__); 4124 return 0; 4125 } 4126 4127 if (hs_ep->isochronous) { 4128 dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name); 4129 return -EINVAL; 4130 } 4131 4132 if (!now && value && !list_empty(&hs_ep->queue)) { 4133 dev_dbg(hs->dev, "%s request is pending, cannot halt\n", 4134 ep->name); 4135 return -EAGAIN; 4136 } 4137 4138 if (hs_ep->dir_in) { 4139 epreg = DIEPCTL(index); 4140 epctl = dwc2_readl(hs->regs + epreg); 4141 4142 if (value) { 4143 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK; 4144 if (epctl & DXEPCTL_EPENA) 4145 epctl |= DXEPCTL_EPDIS; 4146 } else { 4147 epctl &= ~DXEPCTL_STALL; 4148 xfertype = epctl & DXEPCTL_EPTYPE_MASK; 4149 if (xfertype == DXEPCTL_EPTYPE_BULK || 4150 xfertype == DXEPCTL_EPTYPE_INTERRUPT) 4151 epctl |= DXEPCTL_SETD0PID; 4152 } 4153 dwc2_writel(epctl, hs->regs + epreg); 4154 } else { 4155 epreg = DOEPCTL(index); 4156 epctl = dwc2_readl(hs->regs + epreg); 4157 4158 if (value) { 4159 epctl |= DXEPCTL_STALL; 4160 } else { 4161 epctl &= ~DXEPCTL_STALL; 4162 xfertype = epctl & DXEPCTL_EPTYPE_MASK; 4163 if (xfertype == DXEPCTL_EPTYPE_BULK || 4164 xfertype == DXEPCTL_EPTYPE_INTERRUPT) 4165 epctl |= DXEPCTL_SETD0PID; 4166 } 4167 dwc2_writel(epctl, hs->regs + epreg); 4168 } 4169 4170 hs_ep->halted = value; 4171 4172 return 0; 4173 } 4174 4175 /** 4176 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held 4177 * @ep: The endpoint to set halt. 4178 * @value: Set or unset the halt. 4179 */ 4180 static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value) 4181 { 4182 struct dwc2_hsotg_ep *hs_ep = our_ep(ep); 4183 struct dwc2_hsotg *hs = hs_ep->parent; 4184 unsigned long flags = 0; 4185 int ret = 0; 4186 4187 spin_lock_irqsave(&hs->lock, flags); 4188 ret = dwc2_hsotg_ep_sethalt(ep, value, false); 4189 spin_unlock_irqrestore(&hs->lock, flags); 4190 4191 return ret; 4192 } 4193 4194 static const struct usb_ep_ops dwc2_hsotg_ep_ops = { 4195 .enable = dwc2_hsotg_ep_enable, 4196 .disable = dwc2_hsotg_ep_disable, 4197 .alloc_request = dwc2_hsotg_ep_alloc_request, 4198 .free_request = dwc2_hsotg_ep_free_request, 4199 .queue = dwc2_hsotg_ep_queue_lock, 4200 .dequeue = dwc2_hsotg_ep_dequeue, 4201 .set_halt = dwc2_hsotg_ep_sethalt_lock, 4202 /* note, don't believe we have any call for the fifo routines */ 4203 }; 4204 4205 /** 4206 * dwc2_hsotg_init - initialize the usb core 4207 * @hsotg: The driver state 4208 */ 4209 static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg) 4210 { 4211 u32 trdtim; 4212 u32 usbcfg; 4213 /* unmask subset of endpoint interrupts */ 4214 4215 dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | 4216 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK, 4217 hsotg->regs + DIEPMSK); 4218 4219 dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | 4220 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK, 4221 hsotg->regs + DOEPMSK); 4222 4223 dwc2_writel(0, hsotg->regs + DAINTMSK); 4224 4225 /* Be in disconnected state until gadget is registered */ 4226 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SFTDISCON); 4227 4228 /* setup fifos */ 4229 4230 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", 4231 dwc2_readl(hsotg->regs + GRXFSIZ), 4232 dwc2_readl(hsotg->regs + GNPTXFSIZ)); 4233 4234 dwc2_hsotg_init_fifo(hsotg); 4235 4236 /* keep other bits untouched (so e.g. forced modes are not lost) */ 4237 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 4238 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP | 4239 GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK); 4240 4241 /* set the PLL on, remove the HNP/SRP and set the PHY */ 4242 trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; 4243 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) | 4244 (trdtim << GUSBCFG_USBTRDTIM_SHIFT); 4245 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 4246 4247 if (using_dma(hsotg)) 4248 dwc2_set_bit(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN); 4249 } 4250 4251 /** 4252 * dwc2_hsotg_udc_start - prepare the udc for work 4253 * @gadget: The usb gadget state 4254 * @driver: The usb gadget driver 4255 * 4256 * Perform initialization to prepare udc device and driver 4257 * to work. 4258 */ 4259 static int dwc2_hsotg_udc_start(struct usb_gadget *gadget, 4260 struct usb_gadget_driver *driver) 4261 { 4262 struct dwc2_hsotg *hsotg = to_hsotg(gadget); 4263 unsigned long flags; 4264 int ret; 4265 4266 if (!hsotg) { 4267 pr_err("%s: called with no device\n", __func__); 4268 return -ENODEV; 4269 } 4270 4271 if (!driver) { 4272 dev_err(hsotg->dev, "%s: no driver\n", __func__); 4273 return -EINVAL; 4274 } 4275 4276 if (driver->max_speed < USB_SPEED_FULL) 4277 dev_err(hsotg->dev, "%s: bad speed\n", __func__); 4278 4279 if (!driver->setup) { 4280 dev_err(hsotg->dev, "%s: missing entry points\n", __func__); 4281 return -EINVAL; 4282 } 4283 4284 WARN_ON(hsotg->driver); 4285 4286 driver->driver.bus = NULL; 4287 hsotg->driver = driver; 4288 hsotg->gadget.dev.of_node = hsotg->dev->of_node; 4289 hsotg->gadget.speed = USB_SPEED_UNKNOWN; 4290 4291 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) { 4292 ret = dwc2_lowlevel_hw_enable(hsotg); 4293 if (ret) 4294 goto err; 4295 } 4296 4297 if (!IS_ERR_OR_NULL(hsotg->uphy)) 4298 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget); 4299 4300 spin_lock_irqsave(&hsotg->lock, flags); 4301 if (dwc2_hw_is_device(hsotg)) { 4302 dwc2_hsotg_init(hsotg); 4303 dwc2_hsotg_core_init_disconnected(hsotg, false); 4304 } 4305 4306 hsotg->enabled = 0; 4307 spin_unlock_irqrestore(&hsotg->lock, flags); 4308 4309 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name); 4310 4311 return 0; 4312 4313 err: 4314 hsotg->driver = NULL; 4315 return ret; 4316 } 4317 4318 /** 4319 * dwc2_hsotg_udc_stop - stop the udc 4320 * @gadget: The usb gadget state 4321 * 4322 * Stop udc hw block and stay tunned for future transmissions 4323 */ 4324 static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget) 4325 { 4326 struct dwc2_hsotg *hsotg = to_hsotg(gadget); 4327 unsigned long flags = 0; 4328 int ep; 4329 4330 if (!hsotg) 4331 return -ENODEV; 4332 4333 /* all endpoints should be shutdown */ 4334 for (ep = 1; ep < hsotg->num_of_eps; ep++) { 4335 if (hsotg->eps_in[ep]) 4336 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); 4337 if (hsotg->eps_out[ep]) 4338 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); 4339 } 4340 4341 spin_lock_irqsave(&hsotg->lock, flags); 4342 4343 hsotg->driver = NULL; 4344 hsotg->gadget.speed = USB_SPEED_UNKNOWN; 4345 hsotg->enabled = 0; 4346 4347 spin_unlock_irqrestore(&hsotg->lock, flags); 4348 4349 if (!IS_ERR_OR_NULL(hsotg->uphy)) 4350 otg_set_peripheral(hsotg->uphy->otg, NULL); 4351 4352 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) 4353 dwc2_lowlevel_hw_disable(hsotg); 4354 4355 return 0; 4356 } 4357 4358 /** 4359 * dwc2_hsotg_gadget_getframe - read the frame number 4360 * @gadget: The usb gadget state 4361 * 4362 * Read the {micro} frame number 4363 */ 4364 static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget) 4365 { 4366 return dwc2_hsotg_read_frameno(to_hsotg(gadget)); 4367 } 4368 4369 /** 4370 * dwc2_hsotg_pullup - connect/disconnect the USB PHY 4371 * @gadget: The usb gadget state 4372 * @is_on: Current state of the USB PHY 4373 * 4374 * Connect/Disconnect the USB PHY pullup 4375 */ 4376 static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on) 4377 { 4378 struct dwc2_hsotg *hsotg = to_hsotg(gadget); 4379 unsigned long flags = 0; 4380 4381 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on, 4382 hsotg->op_state); 4383 4384 /* Don't modify pullup state while in host mode */ 4385 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { 4386 hsotg->enabled = is_on; 4387 return 0; 4388 } 4389 4390 spin_lock_irqsave(&hsotg->lock, flags); 4391 if (is_on) { 4392 hsotg->enabled = 1; 4393 dwc2_hsotg_core_init_disconnected(hsotg, false); 4394 /* Enable ACG feature in device mode,if supported */ 4395 dwc2_enable_acg(hsotg); 4396 dwc2_hsotg_core_connect(hsotg); 4397 } else { 4398 dwc2_hsotg_core_disconnect(hsotg); 4399 dwc2_hsotg_disconnect(hsotg); 4400 hsotg->enabled = 0; 4401 } 4402 4403 hsotg->gadget.speed = USB_SPEED_UNKNOWN; 4404 spin_unlock_irqrestore(&hsotg->lock, flags); 4405 4406 return 0; 4407 } 4408 4409 static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active) 4410 { 4411 struct dwc2_hsotg *hsotg = to_hsotg(gadget); 4412 unsigned long flags; 4413 4414 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active); 4415 spin_lock_irqsave(&hsotg->lock, flags); 4416 4417 /* 4418 * If controller is hibernated, it must exit from power_down 4419 * before being initialized / de-initialized 4420 */ 4421 if (hsotg->lx_state == DWC2_L2) 4422 dwc2_exit_partial_power_down(hsotg, false); 4423 4424 if (is_active) { 4425 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 4426 4427 dwc2_hsotg_core_init_disconnected(hsotg, false); 4428 if (hsotg->enabled) { 4429 /* Enable ACG feature in device mode,if supported */ 4430 dwc2_enable_acg(hsotg); 4431 dwc2_hsotg_core_connect(hsotg); 4432 } 4433 } else { 4434 dwc2_hsotg_core_disconnect(hsotg); 4435 dwc2_hsotg_disconnect(hsotg); 4436 } 4437 4438 spin_unlock_irqrestore(&hsotg->lock, flags); 4439 return 0; 4440 } 4441 4442 /** 4443 * dwc2_hsotg_vbus_draw - report bMaxPower field 4444 * @gadget: The usb gadget state 4445 * @mA: Amount of current 4446 * 4447 * Report how much power the device may consume to the phy. 4448 */ 4449 static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA) 4450 { 4451 struct dwc2_hsotg *hsotg = to_hsotg(gadget); 4452 4453 if (IS_ERR_OR_NULL(hsotg->uphy)) 4454 return -ENOTSUPP; 4455 return usb_phy_set_power(hsotg->uphy, mA); 4456 } 4457 4458 static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = { 4459 .get_frame = dwc2_hsotg_gadget_getframe, 4460 .udc_start = dwc2_hsotg_udc_start, 4461 .udc_stop = dwc2_hsotg_udc_stop, 4462 .pullup = dwc2_hsotg_pullup, 4463 .vbus_session = dwc2_hsotg_vbus_session, 4464 .vbus_draw = dwc2_hsotg_vbus_draw, 4465 }; 4466 4467 /** 4468 * dwc2_hsotg_initep - initialise a single endpoint 4469 * @hsotg: The device state. 4470 * @hs_ep: The endpoint to be initialised. 4471 * @epnum: The endpoint number 4472 * @dir_in: True if direction is in. 4473 * 4474 * Initialise the given endpoint (as part of the probe and device state 4475 * creation) to give to the gadget driver. Setup the endpoint name, any 4476 * direction information and other state that may be required. 4477 */ 4478 static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg, 4479 struct dwc2_hsotg_ep *hs_ep, 4480 int epnum, 4481 bool dir_in) 4482 { 4483 char *dir; 4484 4485 if (epnum == 0) 4486 dir = ""; 4487 else if (dir_in) 4488 dir = "in"; 4489 else 4490 dir = "out"; 4491 4492 hs_ep->dir_in = dir_in; 4493 hs_ep->index = epnum; 4494 4495 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir); 4496 4497 INIT_LIST_HEAD(&hs_ep->queue); 4498 INIT_LIST_HEAD(&hs_ep->ep.ep_list); 4499 4500 /* add to the list of endpoints known by the gadget driver */ 4501 if (epnum) 4502 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list); 4503 4504 hs_ep->parent = hsotg; 4505 hs_ep->ep.name = hs_ep->name; 4506 4507 if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW) 4508 usb_ep_set_maxpacket_limit(&hs_ep->ep, 8); 4509 else 4510 usb_ep_set_maxpacket_limit(&hs_ep->ep, 4511 epnum ? 1024 : EP0_MPS_LIMIT); 4512 hs_ep->ep.ops = &dwc2_hsotg_ep_ops; 4513 4514 if (epnum == 0) { 4515 hs_ep->ep.caps.type_control = true; 4516 } else { 4517 if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) { 4518 hs_ep->ep.caps.type_iso = true; 4519 hs_ep->ep.caps.type_bulk = true; 4520 } 4521 hs_ep->ep.caps.type_int = true; 4522 } 4523 4524 if (dir_in) 4525 hs_ep->ep.caps.dir_in = true; 4526 else 4527 hs_ep->ep.caps.dir_out = true; 4528 4529 /* 4530 * if we're using dma, we need to set the next-endpoint pointer 4531 * to be something valid. 4532 */ 4533 4534 if (using_dma(hsotg)) { 4535 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); 4536 4537 if (dir_in) 4538 dwc2_writel(next, hsotg->regs + DIEPCTL(epnum)); 4539 else 4540 dwc2_writel(next, hsotg->regs + DOEPCTL(epnum)); 4541 } 4542 } 4543 4544 /** 4545 * dwc2_hsotg_hw_cfg - read HW configuration registers 4546 * @hsotg: Programming view of the DWC_otg controller 4547 * 4548 * Read the USB core HW configuration registers 4549 */ 4550 static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg) 4551 { 4552 u32 cfg; 4553 u32 ep_type; 4554 u32 i; 4555 4556 /* check hardware configuration */ 4557 4558 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep; 4559 4560 /* Add ep0 */ 4561 hsotg->num_of_eps++; 4562 4563 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, 4564 sizeof(struct dwc2_hsotg_ep), 4565 GFP_KERNEL); 4566 if (!hsotg->eps_in[0]) 4567 return -ENOMEM; 4568 /* Same dwc2_hsotg_ep is used in both directions for ep0 */ 4569 hsotg->eps_out[0] = hsotg->eps_in[0]; 4570 4571 cfg = hsotg->hw_params.dev_ep_dirs; 4572 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) { 4573 ep_type = cfg & 3; 4574 /* Direction in or both */ 4575 if (!(ep_type & 2)) { 4576 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev, 4577 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); 4578 if (!hsotg->eps_in[i]) 4579 return -ENOMEM; 4580 } 4581 /* Direction out or both */ 4582 if (!(ep_type & 1)) { 4583 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev, 4584 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); 4585 if (!hsotg->eps_out[i]) 4586 return -ENOMEM; 4587 } 4588 } 4589 4590 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size; 4591 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo; 4592 4593 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n", 4594 hsotg->num_of_eps, 4595 hsotg->dedicated_fifos ? "dedicated" : "shared", 4596 hsotg->fifo_mem); 4597 return 0; 4598 } 4599 4600 /** 4601 * dwc2_hsotg_dump - dump state of the udc 4602 * @hsotg: Programming view of the DWC_otg controller 4603 * 4604 */ 4605 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg) 4606 { 4607 #ifdef DEBUG 4608 struct device *dev = hsotg->dev; 4609 void __iomem *regs = hsotg->regs; 4610 u32 val; 4611 int idx; 4612 4613 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", 4614 dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL), 4615 dwc2_readl(regs + DIEPMSK)); 4616 4617 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n", 4618 dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1)); 4619 4620 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", 4621 dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ)); 4622 4623 /* show periodic fifo settings */ 4624 4625 for (idx = 1; idx < hsotg->num_of_eps; idx++) { 4626 val = dwc2_readl(regs + DPTXFSIZN(idx)); 4627 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, 4628 val >> FIFOSIZE_DEPTH_SHIFT, 4629 val & FIFOSIZE_STARTADDR_MASK); 4630 } 4631 4632 for (idx = 0; idx < hsotg->num_of_eps; idx++) { 4633 dev_info(dev, 4634 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, 4635 dwc2_readl(regs + DIEPCTL(idx)), 4636 dwc2_readl(regs + DIEPTSIZ(idx)), 4637 dwc2_readl(regs + DIEPDMA(idx))); 4638 4639 val = dwc2_readl(regs + DOEPCTL(idx)); 4640 dev_info(dev, 4641 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", 4642 idx, dwc2_readl(regs + DOEPCTL(idx)), 4643 dwc2_readl(regs + DOEPTSIZ(idx)), 4644 dwc2_readl(regs + DOEPDMA(idx))); 4645 } 4646 4647 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", 4648 dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE)); 4649 #endif 4650 } 4651 4652 /** 4653 * dwc2_gadget_init - init function for gadget 4654 * @hsotg: Programming view of the DWC_otg controller 4655 * 4656 */ 4657 int dwc2_gadget_init(struct dwc2_hsotg *hsotg) 4658 { 4659 struct device *dev = hsotg->dev; 4660 int epnum; 4661 int ret; 4662 4663 /* Dump fifo information */ 4664 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n", 4665 hsotg->params.g_np_tx_fifo_size); 4666 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size); 4667 4668 hsotg->gadget.max_speed = USB_SPEED_HIGH; 4669 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops; 4670 hsotg->gadget.name = dev_name(dev); 4671 hsotg->remote_wakeup_allowed = 0; 4672 4673 if (hsotg->params.lpm) 4674 hsotg->gadget.lpm_capable = true; 4675 4676 if (hsotg->dr_mode == USB_DR_MODE_OTG) 4677 hsotg->gadget.is_otg = 1; 4678 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) 4679 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 4680 4681 ret = dwc2_hsotg_hw_cfg(hsotg); 4682 if (ret) { 4683 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret); 4684 return ret; 4685 } 4686 4687 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev, 4688 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); 4689 if (!hsotg->ctrl_buff) 4690 return -ENOMEM; 4691 4692 hsotg->ep0_buff = devm_kzalloc(hsotg->dev, 4693 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); 4694 if (!hsotg->ep0_buff) 4695 return -ENOMEM; 4696 4697 if (using_desc_dma(hsotg)) { 4698 ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg); 4699 if (ret < 0) 4700 return ret; 4701 } 4702 4703 ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq, 4704 IRQF_SHARED, dev_name(hsotg->dev), hsotg); 4705 if (ret < 0) { 4706 dev_err(dev, "cannot claim IRQ for gadget\n"); 4707 return ret; 4708 } 4709 4710 /* hsotg->num_of_eps holds number of EPs other than ep0 */ 4711 4712 if (hsotg->num_of_eps == 0) { 4713 dev_err(dev, "wrong number of EPs (zero)\n"); 4714 return -EINVAL; 4715 } 4716 4717 /* setup endpoint information */ 4718 4719 INIT_LIST_HEAD(&hsotg->gadget.ep_list); 4720 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep; 4721 4722 /* allocate EP0 request */ 4723 4724 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep, 4725 GFP_KERNEL); 4726 if (!hsotg->ctrl_req) { 4727 dev_err(dev, "failed to allocate ctrl req\n"); 4728 return -ENOMEM; 4729 } 4730 4731 /* initialise the endpoints now the core has been initialised */ 4732 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) { 4733 if (hsotg->eps_in[epnum]) 4734 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum], 4735 epnum, 1); 4736 if (hsotg->eps_out[epnum]) 4737 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum], 4738 epnum, 0); 4739 } 4740 4741 ret = usb_add_gadget_udc(dev, &hsotg->gadget); 4742 if (ret) 4743 return ret; 4744 4745 dwc2_hsotg_dump(hsotg); 4746 4747 return 0; 4748 } 4749 4750 /** 4751 * dwc2_hsotg_remove - remove function for hsotg driver 4752 * @hsotg: Programming view of the DWC_otg controller 4753 * 4754 */ 4755 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg) 4756 { 4757 usb_del_gadget_udc(&hsotg->gadget); 4758 4759 return 0; 4760 } 4761 4762 int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg) 4763 { 4764 unsigned long flags; 4765 4766 if (hsotg->lx_state != DWC2_L0) 4767 return 0; 4768 4769 if (hsotg->driver) { 4770 int ep; 4771 4772 dev_info(hsotg->dev, "suspending usb gadget %s\n", 4773 hsotg->driver->driver.name); 4774 4775 spin_lock_irqsave(&hsotg->lock, flags); 4776 if (hsotg->enabled) 4777 dwc2_hsotg_core_disconnect(hsotg); 4778 dwc2_hsotg_disconnect(hsotg); 4779 hsotg->gadget.speed = USB_SPEED_UNKNOWN; 4780 spin_unlock_irqrestore(&hsotg->lock, flags); 4781 4782 for (ep = 0; ep < hsotg->num_of_eps; ep++) { 4783 if (hsotg->eps_in[ep]) 4784 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); 4785 if (hsotg->eps_out[ep]) 4786 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); 4787 } 4788 } 4789 4790 return 0; 4791 } 4792 4793 int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg) 4794 { 4795 unsigned long flags; 4796 4797 if (hsotg->lx_state == DWC2_L2) 4798 return 0; 4799 4800 if (hsotg->driver) { 4801 dev_info(hsotg->dev, "resuming usb gadget %s\n", 4802 hsotg->driver->driver.name); 4803 4804 spin_lock_irqsave(&hsotg->lock, flags); 4805 dwc2_hsotg_core_init_disconnected(hsotg, false); 4806 if (hsotg->enabled) { 4807 /* Enable ACG feature in device mode,if supported */ 4808 dwc2_enable_acg(hsotg); 4809 dwc2_hsotg_core_connect(hsotg); 4810 } 4811 spin_unlock_irqrestore(&hsotg->lock, flags); 4812 } 4813 4814 return 0; 4815 } 4816 4817 /** 4818 * dwc2_backup_device_registers() - Backup controller device registers. 4819 * When suspending usb bus, registers needs to be backuped 4820 * if controller power is disabled once suspended. 4821 * 4822 * @hsotg: Programming view of the DWC_otg controller 4823 */ 4824 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) 4825 { 4826 struct dwc2_dregs_backup *dr; 4827 int i; 4828 4829 dev_dbg(hsotg->dev, "%s\n", __func__); 4830 4831 /* Backup dev regs */ 4832 dr = &hsotg->dr_backup; 4833 4834 dr->dcfg = dwc2_readl(hsotg->regs + DCFG); 4835 dr->dctl = dwc2_readl(hsotg->regs + DCTL); 4836 dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); 4837 dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK); 4838 dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK); 4839 4840 for (i = 0; i < hsotg->num_of_eps; i++) { 4841 /* Backup IN EPs */ 4842 dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i)); 4843 4844 /* Ensure DATA PID is correctly configured */ 4845 if (dr->diepctl[i] & DXEPCTL_DPID) 4846 dr->diepctl[i] |= DXEPCTL_SETD1PID; 4847 else 4848 dr->diepctl[i] |= DXEPCTL_SETD0PID; 4849 4850 dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i)); 4851 dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i)); 4852 4853 /* Backup OUT EPs */ 4854 dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i)); 4855 4856 /* Ensure DATA PID is correctly configured */ 4857 if (dr->doepctl[i] & DXEPCTL_DPID) 4858 dr->doepctl[i] |= DXEPCTL_SETD1PID; 4859 else 4860 dr->doepctl[i] |= DXEPCTL_SETD0PID; 4861 4862 dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i)); 4863 dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i)); 4864 dr->dtxfsiz[i] = dwc2_readl(hsotg->regs + DPTXFSIZN(i)); 4865 } 4866 dr->valid = true; 4867 return 0; 4868 } 4869 4870 /** 4871 * dwc2_restore_device_registers() - Restore controller device registers. 4872 * When resuming usb bus, device registers needs to be restored 4873 * if controller power were disabled. 4874 * 4875 * @hsotg: Programming view of the DWC_otg controller 4876 * @remote_wakeup: Indicates whether resume is initiated by Device or Host. 4877 * 4878 * Return: 0 if successful, negative error code otherwise 4879 */ 4880 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup) 4881 { 4882 struct dwc2_dregs_backup *dr; 4883 int i; 4884 4885 dev_dbg(hsotg->dev, "%s\n", __func__); 4886 4887 /* Restore dev regs */ 4888 dr = &hsotg->dr_backup; 4889 if (!dr->valid) { 4890 dev_err(hsotg->dev, "%s: no device registers to restore\n", 4891 __func__); 4892 return -EINVAL; 4893 } 4894 dr->valid = false; 4895 4896 if (!remote_wakeup) 4897 dwc2_writel(dr->dctl, hsotg->regs + DCTL); 4898 4899 dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK); 4900 dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK); 4901 dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK); 4902 4903 for (i = 0; i < hsotg->num_of_eps; i++) { 4904 /* Restore IN EPs */ 4905 dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i)); 4906 dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i)); 4907 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i)); 4908 /** WA for enabled EPx's IN in DDMA mode. On entering to 4909 * hibernation wrong value read and saved from DIEPDMAx, 4910 * as result BNA interrupt asserted on hibernation exit 4911 * by restoring from saved area. 4912 */ 4913 if (hsotg->params.g_dma_desc && 4914 (dr->diepctl[i] & DXEPCTL_EPENA)) 4915 dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma; 4916 dwc2_writel(dr->dtxfsiz[i], hsotg->regs + DPTXFSIZN(i)); 4917 dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i)); 4918 /* Restore OUT EPs */ 4919 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i)); 4920 /* WA for enabled EPx's OUT in DDMA mode. On entering to 4921 * hibernation wrong value read and saved from DOEPDMAx, 4922 * as result BNA interrupt asserted on hibernation exit 4923 * by restoring from saved area. 4924 */ 4925 if (hsotg->params.g_dma_desc && 4926 (dr->doepctl[i] & DXEPCTL_EPENA)) 4927 dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma; 4928 dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i)); 4929 dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i)); 4930 } 4931 4932 return 0; 4933 } 4934 4935 /** 4936 * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode 4937 * 4938 * @hsotg: Programming view of DWC_otg controller 4939 * 4940 */ 4941 void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) 4942 { 4943 u32 val; 4944 4945 if (!hsotg->params.lpm) 4946 return; 4947 4948 val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES; 4949 val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0; 4950 val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0; 4951 val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT; 4952 val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0; 4953 dwc2_writel(val, hsotg->regs + GLPMCFG); 4954 dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg->regs 4955 + GLPMCFG)); 4956 } 4957 4958 /** 4959 * dwc2_gadget_enter_hibernation() - Put controller in Hibernation. 4960 * 4961 * @hsotg: Programming view of the DWC_otg controller 4962 * 4963 * Return non-zero if failed to enter to hibernation. 4964 */ 4965 int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg) 4966 { 4967 u32 gpwrdn; 4968 int ret = 0; 4969 4970 /* Change to L2(suspend) state */ 4971 hsotg->lx_state = DWC2_L2; 4972 dev_dbg(hsotg->dev, "Start of hibernation completed\n"); 4973 ret = dwc2_backup_global_registers(hsotg); 4974 if (ret) { 4975 dev_err(hsotg->dev, "%s: failed to backup global registers\n", 4976 __func__); 4977 return ret; 4978 } 4979 ret = dwc2_backup_device_registers(hsotg); 4980 if (ret) { 4981 dev_err(hsotg->dev, "%s: failed to backup device registers\n", 4982 __func__); 4983 return ret; 4984 } 4985 4986 gpwrdn = GPWRDN_PWRDNRSTN; 4987 gpwrdn |= GPWRDN_PMUACTV; 4988 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 4989 udelay(10); 4990 4991 /* Set flag to indicate that we are in hibernation */ 4992 hsotg->hibernated = 1; 4993 4994 /* Enable interrupts from wake up logic */ 4995 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 4996 gpwrdn |= GPWRDN_PMUINTSEL; 4997 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 4998 udelay(10); 4999 5000 /* Unmask device mode interrupts in GPWRDN */ 5001 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5002 gpwrdn |= GPWRDN_RST_DET_MSK; 5003 gpwrdn |= GPWRDN_LNSTSCHG_MSK; 5004 gpwrdn |= GPWRDN_STS_CHGINT_MSK; 5005 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 5006 udelay(10); 5007 5008 /* Enable Power Down Clamp */ 5009 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5010 gpwrdn |= GPWRDN_PWRDNCLMP; 5011 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 5012 udelay(10); 5013 5014 /* Switch off VDD */ 5015 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5016 gpwrdn |= GPWRDN_PWRDNSWTCH; 5017 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 5018 udelay(10); 5019 5020 /* Save gpwrdn register for further usage if stschng interrupt */ 5021 hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5022 dev_dbg(hsotg->dev, "Hibernation completed\n"); 5023 5024 return ret; 5025 } 5026 5027 /** 5028 * dwc2_gadget_exit_hibernation() 5029 * This function is for exiting from Device mode hibernation by host initiated 5030 * resume/reset and device initiated remote-wakeup. 5031 * 5032 * @hsotg: Programming view of the DWC_otg controller 5033 * @rem_wakeup: indicates whether resume is initiated by Device or Host. 5034 * @reset: indicates whether resume is initiated by Reset. 5035 * 5036 * Return non-zero if failed to exit from hibernation. 5037 */ 5038 int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, 5039 int rem_wakeup, int reset) 5040 { 5041 u32 pcgcctl; 5042 u32 gpwrdn; 5043 u32 dctl; 5044 int ret = 0; 5045 struct dwc2_gregs_backup *gr; 5046 struct dwc2_dregs_backup *dr; 5047 5048 gr = &hsotg->gr_backup; 5049 dr = &hsotg->dr_backup; 5050 5051 if (!hsotg->hibernated) { 5052 dev_dbg(hsotg->dev, "Already exited from Hibernation\n"); 5053 return 1; 5054 } 5055 dev_dbg(hsotg->dev, 5056 "%s: called with rem_wakeup = %d reset = %d\n", 5057 __func__, rem_wakeup, reset); 5058 5059 dwc2_hib_restore_common(hsotg, rem_wakeup, 0); 5060 5061 if (!reset) { 5062 /* Clear all pending interupts */ 5063 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 5064 } 5065 5066 /* De-assert Restore */ 5067 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5068 gpwrdn &= ~GPWRDN_RESTORE; 5069 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 5070 udelay(10); 5071 5072 if (!rem_wakeup) { 5073 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 5074 pcgcctl &= ~PCGCTL_RSTPDWNMODULE; 5075 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 5076 } 5077 5078 /* Restore GUSBCFG, DCFG and DCTL */ 5079 dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG); 5080 dwc2_writel(dr->dcfg, hsotg->regs + DCFG); 5081 dwc2_writel(dr->dctl, hsotg->regs + DCTL); 5082 5083 /* De-assert Wakeup Logic */ 5084 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 5085 gpwrdn &= ~GPWRDN_PMUACTV; 5086 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 5087 5088 if (rem_wakeup) { 5089 udelay(10); 5090 /* Start Remote Wakeup Signaling */ 5091 dwc2_writel(dr->dctl | DCTL_RMTWKUPSIG, hsotg->regs + DCTL); 5092 } else { 5093 udelay(50); 5094 /* Set Device programming done bit */ 5095 dctl = dwc2_readl(hsotg->regs + DCTL); 5096 dctl |= DCTL_PWRONPRGDONE; 5097 dwc2_writel(dctl, hsotg->regs + DCTL); 5098 } 5099 /* Wait for interrupts which must be cleared */ 5100 mdelay(2); 5101 /* Clear all pending interupts */ 5102 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 5103 5104 /* Restore global registers */ 5105 ret = dwc2_restore_global_registers(hsotg); 5106 if (ret) { 5107 dev_err(hsotg->dev, "%s: failed to restore registers\n", 5108 __func__); 5109 return ret; 5110 } 5111 5112 /* Restore device registers */ 5113 ret = dwc2_restore_device_registers(hsotg, rem_wakeup); 5114 if (ret) { 5115 dev_err(hsotg->dev, "%s: failed to restore device registers\n", 5116 __func__); 5117 return ret; 5118 } 5119 5120 if (rem_wakeup) { 5121 mdelay(10); 5122 dctl = dwc2_readl(hsotg->regs + DCTL); 5123 dctl &= ~DCTL_RMTWKUPSIG; 5124 dwc2_writel(dctl, hsotg->regs + DCTL); 5125 } 5126 5127 hsotg->hibernated = 0; 5128 hsotg->lx_state = DWC2_L0; 5129 dev_dbg(hsotg->dev, "Hibernation recovery completes here\n"); 5130 5131 return ret; 5132 } 5133