1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * debugfs.c - Designware USB2 DRD controller debugfs 4 * 5 * Copyright (C) 2015 Intel Corporation 6 * Mian Yousaf Kaukab <yousaf.kaukab@intel.com> 7 */ 8 9 #include <linux/spinlock.h> 10 #include <linux/debugfs.h> 11 #include <linux/seq_file.h> 12 #include <linux/uaccess.h> 13 14 #include "core.h" 15 #include "debug.h" 16 17 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 18 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 19 20 /** 21 * testmode_write() - change usb test mode state. 22 * @file: The file to write to. 23 * @ubuf: The buffer where user wrote. 24 * @count: The ubuf size. 25 * @ppos: Unused parameter. 26 */ 27 static ssize_t testmode_write(struct file *file, const char __user *ubuf, size_t 28 count, loff_t *ppos) 29 { 30 struct seq_file *s = file->private_data; 31 struct dwc2_hsotg *hsotg = s->private; 32 unsigned long flags; 33 u32 testmode = 0; 34 char buf[32]; 35 36 if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) 37 return -EFAULT; 38 39 if (!strncmp(buf, "test_j", 6)) 40 testmode = TEST_J; 41 else if (!strncmp(buf, "test_k", 6)) 42 testmode = TEST_K; 43 else if (!strncmp(buf, "test_se0_nak", 12)) 44 testmode = TEST_SE0_NAK; 45 else if (!strncmp(buf, "test_packet", 11)) 46 testmode = TEST_PACKET; 47 else if (!strncmp(buf, "test_force_enable", 17)) 48 testmode = TEST_FORCE_EN; 49 else 50 testmode = 0; 51 52 spin_lock_irqsave(&hsotg->lock, flags); 53 dwc2_hsotg_set_test_mode(hsotg, testmode); 54 spin_unlock_irqrestore(&hsotg->lock, flags); 55 return count; 56 } 57 58 /** 59 * testmode_show() - debugfs: show usb test mode state 60 * @s: The seq file to write to. 61 * @unused: Unused parameter. 62 * 63 * This debugfs entry shows which usb test mode is currently enabled. 64 */ 65 static int testmode_show(struct seq_file *s, void *unused) 66 { 67 struct dwc2_hsotg *hsotg = s->private; 68 unsigned long flags; 69 int dctl; 70 71 spin_lock_irqsave(&hsotg->lock, flags); 72 dctl = dwc2_readl(hsotg->regs + DCTL); 73 dctl &= DCTL_TSTCTL_MASK; 74 dctl >>= DCTL_TSTCTL_SHIFT; 75 spin_unlock_irqrestore(&hsotg->lock, flags); 76 77 switch (dctl) { 78 case 0: 79 seq_puts(s, "no test\n"); 80 break; 81 case TEST_J: 82 seq_puts(s, "test_j\n"); 83 break; 84 case TEST_K: 85 seq_puts(s, "test_k\n"); 86 break; 87 case TEST_SE0_NAK: 88 seq_puts(s, "test_se0_nak\n"); 89 break; 90 case TEST_PACKET: 91 seq_puts(s, "test_packet\n"); 92 break; 93 case TEST_FORCE_EN: 94 seq_puts(s, "test_force_enable\n"); 95 break; 96 default: 97 seq_printf(s, "UNKNOWN %d\n", dctl); 98 } 99 100 return 0; 101 } 102 103 static int testmode_open(struct inode *inode, struct file *file) 104 { 105 return single_open(file, testmode_show, inode->i_private); 106 } 107 108 static const struct file_operations testmode_fops = { 109 .owner = THIS_MODULE, 110 .open = testmode_open, 111 .write = testmode_write, 112 .read = seq_read, 113 .llseek = seq_lseek, 114 .release = single_release, 115 }; 116 117 /** 118 * state_show - debugfs: show overall driver and device state. 119 * @seq: The seq file to write to. 120 * @v: Unused parameter. 121 * 122 * This debugfs entry shows the overall state of the hardware and 123 * some general information about each of the endpoints available 124 * to the system. 125 */ 126 static int state_show(struct seq_file *seq, void *v) 127 { 128 struct dwc2_hsotg *hsotg = seq->private; 129 void __iomem *regs = hsotg->regs; 130 int idx; 131 132 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n", 133 dwc2_readl(regs + DCFG), 134 dwc2_readl(regs + DCTL), 135 dwc2_readl(regs + DSTS)); 136 137 seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n", 138 dwc2_readl(regs + DIEPMSK), dwc2_readl(regs + DOEPMSK)); 139 140 seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n", 141 dwc2_readl(regs + GINTMSK), 142 dwc2_readl(regs + GINTSTS)); 143 144 seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n", 145 dwc2_readl(regs + DAINTMSK), 146 dwc2_readl(regs + DAINT)); 147 148 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n", 149 dwc2_readl(regs + GNPTXSTS), 150 dwc2_readl(regs + GRXSTSR)); 151 152 seq_puts(seq, "\nEndpoint status:\n"); 153 154 for (idx = 0; idx < hsotg->num_of_eps; idx++) { 155 u32 in, out; 156 157 in = dwc2_readl(regs + DIEPCTL(idx)); 158 out = dwc2_readl(regs + DOEPCTL(idx)); 159 160 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x", 161 idx, in, out); 162 163 in = dwc2_readl(regs + DIEPTSIZ(idx)); 164 out = dwc2_readl(regs + DOEPTSIZ(idx)); 165 166 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x", 167 in, out); 168 169 seq_puts(seq, "\n"); 170 } 171 172 return 0; 173 } 174 DEFINE_SHOW_ATTRIBUTE(state); 175 176 /** 177 * fifo_show - debugfs: show the fifo information 178 * @seq: The seq_file to write data to. 179 * @v: Unused parameter. 180 * 181 * Show the FIFO information for the overall fifo and all the 182 * periodic transmission FIFOs. 183 */ 184 static int fifo_show(struct seq_file *seq, void *v) 185 { 186 struct dwc2_hsotg *hsotg = seq->private; 187 void __iomem *regs = hsotg->regs; 188 u32 val; 189 int idx; 190 191 seq_puts(seq, "Non-periodic FIFOs:\n"); 192 seq_printf(seq, "RXFIFO: Size %d\n", dwc2_readl(regs + GRXFSIZ)); 193 194 val = dwc2_readl(regs + GNPTXFSIZ); 195 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n", 196 val >> FIFOSIZE_DEPTH_SHIFT, 197 val & FIFOSIZE_STARTADDR_MASK); 198 199 seq_puts(seq, "\nPeriodic TXFIFOs:\n"); 200 201 for (idx = 1; idx < hsotg->num_of_eps; idx++) { 202 val = dwc2_readl(regs + DPTXFSIZN(idx)); 203 204 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx, 205 val >> FIFOSIZE_DEPTH_SHIFT, 206 val & FIFOSIZE_STARTADDR_MASK); 207 } 208 209 return 0; 210 } 211 DEFINE_SHOW_ATTRIBUTE(fifo); 212 213 static const char *decode_direction(int is_in) 214 { 215 return is_in ? "in" : "out"; 216 } 217 218 /** 219 * ep_show - debugfs: show the state of an endpoint. 220 * @seq: The seq_file to write data to. 221 * @v: Unused parameter. 222 * 223 * This debugfs entry shows the state of the given endpoint (one is 224 * registered for each available). 225 */ 226 static int ep_show(struct seq_file *seq, void *v) 227 { 228 struct dwc2_hsotg_ep *ep = seq->private; 229 struct dwc2_hsotg *hsotg = ep->parent; 230 struct dwc2_hsotg_req *req; 231 void __iomem *regs = hsotg->regs; 232 int index = ep->index; 233 int show_limit = 15; 234 unsigned long flags; 235 236 seq_printf(seq, "Endpoint index %d, named %s, dir %s:\n", 237 ep->index, ep->ep.name, decode_direction(ep->dir_in)); 238 239 /* first show the register state */ 240 241 seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n", 242 dwc2_readl(regs + DIEPCTL(index)), 243 dwc2_readl(regs + DOEPCTL(index))); 244 245 seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n", 246 dwc2_readl(regs + DIEPDMA(index)), 247 dwc2_readl(regs + DOEPDMA(index))); 248 249 seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n", 250 dwc2_readl(regs + DIEPINT(index)), 251 dwc2_readl(regs + DOEPINT(index))); 252 253 seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n", 254 dwc2_readl(regs + DIEPTSIZ(index)), 255 dwc2_readl(regs + DOEPTSIZ(index))); 256 257 seq_puts(seq, "\n"); 258 seq_printf(seq, "mps %d\n", ep->ep.maxpacket); 259 seq_printf(seq, "total_data=%ld\n", ep->total_data); 260 261 seq_printf(seq, "request list (%p,%p):\n", 262 ep->queue.next, ep->queue.prev); 263 264 spin_lock_irqsave(&hsotg->lock, flags); 265 266 list_for_each_entry(req, &ep->queue, queue) { 267 if (--show_limit < 0) { 268 seq_puts(seq, "not showing more requests...\n"); 269 break; 270 } 271 272 seq_printf(seq, "%c req %p: %d bytes @%p, ", 273 req == ep->req ? '*' : ' ', 274 req, req->req.length, req->req.buf); 275 seq_printf(seq, "%d done, res %d\n", 276 req->req.actual, req->req.status); 277 } 278 279 spin_unlock_irqrestore(&hsotg->lock, flags); 280 281 return 0; 282 } 283 DEFINE_SHOW_ATTRIBUTE(ep); 284 285 /** 286 * dwc2_hsotg_create_debug - create debugfs directory and files 287 * @hsotg: The driver state 288 * 289 * Create the debugfs files to allow the user to get information 290 * about the state of the system. The directory name is created 291 * with the same name as the device itself, in case we end up 292 * with multiple blocks in future systems. 293 */ 294 static void dwc2_hsotg_create_debug(struct dwc2_hsotg *hsotg) 295 { 296 struct dentry *root; 297 unsigned int epidx; 298 299 root = hsotg->debug_root; 300 301 /* create general state file */ 302 debugfs_create_file("state", 0444, root, hsotg, &state_fops); 303 debugfs_create_file("testmode", 0644, root, hsotg, &testmode_fops); 304 debugfs_create_file("fifo", 0444, root, hsotg, &fifo_fops); 305 306 /* Create one file for each out endpoint */ 307 for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) { 308 struct dwc2_hsotg_ep *ep; 309 310 ep = hsotg->eps_out[epidx]; 311 if (ep) 312 debugfs_create_file(ep->name, 0444, root, ep, &ep_fops); 313 } 314 /* Create one file for each in endpoint. EP0 is handled with out eps */ 315 for (epidx = 1; epidx < hsotg->num_of_eps; epidx++) { 316 struct dwc2_hsotg_ep *ep; 317 318 ep = hsotg->eps_in[epidx]; 319 if (ep) 320 debugfs_create_file(ep->name, 0444, root, ep, &ep_fops); 321 } 322 } 323 #else 324 static inline void dwc2_hsotg_create_debug(struct dwc2_hsotg *hsotg) {} 325 #endif 326 327 /* dwc2_hsotg_delete_debug is removed as cleanup in done in dwc2_debugfs_exit */ 328 329 #define dump_register(nm) \ 330 { \ 331 .name = #nm, \ 332 .offset = nm, \ 333 } 334 335 static const struct debugfs_reg32 dwc2_regs[] = { 336 /* 337 * Accessing registers like this can trigger mode mismatch interrupt. 338 * However, according to dwc2 databook, the register access, in this 339 * case, is completed on the processor bus but is ignored by the core 340 * and does not affect its operation. 341 */ 342 dump_register(GOTGCTL), 343 dump_register(GOTGINT), 344 dump_register(GAHBCFG), 345 dump_register(GUSBCFG), 346 dump_register(GRSTCTL), 347 dump_register(GINTSTS), 348 dump_register(GINTMSK), 349 dump_register(GRXSTSR), 350 /* Omit GRXSTSP */ 351 dump_register(GRXFSIZ), 352 dump_register(GNPTXFSIZ), 353 dump_register(GNPTXSTS), 354 dump_register(GI2CCTL), 355 dump_register(GPVNDCTL), 356 dump_register(GGPIO), 357 dump_register(GUID), 358 dump_register(GSNPSID), 359 dump_register(GHWCFG1), 360 dump_register(GHWCFG2), 361 dump_register(GHWCFG3), 362 dump_register(GHWCFG4), 363 dump_register(GLPMCFG), 364 dump_register(GPWRDN), 365 dump_register(GDFIFOCFG), 366 dump_register(ADPCTL), 367 dump_register(HPTXFSIZ), 368 dump_register(DPTXFSIZN(1)), 369 dump_register(DPTXFSIZN(2)), 370 dump_register(DPTXFSIZN(3)), 371 dump_register(DPTXFSIZN(4)), 372 dump_register(DPTXFSIZN(5)), 373 dump_register(DPTXFSIZN(6)), 374 dump_register(DPTXFSIZN(7)), 375 dump_register(DPTXFSIZN(8)), 376 dump_register(DPTXFSIZN(9)), 377 dump_register(DPTXFSIZN(10)), 378 dump_register(DPTXFSIZN(11)), 379 dump_register(DPTXFSIZN(12)), 380 dump_register(DPTXFSIZN(13)), 381 dump_register(DPTXFSIZN(14)), 382 dump_register(DPTXFSIZN(15)), 383 dump_register(DCFG), 384 dump_register(DCTL), 385 dump_register(DSTS), 386 dump_register(DIEPMSK), 387 dump_register(DOEPMSK), 388 dump_register(DAINT), 389 dump_register(DAINTMSK), 390 dump_register(DTKNQR1), 391 dump_register(DTKNQR2), 392 dump_register(DTKNQR3), 393 dump_register(DTKNQR4), 394 dump_register(DVBUSDIS), 395 dump_register(DVBUSPULSE), 396 dump_register(DIEPCTL(0)), 397 dump_register(DIEPCTL(1)), 398 dump_register(DIEPCTL(2)), 399 dump_register(DIEPCTL(3)), 400 dump_register(DIEPCTL(4)), 401 dump_register(DIEPCTL(5)), 402 dump_register(DIEPCTL(6)), 403 dump_register(DIEPCTL(7)), 404 dump_register(DIEPCTL(8)), 405 dump_register(DIEPCTL(9)), 406 dump_register(DIEPCTL(10)), 407 dump_register(DIEPCTL(11)), 408 dump_register(DIEPCTL(12)), 409 dump_register(DIEPCTL(13)), 410 dump_register(DIEPCTL(14)), 411 dump_register(DIEPCTL(15)), 412 dump_register(DOEPCTL(0)), 413 dump_register(DOEPCTL(1)), 414 dump_register(DOEPCTL(2)), 415 dump_register(DOEPCTL(3)), 416 dump_register(DOEPCTL(4)), 417 dump_register(DOEPCTL(5)), 418 dump_register(DOEPCTL(6)), 419 dump_register(DOEPCTL(7)), 420 dump_register(DOEPCTL(8)), 421 dump_register(DOEPCTL(9)), 422 dump_register(DOEPCTL(10)), 423 dump_register(DOEPCTL(11)), 424 dump_register(DOEPCTL(12)), 425 dump_register(DOEPCTL(13)), 426 dump_register(DOEPCTL(14)), 427 dump_register(DOEPCTL(15)), 428 dump_register(DIEPINT(0)), 429 dump_register(DIEPINT(1)), 430 dump_register(DIEPINT(2)), 431 dump_register(DIEPINT(3)), 432 dump_register(DIEPINT(4)), 433 dump_register(DIEPINT(5)), 434 dump_register(DIEPINT(6)), 435 dump_register(DIEPINT(7)), 436 dump_register(DIEPINT(8)), 437 dump_register(DIEPINT(9)), 438 dump_register(DIEPINT(10)), 439 dump_register(DIEPINT(11)), 440 dump_register(DIEPINT(12)), 441 dump_register(DIEPINT(13)), 442 dump_register(DIEPINT(14)), 443 dump_register(DIEPINT(15)), 444 dump_register(DOEPINT(0)), 445 dump_register(DOEPINT(1)), 446 dump_register(DOEPINT(2)), 447 dump_register(DOEPINT(3)), 448 dump_register(DOEPINT(4)), 449 dump_register(DOEPINT(5)), 450 dump_register(DOEPINT(6)), 451 dump_register(DOEPINT(7)), 452 dump_register(DOEPINT(8)), 453 dump_register(DOEPINT(9)), 454 dump_register(DOEPINT(10)), 455 dump_register(DOEPINT(11)), 456 dump_register(DOEPINT(12)), 457 dump_register(DOEPINT(13)), 458 dump_register(DOEPINT(14)), 459 dump_register(DOEPINT(15)), 460 dump_register(DIEPTSIZ(0)), 461 dump_register(DIEPTSIZ(1)), 462 dump_register(DIEPTSIZ(2)), 463 dump_register(DIEPTSIZ(3)), 464 dump_register(DIEPTSIZ(4)), 465 dump_register(DIEPTSIZ(5)), 466 dump_register(DIEPTSIZ(6)), 467 dump_register(DIEPTSIZ(7)), 468 dump_register(DIEPTSIZ(8)), 469 dump_register(DIEPTSIZ(9)), 470 dump_register(DIEPTSIZ(10)), 471 dump_register(DIEPTSIZ(11)), 472 dump_register(DIEPTSIZ(12)), 473 dump_register(DIEPTSIZ(13)), 474 dump_register(DIEPTSIZ(14)), 475 dump_register(DIEPTSIZ(15)), 476 dump_register(DOEPTSIZ(0)), 477 dump_register(DOEPTSIZ(1)), 478 dump_register(DOEPTSIZ(2)), 479 dump_register(DOEPTSIZ(3)), 480 dump_register(DOEPTSIZ(4)), 481 dump_register(DOEPTSIZ(5)), 482 dump_register(DOEPTSIZ(6)), 483 dump_register(DOEPTSIZ(7)), 484 dump_register(DOEPTSIZ(8)), 485 dump_register(DOEPTSIZ(9)), 486 dump_register(DOEPTSIZ(10)), 487 dump_register(DOEPTSIZ(11)), 488 dump_register(DOEPTSIZ(12)), 489 dump_register(DOEPTSIZ(13)), 490 dump_register(DOEPTSIZ(14)), 491 dump_register(DOEPTSIZ(15)), 492 dump_register(DIEPDMA(0)), 493 dump_register(DIEPDMA(1)), 494 dump_register(DIEPDMA(2)), 495 dump_register(DIEPDMA(3)), 496 dump_register(DIEPDMA(4)), 497 dump_register(DIEPDMA(5)), 498 dump_register(DIEPDMA(6)), 499 dump_register(DIEPDMA(7)), 500 dump_register(DIEPDMA(8)), 501 dump_register(DIEPDMA(9)), 502 dump_register(DIEPDMA(10)), 503 dump_register(DIEPDMA(11)), 504 dump_register(DIEPDMA(12)), 505 dump_register(DIEPDMA(13)), 506 dump_register(DIEPDMA(14)), 507 dump_register(DIEPDMA(15)), 508 dump_register(DOEPDMA(0)), 509 dump_register(DOEPDMA(1)), 510 dump_register(DOEPDMA(2)), 511 dump_register(DOEPDMA(3)), 512 dump_register(DOEPDMA(4)), 513 dump_register(DOEPDMA(5)), 514 dump_register(DOEPDMA(6)), 515 dump_register(DOEPDMA(7)), 516 dump_register(DOEPDMA(8)), 517 dump_register(DOEPDMA(9)), 518 dump_register(DOEPDMA(10)), 519 dump_register(DOEPDMA(11)), 520 dump_register(DOEPDMA(12)), 521 dump_register(DOEPDMA(13)), 522 dump_register(DOEPDMA(14)), 523 dump_register(DOEPDMA(15)), 524 dump_register(DTXFSTS(0)), 525 dump_register(DTXFSTS(1)), 526 dump_register(DTXFSTS(2)), 527 dump_register(DTXFSTS(3)), 528 dump_register(DTXFSTS(4)), 529 dump_register(DTXFSTS(5)), 530 dump_register(DTXFSTS(6)), 531 dump_register(DTXFSTS(7)), 532 dump_register(DTXFSTS(8)), 533 dump_register(DTXFSTS(9)), 534 dump_register(DTXFSTS(10)), 535 dump_register(DTXFSTS(11)), 536 dump_register(DTXFSTS(12)), 537 dump_register(DTXFSTS(13)), 538 dump_register(DTXFSTS(14)), 539 dump_register(DTXFSTS(15)), 540 dump_register(PCGCTL), 541 dump_register(HCFG), 542 dump_register(HFIR), 543 dump_register(HFNUM), 544 dump_register(HPTXSTS), 545 dump_register(HAINT), 546 dump_register(HAINTMSK), 547 dump_register(HFLBADDR), 548 dump_register(HPRT0), 549 dump_register(HCCHAR(0)), 550 dump_register(HCCHAR(1)), 551 dump_register(HCCHAR(2)), 552 dump_register(HCCHAR(3)), 553 dump_register(HCCHAR(4)), 554 dump_register(HCCHAR(5)), 555 dump_register(HCCHAR(6)), 556 dump_register(HCCHAR(7)), 557 dump_register(HCCHAR(8)), 558 dump_register(HCCHAR(9)), 559 dump_register(HCCHAR(10)), 560 dump_register(HCCHAR(11)), 561 dump_register(HCCHAR(12)), 562 dump_register(HCCHAR(13)), 563 dump_register(HCCHAR(14)), 564 dump_register(HCCHAR(15)), 565 dump_register(HCSPLT(0)), 566 dump_register(HCSPLT(1)), 567 dump_register(HCSPLT(2)), 568 dump_register(HCSPLT(3)), 569 dump_register(HCSPLT(4)), 570 dump_register(HCSPLT(5)), 571 dump_register(HCSPLT(6)), 572 dump_register(HCSPLT(7)), 573 dump_register(HCSPLT(8)), 574 dump_register(HCSPLT(9)), 575 dump_register(HCSPLT(10)), 576 dump_register(HCSPLT(11)), 577 dump_register(HCSPLT(12)), 578 dump_register(HCSPLT(13)), 579 dump_register(HCSPLT(14)), 580 dump_register(HCSPLT(15)), 581 dump_register(HCINT(0)), 582 dump_register(HCINT(1)), 583 dump_register(HCINT(2)), 584 dump_register(HCINT(3)), 585 dump_register(HCINT(4)), 586 dump_register(HCINT(5)), 587 dump_register(HCINT(6)), 588 dump_register(HCINT(7)), 589 dump_register(HCINT(8)), 590 dump_register(HCINT(9)), 591 dump_register(HCINT(10)), 592 dump_register(HCINT(11)), 593 dump_register(HCINT(12)), 594 dump_register(HCINT(13)), 595 dump_register(HCINT(14)), 596 dump_register(HCINT(15)), 597 dump_register(HCINTMSK(0)), 598 dump_register(HCINTMSK(1)), 599 dump_register(HCINTMSK(2)), 600 dump_register(HCINTMSK(3)), 601 dump_register(HCINTMSK(4)), 602 dump_register(HCINTMSK(5)), 603 dump_register(HCINTMSK(6)), 604 dump_register(HCINTMSK(7)), 605 dump_register(HCINTMSK(8)), 606 dump_register(HCINTMSK(9)), 607 dump_register(HCINTMSK(10)), 608 dump_register(HCINTMSK(11)), 609 dump_register(HCINTMSK(12)), 610 dump_register(HCINTMSK(13)), 611 dump_register(HCINTMSK(14)), 612 dump_register(HCINTMSK(15)), 613 dump_register(HCTSIZ(0)), 614 dump_register(HCTSIZ(1)), 615 dump_register(HCTSIZ(2)), 616 dump_register(HCTSIZ(3)), 617 dump_register(HCTSIZ(4)), 618 dump_register(HCTSIZ(5)), 619 dump_register(HCTSIZ(6)), 620 dump_register(HCTSIZ(7)), 621 dump_register(HCTSIZ(8)), 622 dump_register(HCTSIZ(9)), 623 dump_register(HCTSIZ(10)), 624 dump_register(HCTSIZ(11)), 625 dump_register(HCTSIZ(12)), 626 dump_register(HCTSIZ(13)), 627 dump_register(HCTSIZ(14)), 628 dump_register(HCTSIZ(15)), 629 dump_register(HCDMA(0)), 630 dump_register(HCDMA(1)), 631 dump_register(HCDMA(2)), 632 dump_register(HCDMA(3)), 633 dump_register(HCDMA(4)), 634 dump_register(HCDMA(5)), 635 dump_register(HCDMA(6)), 636 dump_register(HCDMA(7)), 637 dump_register(HCDMA(8)), 638 dump_register(HCDMA(9)), 639 dump_register(HCDMA(10)), 640 dump_register(HCDMA(11)), 641 dump_register(HCDMA(12)), 642 dump_register(HCDMA(13)), 643 dump_register(HCDMA(14)), 644 dump_register(HCDMA(15)), 645 dump_register(HCDMAB(0)), 646 dump_register(HCDMAB(1)), 647 dump_register(HCDMAB(2)), 648 dump_register(HCDMAB(3)), 649 dump_register(HCDMAB(4)), 650 dump_register(HCDMAB(5)), 651 dump_register(HCDMAB(6)), 652 dump_register(HCDMAB(7)), 653 dump_register(HCDMAB(8)), 654 dump_register(HCDMAB(9)), 655 dump_register(HCDMAB(10)), 656 dump_register(HCDMAB(11)), 657 dump_register(HCDMAB(12)), 658 dump_register(HCDMAB(13)), 659 dump_register(HCDMAB(14)), 660 dump_register(HCDMAB(15)), 661 }; 662 663 #define print_param(_seq, _ptr, _param) \ 664 seq_printf((_seq), "%-30s: %d\n", #_param, (_ptr)->_param) 665 666 #define print_param_hex(_seq, _ptr, _param) \ 667 seq_printf((_seq), "%-30s: 0x%x\n", #_param, (_ptr)->_param) 668 669 static int params_show(struct seq_file *seq, void *v) 670 { 671 struct dwc2_hsotg *hsotg = seq->private; 672 struct dwc2_core_params *p = &hsotg->params; 673 int i; 674 675 print_param(seq, p, otg_cap); 676 print_param(seq, p, dma_desc_enable); 677 print_param(seq, p, dma_desc_fs_enable); 678 print_param(seq, p, speed); 679 print_param(seq, p, enable_dynamic_fifo); 680 print_param(seq, p, en_multiple_tx_fifo); 681 print_param(seq, p, host_rx_fifo_size); 682 print_param(seq, p, host_nperio_tx_fifo_size); 683 print_param(seq, p, host_perio_tx_fifo_size); 684 print_param(seq, p, max_transfer_size); 685 print_param(seq, p, max_packet_count); 686 print_param(seq, p, host_channels); 687 print_param(seq, p, phy_type); 688 print_param(seq, p, phy_utmi_width); 689 print_param(seq, p, phy_ulpi_ddr); 690 print_param(seq, p, phy_ulpi_ext_vbus); 691 print_param(seq, p, i2c_enable); 692 print_param(seq, p, ipg_isoc_en); 693 print_param(seq, p, ulpi_fs_ls); 694 print_param(seq, p, host_support_fs_ls_low_power); 695 print_param(seq, p, host_ls_low_power_phy_clk); 696 print_param(seq, p, ts_dline); 697 print_param(seq, p, reload_ctl); 698 print_param_hex(seq, p, ahbcfg); 699 print_param(seq, p, uframe_sched); 700 print_param(seq, p, external_id_pin_ctl); 701 print_param(seq, p, power_down); 702 print_param(seq, p, lpm); 703 print_param(seq, p, lpm_clock_gating); 704 print_param(seq, p, besl); 705 print_param(seq, p, hird_threshold_en); 706 print_param(seq, p, hird_threshold); 707 print_param(seq, p, host_dma); 708 print_param(seq, p, g_dma); 709 print_param(seq, p, g_dma_desc); 710 print_param(seq, p, g_rx_fifo_size); 711 print_param(seq, p, g_np_tx_fifo_size); 712 713 for (i = 0; i < MAX_EPS_CHANNELS; i++) { 714 char str[32]; 715 716 snprintf(str, 32, "g_tx_fifo_size[%d]", i); 717 seq_printf(seq, "%-30s: %d\n", str, p->g_tx_fifo_size[i]); 718 } 719 720 return 0; 721 } 722 DEFINE_SHOW_ATTRIBUTE(params); 723 724 static int hw_params_show(struct seq_file *seq, void *v) 725 { 726 struct dwc2_hsotg *hsotg = seq->private; 727 struct dwc2_hw_params *hw = &hsotg->hw_params; 728 729 print_param(seq, hw, op_mode); 730 print_param(seq, hw, arch); 731 print_param(seq, hw, dma_desc_enable); 732 print_param(seq, hw, enable_dynamic_fifo); 733 print_param(seq, hw, en_multiple_tx_fifo); 734 print_param(seq, hw, rx_fifo_size); 735 print_param(seq, hw, host_nperio_tx_fifo_size); 736 print_param(seq, hw, dev_nperio_tx_fifo_size); 737 print_param(seq, hw, host_perio_tx_fifo_size); 738 print_param(seq, hw, nperio_tx_q_depth); 739 print_param(seq, hw, host_perio_tx_q_depth); 740 print_param(seq, hw, dev_token_q_depth); 741 print_param(seq, hw, max_transfer_size); 742 print_param(seq, hw, max_packet_count); 743 print_param(seq, hw, host_channels); 744 print_param(seq, hw, hs_phy_type); 745 print_param(seq, hw, fs_phy_type); 746 print_param(seq, hw, i2c_enable); 747 print_param(seq, hw, num_dev_ep); 748 print_param(seq, hw, num_dev_perio_in_ep); 749 print_param(seq, hw, total_fifo_size); 750 print_param(seq, hw, power_optimized); 751 print_param(seq, hw, utmi_phy_data_width); 752 print_param_hex(seq, hw, snpsid); 753 print_param_hex(seq, hw, dev_ep_dirs); 754 755 return 0; 756 } 757 DEFINE_SHOW_ATTRIBUTE(hw_params); 758 759 static int dr_mode_show(struct seq_file *seq, void *v) 760 { 761 struct dwc2_hsotg *hsotg = seq->private; 762 const char *dr_mode = ""; 763 764 device_property_read_string(hsotg->dev, "dr_mode", &dr_mode); 765 seq_printf(seq, "%s\n", dr_mode); 766 return 0; 767 } 768 DEFINE_SHOW_ATTRIBUTE(dr_mode); 769 770 int dwc2_debugfs_init(struct dwc2_hsotg *hsotg) 771 { 772 int ret; 773 struct dentry *root; 774 775 root = debugfs_create_dir(dev_name(hsotg->dev), NULL); 776 hsotg->debug_root = root; 777 778 debugfs_create_file("params", 0444, root, hsotg, ¶ms_fops); 779 debugfs_create_file("hw_params", 0444, root, hsotg, &hw_params_fops); 780 debugfs_create_file("dr_mode", 0444, root, hsotg, &dr_mode_fops); 781 782 /* Add gadget debugfs nodes */ 783 dwc2_hsotg_create_debug(hsotg); 784 785 hsotg->regset = devm_kzalloc(hsotg->dev, sizeof(*hsotg->regset), 786 GFP_KERNEL); 787 if (!hsotg->regset) { 788 ret = -ENOMEM; 789 goto err; 790 } 791 792 hsotg->regset->regs = dwc2_regs; 793 hsotg->regset->nregs = ARRAY_SIZE(dwc2_regs); 794 hsotg->regset->base = hsotg->regs; 795 796 debugfs_create_regset32("regdump", 0444, root, hsotg->regset); 797 798 return 0; 799 err: 800 debugfs_remove_recursive(hsotg->debug_root); 801 return ret; 802 } 803 804 void dwc2_debugfs_exit(struct dwc2_hsotg *hsotg) 805 { 806 debugfs_remove_recursive(hsotg->debug_root); 807 hsotg->debug_root = NULL; 808 } 809