1 /* 2 * core.h - DesignWare HS OTG Controller common declarations 3 * 4 * Copyright (C) 2004-2013 Synopsys, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The names of the above-listed copyright holders may not be used 16 * to endorse or promote products derived from this software without 17 * specific prior written permission. 18 * 19 * ALTERNATIVELY, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") as published by the Free Software 21 * Foundation; either version 2 of the License, or (at your option) any 22 * later version. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #ifndef __DWC2_CORE_H__ 38 #define __DWC2_CORE_H__ 39 40 #include <linux/phy/phy.h> 41 #include <linux/regulator/consumer.h> 42 #include <linux/usb/gadget.h> 43 #include <linux/usb/otg.h> 44 #include <linux/usb/phy.h> 45 #include "hw.h" 46 47 /* 48 * Suggested defines for tracers: 49 * - no_printk: Disable tracing 50 * - pr_info: Print this info to the console 51 * - trace_printk: Print this info to trace buffer (good for verbose logging) 52 */ 53 54 #define DWC2_TRACE_SCHEDULER no_printk 55 #define DWC2_TRACE_SCHEDULER_VB no_printk 56 57 /* Detailed scheduler tracing, but won't overwhelm console */ 58 #define dwc2_sch_dbg(hsotg, fmt, ...) \ 59 DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \ 60 dev_name(hsotg->dev), ##__VA_ARGS__) 61 62 /* Verbose scheduler tracing */ 63 #define dwc2_sch_vdbg(hsotg, fmt, ...) \ 64 DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \ 65 dev_name(hsotg->dev), ##__VA_ARGS__) 66 67 #ifdef CONFIG_MIPS 68 /* 69 * There are some MIPS machines that can run in either big-endian 70 * or little-endian mode and that use the dwc2 register without 71 * a byteswap in both ways. 72 * Unlike other architectures, MIPS apparently does not require a 73 * barrier before the __raw_writel() to synchronize with DMA but does 74 * require the barrier after the __raw_writel() to serialize a set of 75 * writes. This set of operations was added specifically for MIPS and 76 * should only be used there. 77 */ 78 static inline u32 dwc2_readl(const void __iomem *addr) 79 { 80 u32 value = __raw_readl(addr); 81 82 /* In order to preserve endianness __raw_* operation is used. Therefore 83 * a barrier is needed to ensure IO access is not re-ordered across 84 * reads or writes 85 */ 86 mb(); 87 return value; 88 } 89 90 static inline void dwc2_writel(u32 value, void __iomem *addr) 91 { 92 __raw_writel(value, addr); 93 94 /* 95 * In order to preserve endianness __raw_* operation is used. Therefore 96 * a barrier is needed to ensure IO access is not re-ordered across 97 * reads or writes 98 */ 99 mb(); 100 #ifdef DWC2_LOG_WRITES 101 pr_info("INFO:: wrote %08x to %p\n", value, addr); 102 #endif 103 } 104 #else 105 /* Normal architectures just use readl/write */ 106 static inline u32 dwc2_readl(const void __iomem *addr) 107 { 108 return readl(addr); 109 } 110 111 static inline void dwc2_writel(u32 value, void __iomem *addr) 112 { 113 writel(value, addr); 114 115 #ifdef DWC2_LOG_WRITES 116 pr_info("info:: wrote %08x to %p\n", value, addr); 117 #endif 118 } 119 #endif 120 121 /* Maximum number of Endpoints/HostChannels */ 122 #define MAX_EPS_CHANNELS 16 123 124 /* dwc2-hsotg declarations */ 125 static const char * const dwc2_hsotg_supply_names[] = { 126 "vusb_d", /* digital USB supply, 1.2V */ 127 "vusb_a", /* analog USB supply, 1.1V */ 128 }; 129 130 /* 131 * EP0_MPS_LIMIT 132 * 133 * Unfortunately there seems to be a limit of the amount of data that can 134 * be transferred by IN transactions on EP0. This is either 127 bytes or 3 135 * packets (which practically means 1 packet and 63 bytes of data) when the 136 * MPS is set to 64. 137 * 138 * This means if we are wanting to move >127 bytes of data, we need to 139 * split the transactions up, but just doing one packet at a time does 140 * not work (this may be an implicit DATA0 PID on first packet of the 141 * transaction) and doing 2 packets is outside the controller's limits. 142 * 143 * If we try to lower the MPS size for EP0, then no transfers work properly 144 * for EP0, and the system will fail basic enumeration. As no cause for this 145 * has currently been found, we cannot support any large IN transfers for 146 * EP0. 147 */ 148 #define EP0_MPS_LIMIT 64 149 150 struct dwc2_hsotg; 151 struct dwc2_hsotg_req; 152 153 /** 154 * struct dwc2_hsotg_ep - driver endpoint definition. 155 * @ep: The gadget layer representation of the endpoint. 156 * @name: The driver generated name for the endpoint. 157 * @queue: Queue of requests for this endpoint. 158 * @parent: Reference back to the parent device structure. 159 * @req: The current request that the endpoint is processing. This is 160 * used to indicate an request has been loaded onto the endpoint 161 * and has yet to be completed (maybe due to data move, or simply 162 * awaiting an ack from the core all the data has been completed). 163 * @debugfs: File entry for debugfs file for this endpoint. 164 * @lock: State lock to protect contents of endpoint. 165 * @dir_in: Set to true if this endpoint is of the IN direction, which 166 * means that it is sending data to the Host. 167 * @index: The index for the endpoint registers. 168 * @mc: Multi Count - number of transactions per microframe 169 * @interval - Interval for periodic endpoints, in frames or microframes. 170 * @name: The name array passed to the USB core. 171 * @halted: Set if the endpoint has been halted. 172 * @periodic: Set if this is a periodic ep, such as Interrupt 173 * @isochronous: Set if this is a isochronous ep 174 * @send_zlp: Set if we need to send a zero-length packet. 175 * @total_data: The total number of data bytes done. 176 * @fifo_size: The size of the FIFO (for periodic IN endpoints) 177 * @fifo_load: The amount of data loaded into the FIFO (periodic IN) 178 * @last_load: The offset of data for the last start of request. 179 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN 180 * @target_frame: Targeted frame num to setup next ISOC transfer 181 * @frame_overrun: Indicates SOF number overrun in DSTS 182 * 183 * This is the driver's state for each registered enpoint, allowing it 184 * to keep track of transactions that need doing. Each endpoint has a 185 * lock to protect the state, to try and avoid using an overall lock 186 * for the host controller as much as possible. 187 * 188 * For periodic IN endpoints, we have fifo_size and fifo_load to try 189 * and keep track of the amount of data in the periodic FIFO for each 190 * of these as we don't have a status register that tells us how much 191 * is in each of them. (note, this may actually be useless information 192 * as in shared-fifo mode periodic in acts like a single-frame packet 193 * buffer than a fifo) 194 */ 195 struct dwc2_hsotg_ep { 196 struct usb_ep ep; 197 struct list_head queue; 198 struct dwc2_hsotg *parent; 199 struct dwc2_hsotg_req *req; 200 struct dentry *debugfs; 201 202 unsigned long total_data; 203 unsigned int size_loaded; 204 unsigned int last_load; 205 unsigned int fifo_load; 206 unsigned short fifo_size; 207 unsigned short fifo_index; 208 209 unsigned char dir_in; 210 unsigned char index; 211 unsigned char mc; 212 unsigned char interval; 213 214 unsigned int halted:1; 215 unsigned int periodic:1; 216 unsigned int isochronous:1; 217 unsigned int send_zlp:1; 218 unsigned int target_frame; 219 #define TARGET_FRAME_INITIAL 0xFFFFFFFF 220 bool frame_overrun; 221 222 char name[10]; 223 }; 224 225 /** 226 * struct dwc2_hsotg_req - data transfer request 227 * @req: The USB gadget request 228 * @queue: The list of requests for the endpoint this is queued for. 229 * @saved_req_buf: variable to save req.buf when bounce buffers are used. 230 */ 231 struct dwc2_hsotg_req { 232 struct usb_request req; 233 struct list_head queue; 234 void *saved_req_buf; 235 }; 236 237 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 238 #define call_gadget(_hs, _entry) \ 239 do { \ 240 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ 241 (_hs)->driver && (_hs)->driver->_entry) { \ 242 spin_unlock(&_hs->lock); \ 243 (_hs)->driver->_entry(&(_hs)->gadget); \ 244 spin_lock(&_hs->lock); \ 245 } \ 246 } while (0) 247 #else 248 #define call_gadget(_hs, _entry) do {} while (0) 249 #endif 250 251 struct dwc2_hsotg; 252 struct dwc2_host_chan; 253 254 /* Device States */ 255 enum dwc2_lx_state { 256 DWC2_L0, /* On state */ 257 DWC2_L1, /* LPM sleep state */ 258 DWC2_L2, /* USB suspend state */ 259 DWC2_L3, /* Off state */ 260 }; 261 262 /* Gadget ep0 states */ 263 enum dwc2_ep0_state { 264 DWC2_EP0_SETUP, 265 DWC2_EP0_DATA_IN, 266 DWC2_EP0_DATA_OUT, 267 DWC2_EP0_STATUS_IN, 268 DWC2_EP0_STATUS_OUT, 269 }; 270 271 /** 272 * struct dwc2_core_params - Parameters for configuring the core 273 * 274 * @otg_cap: Specifies the OTG capabilities. 275 * 0 - HNP and SRP capable 276 * 1 - SRP Only capable 277 * 2 - No HNP/SRP capable (always available) 278 * Defaults to best available option (0, 1, then 2) 279 * @otg_ver: OTG version supported 280 * 0 - 1.3 (default) 281 * 1 - 2.0 282 * @dma_enable: Specifies whether to use slave or DMA mode for accessing 283 * the data FIFOs. The driver will automatically detect the 284 * value for this parameter if none is specified. 285 * 0 - Slave (always available) 286 * 1 - DMA (default, if available) 287 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 288 * address DMA mode or descriptor DMA mode for accessing 289 * the data FIFOs. The driver will automatically detect the 290 * value for this if none is specified. 291 * 0 - Address DMA 292 * 1 - Descriptor DMA (default, if available) 293 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use 294 * address DMA mode or descriptor DMA mode for accessing 295 * the data FIFOs in Full Speed mode only. The driver 296 * will automatically detect the value for this if none is 297 * specified. 298 * 0 - Address DMA 299 * 1 - Descriptor DMA in FS (default, if available) 300 * @speed: Specifies the maximum speed of operation in host and 301 * device mode. The actual speed depends on the speed of 302 * the attached device and the value of phy_type. 303 * 0 - High Speed 304 * (default when phy_type is UTMI+ or ULPI) 305 * 1 - Full Speed 306 * (default when phy_type is Full Speed) 307 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 308 * 1 - Allow dynamic FIFO sizing (default, if available) 309 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 310 * are enabled 311 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 312 * dynamic FIFO sizing is enabled 313 * 16 to 32768 314 * Actual maximum value is autodetected and also 315 * the default. 316 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 317 * in host mode when dynamic FIFO sizing is enabled 318 * 16 to 32768 319 * Actual maximum value is autodetected and also 320 * the default. 321 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 322 * host mode when dynamic FIFO sizing is enabled 323 * 16 to 32768 324 * Actual maximum value is autodetected and also 325 * the default. 326 * @max_transfer_size: The maximum transfer size supported, in bytes 327 * 2047 to 65,535 328 * Actual maximum value is autodetected and also 329 * the default. 330 * @max_packet_count: The maximum number of packets in a transfer 331 * 15 to 511 332 * Actual maximum value is autodetected and also 333 * the default. 334 * @host_channels: The number of host channel registers to use 335 * 1 to 16 336 * Actual maximum value is autodetected and also 337 * the default. 338 * @phy_type: Specifies the type of PHY interface to use. By default, 339 * the driver will automatically detect the phy_type. 340 * 0 - Full Speed Phy 341 * 1 - UTMI+ Phy 342 * 2 - ULPI Phy 343 * Defaults to best available option (2, 1, then 0) 344 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 345 * is applicable for a phy_type of UTMI+ or ULPI. (For a 346 * ULPI phy_type, this parameter indicates the data width 347 * between the MAC and the ULPI Wrapper.) Also, this 348 * parameter is applicable only if the OTG_HSPHY_WIDTH cC 349 * parameter was set to "8 and 16 bits", meaning that the 350 * core has been configured to work at either data path 351 * width. 352 * 8 or 16 (default 16 if available) 353 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 354 * data rate. This parameter is only applicable if phy_type 355 * is ULPI. 356 * 0 - single data rate ULPI interface with 8 bit wide 357 * data bus (default) 358 * 1 - double data rate ULPI interface with 4 bit wide 359 * data bus 360 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 361 * external supply to drive the VBus 362 * 0 - Internal supply (default) 363 * 1 - External supply 364 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 365 * speed PHY. This parameter is only applicable if phy_type 366 * is FS. 367 * 0 - No (default) 368 * 1 - Yes 369 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 370 * 0 - No (default) 371 * 1 - Yes 372 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 373 * when attached to a Full Speed or Low Speed device in 374 * host mode. 375 * 0 - Don't support low power mode (default) 376 * 1 - Support low power mode 377 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 378 * when connected to a Low Speed device in host 379 * mode. This parameter is applicable only if 380 * host_support_fs_ls_low_power is enabled. 381 * 0 - 48 MHz 382 * (default when phy_type is UTMI+ or ULPI) 383 * 1 - 6 MHz 384 * (default when phy_type is Full Speed) 385 * @ts_dline: Enable Term Select Dline pulsing 386 * 0 - No (default) 387 * 1 - Yes 388 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 389 * 0 - No (default for core < 2.92a) 390 * 1 - Yes (default for core >= 2.92a) 391 * @ahbcfg: This field allows the default value of the GAHBCFG 392 * register to be overridden 393 * -1 - GAHBCFG value will be set to 0x06 394 * (INCR4, default) 395 * all others - GAHBCFG value will be overridden with 396 * this value 397 * Not all bits can be controlled like this, the 398 * bits defined by GAHBCFG_CTRL_MASK are controlled 399 * by the driver and are ignored in this 400 * configuration value. 401 * @uframe_sched: True to enable the microframe scheduler 402 * @external_id_pin_ctl: Specifies whether ID pin is handled externally. 403 * Disable CONIDSTSCHNG controller interrupt in such 404 * case. 405 * 0 - No (default) 406 * 1 - Yes 407 * @hibernation: Specifies whether the controller support hibernation. 408 * If hibernation is enabled, the controller will enter 409 * hibernation in both peripheral and host mode when 410 * needed. 411 * 0 - No (default) 412 * 1 - Yes 413 * 414 * The following parameters may be specified when starting the module. These 415 * parameters define how the DWC_otg controller should be configured. A 416 * value of -1 (or any other out of range value) for any parameter means 417 * to read the value from hardware (if possible) or use the builtin 418 * default described above. 419 */ 420 struct dwc2_core_params { 421 /* 422 * Don't add any non-int members here, this will break 423 * dwc2_set_all_params! 424 */ 425 int otg_cap; 426 int otg_ver; 427 int dma_enable; 428 int dma_desc_enable; 429 int dma_desc_fs_enable; 430 int speed; 431 int enable_dynamic_fifo; 432 int en_multiple_tx_fifo; 433 int host_rx_fifo_size; 434 int host_nperio_tx_fifo_size; 435 int host_perio_tx_fifo_size; 436 int max_transfer_size; 437 int max_packet_count; 438 int host_channels; 439 int phy_type; 440 int phy_utmi_width; 441 int phy_ulpi_ddr; 442 int phy_ulpi_ext_vbus; 443 int i2c_enable; 444 int ulpi_fs_ls; 445 int host_support_fs_ls_low_power; 446 int host_ls_low_power_phy_clk; 447 int ts_dline; 448 int reload_ctl; 449 int ahbcfg; 450 int uframe_sched; 451 int external_id_pin_ctl; 452 int hibernation; 453 }; 454 455 /** 456 * struct dwc2_hw_params - Autodetected parameters. 457 * 458 * These parameters are the various parameters read from hardware 459 * registers during initialization. They typically contain the best 460 * supported or maximum value that can be configured in the 461 * corresponding dwc2_core_params value. 462 * 463 * The values that are not in dwc2_core_params are documented below. 464 * 465 * @op_mode Mode of Operation 466 * 0 - HNP- and SRP-Capable OTG (Host & Device) 467 * 1 - SRP-Capable OTG (Host & Device) 468 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 469 * 3 - SRP-Capable Device 470 * 4 - Non-OTG Device 471 * 5 - SRP-Capable Host 472 * 6 - Non-OTG Host 473 * @arch Architecture 474 * 0 - Slave only 475 * 1 - External DMA 476 * 2 - Internal DMA 477 * @power_optimized Are power optimizations enabled? 478 * @num_dev_ep Number of device endpoints available 479 * @num_dev_perio_in_ep Number of device periodic IN endpoints 480 * available 481 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue 482 * Depth 483 * 0 to 30 484 * @host_perio_tx_q_depth 485 * Host Mode Periodic Request Queue Depth 486 * 2, 4 or 8 487 * @nperio_tx_q_depth 488 * Non-Periodic Request Queue Depth 489 * 2, 4 or 8 490 * @hs_phy_type High-speed PHY interface type 491 * 0 - High-speed interface not supported 492 * 1 - UTMI+ 493 * 2 - ULPI 494 * 3 - UTMI+ and ULPI 495 * @fs_phy_type Full-speed PHY interface type 496 * 0 - Full speed interface not supported 497 * 1 - Dedicated full speed interface 498 * 2 - FS pins shared with UTMI+ pins 499 * 3 - FS pins shared with ULPI pins 500 * @total_fifo_size: Total internal RAM for FIFOs (bytes) 501 * @utmi_phy_data_width UTMI+ PHY data width 502 * 0 - 8 bits 503 * 1 - 16 bits 504 * 2 - 8 or 16 bits 505 * @snpsid: Value from SNPSID register 506 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1) 507 */ 508 struct dwc2_hw_params { 509 unsigned op_mode:3; 510 unsigned arch:2; 511 unsigned dma_desc_enable:1; 512 unsigned dma_desc_fs_enable:1; 513 unsigned enable_dynamic_fifo:1; 514 unsigned en_multiple_tx_fifo:1; 515 unsigned host_rx_fifo_size:16; 516 unsigned host_nperio_tx_fifo_size:16; 517 unsigned dev_nperio_tx_fifo_size:16; 518 unsigned host_perio_tx_fifo_size:16; 519 unsigned nperio_tx_q_depth:3; 520 unsigned host_perio_tx_q_depth:3; 521 unsigned dev_token_q_depth:5; 522 unsigned max_transfer_size:26; 523 unsigned max_packet_count:11; 524 unsigned host_channels:5; 525 unsigned hs_phy_type:2; 526 unsigned fs_phy_type:2; 527 unsigned i2c_enable:1; 528 unsigned num_dev_ep:4; 529 unsigned num_dev_perio_in_ep:4; 530 unsigned total_fifo_size:16; 531 unsigned power_optimized:1; 532 unsigned utmi_phy_data_width:2; 533 u32 snpsid; 534 u32 dev_ep_dirs; 535 }; 536 537 /* Size of control and EP0 buffers */ 538 #define DWC2_CTRL_BUFF_SIZE 8 539 540 /** 541 * struct dwc2_gregs_backup - Holds global registers state before entering partial 542 * power down 543 * @gotgctl: Backup of GOTGCTL register 544 * @gintmsk: Backup of GINTMSK register 545 * @gahbcfg: Backup of GAHBCFG register 546 * @gusbcfg: Backup of GUSBCFG register 547 * @grxfsiz: Backup of GRXFSIZ register 548 * @gnptxfsiz: Backup of GNPTXFSIZ register 549 * @gi2cctl: Backup of GI2CCTL register 550 * @hptxfsiz: Backup of HPTXFSIZ register 551 * @gdfifocfg: Backup of GDFIFOCFG register 552 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 553 * @gpwrdn: Backup of GPWRDN register 554 */ 555 struct dwc2_gregs_backup { 556 u32 gotgctl; 557 u32 gintmsk; 558 u32 gahbcfg; 559 u32 gusbcfg; 560 u32 grxfsiz; 561 u32 gnptxfsiz; 562 u32 gi2cctl; 563 u32 hptxfsiz; 564 u32 pcgcctl; 565 u32 gdfifocfg; 566 u32 dtxfsiz[MAX_EPS_CHANNELS]; 567 u32 gpwrdn; 568 bool valid; 569 }; 570 571 /** 572 * struct dwc2_dregs_backup - Holds device registers state before entering partial 573 * power down 574 * @dcfg: Backup of DCFG register 575 * @dctl: Backup of DCTL register 576 * @daintmsk: Backup of DAINTMSK register 577 * @diepmsk: Backup of DIEPMSK register 578 * @doepmsk: Backup of DOEPMSK register 579 * @diepctl: Backup of DIEPCTL register 580 * @dieptsiz: Backup of DIEPTSIZ register 581 * @diepdma: Backup of DIEPDMA register 582 * @doepctl: Backup of DOEPCTL register 583 * @doeptsiz: Backup of DOEPTSIZ register 584 * @doepdma: Backup of DOEPDMA register 585 */ 586 struct dwc2_dregs_backup { 587 u32 dcfg; 588 u32 dctl; 589 u32 daintmsk; 590 u32 diepmsk; 591 u32 doepmsk; 592 u32 diepctl[MAX_EPS_CHANNELS]; 593 u32 dieptsiz[MAX_EPS_CHANNELS]; 594 u32 diepdma[MAX_EPS_CHANNELS]; 595 u32 doepctl[MAX_EPS_CHANNELS]; 596 u32 doeptsiz[MAX_EPS_CHANNELS]; 597 u32 doepdma[MAX_EPS_CHANNELS]; 598 bool valid; 599 }; 600 601 /** 602 * struct dwc2_hregs_backup - Holds host registers state before entering partial 603 * power down 604 * @hcfg: Backup of HCFG register 605 * @haintmsk: Backup of HAINTMSK register 606 * @hcintmsk: Backup of HCINTMSK register 607 * @hptr0: Backup of HPTR0 register 608 * @hfir: Backup of HFIR register 609 */ 610 struct dwc2_hregs_backup { 611 u32 hcfg; 612 u32 haintmsk; 613 u32 hcintmsk[MAX_EPS_CHANNELS]; 614 u32 hprt0; 615 u32 hfir; 616 bool valid; 617 }; 618 619 /* 620 * Constants related to high speed periodic scheduling 621 * 622 * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a 623 * reservation point of view it's assumed that the schedule goes right back to 624 * the beginning after the end of the schedule. 625 * 626 * What does that mean for scheduling things with a long interval? It means 627 * we'll reserve time for them in every possible microframe that they could 628 * ever be scheduled in. ...but we'll still only actually schedule them as 629 * often as they were requested. 630 * 631 * We keep our schedule in a "bitmap" structure. This simplifies having 632 * to keep track of and merge intervals: we just let the bitmap code do most 633 * of the heavy lifting. In a way scheduling is much like memory allocation. 634 * 635 * We schedule 100us per uframe or 80% of 125us (the maximum amount you're 636 * supposed to schedule for periodic transfers). That's according to spec. 637 * 638 * Note that though we only schedule 80% of each microframe, the bitmap that we 639 * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of 640 * space for each uFrame). 641 * 642 * Requirements: 643 * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1) 644 * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably 645 * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might 646 * be bugs). The 8 comes from the USB spec: number of microframes per frame. 647 */ 648 #define DWC2_US_PER_UFRAME 125 649 #define DWC2_HS_PERIODIC_US_PER_UFRAME 100 650 651 #define DWC2_HS_SCHEDULE_UFRAMES 8 652 #define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \ 653 DWC2_HS_PERIODIC_US_PER_UFRAME) 654 655 /* 656 * Constants related to low speed scheduling 657 * 658 * For high speed we schedule every 1us. For low speed that's a bit overkill, 659 * so we make up a unit called a "slice" that's worth 25us. There are 40 660 * slices in a full frame and we can schedule 36 of those (90%) for periodic 661 * transfers. 662 * 663 * Our low speed schedule can be as short as 1 frame or could be longer. When 664 * we only schedule 1 frame it means that we'll need to reserve a time every 665 * frame even for things that only transfer very rarely, so something that runs 666 * every 2048 frames will get time reserved in every frame. Our low speed 667 * schedule can be longer and we'll be able to handle more overlap, but that 668 * will come at increased memory cost and increased time to schedule. 669 * 670 * Note: one other advantage of a short low speed schedule is that if we mess 671 * up and miss scheduling we can jump in and use any of the slots that we 672 * happened to reserve. 673 * 674 * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for 675 * the schedule. There will be one schedule per TT. 676 * 677 * Requirements: 678 * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME. 679 */ 680 #define DWC2_US_PER_SLICE 25 681 #define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE) 682 683 #define DWC2_ROUND_US_TO_SLICE(us) \ 684 (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \ 685 DWC2_US_PER_SLICE) 686 687 #define DWC2_LS_PERIODIC_US_PER_FRAME \ 688 900 689 #define DWC2_LS_PERIODIC_SLICES_PER_FRAME \ 690 (DWC2_LS_PERIODIC_US_PER_FRAME / \ 691 DWC2_US_PER_SLICE) 692 693 #define DWC2_LS_SCHEDULE_FRAMES 1 694 #define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \ 695 DWC2_LS_PERIODIC_SLICES_PER_FRAME) 696 697 /** 698 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 699 * and periodic schedules 700 * 701 * These are common for both host and peripheral modes: 702 * 703 * @dev: The struct device pointer 704 * @regs: Pointer to controller regs 705 * @hw_params: Parameters that were autodetected from the 706 * hardware registers 707 * @core_params: Parameters that define how the core should be configured 708 * @op_state: The operational State, during transitions (a_host=> 709 * a_peripheral and b_device=>b_host) this may not match 710 * the core, but allows the software to determine 711 * transitions 712 * @dr_mode: Requested mode of operation, one of following: 713 * - USB_DR_MODE_PERIPHERAL 714 * - USB_DR_MODE_HOST 715 * - USB_DR_MODE_OTG 716 * @hcd_enabled Host mode sub-driver initialization indicator. 717 * @gadget_enabled Peripheral mode sub-driver initialization indicator. 718 * @ll_hw_enabled Status of low-level hardware resources. 719 * @phy: The otg phy transceiver structure for phy control. 720 * @uphy: The otg phy transceiver structure for old USB phy control. 721 * @plat: The platform specific configuration data. This can be removed once 722 * all SoCs support usb transceiver. 723 * @supplies: Definition of USB power supplies 724 * @phyif: PHY interface width 725 * @lock: Spinlock that protects all the driver data structures 726 * @priv: Stores a pointer to the struct usb_hcd 727 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 728 * transfer are in process of being queued 729 * @srp_success: Stores status of SRP request in the case of a FS PHY 730 * with an I2C interface 731 * @wq_otg: Workqueue object used for handling of some interrupts 732 * @wf_otg: Work object for handling Connector ID Status Change 733 * interrupt 734 * @wkp_timer: Timer object for handling Wakeup Detected interrupt 735 * @lx_state: Lx state of connected device 736 * @gregs_backup: Backup of global registers during suspend 737 * @dregs_backup: Backup of device registers during suspend 738 * @hregs_backup: Backup of host registers during suspend 739 * 740 * These are for host mode: 741 * 742 * @flags: Flags for handling root port state changes 743 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 744 * Transfers associated with these QHs are not currently 745 * assigned to a host channel. 746 * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 747 * Transfers associated with these QHs are currently 748 * assigned to a host channel. 749 * @non_periodic_qh_ptr: Pointer to next QH to process in the active 750 * non-periodic schedule 751 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 752 * list of QHs for periodic transfers that are _not_ 753 * scheduled for the next frame. Each QH in the list has an 754 * interval counter that determines when it needs to be 755 * scheduled for execution. This scheduling mechanism 756 * allows only a simple calculation for periodic bandwidth 757 * used (i.e. must assume that all periodic transfers may 758 * need to execute in the same frame). However, it greatly 759 * simplifies scheduling and should be sufficient for the 760 * vast majority of OTG hosts, which need to connect to a 761 * small number of peripherals at one time. Items move from 762 * this list to periodic_sched_ready when the QH interval 763 * counter is 0 at SOF. 764 * @periodic_sched_ready: List of periodic QHs that are ready for execution in 765 * the next frame, but have not yet been assigned to host 766 * channels. Items move from this list to 767 * periodic_sched_assigned as host channels become 768 * available during the current frame. 769 * @periodic_sched_assigned: List of periodic QHs to be executed in the next 770 * frame that are assigned to host channels. Items move 771 * from this list to periodic_sched_queued as the 772 * transactions for the QH are queued to the DWC_otg 773 * controller. 774 * @periodic_sched_queued: List of periodic QHs that have been queued for 775 * execution. Items move from this list to either 776 * periodic_sched_inactive or periodic_sched_ready when the 777 * channel associated with the transfer is released. If the 778 * interval for the QH is 1, the item moves to 779 * periodic_sched_ready because it must be rescheduled for 780 * the next frame. Otherwise, the item moves to 781 * periodic_sched_inactive. 782 * @split_order: List keeping track of channels doing splits, in order. 783 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 784 * This value is in microseconds per (micro)frame. The 785 * assumption is that all periodic transfers may occur in 786 * the same (micro)frame. 787 * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the 788 * host is in high speed mode; low speed schedules are 789 * stored elsewhere since we need one per TT. 790 * @frame_number: Frame number read from the core at SOF. The value ranges 791 * from 0 to HFNUM_MAX_FRNUM. 792 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 793 * SOF enable/disable. 794 * @free_hc_list: Free host channels in the controller. This is a list of 795 * struct dwc2_host_chan items. 796 * @periodic_channels: Number of host channels assigned to periodic transfers. 797 * Currently assuming that there is a dedicated host 798 * channel for each periodic transaction and at least one 799 * host channel is available for non-periodic transactions. 800 * @non_periodic_channels: Number of host channels assigned to non-periodic 801 * transfers 802 * @available_host_channels Number of host channels available for the microframe 803 * scheduler to use 804 * @hc_ptr_array: Array of pointers to the host channel descriptors. 805 * Allows accessing a host channel descriptor given the 806 * host channel number. This is useful in interrupt 807 * handlers. 808 * @status_buf: Buffer used for data received during the status phase of 809 * a control transfer. 810 * @status_buf_dma: DMA address for status_buf 811 * @start_work: Delayed work for handling host A-cable connection 812 * @reset_work: Delayed work for handling a port reset 813 * @otg_port: OTG port number 814 * @frame_list: Frame list 815 * @frame_list_dma: Frame list DMA address 816 * @frame_list_sz: Frame list size 817 * @desc_gen_cache: Kmem cache for generic descriptors 818 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors 819 * 820 * These are for peripheral mode: 821 * 822 * @driver: USB gadget driver 823 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 824 * @num_of_eps: Number of available EPs (excluding EP0) 825 * @debug_root: Root directrory for debugfs. 826 * @debug_file: Main status file for debugfs. 827 * @debug_testmode: Testmode status file for debugfs. 828 * @debug_fifo: FIFO status file for debugfs. 829 * @ep0_reply: Request used for ep0 reply. 830 * @ep0_buff: Buffer for EP0 reply data, if needed. 831 * @ctrl_buff: Buffer for EP0 control requests. 832 * @ctrl_req: Request for EP0 control packets. 833 * @ep0_state: EP0 control transfers state 834 * @test_mode: USB test mode requested by the host 835 * @eps: The endpoints being supplied to the gadget framework 836 * @g_using_dma: Indicate if dma usage is enabled 837 * @g_rx_fifo_sz: Contains rx fifo size value 838 * @g_np_g_tx_fifo_sz: Contains Non-Periodic tx fifo size value 839 * @g_tx_fifo_sz: Contains tx fifo size value per endpoints 840 */ 841 struct dwc2_hsotg { 842 struct device *dev; 843 void __iomem *regs; 844 /** Params detected from hardware */ 845 struct dwc2_hw_params hw_params; 846 /** Params to actually use */ 847 struct dwc2_core_params *core_params; 848 enum usb_otg_state op_state; 849 enum usb_dr_mode dr_mode; 850 unsigned int hcd_enabled:1; 851 unsigned int gadget_enabled:1; 852 unsigned int ll_hw_enabled:1; 853 854 struct phy *phy; 855 struct usb_phy *uphy; 856 struct dwc2_hsotg_plat *plat; 857 struct regulator_bulk_data supplies[ARRAY_SIZE(dwc2_hsotg_supply_names)]; 858 u32 phyif; 859 860 spinlock_t lock; 861 void *priv; 862 int irq; 863 struct clk *clk; 864 struct reset_control *reset; 865 866 unsigned int queuing_high_bandwidth:1; 867 unsigned int srp_success:1; 868 869 struct workqueue_struct *wq_otg; 870 struct work_struct wf_otg; 871 struct timer_list wkp_timer; 872 enum dwc2_lx_state lx_state; 873 struct dwc2_gregs_backup gr_backup; 874 struct dwc2_dregs_backup dr_backup; 875 struct dwc2_hregs_backup hr_backup; 876 877 struct dentry *debug_root; 878 struct debugfs_regset32 *regset; 879 880 /* DWC OTG HW Release versions */ 881 #define DWC2_CORE_REV_2_71a 0x4f54271a 882 #define DWC2_CORE_REV_2_90a 0x4f54290a 883 #define DWC2_CORE_REV_2_92a 0x4f54292a 884 #define DWC2_CORE_REV_2_94a 0x4f54294a 885 #define DWC2_CORE_REV_3_00a 0x4f54300a 886 #define DWC2_CORE_REV_3_10a 0x4f54310a 887 888 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 889 union dwc2_hcd_internal_flags { 890 u32 d32; 891 struct { 892 unsigned port_connect_status_change:1; 893 unsigned port_connect_status:1; 894 unsigned port_reset_change:1; 895 unsigned port_enable_change:1; 896 unsigned port_suspend_change:1; 897 unsigned port_over_current_change:1; 898 unsigned port_l1_change:1; 899 unsigned reserved:25; 900 } b; 901 } flags; 902 903 struct list_head non_periodic_sched_inactive; 904 struct list_head non_periodic_sched_active; 905 struct list_head *non_periodic_qh_ptr; 906 struct list_head periodic_sched_inactive; 907 struct list_head periodic_sched_ready; 908 struct list_head periodic_sched_assigned; 909 struct list_head periodic_sched_queued; 910 struct list_head split_order; 911 u16 periodic_usecs; 912 unsigned long hs_periodic_bitmap[ 913 DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)]; 914 u16 frame_number; 915 u16 periodic_qh_count; 916 bool bus_suspended; 917 bool new_connection; 918 919 u16 last_frame_num; 920 921 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 922 #define FRAME_NUM_ARRAY_SIZE 1000 923 u16 *frame_num_array; 924 u16 *last_frame_num_array; 925 int frame_num_idx; 926 int dumped_frame_num_array; 927 #endif 928 929 struct list_head free_hc_list; 930 int periodic_channels; 931 int non_periodic_channels; 932 int available_host_channels; 933 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 934 u8 *status_buf; 935 dma_addr_t status_buf_dma; 936 #define DWC2_HCD_STATUS_BUF_SIZE 64 937 938 struct delayed_work start_work; 939 struct delayed_work reset_work; 940 u8 otg_port; 941 u32 *frame_list; 942 dma_addr_t frame_list_dma; 943 u32 frame_list_sz; 944 struct kmem_cache *desc_gen_cache; 945 struct kmem_cache *desc_hsisoc_cache; 946 947 #ifdef DEBUG 948 u32 frrem_samples; 949 u64 frrem_accum; 950 951 u32 hfnum_7_samples_a; 952 u64 hfnum_7_frrem_accum_a; 953 u32 hfnum_0_samples_a; 954 u64 hfnum_0_frrem_accum_a; 955 u32 hfnum_other_samples_a; 956 u64 hfnum_other_frrem_accum_a; 957 958 u32 hfnum_7_samples_b; 959 u64 hfnum_7_frrem_accum_b; 960 u32 hfnum_0_samples_b; 961 u64 hfnum_0_frrem_accum_b; 962 u32 hfnum_other_samples_b; 963 u64 hfnum_other_frrem_accum_b; 964 #endif 965 #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ 966 967 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 968 /* Gadget structures */ 969 struct usb_gadget_driver *driver; 970 int fifo_mem; 971 unsigned int dedicated_fifos:1; 972 unsigned char num_of_eps; 973 u32 fifo_map; 974 975 struct usb_request *ep0_reply; 976 struct usb_request *ctrl_req; 977 void *ep0_buff; 978 void *ctrl_buff; 979 enum dwc2_ep0_state ep0_state; 980 u8 test_mode; 981 982 struct usb_gadget gadget; 983 unsigned int enabled:1; 984 unsigned int connected:1; 985 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS]; 986 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS]; 987 u32 g_using_dma; 988 u32 g_rx_fifo_sz; 989 u32 g_np_g_tx_fifo_sz; 990 u32 g_tx_fifo_sz[MAX_EPS_CHANNELS]; 991 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 992 }; 993 994 /* Reasons for halting a host channel */ 995 enum dwc2_halt_status { 996 DWC2_HC_XFER_NO_HALT_STATUS, 997 DWC2_HC_XFER_COMPLETE, 998 DWC2_HC_XFER_URB_COMPLETE, 999 DWC2_HC_XFER_ACK, 1000 DWC2_HC_XFER_NAK, 1001 DWC2_HC_XFER_NYET, 1002 DWC2_HC_XFER_STALL, 1003 DWC2_HC_XFER_XACT_ERR, 1004 DWC2_HC_XFER_FRAME_OVERRUN, 1005 DWC2_HC_XFER_BABBLE_ERR, 1006 DWC2_HC_XFER_DATA_TOGGLE_ERR, 1007 DWC2_HC_XFER_AHB_ERR, 1008 DWC2_HC_XFER_PERIODIC_INCOMPLETE, 1009 DWC2_HC_XFER_URB_DEQUEUE, 1010 }; 1011 1012 /* 1013 * The following functions support initialization of the core driver component 1014 * and the DWC_otg controller 1015 */ 1016 extern int dwc2_core_reset(struct dwc2_hsotg *hsotg); 1017 extern int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg); 1018 extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg); 1019 extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore); 1020 1021 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg); 1022 1023 extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 1024 1025 /* 1026 * Common core Functions. 1027 * The following functions support managing the DWC_otg controller in either 1028 * device or host mode. 1029 */ 1030 extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 1031 extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 1032 extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 1033 1034 extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 1035 extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 1036 1037 /* This function should be called on every hardware interrupt. */ 1038 extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 1039 1040 /* OTG Core Parameters */ 1041 1042 /* 1043 * Specifies the OTG capabilities. The driver will automatically 1044 * detect the value for this parameter if none is specified. 1045 * 0 - HNP and SRP capable (default) 1046 * 1 - SRP Only capable 1047 * 2 - No HNP/SRP capable 1048 */ 1049 extern void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val); 1050 #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 1051 #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 1052 #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 1053 1054 /* 1055 * Specifies whether to use slave or DMA mode for accessing the data 1056 * FIFOs. The driver will automatically detect the value for this 1057 * parameter if none is specified. 1058 * 0 - Slave 1059 * 1 - DMA (default, if available) 1060 */ 1061 extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val); 1062 1063 /* 1064 * When DMA mode is enabled specifies whether to use 1065 * address DMA or DMA Descritor mode for accessing the data 1066 * FIFOs in device mode. The driver will automatically detect 1067 * the value for this parameter if none is specified. 1068 * 0 - address DMA 1069 * 1 - DMA Descriptor(default, if available) 1070 */ 1071 extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val); 1072 1073 /* 1074 * When DMA mode is enabled specifies whether to use 1075 * address DMA or DMA Descritor mode with full speed devices 1076 * for accessing the data FIFOs in host mode. 1077 * 0 - address DMA 1078 * 1 - FS DMA Descriptor(default, if available) 1079 */ 1080 extern void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg, 1081 int val); 1082 1083 /* 1084 * Specifies the maximum speed of operation in host and device mode. 1085 * The actual speed depends on the speed of the attached device and 1086 * the value of phy_type. The actual speed depends on the speed of the 1087 * attached device. 1088 * 0 - High Speed (default) 1089 * 1 - Full Speed 1090 */ 1091 extern void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val); 1092 #define DWC2_SPEED_PARAM_HIGH 0 1093 #define DWC2_SPEED_PARAM_FULL 1 1094 1095 /* 1096 * Specifies whether low power mode is supported when attached 1097 * to a Full Speed or Low Speed device in host mode. 1098 * 1099 * 0 - Don't support low power mode (default) 1100 * 1 - Support low power mode 1101 */ 1102 extern void dwc2_set_param_host_support_fs_ls_low_power( 1103 struct dwc2_hsotg *hsotg, int val); 1104 1105 /* 1106 * Specifies the PHY clock rate in low power mode when connected to a 1107 * Low Speed device in host mode. This parameter is applicable only if 1108 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS 1109 * then defaults to 6 MHZ otherwise 48 MHZ. 1110 * 1111 * 0 - 48 MHz 1112 * 1 - 6 MHz 1113 */ 1114 extern void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, 1115 int val); 1116 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 1117 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 1118 1119 /* 1120 * 0 - Use cC FIFO size parameters 1121 * 1 - Allow dynamic FIFO sizing (default) 1122 */ 1123 extern void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, 1124 int val); 1125 1126 /* 1127 * Number of 4-byte words in the Rx FIFO in host mode when dynamic 1128 * FIFO sizing is enabled. 1129 * 16 to 32768 (default 1024) 1130 */ 1131 extern void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val); 1132 1133 /* 1134 * Number of 4-byte words in the non-periodic Tx FIFO in host mode 1135 * when Dynamic FIFO sizing is enabled in the core. 1136 * 16 to 32768 (default 256) 1137 */ 1138 extern void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, 1139 int val); 1140 1141 /* 1142 * Number of 4-byte words in the host periodic Tx FIFO when dynamic 1143 * FIFO sizing is enabled. 1144 * 16 to 32768 (default 256) 1145 */ 1146 extern void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, 1147 int val); 1148 1149 /* 1150 * The maximum transfer size supported in bytes. 1151 * 2047 to 65,535 (default 65,535) 1152 */ 1153 extern void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val); 1154 1155 /* 1156 * The maximum number of packets in a transfer. 1157 * 15 to 511 (default 511) 1158 */ 1159 extern void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val); 1160 1161 /* 1162 * The number of host channel registers to use. 1163 * 1 to 16 (default 11) 1164 * Note: The FPGA configuration supports a maximum of 11 host channels. 1165 */ 1166 extern void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val); 1167 1168 /* 1169 * Specifies the type of PHY interface to use. By default, the driver 1170 * will automatically detect the phy_type. 1171 * 1172 * 0 - Full Speed PHY 1173 * 1 - UTMI+ (default) 1174 * 2 - ULPI 1175 */ 1176 extern void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val); 1177 #define DWC2_PHY_TYPE_PARAM_FS 0 1178 #define DWC2_PHY_TYPE_PARAM_UTMI 1 1179 #define DWC2_PHY_TYPE_PARAM_ULPI 2 1180 1181 /* 1182 * Specifies the UTMI+ Data Width. This parameter is 1183 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI 1184 * PHY_TYPE, this parameter indicates the data width between 1185 * the MAC and the ULPI Wrapper.) Also, this parameter is 1186 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set 1187 * to "8 and 16 bits", meaning that the core has been 1188 * configured to work at either data path width. 1189 * 1190 * 8 or 16 bits (default 16) 1191 */ 1192 extern void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val); 1193 1194 /* 1195 * Specifies whether the ULPI operates at double or single 1196 * data rate. This parameter is only applicable if PHY_TYPE is 1197 * ULPI. 1198 * 1199 * 0 - single data rate ULPI interface with 8 bit wide data 1200 * bus (default) 1201 * 1 - double data rate ULPI interface with 4 bit wide data 1202 * bus 1203 */ 1204 extern void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val); 1205 1206 /* 1207 * Specifies whether to use the internal or external supply to 1208 * drive the vbus with a ULPI phy. 1209 */ 1210 extern void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val); 1211 #define DWC2_PHY_ULPI_INTERNAL_VBUS 0 1212 #define DWC2_PHY_ULPI_EXTERNAL_VBUS 1 1213 1214 /* 1215 * Specifies whether to use the I2Cinterface for full speed PHY. This 1216 * parameter is only applicable if PHY_TYPE is FS. 1217 * 0 - No (default) 1218 * 1 - Yes 1219 */ 1220 extern void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val); 1221 1222 extern void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val); 1223 1224 extern void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val); 1225 1226 /* 1227 * Specifies whether dedicated transmit FIFOs are 1228 * enabled for non periodic IN endpoints in device mode 1229 * 0 - No 1230 * 1 - Yes 1231 */ 1232 extern void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, 1233 int val); 1234 1235 extern void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val); 1236 1237 extern void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val); 1238 1239 extern void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val); 1240 1241 extern void dwc2_set_parameters(struct dwc2_hsotg *hsotg, 1242 const struct dwc2_core_params *params); 1243 1244 extern void dwc2_set_all_params(struct dwc2_core_params *params, int value); 1245 1246 extern int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); 1247 1248 extern int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg); 1249 extern int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg); 1250 1251 /* 1252 * The following functions check the controller's OTG operation mode 1253 * capability (GHWCFG2.OTG_MODE). 1254 * 1255 * These functions can be used before the internal hsotg->hw_params 1256 * are read in and cached so they always read directly from the 1257 * GHWCFG2 register. 1258 */ 1259 unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg); 1260 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg); 1261 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg); 1262 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg); 1263 1264 /* 1265 * Returns the mode of operation, host or device 1266 */ 1267 static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) 1268 { 1269 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0; 1270 } 1271 static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) 1272 { 1273 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0; 1274 } 1275 1276 /* 1277 * Dump core registers and SPRAM 1278 */ 1279 extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 1280 extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 1281 extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 1282 1283 /* 1284 * Return OTG version - either 1.3 or 2.0 1285 */ 1286 extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg); 1287 1288 /* Gadget defines */ 1289 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1290 extern int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg); 1291 extern int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2); 1292 extern int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2); 1293 extern int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq); 1294 extern void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1295 bool reset); 1296 extern void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg); 1297 extern void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2); 1298 extern int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode); 1299 #define dwc2_is_device_connected(hsotg) (hsotg->connected) 1300 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg); 1301 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg); 1302 #else 1303 static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2) 1304 { return 0; } 1305 static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2) 1306 { return 0; } 1307 static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2) 1308 { return 0; } 1309 static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) 1310 { return 0; } 1311 static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1312 bool reset) {} 1313 static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} 1314 static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} 1315 static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, 1316 int testmode) 1317 { return 0; } 1318 #define dwc2_is_device_connected(hsotg) (0) 1319 static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) 1320 { return 0; } 1321 static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg) 1322 { return 0; } 1323 #endif 1324 1325 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1326 extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 1327 extern int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us); 1328 extern void dwc2_hcd_connect(struct dwc2_hsotg *hsotg); 1329 extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force); 1330 extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 1331 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg); 1332 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg); 1333 #else 1334 static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1335 { return 0; } 1336 static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, 1337 int us) 1338 { return 0; } 1339 static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {} 1340 static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {} 1341 static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} 1342 static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} 1343 static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) 1344 { return 0; } 1345 static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 1346 { return 0; } 1347 static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 1348 { return 0; } 1349 1350 #endif 1351 1352 #endif /* __DWC2_CORE_H__ */ 1353