1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* 3 * core.h - DesignWare HS OTG Controller common declarations 4 * 5 * Copyright (C) 2004-2013 Synopsys, Inc. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The names of the above-listed copyright holders may not be used 17 * to endorse or promote products derived from this software without 18 * specific prior written permission. 19 * 20 * ALTERNATIVELY, this software may be distributed under the terms of the 21 * GNU General Public License ("GPL") as published by the Free Software 22 * Foundation; either version 2 of the License, or (at your option) any 23 * later version. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef __DWC2_CORE_H__ 39 #define __DWC2_CORE_H__ 40 41 #include <linux/phy/phy.h> 42 #include <linux/regulator/consumer.h> 43 #include <linux/usb/gadget.h> 44 #include <linux/usb/otg.h> 45 #include <linux/usb/phy.h> 46 #include "hw.h" 47 48 /* 49 * Suggested defines for tracers: 50 * - no_printk: Disable tracing 51 * - pr_info: Print this info to the console 52 * - trace_printk: Print this info to trace buffer (good for verbose logging) 53 */ 54 55 #define DWC2_TRACE_SCHEDULER no_printk 56 #define DWC2_TRACE_SCHEDULER_VB no_printk 57 58 /* Detailed scheduler tracing, but won't overwhelm console */ 59 #define dwc2_sch_dbg(hsotg, fmt, ...) \ 60 DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \ 61 dev_name(hsotg->dev), ##__VA_ARGS__) 62 63 /* Verbose scheduler tracing */ 64 #define dwc2_sch_vdbg(hsotg, fmt, ...) \ 65 DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \ 66 dev_name(hsotg->dev), ##__VA_ARGS__) 67 68 /* Maximum number of Endpoints/HostChannels */ 69 #define MAX_EPS_CHANNELS 16 70 71 /* dwc2-hsotg declarations */ 72 static const char * const dwc2_hsotg_supply_names[] = { 73 "vusb_d", /* digital USB supply, 1.2V */ 74 "vusb_a", /* analog USB supply, 1.1V */ 75 }; 76 77 #define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names) 78 79 /* 80 * EP0_MPS_LIMIT 81 * 82 * Unfortunately there seems to be a limit of the amount of data that can 83 * be transferred by IN transactions on EP0. This is either 127 bytes or 3 84 * packets (which practically means 1 packet and 63 bytes of data) when the 85 * MPS is set to 64. 86 * 87 * This means if we are wanting to move >127 bytes of data, we need to 88 * split the transactions up, but just doing one packet at a time does 89 * not work (this may be an implicit DATA0 PID on first packet of the 90 * transaction) and doing 2 packets is outside the controller's limits. 91 * 92 * If we try to lower the MPS size for EP0, then no transfers work properly 93 * for EP0, and the system will fail basic enumeration. As no cause for this 94 * has currently been found, we cannot support any large IN transfers for 95 * EP0. 96 */ 97 #define EP0_MPS_LIMIT 64 98 99 struct dwc2_hsotg; 100 struct dwc2_hsotg_req; 101 102 /** 103 * struct dwc2_hsotg_ep - driver endpoint definition. 104 * @ep: The gadget layer representation of the endpoint. 105 * @name: The driver generated name for the endpoint. 106 * @queue: Queue of requests for this endpoint. 107 * @parent: Reference back to the parent device structure. 108 * @req: The current request that the endpoint is processing. This is 109 * used to indicate an request has been loaded onto the endpoint 110 * and has yet to be completed (maybe due to data move, or simply 111 * awaiting an ack from the core all the data has been completed). 112 * @debugfs: File entry for debugfs file for this endpoint. 113 * @dir_in: Set to true if this endpoint is of the IN direction, which 114 * means that it is sending data to the Host. 115 * @index: The index for the endpoint registers. 116 * @mc: Multi Count - number of transactions per microframe 117 * @interval: Interval for periodic endpoints, in frames or microframes. 118 * @name: The name array passed to the USB core. 119 * @halted: Set if the endpoint has been halted. 120 * @periodic: Set if this is a periodic ep, such as Interrupt 121 * @isochronous: Set if this is a isochronous ep 122 * @send_zlp: Set if we need to send a zero-length packet. 123 * @desc_list_dma: The DMA address of descriptor chain currently in use. 124 * @desc_list: Pointer to descriptor DMA chain head currently in use. 125 * @desc_count: Count of entries within the DMA descriptor chain of EP. 126 * @next_desc: index of next free descriptor in the ISOC chain under SW control. 127 * @compl_desc: index of next descriptor to be completed by xFerComplete 128 * @total_data: The total number of data bytes done. 129 * @fifo_size: The size of the FIFO (for periodic IN endpoints) 130 * @fifo_index: For Dedicated FIFO operation, only FIFO0 can be used for EP0. 131 * @fifo_load: The amount of data loaded into the FIFO (periodic IN) 132 * @last_load: The offset of data for the last start of request. 133 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN 134 * @target_frame: Targeted frame num to setup next ISOC transfer 135 * @frame_overrun: Indicates SOF number overrun in DSTS 136 * 137 * This is the driver's state for each registered enpoint, allowing it 138 * to keep track of transactions that need doing. Each endpoint has a 139 * lock to protect the state, to try and avoid using an overall lock 140 * for the host controller as much as possible. 141 * 142 * For periodic IN endpoints, we have fifo_size and fifo_load to try 143 * and keep track of the amount of data in the periodic FIFO for each 144 * of these as we don't have a status register that tells us how much 145 * is in each of them. (note, this may actually be useless information 146 * as in shared-fifo mode periodic in acts like a single-frame packet 147 * buffer than a fifo) 148 */ 149 struct dwc2_hsotg_ep { 150 struct usb_ep ep; 151 struct list_head queue; 152 struct dwc2_hsotg *parent; 153 struct dwc2_hsotg_req *req; 154 struct dentry *debugfs; 155 156 unsigned long total_data; 157 unsigned int size_loaded; 158 unsigned int last_load; 159 unsigned int fifo_load; 160 unsigned short fifo_size; 161 unsigned short fifo_index; 162 163 unsigned char dir_in; 164 unsigned char index; 165 unsigned char mc; 166 u16 interval; 167 168 unsigned int halted:1; 169 unsigned int periodic:1; 170 unsigned int isochronous:1; 171 unsigned int send_zlp:1; 172 unsigned int target_frame; 173 #define TARGET_FRAME_INITIAL 0xFFFFFFFF 174 bool frame_overrun; 175 176 dma_addr_t desc_list_dma; 177 struct dwc2_dma_desc *desc_list; 178 u8 desc_count; 179 180 unsigned int next_desc; 181 unsigned int compl_desc; 182 183 char name[10]; 184 }; 185 186 /** 187 * struct dwc2_hsotg_req - data transfer request 188 * @req: The USB gadget request 189 * @queue: The list of requests for the endpoint this is queued for. 190 * @saved_req_buf: variable to save req.buf when bounce buffers are used. 191 */ 192 struct dwc2_hsotg_req { 193 struct usb_request req; 194 struct list_head queue; 195 void *saved_req_buf; 196 }; 197 198 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 199 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 200 #define call_gadget(_hs, _entry) \ 201 do { \ 202 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ 203 (_hs)->driver && (_hs)->driver->_entry) { \ 204 spin_unlock(&_hs->lock); \ 205 (_hs)->driver->_entry(&(_hs)->gadget); \ 206 spin_lock(&_hs->lock); \ 207 } \ 208 } while (0) 209 #else 210 #define call_gadget(_hs, _entry) do {} while (0) 211 #endif 212 213 struct dwc2_hsotg; 214 struct dwc2_host_chan; 215 216 /* Device States */ 217 enum dwc2_lx_state { 218 DWC2_L0, /* On state */ 219 DWC2_L1, /* LPM sleep state */ 220 DWC2_L2, /* USB suspend state */ 221 DWC2_L3, /* Off state */ 222 }; 223 224 /* Gadget ep0 states */ 225 enum dwc2_ep0_state { 226 DWC2_EP0_SETUP, 227 DWC2_EP0_DATA_IN, 228 DWC2_EP0_DATA_OUT, 229 DWC2_EP0_STATUS_IN, 230 DWC2_EP0_STATUS_OUT, 231 }; 232 233 /** 234 * struct dwc2_core_params - Parameters for configuring the core 235 * 236 * @otg_cap: Specifies the OTG capabilities. 237 * 0 - HNP and SRP capable 238 * 1 - SRP Only capable 239 * 2 - No HNP/SRP capable (always available) 240 * Defaults to best available option (0, 1, then 2) 241 * @host_dma: Specifies whether to use slave or DMA mode for accessing 242 * the data FIFOs. The driver will automatically detect the 243 * value for this parameter if none is specified. 244 * 0 - Slave (always available) 245 * 1 - DMA (default, if available) 246 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 247 * address DMA mode or descriptor DMA mode for accessing 248 * the data FIFOs. The driver will automatically detect the 249 * value for this if none is specified. 250 * 0 - Address DMA 251 * 1 - Descriptor DMA (default, if available) 252 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use 253 * address DMA mode or descriptor DMA mode for accessing 254 * the data FIFOs in Full Speed mode only. The driver 255 * will automatically detect the value for this if none is 256 * specified. 257 * 0 - Address DMA 258 * 1 - Descriptor DMA in FS (default, if available) 259 * @speed: Specifies the maximum speed of operation in host and 260 * device mode. The actual speed depends on the speed of 261 * the attached device and the value of phy_type. 262 * 0 - High Speed 263 * (default when phy_type is UTMI+ or ULPI) 264 * 1 - Full Speed 265 * (default when phy_type is Full Speed) 266 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 267 * 1 - Allow dynamic FIFO sizing (default, if available) 268 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 269 * are enabled for non-periodic IN endpoints in device 270 * mode. 271 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 272 * dynamic FIFO sizing is enabled 273 * 16 to 32768 274 * Actual maximum value is autodetected and also 275 * the default. 276 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 277 * in host mode when dynamic FIFO sizing is enabled 278 * 16 to 32768 279 * Actual maximum value is autodetected and also 280 * the default. 281 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 282 * host mode when dynamic FIFO sizing is enabled 283 * 16 to 32768 284 * Actual maximum value is autodetected and also 285 * the default. 286 * @max_transfer_size: The maximum transfer size supported, in bytes 287 * 2047 to 65,535 288 * Actual maximum value is autodetected and also 289 * the default. 290 * @max_packet_count: The maximum number of packets in a transfer 291 * 15 to 511 292 * Actual maximum value is autodetected and also 293 * the default. 294 * @host_channels: The number of host channel registers to use 295 * 1 to 16 296 * Actual maximum value is autodetected and also 297 * the default. 298 * @phy_type: Specifies the type of PHY interface to use. By default, 299 * the driver will automatically detect the phy_type. 300 * 0 - Full Speed Phy 301 * 1 - UTMI+ Phy 302 * 2 - ULPI Phy 303 * Defaults to best available option (2, 1, then 0) 304 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 305 * is applicable for a phy_type of UTMI+ or ULPI. (For a 306 * ULPI phy_type, this parameter indicates the data width 307 * between the MAC and the ULPI Wrapper.) Also, this 308 * parameter is applicable only if the OTG_HSPHY_WIDTH cC 309 * parameter was set to "8 and 16 bits", meaning that the 310 * core has been configured to work at either data path 311 * width. 312 * 8 or 16 (default 16 if available) 313 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 314 * data rate. This parameter is only applicable if phy_type 315 * is ULPI. 316 * 0 - single data rate ULPI interface with 8 bit wide 317 * data bus (default) 318 * 1 - double data rate ULPI interface with 4 bit wide 319 * data bus 320 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 321 * external supply to drive the VBus 322 * 0 - Internal supply (default) 323 * 1 - External supply 324 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 325 * speed PHY. This parameter is only applicable if phy_type 326 * is FS. 327 * 0 - No (default) 328 * 1 - Yes 329 * @ipg_isoc_en: Indicates the IPG supports is enabled or disabled. 330 * 0 - Disable (default) 331 * 1 - Enable 332 * @acg_enable: For enabling Active Clock Gating in the controller 333 * 0 - No 334 * 1 - Yes 335 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 336 * 0 - No (default) 337 * 1 - Yes 338 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 339 * when attached to a Full Speed or Low Speed device in 340 * host mode. 341 * 0 - Don't support low power mode (default) 342 * 1 - Support low power mode 343 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 344 * when connected to a Low Speed device in host 345 * mode. This parameter is applicable only if 346 * host_support_fs_ls_low_power is enabled. 347 * 0 - 48 MHz 348 * (default when phy_type is UTMI+ or ULPI) 349 * 1 - 6 MHz 350 * (default when phy_type is Full Speed) 351 * @oc_disable: Flag to disable overcurrent condition. 352 * 0 - Allow overcurrent condition to get detected 353 * 1 - Disable overcurrent condtion to get detected 354 * @ts_dline: Enable Term Select Dline pulsing 355 * 0 - No (default) 356 * 1 - Yes 357 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 358 * 0 - No (default for core < 2.92a) 359 * 1 - Yes (default for core >= 2.92a) 360 * @ahbcfg: This field allows the default value of the GAHBCFG 361 * register to be overridden 362 * -1 - GAHBCFG value will be set to 0x06 363 * (INCR, default) 364 * all others - GAHBCFG value will be overridden with 365 * this value 366 * Not all bits can be controlled like this, the 367 * bits defined by GAHBCFG_CTRL_MASK are controlled 368 * by the driver and are ignored in this 369 * configuration value. 370 * @uframe_sched: True to enable the microframe scheduler 371 * @external_id_pin_ctl: Specifies whether ID pin is handled externally. 372 * Disable CONIDSTSCHNG controller interrupt in such 373 * case. 374 * 0 - No (default) 375 * 1 - Yes 376 * @power_down: Specifies whether the controller support power_down. 377 * If power_down is enabled, the controller will enter 378 * power_down in both peripheral and host mode when 379 * needed. 380 * 0 - No (default) 381 * 1 - Partial power down 382 * 2 - Hibernation 383 * @lpm: Enable LPM support. 384 * 0 - No 385 * 1 - Yes 386 * @lpm_clock_gating: Enable core PHY clock gating. 387 * 0 - No 388 * 1 - Yes 389 * @besl: Enable LPM Errata support. 390 * 0 - No 391 * 1 - Yes 392 * @hird_threshold_en: HIRD or HIRD Threshold enable. 393 * 0 - No 394 * 1 - Yes 395 * @hird_threshold: Value of BESL or HIRD Threshold. 396 * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO 397 * register. 398 * 0 - Deactivate the transceiver (default) 399 * 1 - Activate the transceiver 400 * @g_dma: Enables gadget dma usage (default: autodetect). 401 * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect). 402 * @g_rx_fifo_size: The periodic rx fifo size for the device, in 403 * DWORDS from 16-32768 (default: 2048 if 404 * possible, otherwise autodetect). 405 * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in 406 * DWORDS from 16-32768 (default: 1024 if 407 * possible, otherwise autodetect). 408 * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo 409 * mode. Each value corresponds to one EP 410 * starting from EP1 (max 15 values). Sizes are 411 * in DWORDS with possible values from from 412 * 16-32768 (default: 256, 256, 256, 256, 768, 413 * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0). 414 * @change_speed_quirk: Change speed configuration to DWC2_SPEED_PARAM_FULL 415 * while full&low speed device connect. And change speed 416 * back to DWC2_SPEED_PARAM_HIGH while device is gone. 417 * 0 - No (default) 418 * 1 - Yes 419 * 420 * The following parameters may be specified when starting the module. These 421 * parameters define how the DWC_otg controller should be configured. A 422 * value of -1 (or any other out of range value) for any parameter means 423 * to read the value from hardware (if possible) or use the builtin 424 * default described above. 425 */ 426 struct dwc2_core_params { 427 u8 otg_cap; 428 #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 429 #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 430 #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 431 432 u8 phy_type; 433 #define DWC2_PHY_TYPE_PARAM_FS 0 434 #define DWC2_PHY_TYPE_PARAM_UTMI 1 435 #define DWC2_PHY_TYPE_PARAM_ULPI 2 436 437 u8 speed; 438 #define DWC2_SPEED_PARAM_HIGH 0 439 #define DWC2_SPEED_PARAM_FULL 1 440 #define DWC2_SPEED_PARAM_LOW 2 441 442 u8 phy_utmi_width; 443 bool phy_ulpi_ddr; 444 bool phy_ulpi_ext_vbus; 445 bool enable_dynamic_fifo; 446 bool en_multiple_tx_fifo; 447 bool i2c_enable; 448 bool acg_enable; 449 bool ulpi_fs_ls; 450 bool ts_dline; 451 bool reload_ctl; 452 bool uframe_sched; 453 bool external_id_pin_ctl; 454 455 int power_down; 456 #define DWC2_POWER_DOWN_PARAM_NONE 0 457 #define DWC2_POWER_DOWN_PARAM_PARTIAL 1 458 #define DWC2_POWER_DOWN_PARAM_HIBERNATION 2 459 460 bool lpm; 461 bool lpm_clock_gating; 462 bool besl; 463 bool hird_threshold_en; 464 u8 hird_threshold; 465 bool activate_stm_fs_transceiver; 466 bool ipg_isoc_en; 467 u16 max_packet_count; 468 u32 max_transfer_size; 469 u32 ahbcfg; 470 471 /* Host parameters */ 472 bool host_dma; 473 bool dma_desc_enable; 474 bool dma_desc_fs_enable; 475 bool host_support_fs_ls_low_power; 476 bool host_ls_low_power_phy_clk; 477 bool oc_disable; 478 479 u8 host_channels; 480 u16 host_rx_fifo_size; 481 u16 host_nperio_tx_fifo_size; 482 u16 host_perio_tx_fifo_size; 483 484 /* Gadget parameters */ 485 bool g_dma; 486 bool g_dma_desc; 487 u32 g_rx_fifo_size; 488 u32 g_np_tx_fifo_size; 489 u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; 490 491 bool change_speed_quirk; 492 }; 493 494 /** 495 * struct dwc2_hw_params - Autodetected parameters. 496 * 497 * These parameters are the various parameters read from hardware 498 * registers during initialization. They typically contain the best 499 * supported or maximum value that can be configured in the 500 * corresponding dwc2_core_params value. 501 * 502 * The values that are not in dwc2_core_params are documented below. 503 * 504 * @op_mode: Mode of Operation 505 * 0 - HNP- and SRP-Capable OTG (Host & Device) 506 * 1 - SRP-Capable OTG (Host & Device) 507 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 508 * 3 - SRP-Capable Device 509 * 4 - Non-OTG Device 510 * 5 - SRP-Capable Host 511 * 6 - Non-OTG Host 512 * @arch: Architecture 513 * 0 - Slave only 514 * 1 - External DMA 515 * 2 - Internal DMA 516 * @ipg_isoc_en: This feature indicates that the controller supports 517 * the worst-case scenario of Rx followed by Rx 518 * Interpacket Gap (IPG) (32 bitTimes) as per the utmi 519 * specification for any token following ISOC OUT token. 520 * 0 - Don't support 521 * 1 - Support 522 * @power_optimized: Are power optimizations enabled? 523 * @num_dev_ep: Number of device endpoints available 524 * @num_dev_in_eps: Number of device IN endpoints available 525 * @num_dev_perio_in_ep: Number of device periodic IN endpoints 526 * available 527 * @dev_token_q_depth: Device Mode IN Token Sequence Learning Queue 528 * Depth 529 * 0 to 30 530 * @host_perio_tx_q_depth: 531 * Host Mode Periodic Request Queue Depth 532 * 2, 4 or 8 533 * @nperio_tx_q_depth: 534 * Non-Periodic Request Queue Depth 535 * 2, 4 or 8 536 * @hs_phy_type: High-speed PHY interface type 537 * 0 - High-speed interface not supported 538 * 1 - UTMI+ 539 * 2 - ULPI 540 * 3 - UTMI+ and ULPI 541 * @fs_phy_type: Full-speed PHY interface type 542 * 0 - Full speed interface not supported 543 * 1 - Dedicated full speed interface 544 * 2 - FS pins shared with UTMI+ pins 545 * 3 - FS pins shared with ULPI pins 546 * @total_fifo_size: Total internal RAM for FIFOs (bytes) 547 * @hibernation: Is hibernation enabled? 548 * @utmi_phy_data_width: UTMI+ PHY data width 549 * 0 - 8 bits 550 * 1 - 16 bits 551 * 2 - 8 or 16 bits 552 * @snpsid: Value from SNPSID register 553 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1) 554 * @g_tx_fifo_size: Power-on values of TxFIFO sizes 555 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 556 * address DMA mode or descriptor DMA mode for accessing 557 * the data FIFOs. The driver will automatically detect the 558 * value for this if none is specified. 559 * 0 - Address DMA 560 * 1 - Descriptor DMA (default, if available) 561 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 562 * 1 - Allow dynamic FIFO sizing (default, if available) 563 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 564 * are enabled for non-periodic IN endpoints in device 565 * mode. 566 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 567 * in host mode when dynamic FIFO sizing is enabled 568 * 16 to 32768 569 * Actual maximum value is autodetected and also 570 * the default. 571 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 572 * host mode when dynamic FIFO sizing is enabled 573 * 16 to 32768 574 * Actual maximum value is autodetected and also 575 * the default. 576 * @max_transfer_size: The maximum transfer size supported, in bytes 577 * 2047 to 65,535 578 * Actual maximum value is autodetected and also 579 * the default. 580 * @max_packet_count: The maximum number of packets in a transfer 581 * 15 to 511 582 * Actual maximum value is autodetected and also 583 * the default. 584 * @host_channels: The number of host channel registers to use 585 * 1 to 16 586 * Actual maximum value is autodetected and also 587 * the default. 588 * @dev_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 589 * in device mode when dynamic FIFO sizing is enabled 590 * 16 to 32768 591 * Actual maximum value is autodetected and also 592 * the default. 593 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 594 * speed PHY. This parameter is only applicable if phy_type 595 * is FS. 596 * 0 - No (default) 597 * 1 - Yes 598 * @acg_enable: For enabling Active Clock Gating in the controller 599 * 0 - Disable 600 * 1 - Enable 601 * @lpm_mode: For enabling Link Power Management in the controller 602 * 0 - Disable 603 * 1 - Enable 604 * @rx_fifo_size: Number of 4-byte words in the Rx FIFO when dynamic 605 * FIFO sizing is enabled 16 to 32768 606 * Actual maximum value is autodetected and also 607 * the default. 608 */ 609 struct dwc2_hw_params { 610 unsigned op_mode:3; 611 unsigned arch:2; 612 unsigned dma_desc_enable:1; 613 unsigned enable_dynamic_fifo:1; 614 unsigned en_multiple_tx_fifo:1; 615 unsigned rx_fifo_size:16; 616 unsigned host_nperio_tx_fifo_size:16; 617 unsigned dev_nperio_tx_fifo_size:16; 618 unsigned host_perio_tx_fifo_size:16; 619 unsigned nperio_tx_q_depth:3; 620 unsigned host_perio_tx_q_depth:3; 621 unsigned dev_token_q_depth:5; 622 unsigned max_transfer_size:26; 623 unsigned max_packet_count:11; 624 unsigned host_channels:5; 625 unsigned hs_phy_type:2; 626 unsigned fs_phy_type:2; 627 unsigned i2c_enable:1; 628 unsigned acg_enable:1; 629 unsigned num_dev_ep:4; 630 unsigned num_dev_in_eps : 4; 631 unsigned num_dev_perio_in_ep:4; 632 unsigned total_fifo_size:16; 633 unsigned power_optimized:1; 634 unsigned hibernation:1; 635 unsigned utmi_phy_data_width:2; 636 unsigned lpm_mode:1; 637 unsigned ipg_isoc_en:1; 638 u32 snpsid; 639 u32 dev_ep_dirs; 640 u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; 641 }; 642 643 /* Size of control and EP0 buffers */ 644 #define DWC2_CTRL_BUFF_SIZE 8 645 646 /** 647 * struct dwc2_gregs_backup - Holds global registers state before 648 * entering partial power down 649 * @gotgctl: Backup of GOTGCTL register 650 * @gintmsk: Backup of GINTMSK register 651 * @gahbcfg: Backup of GAHBCFG register 652 * @gusbcfg: Backup of GUSBCFG register 653 * @grxfsiz: Backup of GRXFSIZ register 654 * @gnptxfsiz: Backup of GNPTXFSIZ register 655 * @gi2cctl: Backup of GI2CCTL register 656 * @glpmcfg: Backup of GLPMCFG register 657 * @gdfifocfg: Backup of GDFIFOCFG register 658 * @pcgcctl: Backup of PCGCCTL register 659 * @pcgcctl1: Backup of PCGCCTL1 register 660 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 661 * @gpwrdn: Backup of GPWRDN register 662 * @valid: True if registers values backuped. 663 */ 664 struct dwc2_gregs_backup { 665 u32 gotgctl; 666 u32 gintmsk; 667 u32 gahbcfg; 668 u32 gusbcfg; 669 u32 grxfsiz; 670 u32 gnptxfsiz; 671 u32 gi2cctl; 672 u32 glpmcfg; 673 u32 pcgcctl; 674 u32 pcgcctl1; 675 u32 gdfifocfg; 676 u32 gpwrdn; 677 bool valid; 678 }; 679 680 /** 681 * struct dwc2_dregs_backup - Holds device registers state before 682 * entering partial power down 683 * @dcfg: Backup of DCFG register 684 * @dctl: Backup of DCTL register 685 * @daintmsk: Backup of DAINTMSK register 686 * @diepmsk: Backup of DIEPMSK register 687 * @doepmsk: Backup of DOEPMSK register 688 * @diepctl: Backup of DIEPCTL register 689 * @dieptsiz: Backup of DIEPTSIZ register 690 * @diepdma: Backup of DIEPDMA register 691 * @doepctl: Backup of DOEPCTL register 692 * @doeptsiz: Backup of DOEPTSIZ register 693 * @doepdma: Backup of DOEPDMA register 694 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 695 * @valid: True if registers values backuped. 696 */ 697 struct dwc2_dregs_backup { 698 u32 dcfg; 699 u32 dctl; 700 u32 daintmsk; 701 u32 diepmsk; 702 u32 doepmsk; 703 u32 diepctl[MAX_EPS_CHANNELS]; 704 u32 dieptsiz[MAX_EPS_CHANNELS]; 705 u32 diepdma[MAX_EPS_CHANNELS]; 706 u32 doepctl[MAX_EPS_CHANNELS]; 707 u32 doeptsiz[MAX_EPS_CHANNELS]; 708 u32 doepdma[MAX_EPS_CHANNELS]; 709 u32 dtxfsiz[MAX_EPS_CHANNELS]; 710 bool valid; 711 }; 712 713 /** 714 * struct dwc2_hregs_backup - Holds host registers state before 715 * entering partial power down 716 * @hcfg: Backup of HCFG register 717 * @haintmsk: Backup of HAINTMSK register 718 * @hcintmsk: Backup of HCINTMSK register 719 * @hprt0: Backup of HPTR0 register 720 * @hfir: Backup of HFIR register 721 * @hptxfsiz: Backup of HPTXFSIZ register 722 * @valid: True if registers values backuped. 723 */ 724 struct dwc2_hregs_backup { 725 u32 hcfg; 726 u32 haintmsk; 727 u32 hcintmsk[MAX_EPS_CHANNELS]; 728 u32 hprt0; 729 u32 hfir; 730 u32 hptxfsiz; 731 bool valid; 732 }; 733 734 /* 735 * Constants related to high speed periodic scheduling 736 * 737 * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a 738 * reservation point of view it's assumed that the schedule goes right back to 739 * the beginning after the end of the schedule. 740 * 741 * What does that mean for scheduling things with a long interval? It means 742 * we'll reserve time for them in every possible microframe that they could 743 * ever be scheduled in. ...but we'll still only actually schedule them as 744 * often as they were requested. 745 * 746 * We keep our schedule in a "bitmap" structure. This simplifies having 747 * to keep track of and merge intervals: we just let the bitmap code do most 748 * of the heavy lifting. In a way scheduling is much like memory allocation. 749 * 750 * We schedule 100us per uframe or 80% of 125us (the maximum amount you're 751 * supposed to schedule for periodic transfers). That's according to spec. 752 * 753 * Note that though we only schedule 80% of each microframe, the bitmap that we 754 * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of 755 * space for each uFrame). 756 * 757 * Requirements: 758 * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1) 759 * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably 760 * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might 761 * be bugs). The 8 comes from the USB spec: number of microframes per frame. 762 */ 763 #define DWC2_US_PER_UFRAME 125 764 #define DWC2_HS_PERIODIC_US_PER_UFRAME 100 765 766 #define DWC2_HS_SCHEDULE_UFRAMES 8 767 #define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \ 768 DWC2_HS_PERIODIC_US_PER_UFRAME) 769 770 /* 771 * Constants related to low speed scheduling 772 * 773 * For high speed we schedule every 1us. For low speed that's a bit overkill, 774 * so we make up a unit called a "slice" that's worth 25us. There are 40 775 * slices in a full frame and we can schedule 36 of those (90%) for periodic 776 * transfers. 777 * 778 * Our low speed schedule can be as short as 1 frame or could be longer. When 779 * we only schedule 1 frame it means that we'll need to reserve a time every 780 * frame even for things that only transfer very rarely, so something that runs 781 * every 2048 frames will get time reserved in every frame. Our low speed 782 * schedule can be longer and we'll be able to handle more overlap, but that 783 * will come at increased memory cost and increased time to schedule. 784 * 785 * Note: one other advantage of a short low speed schedule is that if we mess 786 * up and miss scheduling we can jump in and use any of the slots that we 787 * happened to reserve. 788 * 789 * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for 790 * the schedule. There will be one schedule per TT. 791 * 792 * Requirements: 793 * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME. 794 */ 795 #define DWC2_US_PER_SLICE 25 796 #define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE) 797 798 #define DWC2_ROUND_US_TO_SLICE(us) \ 799 (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \ 800 DWC2_US_PER_SLICE) 801 802 #define DWC2_LS_PERIODIC_US_PER_FRAME \ 803 900 804 #define DWC2_LS_PERIODIC_SLICES_PER_FRAME \ 805 (DWC2_LS_PERIODIC_US_PER_FRAME / \ 806 DWC2_US_PER_SLICE) 807 808 #define DWC2_LS_SCHEDULE_FRAMES 1 809 #define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \ 810 DWC2_LS_PERIODIC_SLICES_PER_FRAME) 811 812 /** 813 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 814 * and periodic schedules 815 * 816 * These are common for both host and peripheral modes: 817 * 818 * @dev: The struct device pointer 819 * @regs: Pointer to controller regs 820 * @hw_params: Parameters that were autodetected from the 821 * hardware registers 822 * @params: Parameters that define how the core should be configured 823 * @op_state: The operational State, during transitions (a_host=> 824 * a_peripheral and b_device=>b_host) this may not match 825 * the core, but allows the software to determine 826 * transitions 827 * @dr_mode: Requested mode of operation, one of following: 828 * - USB_DR_MODE_PERIPHERAL 829 * - USB_DR_MODE_HOST 830 * - USB_DR_MODE_OTG 831 * @hcd_enabled: Host mode sub-driver initialization indicator. 832 * @gadget_enabled: Peripheral mode sub-driver initialization indicator. 833 * @ll_hw_enabled: Status of low-level hardware resources. 834 * @hibernated: True if core is hibernated 835 * @frame_number: Frame number read from the core. For both device 836 * and host modes. The value ranges are from 0 837 * to HFNUM_MAX_FRNUM. 838 * @phy: The otg phy transceiver structure for phy control. 839 * @uphy: The otg phy transceiver structure for old USB phy 840 * control. 841 * @plat: The platform specific configuration data. This can be 842 * removed once all SoCs support usb transceiver. 843 * @supplies: Definition of USB power supplies 844 * @vbus_supply: Regulator supplying vbus. 845 * @phyif: PHY interface width 846 * @lock: Spinlock that protects all the driver data structures 847 * @priv: Stores a pointer to the struct usb_hcd 848 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 849 * transfer are in process of being queued 850 * @srp_success: Stores status of SRP request in the case of a FS PHY 851 * with an I2C interface 852 * @wq_otg: Workqueue object used for handling of some interrupts 853 * @wf_otg: Work object for handling Connector ID Status Change 854 * interrupt 855 * @wkp_timer: Timer object for handling Wakeup Detected interrupt 856 * @lx_state: Lx state of connected device 857 * @gr_backup: Backup of global registers during suspend 858 * @dr_backup: Backup of device registers during suspend 859 * @hr_backup: Backup of host registers during suspend 860 * @needs_byte_swap: Specifies whether the opposite endianness. 861 * 862 * These are for host mode: 863 * 864 * @flags: Flags for handling root port state changes 865 * @flags.d32: Contain all root port flags 866 * @flags.b: Separate root port flags from each other 867 * @flags.b.port_connect_status_change: True if root port connect status 868 * changed 869 * @flags.b.port_connect_status: True if device connected to root port 870 * @flags.b.port_reset_change: True if root port reset status changed 871 * @flags.b.port_enable_change: True if root port enable status changed 872 * @flags.b.port_suspend_change: True if root port suspend status changed 873 * @flags.b.port_over_current_change: True if root port over current state 874 * changed. 875 * @flags.b.port_l1_change: True if root port l1 status changed 876 * @flags.b.reserved: Reserved bits of root port register 877 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 878 * Transfers associated with these QHs are not currently 879 * assigned to a host channel. 880 * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 881 * Transfers associated with these QHs are currently 882 * assigned to a host channel. 883 * @non_periodic_qh_ptr: Pointer to next QH to process in the active 884 * non-periodic schedule 885 * @non_periodic_sched_waiting: Waiting QHs in the non-periodic schedule. 886 * Transfers associated with these QHs are not currently 887 * assigned to a host channel. 888 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 889 * list of QHs for periodic transfers that are _not_ 890 * scheduled for the next frame. Each QH in the list has an 891 * interval counter that determines when it needs to be 892 * scheduled for execution. This scheduling mechanism 893 * allows only a simple calculation for periodic bandwidth 894 * used (i.e. must assume that all periodic transfers may 895 * need to execute in the same frame). However, it greatly 896 * simplifies scheduling and should be sufficient for the 897 * vast majority of OTG hosts, which need to connect to a 898 * small number of peripherals at one time. Items move from 899 * this list to periodic_sched_ready when the QH interval 900 * counter is 0 at SOF. 901 * @periodic_sched_ready: List of periodic QHs that are ready for execution in 902 * the next frame, but have not yet been assigned to host 903 * channels. Items move from this list to 904 * periodic_sched_assigned as host channels become 905 * available during the current frame. 906 * @periodic_sched_assigned: List of periodic QHs to be executed in the next 907 * frame that are assigned to host channels. Items move 908 * from this list to periodic_sched_queued as the 909 * transactions for the QH are queued to the DWC_otg 910 * controller. 911 * @periodic_sched_queued: List of periodic QHs that have been queued for 912 * execution. Items move from this list to either 913 * periodic_sched_inactive or periodic_sched_ready when the 914 * channel associated with the transfer is released. If the 915 * interval for the QH is 1, the item moves to 916 * periodic_sched_ready because it must be rescheduled for 917 * the next frame. Otherwise, the item moves to 918 * periodic_sched_inactive. 919 * @split_order: List keeping track of channels doing splits, in order. 920 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 921 * This value is in microseconds per (micro)frame. The 922 * assumption is that all periodic transfers may occur in 923 * the same (micro)frame. 924 * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the 925 * host is in high speed mode; low speed schedules are 926 * stored elsewhere since we need one per TT. 927 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 928 * SOF enable/disable. 929 * @free_hc_list: Free host channels in the controller. This is a list of 930 * struct dwc2_host_chan items. 931 * @periodic_channels: Number of host channels assigned to periodic transfers. 932 * Currently assuming that there is a dedicated host 933 * channel for each periodic transaction and at least one 934 * host channel is available for non-periodic transactions. 935 * @non_periodic_channels: Number of host channels assigned to non-periodic 936 * transfers 937 * @available_host_channels: Number of host channels available for the 938 * microframe scheduler to use 939 * @hc_ptr_array: Array of pointers to the host channel descriptors. 940 * Allows accessing a host channel descriptor given the 941 * host channel number. This is useful in interrupt 942 * handlers. 943 * @status_buf: Buffer used for data received during the status phase of 944 * a control transfer. 945 * @status_buf_dma: DMA address for status_buf 946 * @start_work: Delayed work for handling host A-cable connection 947 * @reset_work: Delayed work for handling a port reset 948 * @otg_port: OTG port number 949 * @frame_list: Frame list 950 * @frame_list_dma: Frame list DMA address 951 * @frame_list_sz: Frame list size 952 * @desc_gen_cache: Kmem cache for generic descriptors 953 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors 954 * @unaligned_cache: Kmem cache for DMA mode to handle non-aligned buf 955 * 956 * These are for peripheral mode: 957 * 958 * @driver: USB gadget driver 959 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 960 * @num_of_eps: Number of available EPs (excluding EP0) 961 * @debug_root: Root directrory for debugfs. 962 * @ep0_reply: Request used for ep0 reply. 963 * @ep0_buff: Buffer for EP0 reply data, if needed. 964 * @ctrl_buff: Buffer for EP0 control requests. 965 * @ctrl_req: Request for EP0 control packets. 966 * @ep0_state: EP0 control transfers state 967 * @test_mode: USB test mode requested by the host 968 * @remote_wakeup_allowed: True if device is allowed to wake-up host by 969 * remote-wakeup signalling 970 * @setup_desc_dma: EP0 setup stage desc chain DMA address 971 * @setup_desc: EP0 setup stage desc chain pointer 972 * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address 973 * @ctrl_in_desc: EP0 IN data phase desc chain pointer 974 * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address 975 * @ctrl_out_desc: EP0 OUT data phase desc chain pointer 976 * @irq: Interrupt request line number 977 * @clk: Pointer to otg clock 978 * @reset: Pointer to dwc2 reset controller 979 * @reset_ecc: Pointer to dwc2 optional reset controller in Stratix10. 980 * @regset: A pointer to a struct debugfs_regset32, which contains 981 * a pointer to an array of register definitions, the 982 * array size and the base address where the register bank 983 * is to be found. 984 * @bus_suspended: True if bus is suspended 985 * @last_frame_num: Number of last frame. Range from 0 to 32768 986 * @frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is 987 * defined, for missed SOFs tracking. Array holds that 988 * frame numbers, which not equal to last_frame_num +1 989 * @last_frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is 990 * defined, for missed SOFs tracking. 991 * If current_frame_number != last_frame_num+1 992 * then last_frame_num added to this array 993 * @frame_num_idx: Actual size of frame_num_array and last_frame_num_array 994 * @dumped_frame_num_array: 1 - if missed SOFs frame numbers dumbed 995 * 0 - if missed SOFs frame numbers not dumbed 996 * @fifo_mem: Total internal RAM for FIFOs (bytes) 997 * @fifo_map: Each bit intend for concrete fifo. If that bit is set, 998 * then that fifo is used 999 * @gadget: Represents a usb slave device 1000 * @connected: Used in slave mode. True if device connected with host 1001 * @eps_in: The IN endpoints being supplied to the gadget framework 1002 * @eps_out: The OUT endpoints being supplied to the gadget framework 1003 * @new_connection: Used in host mode. True if there are new connected 1004 * device 1005 * @enabled: Indicates the enabling state of controller 1006 * 1007 */ 1008 struct dwc2_hsotg { 1009 struct device *dev; 1010 void __iomem *regs; 1011 /** Params detected from hardware */ 1012 struct dwc2_hw_params hw_params; 1013 /** Params to actually use */ 1014 struct dwc2_core_params params; 1015 enum usb_otg_state op_state; 1016 enum usb_dr_mode dr_mode; 1017 unsigned int hcd_enabled:1; 1018 unsigned int gadget_enabled:1; 1019 unsigned int ll_hw_enabled:1; 1020 unsigned int hibernated:1; 1021 u16 frame_number; 1022 1023 struct phy *phy; 1024 struct usb_phy *uphy; 1025 struct dwc2_hsotg_plat *plat; 1026 struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES]; 1027 struct regulator *vbus_supply; 1028 u32 phyif; 1029 1030 spinlock_t lock; 1031 void *priv; 1032 int irq; 1033 struct clk *clk; 1034 struct reset_control *reset; 1035 struct reset_control *reset_ecc; 1036 1037 unsigned int queuing_high_bandwidth:1; 1038 unsigned int srp_success:1; 1039 1040 struct workqueue_struct *wq_otg; 1041 struct work_struct wf_otg; 1042 struct timer_list wkp_timer; 1043 enum dwc2_lx_state lx_state; 1044 struct dwc2_gregs_backup gr_backup; 1045 struct dwc2_dregs_backup dr_backup; 1046 struct dwc2_hregs_backup hr_backup; 1047 1048 struct dentry *debug_root; 1049 struct debugfs_regset32 *regset; 1050 bool needs_byte_swap; 1051 1052 /* DWC OTG HW Release versions */ 1053 #define DWC2_CORE_REV_2_71a 0x4f54271a 1054 #define DWC2_CORE_REV_2_72a 0x4f54272a 1055 #define DWC2_CORE_REV_2_80a 0x4f54280a 1056 #define DWC2_CORE_REV_2_90a 0x4f54290a 1057 #define DWC2_CORE_REV_2_91a 0x4f54291a 1058 #define DWC2_CORE_REV_2_92a 0x4f54292a 1059 #define DWC2_CORE_REV_2_94a 0x4f54294a 1060 #define DWC2_CORE_REV_3_00a 0x4f54300a 1061 #define DWC2_CORE_REV_3_10a 0x4f54310a 1062 #define DWC2_CORE_REV_4_00a 0x4f54400a 1063 #define DWC2_FS_IOT_REV_1_00a 0x5531100a 1064 #define DWC2_HS_IOT_REV_1_00a 0x5532100a 1065 1066 /* DWC OTG HW Core ID */ 1067 #define DWC2_OTG_ID 0x4f540000 1068 #define DWC2_FS_IOT_ID 0x55310000 1069 #define DWC2_HS_IOT_ID 0x55320000 1070 1071 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1072 union dwc2_hcd_internal_flags { 1073 u32 d32; 1074 struct { 1075 unsigned port_connect_status_change:1; 1076 unsigned port_connect_status:1; 1077 unsigned port_reset_change:1; 1078 unsigned port_enable_change:1; 1079 unsigned port_suspend_change:1; 1080 unsigned port_over_current_change:1; 1081 unsigned port_l1_change:1; 1082 unsigned reserved:25; 1083 } b; 1084 } flags; 1085 1086 struct list_head non_periodic_sched_inactive; 1087 struct list_head non_periodic_sched_waiting; 1088 struct list_head non_periodic_sched_active; 1089 struct list_head *non_periodic_qh_ptr; 1090 struct list_head periodic_sched_inactive; 1091 struct list_head periodic_sched_ready; 1092 struct list_head periodic_sched_assigned; 1093 struct list_head periodic_sched_queued; 1094 struct list_head split_order; 1095 u16 periodic_usecs; 1096 unsigned long hs_periodic_bitmap[ 1097 DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)]; 1098 u16 periodic_qh_count; 1099 bool bus_suspended; 1100 bool new_connection; 1101 1102 u16 last_frame_num; 1103 1104 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 1105 #define FRAME_NUM_ARRAY_SIZE 1000 1106 u16 *frame_num_array; 1107 u16 *last_frame_num_array; 1108 int frame_num_idx; 1109 int dumped_frame_num_array; 1110 #endif 1111 1112 struct list_head free_hc_list; 1113 int periodic_channels; 1114 int non_periodic_channels; 1115 int available_host_channels; 1116 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 1117 u8 *status_buf; 1118 dma_addr_t status_buf_dma; 1119 #define DWC2_HCD_STATUS_BUF_SIZE 64 1120 1121 struct delayed_work start_work; 1122 struct delayed_work reset_work; 1123 u8 otg_port; 1124 u32 *frame_list; 1125 dma_addr_t frame_list_dma; 1126 u32 frame_list_sz; 1127 struct kmem_cache *desc_gen_cache; 1128 struct kmem_cache *desc_hsisoc_cache; 1129 struct kmem_cache *unaligned_cache; 1130 #define DWC2_KMEM_UNALIGNED_BUF_SIZE 1024 1131 1132 #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ 1133 1134 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1135 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1136 /* Gadget structures */ 1137 struct usb_gadget_driver *driver; 1138 int fifo_mem; 1139 unsigned int dedicated_fifos:1; 1140 unsigned char num_of_eps; 1141 u32 fifo_map; 1142 1143 struct usb_request *ep0_reply; 1144 struct usb_request *ctrl_req; 1145 void *ep0_buff; 1146 void *ctrl_buff; 1147 enum dwc2_ep0_state ep0_state; 1148 u8 test_mode; 1149 1150 dma_addr_t setup_desc_dma[2]; 1151 struct dwc2_dma_desc *setup_desc[2]; 1152 dma_addr_t ctrl_in_desc_dma; 1153 struct dwc2_dma_desc *ctrl_in_desc; 1154 dma_addr_t ctrl_out_desc_dma; 1155 struct dwc2_dma_desc *ctrl_out_desc; 1156 1157 struct usb_gadget gadget; 1158 unsigned int enabled:1; 1159 unsigned int connected:1; 1160 unsigned int remote_wakeup_allowed:1; 1161 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS]; 1162 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS]; 1163 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 1164 }; 1165 1166 /* Normal architectures just use readl/write */ 1167 static inline u32 dwc2_readl(struct dwc2_hsotg *hsotg, u32 offset) 1168 { 1169 u32 val; 1170 1171 val = readl(hsotg->regs + offset); 1172 if (hsotg->needs_byte_swap) 1173 return swab32(val); 1174 else 1175 return val; 1176 } 1177 1178 static inline void dwc2_writel(struct dwc2_hsotg *hsotg, u32 value, u32 offset) 1179 { 1180 if (hsotg->needs_byte_swap) 1181 writel(swab32(value), hsotg->regs + offset); 1182 else 1183 writel(value, hsotg->regs + offset); 1184 1185 #ifdef DWC2_LOG_WRITES 1186 pr_info("info:: wrote %08x to %p\n", value, hsotg->regs + offset); 1187 #endif 1188 } 1189 1190 static inline void dwc2_readl_rep(struct dwc2_hsotg *hsotg, u32 offset, 1191 void *buffer, unsigned int count) 1192 { 1193 if (count) { 1194 u32 *buf = buffer; 1195 1196 do { 1197 u32 x = dwc2_readl(hsotg, offset); 1198 *buf++ = x; 1199 } while (--count); 1200 } 1201 } 1202 1203 static inline void dwc2_writel_rep(struct dwc2_hsotg *hsotg, u32 offset, 1204 const void *buffer, unsigned int count) 1205 { 1206 if (count) { 1207 const u32 *buf = buffer; 1208 1209 do { 1210 dwc2_writel(hsotg, *buf++, offset); 1211 } while (--count); 1212 } 1213 } 1214 1215 /* Reasons for halting a host channel */ 1216 enum dwc2_halt_status { 1217 DWC2_HC_XFER_NO_HALT_STATUS, 1218 DWC2_HC_XFER_COMPLETE, 1219 DWC2_HC_XFER_URB_COMPLETE, 1220 DWC2_HC_XFER_ACK, 1221 DWC2_HC_XFER_NAK, 1222 DWC2_HC_XFER_NYET, 1223 DWC2_HC_XFER_STALL, 1224 DWC2_HC_XFER_XACT_ERR, 1225 DWC2_HC_XFER_FRAME_OVERRUN, 1226 DWC2_HC_XFER_BABBLE_ERR, 1227 DWC2_HC_XFER_DATA_TOGGLE_ERR, 1228 DWC2_HC_XFER_AHB_ERR, 1229 DWC2_HC_XFER_PERIODIC_INCOMPLETE, 1230 DWC2_HC_XFER_URB_DEQUEUE, 1231 }; 1232 1233 /* Core version information */ 1234 static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg) 1235 { 1236 return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000; 1237 } 1238 1239 static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg) 1240 { 1241 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000; 1242 } 1243 1244 static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg) 1245 { 1246 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000; 1247 } 1248 1249 /* 1250 * The following functions support initialization of the core driver component 1251 * and the DWC_otg controller 1252 */ 1253 int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait); 1254 int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg); 1255 int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, bool restore); 1256 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host); 1257 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup, 1258 int reset, int is_host); 1259 1260 void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host); 1261 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg); 1262 1263 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 1264 1265 /* 1266 * Common core Functions. 1267 * The following functions support managing the DWC_otg controller in either 1268 * device or host mode. 1269 */ 1270 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 1271 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 1272 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 1273 1274 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 1275 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 1276 1277 void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup, 1278 int is_host); 1279 int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg); 1280 int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg); 1281 1282 void dwc2_enable_acg(struct dwc2_hsotg *hsotg); 1283 1284 /* This function should be called on every hardware interrupt. */ 1285 irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 1286 1287 /* The device ID match table */ 1288 extern const struct of_device_id dwc2_of_match_table[]; 1289 1290 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg); 1291 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg); 1292 1293 /* Common polling functions */ 1294 int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit, 1295 u32 timeout); 1296 int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit, 1297 u32 timeout); 1298 /* Parameters */ 1299 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); 1300 int dwc2_init_params(struct dwc2_hsotg *hsotg); 1301 1302 /* 1303 * The following functions check the controller's OTG operation mode 1304 * capability (GHWCFG2.OTG_MODE). 1305 * 1306 * These functions can be used before the internal hsotg->hw_params 1307 * are read in and cached so they always read directly from the 1308 * GHWCFG2 register. 1309 */ 1310 unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg); 1311 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg); 1312 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg); 1313 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg); 1314 1315 /* 1316 * Returns the mode of operation, host or device 1317 */ 1318 static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) 1319 { 1320 return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) != 0; 1321 } 1322 1323 static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) 1324 { 1325 return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) == 0; 1326 } 1327 1328 /* 1329 * Dump core registers and SPRAM 1330 */ 1331 void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 1332 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 1333 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 1334 1335 /* Gadget defines */ 1336 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1337 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1338 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg); 1339 int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2); 1340 int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2); 1341 int dwc2_gadget_init(struct dwc2_hsotg *hsotg); 1342 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1343 bool reset); 1344 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg); 1345 void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2); 1346 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode); 1347 #define dwc2_is_device_connected(hsotg) (hsotg->connected) 1348 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg); 1349 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup); 1350 int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg); 1351 int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, 1352 int rem_wakeup, int reset); 1353 int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg); 1354 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg); 1355 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg); 1356 void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg); 1357 #else 1358 static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2) 1359 { return 0; } 1360 static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2) 1361 { return 0; } 1362 static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2) 1363 { return 0; } 1364 static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg) 1365 { return 0; } 1366 static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1367 bool reset) {} 1368 static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} 1369 static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} 1370 static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, 1371 int testmode) 1372 { return 0; } 1373 #define dwc2_is_device_connected(hsotg) (0) 1374 static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) 1375 { return 0; } 1376 static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, 1377 int remote_wakeup) 1378 { return 0; } 1379 static inline int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg) 1380 { return 0; } 1381 static inline int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, 1382 int rem_wakeup, int reset) 1383 { return 0; } 1384 static inline int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg) 1385 { return 0; } 1386 static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) 1387 { return 0; } 1388 static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg) 1389 { return 0; } 1390 static inline void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) {} 1391 #endif 1392 1393 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1394 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 1395 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us); 1396 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg); 1397 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force); 1398 void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 1399 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup); 1400 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg); 1401 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg); 1402 int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg); 1403 int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, 1404 int rem_wakeup, int reset); 1405 #else 1406 static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1407 { return 0; } 1408 static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, 1409 int us) 1410 { return 0; } 1411 static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {} 1412 static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {} 1413 static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} 1414 static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} 1415 static inline int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) 1416 { return 0; } 1417 static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg) 1418 { return 0; } 1419 static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 1420 { return 0; } 1421 static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 1422 { return 0; } 1423 static inline int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg) 1424 { return 0; } 1425 static inline int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, 1426 int rem_wakeup, int reset) 1427 { return 0; } 1428 1429 #endif 1430 1431 #endif /* __DWC2_CORE_H__ */ 1432