1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* 3 * core.h - DesignWare HS OTG Controller common declarations 4 * 5 * Copyright (C) 2004-2013 Synopsys, Inc. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The names of the above-listed copyright holders may not be used 17 * to endorse or promote products derived from this software without 18 * specific prior written permission. 19 * 20 * ALTERNATIVELY, this software may be distributed under the terms of the 21 * GNU General Public License ("GPL") as published by the Free Software 22 * Foundation; either version 2 of the License, or (at your option) any 23 * later version. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef __DWC2_CORE_H__ 39 #define __DWC2_CORE_H__ 40 41 #include <linux/phy/phy.h> 42 #include <linux/regulator/consumer.h> 43 #include <linux/usb/gadget.h> 44 #include <linux/usb/otg.h> 45 #include <linux/usb/phy.h> 46 #include "hw.h" 47 48 /* 49 * Suggested defines for tracers: 50 * - no_printk: Disable tracing 51 * - pr_info: Print this info to the console 52 * - trace_printk: Print this info to trace buffer (good for verbose logging) 53 */ 54 55 #define DWC2_TRACE_SCHEDULER no_printk 56 #define DWC2_TRACE_SCHEDULER_VB no_printk 57 58 /* Detailed scheduler tracing, but won't overwhelm console */ 59 #define dwc2_sch_dbg(hsotg, fmt, ...) \ 60 DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \ 61 dev_name(hsotg->dev), ##__VA_ARGS__) 62 63 /* Verbose scheduler tracing */ 64 #define dwc2_sch_vdbg(hsotg, fmt, ...) \ 65 DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \ 66 dev_name(hsotg->dev), ##__VA_ARGS__) 67 68 #ifdef CONFIG_MIPS 69 /* 70 * There are some MIPS machines that can run in either big-endian 71 * or little-endian mode and that use the dwc2 register without 72 * a byteswap in both ways. 73 * Unlike other architectures, MIPS apparently does not require a 74 * barrier before the __raw_writel() to synchronize with DMA but does 75 * require the barrier after the __raw_writel() to serialize a set of 76 * writes. This set of operations was added specifically for MIPS and 77 * should only be used there. 78 */ 79 static inline u32 dwc2_readl(const void __iomem *addr) 80 { 81 u32 value = __raw_readl(addr); 82 83 /* In order to preserve endianness __raw_* operation is used. Therefore 84 * a barrier is needed to ensure IO access is not re-ordered across 85 * reads or writes 86 */ 87 mb(); 88 return value; 89 } 90 91 static inline void dwc2_writel(u32 value, void __iomem *addr) 92 { 93 __raw_writel(value, addr); 94 95 /* 96 * In order to preserve endianness __raw_* operation is used. Therefore 97 * a barrier is needed to ensure IO access is not re-ordered across 98 * reads or writes 99 */ 100 mb(); 101 #ifdef DWC2_LOG_WRITES 102 pr_info("INFO:: wrote %08x to %p\n", value, addr); 103 #endif 104 } 105 #else 106 /* Normal architectures just use readl/write */ 107 static inline u32 dwc2_readl(const void __iomem *addr) 108 { 109 return readl(addr); 110 } 111 112 static inline void dwc2_writel(u32 value, void __iomem *addr) 113 { 114 writel(value, addr); 115 116 #ifdef DWC2_LOG_WRITES 117 pr_info("info:: wrote %08x to %p\n", value, addr); 118 #endif 119 } 120 #endif 121 122 /* Maximum number of Endpoints/HostChannels */ 123 #define MAX_EPS_CHANNELS 16 124 125 /* dwc2-hsotg declarations */ 126 static const char * const dwc2_hsotg_supply_names[] = { 127 "vusb_d", /* digital USB supply, 1.2V */ 128 "vusb_a", /* analog USB supply, 1.1V */ 129 }; 130 131 #define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names) 132 133 /* 134 * EP0_MPS_LIMIT 135 * 136 * Unfortunately there seems to be a limit of the amount of data that can 137 * be transferred by IN transactions on EP0. This is either 127 bytes or 3 138 * packets (which practically means 1 packet and 63 bytes of data) when the 139 * MPS is set to 64. 140 * 141 * This means if we are wanting to move >127 bytes of data, we need to 142 * split the transactions up, but just doing one packet at a time does 143 * not work (this may be an implicit DATA0 PID on first packet of the 144 * transaction) and doing 2 packets is outside the controller's limits. 145 * 146 * If we try to lower the MPS size for EP0, then no transfers work properly 147 * for EP0, and the system will fail basic enumeration. As no cause for this 148 * has currently been found, we cannot support any large IN transfers for 149 * EP0. 150 */ 151 #define EP0_MPS_LIMIT 64 152 153 struct dwc2_hsotg; 154 struct dwc2_hsotg_req; 155 156 /** 157 * struct dwc2_hsotg_ep - driver endpoint definition. 158 * @ep: The gadget layer representation of the endpoint. 159 * @name: The driver generated name for the endpoint. 160 * @queue: Queue of requests for this endpoint. 161 * @parent: Reference back to the parent device structure. 162 * @req: The current request that the endpoint is processing. This is 163 * used to indicate an request has been loaded onto the endpoint 164 * and has yet to be completed (maybe due to data move, or simply 165 * awaiting an ack from the core all the data has been completed). 166 * @debugfs: File entry for debugfs file for this endpoint. 167 * @dir_in: Set to true if this endpoint is of the IN direction, which 168 * means that it is sending data to the Host. 169 * @index: The index for the endpoint registers. 170 * @mc: Multi Count - number of transactions per microframe 171 * @interval: Interval for periodic endpoints, in frames or microframes. 172 * @name: The name array passed to the USB core. 173 * @halted: Set if the endpoint has been halted. 174 * @periodic: Set if this is a periodic ep, such as Interrupt 175 * @isochronous: Set if this is a isochronous ep 176 * @send_zlp: Set if we need to send a zero-length packet. 177 * @desc_list_dma: The DMA address of descriptor chain currently in use. 178 * @desc_list: Pointer to descriptor DMA chain head currently in use. 179 * @desc_count: Count of entries within the DMA descriptor chain of EP. 180 * @next_desc: index of next free descriptor in the ISOC chain under SW control. 181 * @compl_desc: index of next descriptor to be completed by xFerComplete 182 * @total_data: The total number of data bytes done. 183 * @fifo_size: The size of the FIFO (for periodic IN endpoints) 184 * @fifo_index: For Dedicated FIFO operation, only FIFO0 can be used for EP0. 185 * @fifo_load: The amount of data loaded into the FIFO (periodic IN) 186 * @last_load: The offset of data for the last start of request. 187 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN 188 * @target_frame: Targeted frame num to setup next ISOC transfer 189 * @frame_overrun: Indicates SOF number overrun in DSTS 190 * 191 * This is the driver's state for each registered enpoint, allowing it 192 * to keep track of transactions that need doing. Each endpoint has a 193 * lock to protect the state, to try and avoid using an overall lock 194 * for the host controller as much as possible. 195 * 196 * For periodic IN endpoints, we have fifo_size and fifo_load to try 197 * and keep track of the amount of data in the periodic FIFO for each 198 * of these as we don't have a status register that tells us how much 199 * is in each of them. (note, this may actually be useless information 200 * as in shared-fifo mode periodic in acts like a single-frame packet 201 * buffer than a fifo) 202 */ 203 struct dwc2_hsotg_ep { 204 struct usb_ep ep; 205 struct list_head queue; 206 struct dwc2_hsotg *parent; 207 struct dwc2_hsotg_req *req; 208 struct dentry *debugfs; 209 210 unsigned long total_data; 211 unsigned int size_loaded; 212 unsigned int last_load; 213 unsigned int fifo_load; 214 unsigned short fifo_size; 215 unsigned short fifo_index; 216 217 unsigned char dir_in; 218 unsigned char index; 219 unsigned char mc; 220 u16 interval; 221 222 unsigned int halted:1; 223 unsigned int periodic:1; 224 unsigned int isochronous:1; 225 unsigned int send_zlp:1; 226 unsigned int target_frame; 227 #define TARGET_FRAME_INITIAL 0xFFFFFFFF 228 bool frame_overrun; 229 230 dma_addr_t desc_list_dma; 231 struct dwc2_dma_desc *desc_list; 232 u8 desc_count; 233 234 unsigned int next_desc; 235 unsigned int compl_desc; 236 237 char name[10]; 238 }; 239 240 /** 241 * struct dwc2_hsotg_req - data transfer request 242 * @req: The USB gadget request 243 * @queue: The list of requests for the endpoint this is queued for. 244 * @saved_req_buf: variable to save req.buf when bounce buffers are used. 245 */ 246 struct dwc2_hsotg_req { 247 struct usb_request req; 248 struct list_head queue; 249 void *saved_req_buf; 250 }; 251 252 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 253 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 254 #define call_gadget(_hs, _entry) \ 255 do { \ 256 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ 257 (_hs)->driver && (_hs)->driver->_entry) { \ 258 spin_unlock(&_hs->lock); \ 259 (_hs)->driver->_entry(&(_hs)->gadget); \ 260 spin_lock(&_hs->lock); \ 261 } \ 262 } while (0) 263 #else 264 #define call_gadget(_hs, _entry) do {} while (0) 265 #endif 266 267 struct dwc2_hsotg; 268 struct dwc2_host_chan; 269 270 /* Device States */ 271 enum dwc2_lx_state { 272 DWC2_L0, /* On state */ 273 DWC2_L1, /* LPM sleep state */ 274 DWC2_L2, /* USB suspend state */ 275 DWC2_L3, /* Off state */ 276 }; 277 278 /* Gadget ep0 states */ 279 enum dwc2_ep0_state { 280 DWC2_EP0_SETUP, 281 DWC2_EP0_DATA_IN, 282 DWC2_EP0_DATA_OUT, 283 DWC2_EP0_STATUS_IN, 284 DWC2_EP0_STATUS_OUT, 285 }; 286 287 /** 288 * struct dwc2_core_params - Parameters for configuring the core 289 * 290 * @otg_cap: Specifies the OTG capabilities. 291 * 0 - HNP and SRP capable 292 * 1 - SRP Only capable 293 * 2 - No HNP/SRP capable (always available) 294 * Defaults to best available option (0, 1, then 2) 295 * @host_dma: Specifies whether to use slave or DMA mode for accessing 296 * the data FIFOs. The driver will automatically detect the 297 * value for this parameter if none is specified. 298 * 0 - Slave (always available) 299 * 1 - DMA (default, if available) 300 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 301 * address DMA mode or descriptor DMA mode for accessing 302 * the data FIFOs. The driver will automatically detect the 303 * value for this if none is specified. 304 * 0 - Address DMA 305 * 1 - Descriptor DMA (default, if available) 306 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use 307 * address DMA mode or descriptor DMA mode for accessing 308 * the data FIFOs in Full Speed mode only. The driver 309 * will automatically detect the value for this if none is 310 * specified. 311 * 0 - Address DMA 312 * 1 - Descriptor DMA in FS (default, if available) 313 * @speed: Specifies the maximum speed of operation in host and 314 * device mode. The actual speed depends on the speed of 315 * the attached device and the value of phy_type. 316 * 0 - High Speed 317 * (default when phy_type is UTMI+ or ULPI) 318 * 1 - Full Speed 319 * (default when phy_type is Full Speed) 320 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 321 * 1 - Allow dynamic FIFO sizing (default, if available) 322 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 323 * are enabled for non-periodic IN endpoints in device 324 * mode. 325 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 326 * dynamic FIFO sizing is enabled 327 * 16 to 32768 328 * Actual maximum value is autodetected and also 329 * the default. 330 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 331 * in host mode when dynamic FIFO sizing is enabled 332 * 16 to 32768 333 * Actual maximum value is autodetected and also 334 * the default. 335 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 336 * host mode when dynamic FIFO sizing is enabled 337 * 16 to 32768 338 * Actual maximum value is autodetected and also 339 * the default. 340 * @max_transfer_size: The maximum transfer size supported, in bytes 341 * 2047 to 65,535 342 * Actual maximum value is autodetected and also 343 * the default. 344 * @max_packet_count: The maximum number of packets in a transfer 345 * 15 to 511 346 * Actual maximum value is autodetected and also 347 * the default. 348 * @host_channels: The number of host channel registers to use 349 * 1 to 16 350 * Actual maximum value is autodetected and also 351 * the default. 352 * @phy_type: Specifies the type of PHY interface to use. By default, 353 * the driver will automatically detect the phy_type. 354 * 0 - Full Speed Phy 355 * 1 - UTMI+ Phy 356 * 2 - ULPI Phy 357 * Defaults to best available option (2, 1, then 0) 358 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 359 * is applicable for a phy_type of UTMI+ or ULPI. (For a 360 * ULPI phy_type, this parameter indicates the data width 361 * between the MAC and the ULPI Wrapper.) Also, this 362 * parameter is applicable only if the OTG_HSPHY_WIDTH cC 363 * parameter was set to "8 and 16 bits", meaning that the 364 * core has been configured to work at either data path 365 * width. 366 * 8 or 16 (default 16 if available) 367 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 368 * data rate. This parameter is only applicable if phy_type 369 * is ULPI. 370 * 0 - single data rate ULPI interface with 8 bit wide 371 * data bus (default) 372 * 1 - double data rate ULPI interface with 4 bit wide 373 * data bus 374 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 375 * external supply to drive the VBus 376 * 0 - Internal supply (default) 377 * 1 - External supply 378 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 379 * speed PHY. This parameter is only applicable if phy_type 380 * is FS. 381 * 0 - No (default) 382 * 1 - Yes 383 * @ipg_isoc_en: Indicates the IPG supports is enabled or disabled. 384 * 0 - Disable (default) 385 * 1 - Enable 386 * @acg_enable: For enabling Active Clock Gating in the controller 387 * 0 - No 388 * 1 - Yes 389 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 390 * 0 - No (default) 391 * 1 - Yes 392 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 393 * when attached to a Full Speed or Low Speed device in 394 * host mode. 395 * 0 - Don't support low power mode (default) 396 * 1 - Support low power mode 397 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 398 * when connected to a Low Speed device in host 399 * mode. This parameter is applicable only if 400 * host_support_fs_ls_low_power is enabled. 401 * 0 - 48 MHz 402 * (default when phy_type is UTMI+ or ULPI) 403 * 1 - 6 MHz 404 * (default when phy_type is Full Speed) 405 * @oc_disable: Flag to disable overcurrent condition. 406 * 0 - Allow overcurrent condition to get detected 407 * 1 - Disable overcurrent condtion to get detected 408 * @ts_dline: Enable Term Select Dline pulsing 409 * 0 - No (default) 410 * 1 - Yes 411 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 412 * 0 - No (default for core < 2.92a) 413 * 1 - Yes (default for core >= 2.92a) 414 * @ahbcfg: This field allows the default value of the GAHBCFG 415 * register to be overridden 416 * -1 - GAHBCFG value will be set to 0x06 417 * (INCR, default) 418 * all others - GAHBCFG value will be overridden with 419 * this value 420 * Not all bits can be controlled like this, the 421 * bits defined by GAHBCFG_CTRL_MASK are controlled 422 * by the driver and are ignored in this 423 * configuration value. 424 * @uframe_sched: True to enable the microframe scheduler 425 * @external_id_pin_ctl: Specifies whether ID pin is handled externally. 426 * Disable CONIDSTSCHNG controller interrupt in such 427 * case. 428 * 0 - No (default) 429 * 1 - Yes 430 * @power_down: Specifies whether the controller support power_down. 431 * If power_down is enabled, the controller will enter 432 * power_down in both peripheral and host mode when 433 * needed. 434 * 0 - No (default) 435 * 1 - Partial power down 436 * 2 - Hibernation 437 * @lpm: Enable LPM support. 438 * 0 - No 439 * 1 - Yes 440 * @lpm_clock_gating: Enable core PHY clock gating. 441 * 0 - No 442 * 1 - Yes 443 * @besl: Enable LPM Errata support. 444 * 0 - No 445 * 1 - Yes 446 * @hird_threshold_en: HIRD or HIRD Threshold enable. 447 * 0 - No 448 * 1 - Yes 449 * @hird_threshold: Value of BESL or HIRD Threshold. 450 * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO 451 * register. 452 * 0 - Deactivate the transceiver (default) 453 * 1 - Activate the transceiver 454 * @g_dma: Enables gadget dma usage (default: autodetect). 455 * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect). 456 * @g_rx_fifo_size: The periodic rx fifo size for the device, in 457 * DWORDS from 16-32768 (default: 2048 if 458 * possible, otherwise autodetect). 459 * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in 460 * DWORDS from 16-32768 (default: 1024 if 461 * possible, otherwise autodetect). 462 * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo 463 * mode. Each value corresponds to one EP 464 * starting from EP1 (max 15 values). Sizes are 465 * in DWORDS with possible values from from 466 * 16-32768 (default: 256, 256, 256, 256, 768, 467 * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0). 468 * @change_speed_quirk: Change speed configuration to DWC2_SPEED_PARAM_FULL 469 * while full&low speed device connect. And change speed 470 * back to DWC2_SPEED_PARAM_HIGH while device is gone. 471 * 0 - No (default) 472 * 1 - Yes 473 * 474 * The following parameters may be specified when starting the module. These 475 * parameters define how the DWC_otg controller should be configured. A 476 * value of -1 (or any other out of range value) for any parameter means 477 * to read the value from hardware (if possible) or use the builtin 478 * default described above. 479 */ 480 struct dwc2_core_params { 481 u8 otg_cap; 482 #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 483 #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 484 #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 485 486 u8 phy_type; 487 #define DWC2_PHY_TYPE_PARAM_FS 0 488 #define DWC2_PHY_TYPE_PARAM_UTMI 1 489 #define DWC2_PHY_TYPE_PARAM_ULPI 2 490 491 u8 speed; 492 #define DWC2_SPEED_PARAM_HIGH 0 493 #define DWC2_SPEED_PARAM_FULL 1 494 #define DWC2_SPEED_PARAM_LOW 2 495 496 u8 phy_utmi_width; 497 bool phy_ulpi_ddr; 498 bool phy_ulpi_ext_vbus; 499 bool enable_dynamic_fifo; 500 bool en_multiple_tx_fifo; 501 bool i2c_enable; 502 bool acg_enable; 503 bool ulpi_fs_ls; 504 bool ts_dline; 505 bool reload_ctl; 506 bool uframe_sched; 507 bool external_id_pin_ctl; 508 509 int power_down; 510 #define DWC2_POWER_DOWN_PARAM_NONE 0 511 #define DWC2_POWER_DOWN_PARAM_PARTIAL 1 512 #define DWC2_POWER_DOWN_PARAM_HIBERNATION 2 513 514 bool lpm; 515 bool lpm_clock_gating; 516 bool besl; 517 bool hird_threshold_en; 518 u8 hird_threshold; 519 bool activate_stm_fs_transceiver; 520 bool ipg_isoc_en; 521 u16 max_packet_count; 522 u32 max_transfer_size; 523 u32 ahbcfg; 524 525 /* Host parameters */ 526 bool host_dma; 527 bool dma_desc_enable; 528 bool dma_desc_fs_enable; 529 bool host_support_fs_ls_low_power; 530 bool host_ls_low_power_phy_clk; 531 bool oc_disable; 532 533 u8 host_channels; 534 u16 host_rx_fifo_size; 535 u16 host_nperio_tx_fifo_size; 536 u16 host_perio_tx_fifo_size; 537 538 /* Gadget parameters */ 539 bool g_dma; 540 bool g_dma_desc; 541 u32 g_rx_fifo_size; 542 u32 g_np_tx_fifo_size; 543 u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; 544 545 bool change_speed_quirk; 546 }; 547 548 /** 549 * struct dwc2_hw_params - Autodetected parameters. 550 * 551 * These parameters are the various parameters read from hardware 552 * registers during initialization. They typically contain the best 553 * supported or maximum value that can be configured in the 554 * corresponding dwc2_core_params value. 555 * 556 * The values that are not in dwc2_core_params are documented below. 557 * 558 * @op_mode: Mode of Operation 559 * 0 - HNP- and SRP-Capable OTG (Host & Device) 560 * 1 - SRP-Capable OTG (Host & Device) 561 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 562 * 3 - SRP-Capable Device 563 * 4 - Non-OTG Device 564 * 5 - SRP-Capable Host 565 * 6 - Non-OTG Host 566 * @arch: Architecture 567 * 0 - Slave only 568 * 1 - External DMA 569 * 2 - Internal DMA 570 * @ipg_isoc_en: This feature indicates that the controller supports 571 * the worst-case scenario of Rx followed by Rx 572 * Interpacket Gap (IPG) (32 bitTimes) as per the utmi 573 * specification for any token following ISOC OUT token. 574 * 0 - Don't support 575 * 1 - Support 576 * @power_optimized: Are power optimizations enabled? 577 * @num_dev_ep: Number of device endpoints available 578 * @num_dev_in_eps: Number of device IN endpoints available 579 * @num_dev_perio_in_ep: Number of device periodic IN endpoints 580 * available 581 * @dev_token_q_depth: Device Mode IN Token Sequence Learning Queue 582 * Depth 583 * 0 to 30 584 * @host_perio_tx_q_depth: 585 * Host Mode Periodic Request Queue Depth 586 * 2, 4 or 8 587 * @nperio_tx_q_depth: 588 * Non-Periodic Request Queue Depth 589 * 2, 4 or 8 590 * @hs_phy_type: High-speed PHY interface type 591 * 0 - High-speed interface not supported 592 * 1 - UTMI+ 593 * 2 - ULPI 594 * 3 - UTMI+ and ULPI 595 * @fs_phy_type: Full-speed PHY interface type 596 * 0 - Full speed interface not supported 597 * 1 - Dedicated full speed interface 598 * 2 - FS pins shared with UTMI+ pins 599 * 3 - FS pins shared with ULPI pins 600 * @total_fifo_size: Total internal RAM for FIFOs (bytes) 601 * @hibernation: Is hibernation enabled? 602 * @utmi_phy_data_width: UTMI+ PHY data width 603 * 0 - 8 bits 604 * 1 - 16 bits 605 * 2 - 8 or 16 bits 606 * @snpsid: Value from SNPSID register 607 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1) 608 * @g_tx_fifo_size: Power-on values of TxFIFO sizes 609 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 610 * address DMA mode or descriptor DMA mode for accessing 611 * the data FIFOs. The driver will automatically detect the 612 * value for this if none is specified. 613 * 0 - Address DMA 614 * 1 - Descriptor DMA (default, if available) 615 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 616 * 1 - Allow dynamic FIFO sizing (default, if available) 617 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 618 * are enabled for non-periodic IN endpoints in device 619 * mode. 620 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 621 * in host mode when dynamic FIFO sizing is enabled 622 * 16 to 32768 623 * Actual maximum value is autodetected and also 624 * the default. 625 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 626 * host mode when dynamic FIFO sizing is enabled 627 * 16 to 32768 628 * Actual maximum value is autodetected and also 629 * the default. 630 * @max_transfer_size: The maximum transfer size supported, in bytes 631 * 2047 to 65,535 632 * Actual maximum value is autodetected and also 633 * the default. 634 * @max_packet_count: The maximum number of packets in a transfer 635 * 15 to 511 636 * Actual maximum value is autodetected and also 637 * the default. 638 * @host_channels: The number of host channel registers to use 639 * 1 to 16 640 * Actual maximum value is autodetected and also 641 * the default. 642 * @dev_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 643 * in device mode when dynamic FIFO sizing is enabled 644 * 16 to 32768 645 * Actual maximum value is autodetected and also 646 * the default. 647 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 648 * speed PHY. This parameter is only applicable if phy_type 649 * is FS. 650 * 0 - No (default) 651 * 1 - Yes 652 * @acg_enable: For enabling Active Clock Gating in the controller 653 * 0 - Disable 654 * 1 - Enable 655 * @lpm_mode: For enabling Link Power Management in the controller 656 * 0 - Disable 657 * 1 - Enable 658 * @rx_fifo_size: Number of 4-byte words in the Rx FIFO when dynamic 659 * FIFO sizing is enabled 16 to 32768 660 * Actual maximum value is autodetected and also 661 * the default. 662 */ 663 struct dwc2_hw_params { 664 unsigned op_mode:3; 665 unsigned arch:2; 666 unsigned dma_desc_enable:1; 667 unsigned enable_dynamic_fifo:1; 668 unsigned en_multiple_tx_fifo:1; 669 unsigned rx_fifo_size:16; 670 unsigned host_nperio_tx_fifo_size:16; 671 unsigned dev_nperio_tx_fifo_size:16; 672 unsigned host_perio_tx_fifo_size:16; 673 unsigned nperio_tx_q_depth:3; 674 unsigned host_perio_tx_q_depth:3; 675 unsigned dev_token_q_depth:5; 676 unsigned max_transfer_size:26; 677 unsigned max_packet_count:11; 678 unsigned host_channels:5; 679 unsigned hs_phy_type:2; 680 unsigned fs_phy_type:2; 681 unsigned i2c_enable:1; 682 unsigned acg_enable:1; 683 unsigned num_dev_ep:4; 684 unsigned num_dev_in_eps : 4; 685 unsigned num_dev_perio_in_ep:4; 686 unsigned total_fifo_size:16; 687 unsigned power_optimized:1; 688 unsigned hibernation:1; 689 unsigned utmi_phy_data_width:2; 690 unsigned lpm_mode:1; 691 unsigned ipg_isoc_en:1; 692 u32 snpsid; 693 u32 dev_ep_dirs; 694 u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; 695 }; 696 697 /* Size of control and EP0 buffers */ 698 #define DWC2_CTRL_BUFF_SIZE 8 699 700 /** 701 * struct dwc2_gregs_backup - Holds global registers state before 702 * entering partial power down 703 * @gotgctl: Backup of GOTGCTL register 704 * @gintmsk: Backup of GINTMSK register 705 * @gahbcfg: Backup of GAHBCFG register 706 * @gusbcfg: Backup of GUSBCFG register 707 * @grxfsiz: Backup of GRXFSIZ register 708 * @gnptxfsiz: Backup of GNPTXFSIZ register 709 * @gi2cctl: Backup of GI2CCTL register 710 * @glpmcfg: Backup of GLPMCFG register 711 * @gdfifocfg: Backup of GDFIFOCFG register 712 * @pcgcctl: Backup of PCGCCTL register 713 * @pcgcctl1: Backup of PCGCCTL1 register 714 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 715 * @gpwrdn: Backup of GPWRDN register 716 * @valid: True if registers values backuped. 717 */ 718 struct dwc2_gregs_backup { 719 u32 gotgctl; 720 u32 gintmsk; 721 u32 gahbcfg; 722 u32 gusbcfg; 723 u32 grxfsiz; 724 u32 gnptxfsiz; 725 u32 gi2cctl; 726 u32 glpmcfg; 727 u32 pcgcctl; 728 u32 pcgcctl1; 729 u32 gdfifocfg; 730 u32 gpwrdn; 731 bool valid; 732 }; 733 734 /** 735 * struct dwc2_dregs_backup - Holds device registers state before 736 * entering partial power down 737 * @dcfg: Backup of DCFG register 738 * @dctl: Backup of DCTL register 739 * @daintmsk: Backup of DAINTMSK register 740 * @diepmsk: Backup of DIEPMSK register 741 * @doepmsk: Backup of DOEPMSK register 742 * @diepctl: Backup of DIEPCTL register 743 * @dieptsiz: Backup of DIEPTSIZ register 744 * @diepdma: Backup of DIEPDMA register 745 * @doepctl: Backup of DOEPCTL register 746 * @doeptsiz: Backup of DOEPTSIZ register 747 * @doepdma: Backup of DOEPDMA register 748 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 749 * @valid: True if registers values backuped. 750 */ 751 struct dwc2_dregs_backup { 752 u32 dcfg; 753 u32 dctl; 754 u32 daintmsk; 755 u32 diepmsk; 756 u32 doepmsk; 757 u32 diepctl[MAX_EPS_CHANNELS]; 758 u32 dieptsiz[MAX_EPS_CHANNELS]; 759 u32 diepdma[MAX_EPS_CHANNELS]; 760 u32 doepctl[MAX_EPS_CHANNELS]; 761 u32 doeptsiz[MAX_EPS_CHANNELS]; 762 u32 doepdma[MAX_EPS_CHANNELS]; 763 u32 dtxfsiz[MAX_EPS_CHANNELS]; 764 bool valid; 765 }; 766 767 /** 768 * struct dwc2_hregs_backup - Holds host registers state before 769 * entering partial power down 770 * @hcfg: Backup of HCFG register 771 * @haintmsk: Backup of HAINTMSK register 772 * @hcintmsk: Backup of HCINTMSK register 773 * @hprt0: Backup of HPTR0 register 774 * @hfir: Backup of HFIR register 775 * @hptxfsiz: Backup of HPTXFSIZ register 776 * @valid: True if registers values backuped. 777 */ 778 struct dwc2_hregs_backup { 779 u32 hcfg; 780 u32 haintmsk; 781 u32 hcintmsk[MAX_EPS_CHANNELS]; 782 u32 hprt0; 783 u32 hfir; 784 u32 hptxfsiz; 785 bool valid; 786 }; 787 788 /* 789 * Constants related to high speed periodic scheduling 790 * 791 * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a 792 * reservation point of view it's assumed that the schedule goes right back to 793 * the beginning after the end of the schedule. 794 * 795 * What does that mean for scheduling things with a long interval? It means 796 * we'll reserve time for them in every possible microframe that they could 797 * ever be scheduled in. ...but we'll still only actually schedule them as 798 * often as they were requested. 799 * 800 * We keep our schedule in a "bitmap" structure. This simplifies having 801 * to keep track of and merge intervals: we just let the bitmap code do most 802 * of the heavy lifting. In a way scheduling is much like memory allocation. 803 * 804 * We schedule 100us per uframe or 80% of 125us (the maximum amount you're 805 * supposed to schedule for periodic transfers). That's according to spec. 806 * 807 * Note that though we only schedule 80% of each microframe, the bitmap that we 808 * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of 809 * space for each uFrame). 810 * 811 * Requirements: 812 * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1) 813 * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably 814 * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might 815 * be bugs). The 8 comes from the USB spec: number of microframes per frame. 816 */ 817 #define DWC2_US_PER_UFRAME 125 818 #define DWC2_HS_PERIODIC_US_PER_UFRAME 100 819 820 #define DWC2_HS_SCHEDULE_UFRAMES 8 821 #define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \ 822 DWC2_HS_PERIODIC_US_PER_UFRAME) 823 824 /* 825 * Constants related to low speed scheduling 826 * 827 * For high speed we schedule every 1us. For low speed that's a bit overkill, 828 * so we make up a unit called a "slice" that's worth 25us. There are 40 829 * slices in a full frame and we can schedule 36 of those (90%) for periodic 830 * transfers. 831 * 832 * Our low speed schedule can be as short as 1 frame or could be longer. When 833 * we only schedule 1 frame it means that we'll need to reserve a time every 834 * frame even for things that only transfer very rarely, so something that runs 835 * every 2048 frames will get time reserved in every frame. Our low speed 836 * schedule can be longer and we'll be able to handle more overlap, but that 837 * will come at increased memory cost and increased time to schedule. 838 * 839 * Note: one other advantage of a short low speed schedule is that if we mess 840 * up and miss scheduling we can jump in and use any of the slots that we 841 * happened to reserve. 842 * 843 * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for 844 * the schedule. There will be one schedule per TT. 845 * 846 * Requirements: 847 * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME. 848 */ 849 #define DWC2_US_PER_SLICE 25 850 #define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE) 851 852 #define DWC2_ROUND_US_TO_SLICE(us) \ 853 (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \ 854 DWC2_US_PER_SLICE) 855 856 #define DWC2_LS_PERIODIC_US_PER_FRAME \ 857 900 858 #define DWC2_LS_PERIODIC_SLICES_PER_FRAME \ 859 (DWC2_LS_PERIODIC_US_PER_FRAME / \ 860 DWC2_US_PER_SLICE) 861 862 #define DWC2_LS_SCHEDULE_FRAMES 1 863 #define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \ 864 DWC2_LS_PERIODIC_SLICES_PER_FRAME) 865 866 /** 867 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 868 * and periodic schedules 869 * 870 * These are common for both host and peripheral modes: 871 * 872 * @dev: The struct device pointer 873 * @regs: Pointer to controller regs 874 * @hw_params: Parameters that were autodetected from the 875 * hardware registers 876 * @params: Parameters that define how the core should be configured 877 * @op_state: The operational State, during transitions (a_host=> 878 * a_peripheral and b_device=>b_host) this may not match 879 * the core, but allows the software to determine 880 * transitions 881 * @dr_mode: Requested mode of operation, one of following: 882 * - USB_DR_MODE_PERIPHERAL 883 * - USB_DR_MODE_HOST 884 * - USB_DR_MODE_OTG 885 * @hcd_enabled: Host mode sub-driver initialization indicator. 886 * @gadget_enabled: Peripheral mode sub-driver initialization indicator. 887 * @ll_hw_enabled: Status of low-level hardware resources. 888 * @hibernated: True if core is hibernated 889 * @frame_number: Frame number read from the core. For both device 890 * and host modes. The value ranges are from 0 891 * to HFNUM_MAX_FRNUM. 892 * @phy: The otg phy transceiver structure for phy control. 893 * @uphy: The otg phy transceiver structure for old USB phy 894 * control. 895 * @plat: The platform specific configuration data. This can be 896 * removed once all SoCs support usb transceiver. 897 * @supplies: Definition of USB power supplies 898 * @vbus_supply: Regulator supplying vbus. 899 * @phyif: PHY interface width 900 * @lock: Spinlock that protects all the driver data structures 901 * @priv: Stores a pointer to the struct usb_hcd 902 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 903 * transfer are in process of being queued 904 * @srp_success: Stores status of SRP request in the case of a FS PHY 905 * with an I2C interface 906 * @wq_otg: Workqueue object used for handling of some interrupts 907 * @wf_otg: Work object for handling Connector ID Status Change 908 * interrupt 909 * @wkp_timer: Timer object for handling Wakeup Detected interrupt 910 * @lx_state: Lx state of connected device 911 * @gr_backup: Backup of global registers during suspend 912 * @dr_backup: Backup of device registers during suspend 913 * @hr_backup: Backup of host registers during suspend 914 * 915 * These are for host mode: 916 * 917 * @flags: Flags for handling root port state changes 918 * @flags.d32: Contain all root port flags 919 * @flags.b: Separate root port flags from each other 920 * @flags.b.port_connect_status_change: True if root port connect status 921 * changed 922 * @flags.b.port_connect_status: True if device connected to root port 923 * @flags.b.port_reset_change: True if root port reset status changed 924 * @flags.b.port_enable_change: True if root port enable status changed 925 * @flags.b.port_suspend_change: True if root port suspend status changed 926 * @flags.b.port_over_current_change: True if root port over current state 927 * changed. 928 * @flags.b.port_l1_change: True if root port l1 status changed 929 * @flags.b.reserved: Reserved bits of root port register 930 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 931 * Transfers associated with these QHs are not currently 932 * assigned to a host channel. 933 * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 934 * Transfers associated with these QHs are currently 935 * assigned to a host channel. 936 * @non_periodic_qh_ptr: Pointer to next QH to process in the active 937 * non-periodic schedule 938 * @non_periodic_sched_waiting: Waiting QHs in the non-periodic schedule. 939 * Transfers associated with these QHs are not currently 940 * assigned to a host channel. 941 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 942 * list of QHs for periodic transfers that are _not_ 943 * scheduled for the next frame. Each QH in the list has an 944 * interval counter that determines when it needs to be 945 * scheduled for execution. This scheduling mechanism 946 * allows only a simple calculation for periodic bandwidth 947 * used (i.e. must assume that all periodic transfers may 948 * need to execute in the same frame). However, it greatly 949 * simplifies scheduling and should be sufficient for the 950 * vast majority of OTG hosts, which need to connect to a 951 * small number of peripherals at one time. Items move from 952 * this list to periodic_sched_ready when the QH interval 953 * counter is 0 at SOF. 954 * @periodic_sched_ready: List of periodic QHs that are ready for execution in 955 * the next frame, but have not yet been assigned to host 956 * channels. Items move from this list to 957 * periodic_sched_assigned as host channels become 958 * available during the current frame. 959 * @periodic_sched_assigned: List of periodic QHs to be executed in the next 960 * frame that are assigned to host channels. Items move 961 * from this list to periodic_sched_queued as the 962 * transactions for the QH are queued to the DWC_otg 963 * controller. 964 * @periodic_sched_queued: List of periodic QHs that have been queued for 965 * execution. Items move from this list to either 966 * periodic_sched_inactive or periodic_sched_ready when the 967 * channel associated with the transfer is released. If the 968 * interval for the QH is 1, the item moves to 969 * periodic_sched_ready because it must be rescheduled for 970 * the next frame. Otherwise, the item moves to 971 * periodic_sched_inactive. 972 * @split_order: List keeping track of channels doing splits, in order. 973 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 974 * This value is in microseconds per (micro)frame. The 975 * assumption is that all periodic transfers may occur in 976 * the same (micro)frame. 977 * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the 978 * host is in high speed mode; low speed schedules are 979 * stored elsewhere since we need one per TT. 980 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 981 * SOF enable/disable. 982 * @free_hc_list: Free host channels in the controller. This is a list of 983 * struct dwc2_host_chan items. 984 * @periodic_channels: Number of host channels assigned to periodic transfers. 985 * Currently assuming that there is a dedicated host 986 * channel for each periodic transaction and at least one 987 * host channel is available for non-periodic transactions. 988 * @non_periodic_channels: Number of host channels assigned to non-periodic 989 * transfers 990 * @available_host_channels: Number of host channels available for the 991 * microframe scheduler to use 992 * @hc_ptr_array: Array of pointers to the host channel descriptors. 993 * Allows accessing a host channel descriptor given the 994 * host channel number. This is useful in interrupt 995 * handlers. 996 * @status_buf: Buffer used for data received during the status phase of 997 * a control transfer. 998 * @status_buf_dma: DMA address for status_buf 999 * @start_work: Delayed work for handling host A-cable connection 1000 * @reset_work: Delayed work for handling a port reset 1001 * @otg_port: OTG port number 1002 * @frame_list: Frame list 1003 * @frame_list_dma: Frame list DMA address 1004 * @frame_list_sz: Frame list size 1005 * @desc_gen_cache: Kmem cache for generic descriptors 1006 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors 1007 * 1008 * These are for peripheral mode: 1009 * 1010 * @driver: USB gadget driver 1011 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 1012 * @num_of_eps: Number of available EPs (excluding EP0) 1013 * @debug_root: Root directrory for debugfs. 1014 * @ep0_reply: Request used for ep0 reply. 1015 * @ep0_buff: Buffer for EP0 reply data, if needed. 1016 * @ctrl_buff: Buffer for EP0 control requests. 1017 * @ctrl_req: Request for EP0 control packets. 1018 * @ep0_state: EP0 control transfers state 1019 * @test_mode: USB test mode requested by the host 1020 * @remote_wakeup_allowed: True if device is allowed to wake-up host by 1021 * remote-wakeup signalling 1022 * @setup_desc_dma: EP0 setup stage desc chain DMA address 1023 * @setup_desc: EP0 setup stage desc chain pointer 1024 * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address 1025 * @ctrl_in_desc: EP0 IN data phase desc chain pointer 1026 * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address 1027 * @ctrl_out_desc: EP0 OUT data phase desc chain pointer 1028 * @irq: Interrupt request line number 1029 * @clk: Pointer to otg clock 1030 * @reset: Pointer to dwc2 reset controller 1031 * @reset_ecc: Pointer to dwc2 optional reset controller in Stratix10. 1032 * @regset: A pointer to a struct debugfs_regset32, which contains 1033 * a pointer to an array of register definitions, the 1034 * array size and the base address where the register bank 1035 * is to be found. 1036 * @bus_suspended: True if bus is suspended 1037 * @last_frame_num: Number of last frame. Range from 0 to 32768 1038 * @frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is 1039 * defined, for missed SOFs tracking. Array holds that 1040 * frame numbers, which not equal to last_frame_num +1 1041 * @last_frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is 1042 * defined, for missed SOFs tracking. 1043 * If current_frame_number != last_frame_num+1 1044 * then last_frame_num added to this array 1045 * @frame_num_idx: Actual size of frame_num_array and last_frame_num_array 1046 * @dumped_frame_num_array: 1 - if missed SOFs frame numbers dumbed 1047 * 0 - if missed SOFs frame numbers not dumbed 1048 * @fifo_mem: Total internal RAM for FIFOs (bytes) 1049 * @fifo_map: Each bit intend for concrete fifo. If that bit is set, 1050 * then that fifo is used 1051 * @gadget: Represents a usb slave device 1052 * @connected: Used in slave mode. True if device connected with host 1053 * @eps_in: The IN endpoints being supplied to the gadget framework 1054 * @eps_out: The OUT endpoints being supplied to the gadget framework 1055 * @new_connection: Used in host mode. True if there are new connected 1056 * device 1057 * @enabled: Indicates the enabling state of controller 1058 * 1059 */ 1060 struct dwc2_hsotg { 1061 struct device *dev; 1062 void __iomem *regs; 1063 /** Params detected from hardware */ 1064 struct dwc2_hw_params hw_params; 1065 /** Params to actually use */ 1066 struct dwc2_core_params params; 1067 enum usb_otg_state op_state; 1068 enum usb_dr_mode dr_mode; 1069 unsigned int hcd_enabled:1; 1070 unsigned int gadget_enabled:1; 1071 unsigned int ll_hw_enabled:1; 1072 unsigned int hibernated:1; 1073 u16 frame_number; 1074 1075 struct phy *phy; 1076 struct usb_phy *uphy; 1077 struct dwc2_hsotg_plat *plat; 1078 struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES]; 1079 struct regulator *vbus_supply; 1080 u32 phyif; 1081 1082 spinlock_t lock; 1083 void *priv; 1084 int irq; 1085 struct clk *clk; 1086 struct reset_control *reset; 1087 struct reset_control *reset_ecc; 1088 1089 unsigned int queuing_high_bandwidth:1; 1090 unsigned int srp_success:1; 1091 1092 struct workqueue_struct *wq_otg; 1093 struct work_struct wf_otg; 1094 struct timer_list wkp_timer; 1095 enum dwc2_lx_state lx_state; 1096 struct dwc2_gregs_backup gr_backup; 1097 struct dwc2_dregs_backup dr_backup; 1098 struct dwc2_hregs_backup hr_backup; 1099 1100 struct dentry *debug_root; 1101 struct debugfs_regset32 *regset; 1102 1103 /* DWC OTG HW Release versions */ 1104 #define DWC2_CORE_REV_2_71a 0x4f54271a 1105 #define DWC2_CORE_REV_2_72a 0x4f54272a 1106 #define DWC2_CORE_REV_2_80a 0x4f54280a 1107 #define DWC2_CORE_REV_2_90a 0x4f54290a 1108 #define DWC2_CORE_REV_2_91a 0x4f54291a 1109 #define DWC2_CORE_REV_2_92a 0x4f54292a 1110 #define DWC2_CORE_REV_2_94a 0x4f54294a 1111 #define DWC2_CORE_REV_3_00a 0x4f54300a 1112 #define DWC2_CORE_REV_3_10a 0x4f54310a 1113 #define DWC2_CORE_REV_4_00a 0x4f54400a 1114 #define DWC2_FS_IOT_REV_1_00a 0x5531100a 1115 #define DWC2_HS_IOT_REV_1_00a 0x5532100a 1116 1117 /* DWC OTG HW Core ID */ 1118 #define DWC2_OTG_ID 0x4f540000 1119 #define DWC2_FS_IOT_ID 0x55310000 1120 #define DWC2_HS_IOT_ID 0x55320000 1121 1122 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1123 union dwc2_hcd_internal_flags { 1124 u32 d32; 1125 struct { 1126 unsigned port_connect_status_change:1; 1127 unsigned port_connect_status:1; 1128 unsigned port_reset_change:1; 1129 unsigned port_enable_change:1; 1130 unsigned port_suspend_change:1; 1131 unsigned port_over_current_change:1; 1132 unsigned port_l1_change:1; 1133 unsigned reserved:25; 1134 } b; 1135 } flags; 1136 1137 struct list_head non_periodic_sched_inactive; 1138 struct list_head non_periodic_sched_waiting; 1139 struct list_head non_periodic_sched_active; 1140 struct list_head *non_periodic_qh_ptr; 1141 struct list_head periodic_sched_inactive; 1142 struct list_head periodic_sched_ready; 1143 struct list_head periodic_sched_assigned; 1144 struct list_head periodic_sched_queued; 1145 struct list_head split_order; 1146 u16 periodic_usecs; 1147 unsigned long hs_periodic_bitmap[ 1148 DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)]; 1149 u16 periodic_qh_count; 1150 bool bus_suspended; 1151 bool new_connection; 1152 1153 u16 last_frame_num; 1154 1155 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 1156 #define FRAME_NUM_ARRAY_SIZE 1000 1157 u16 *frame_num_array; 1158 u16 *last_frame_num_array; 1159 int frame_num_idx; 1160 int dumped_frame_num_array; 1161 #endif 1162 1163 struct list_head free_hc_list; 1164 int periodic_channels; 1165 int non_periodic_channels; 1166 int available_host_channels; 1167 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 1168 u8 *status_buf; 1169 dma_addr_t status_buf_dma; 1170 #define DWC2_HCD_STATUS_BUF_SIZE 64 1171 1172 struct delayed_work start_work; 1173 struct delayed_work reset_work; 1174 u8 otg_port; 1175 u32 *frame_list; 1176 dma_addr_t frame_list_dma; 1177 u32 frame_list_sz; 1178 struct kmem_cache *desc_gen_cache; 1179 struct kmem_cache *desc_hsisoc_cache; 1180 1181 #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ 1182 1183 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1184 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1185 /* Gadget structures */ 1186 struct usb_gadget_driver *driver; 1187 int fifo_mem; 1188 unsigned int dedicated_fifos:1; 1189 unsigned char num_of_eps; 1190 u32 fifo_map; 1191 1192 struct usb_request *ep0_reply; 1193 struct usb_request *ctrl_req; 1194 void *ep0_buff; 1195 void *ctrl_buff; 1196 enum dwc2_ep0_state ep0_state; 1197 u8 test_mode; 1198 1199 dma_addr_t setup_desc_dma[2]; 1200 struct dwc2_dma_desc *setup_desc[2]; 1201 dma_addr_t ctrl_in_desc_dma; 1202 struct dwc2_dma_desc *ctrl_in_desc; 1203 dma_addr_t ctrl_out_desc_dma; 1204 struct dwc2_dma_desc *ctrl_out_desc; 1205 1206 struct usb_gadget gadget; 1207 unsigned int enabled:1; 1208 unsigned int connected:1; 1209 unsigned int remote_wakeup_allowed:1; 1210 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS]; 1211 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS]; 1212 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 1213 }; 1214 1215 /* Reasons for halting a host channel */ 1216 enum dwc2_halt_status { 1217 DWC2_HC_XFER_NO_HALT_STATUS, 1218 DWC2_HC_XFER_COMPLETE, 1219 DWC2_HC_XFER_URB_COMPLETE, 1220 DWC2_HC_XFER_ACK, 1221 DWC2_HC_XFER_NAK, 1222 DWC2_HC_XFER_NYET, 1223 DWC2_HC_XFER_STALL, 1224 DWC2_HC_XFER_XACT_ERR, 1225 DWC2_HC_XFER_FRAME_OVERRUN, 1226 DWC2_HC_XFER_BABBLE_ERR, 1227 DWC2_HC_XFER_DATA_TOGGLE_ERR, 1228 DWC2_HC_XFER_AHB_ERR, 1229 DWC2_HC_XFER_PERIODIC_INCOMPLETE, 1230 DWC2_HC_XFER_URB_DEQUEUE, 1231 }; 1232 1233 /* Core version information */ 1234 static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg) 1235 { 1236 return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000; 1237 } 1238 1239 static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg) 1240 { 1241 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000; 1242 } 1243 1244 static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg) 1245 { 1246 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000; 1247 } 1248 1249 /* 1250 * The following functions support initialization of the core driver component 1251 * and the DWC_otg controller 1252 */ 1253 int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait); 1254 int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg); 1255 int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, bool restore); 1256 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host); 1257 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup, 1258 int reset, int is_host); 1259 1260 void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host); 1261 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg); 1262 1263 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 1264 1265 /* 1266 * Common core Functions. 1267 * The following functions support managing the DWC_otg controller in either 1268 * device or host mode. 1269 */ 1270 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 1271 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 1272 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 1273 1274 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 1275 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 1276 1277 void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup, 1278 int is_host); 1279 int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg); 1280 int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg); 1281 1282 void dwc2_enable_acg(struct dwc2_hsotg *hsotg); 1283 1284 /* This function should be called on every hardware interrupt. */ 1285 irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 1286 1287 /* The device ID match table */ 1288 extern const struct of_device_id dwc2_of_match_table[]; 1289 1290 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg); 1291 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg); 1292 1293 /* Common polling functions */ 1294 int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit, 1295 u32 timeout); 1296 int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit, 1297 u32 timeout); 1298 /* Parameters */ 1299 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); 1300 int dwc2_init_params(struct dwc2_hsotg *hsotg); 1301 1302 /* 1303 * The following functions check the controller's OTG operation mode 1304 * capability (GHWCFG2.OTG_MODE). 1305 * 1306 * These functions can be used before the internal hsotg->hw_params 1307 * are read in and cached so they always read directly from the 1308 * GHWCFG2 register. 1309 */ 1310 unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg); 1311 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg); 1312 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg); 1313 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg); 1314 1315 /* 1316 * Returns the mode of operation, host or device 1317 */ 1318 static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) 1319 { 1320 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0; 1321 } 1322 1323 static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) 1324 { 1325 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0; 1326 } 1327 1328 /* 1329 * Dump core registers and SPRAM 1330 */ 1331 void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 1332 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 1333 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 1334 1335 /* Gadget defines */ 1336 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1337 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1338 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg); 1339 int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2); 1340 int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2); 1341 int dwc2_gadget_init(struct dwc2_hsotg *hsotg); 1342 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1343 bool reset); 1344 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg); 1345 void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2); 1346 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode); 1347 #define dwc2_is_device_connected(hsotg) (hsotg->connected) 1348 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg); 1349 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup); 1350 int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg); 1351 int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, 1352 int rem_wakeup, int reset); 1353 int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg); 1354 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg); 1355 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg); 1356 void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg); 1357 #else 1358 static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2) 1359 { return 0; } 1360 static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2) 1361 { return 0; } 1362 static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2) 1363 { return 0; } 1364 static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg) 1365 { return 0; } 1366 static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1367 bool reset) {} 1368 static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} 1369 static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} 1370 static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, 1371 int testmode) 1372 { return 0; } 1373 #define dwc2_is_device_connected(hsotg) (0) 1374 static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) 1375 { return 0; } 1376 static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, 1377 int remote_wakeup) 1378 { return 0; } 1379 static inline int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg) 1380 { return 0; } 1381 static inline int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, 1382 int rem_wakeup, int reset) 1383 { return 0; } 1384 static inline int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg) 1385 { return 0; } 1386 static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) 1387 { return 0; } 1388 static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg) 1389 { return 0; } 1390 static inline void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) {} 1391 #endif 1392 1393 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1394 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 1395 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us); 1396 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg); 1397 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force); 1398 void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 1399 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup); 1400 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg); 1401 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg); 1402 int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg); 1403 int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, 1404 int rem_wakeup, int reset); 1405 #else 1406 static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1407 { return 0; } 1408 static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, 1409 int us) 1410 { return 0; } 1411 static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {} 1412 static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {} 1413 static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} 1414 static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} 1415 static inline int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) 1416 { return 0; } 1417 static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg) 1418 { return 0; } 1419 static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 1420 { return 0; } 1421 static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 1422 { return 0; } 1423 static inline int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg) 1424 { return 0; } 1425 static inline int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, 1426 int rem_wakeup, int reset) 1427 { return 0; } 1428 1429 #endif 1430 1431 #endif /* __DWC2_CORE_H__ */ 1432