1 /* 2 * core.h - DesignWare HS OTG Controller common declarations 3 * 4 * Copyright (C) 2004-2013 Synopsys, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The names of the above-listed copyright holders may not be used 16 * to endorse or promote products derived from this software without 17 * specific prior written permission. 18 * 19 * ALTERNATIVELY, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") as published by the Free Software 21 * Foundation; either version 2 of the License, or (at your option) any 22 * later version. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #ifndef __DWC2_CORE_H__ 38 #define __DWC2_CORE_H__ 39 40 #include <linux/phy/phy.h> 41 #include <linux/regulator/consumer.h> 42 #include <linux/usb/gadget.h> 43 #include <linux/usb/otg.h> 44 #include <linux/usb/phy.h> 45 #include "hw.h" 46 47 #ifdef DWC2_LOG_WRITES 48 static inline void do_write(u32 value, void *addr) 49 { 50 writel(value, addr); 51 pr_info("INFO:: wrote %08x to %p\n", value, addr); 52 } 53 54 #undef writel 55 #define writel(v, a) do_write(v, a) 56 #endif 57 58 /* Maximum number of Endpoints/HostChannels */ 59 #define MAX_EPS_CHANNELS 16 60 61 /* s3c-hsotg declarations */ 62 static const char * const s3c_hsotg_supply_names[] = { 63 "vusb_d", /* digital USB supply, 1.2V */ 64 "vusb_a", /* analog USB supply, 1.1V */ 65 }; 66 67 /* 68 * EP0_MPS_LIMIT 69 * 70 * Unfortunately there seems to be a limit of the amount of data that can 71 * be transferred by IN transactions on EP0. This is either 127 bytes or 3 72 * packets (which practically means 1 packet and 63 bytes of data) when the 73 * MPS is set to 64. 74 * 75 * This means if we are wanting to move >127 bytes of data, we need to 76 * split the transactions up, but just doing one packet at a time does 77 * not work (this may be an implicit DATA0 PID on first packet of the 78 * transaction) and doing 2 packets is outside the controller's limits. 79 * 80 * If we try to lower the MPS size for EP0, then no transfers work properly 81 * for EP0, and the system will fail basic enumeration. As no cause for this 82 * has currently been found, we cannot support any large IN transfers for 83 * EP0. 84 */ 85 #define EP0_MPS_LIMIT 64 86 87 struct s3c_hsotg; 88 struct s3c_hsotg_req; 89 90 /** 91 * struct s3c_hsotg_ep - driver endpoint definition. 92 * @ep: The gadget layer representation of the endpoint. 93 * @name: The driver generated name for the endpoint. 94 * @queue: Queue of requests for this endpoint. 95 * @parent: Reference back to the parent device structure. 96 * @req: The current request that the endpoint is processing. This is 97 * used to indicate an request has been loaded onto the endpoint 98 * and has yet to be completed (maybe due to data move, or simply 99 * awaiting an ack from the core all the data has been completed). 100 * @debugfs: File entry for debugfs file for this endpoint. 101 * @lock: State lock to protect contents of endpoint. 102 * @dir_in: Set to true if this endpoint is of the IN direction, which 103 * means that it is sending data to the Host. 104 * @index: The index for the endpoint registers. 105 * @mc: Multi Count - number of transactions per microframe 106 * @interval - Interval for periodic endpoints 107 * @name: The name array passed to the USB core. 108 * @halted: Set if the endpoint has been halted. 109 * @periodic: Set if this is a periodic ep, such as Interrupt 110 * @isochronous: Set if this is a isochronous ep 111 * @sent_zlp: Set if we've sent a zero-length packet. 112 * @total_data: The total number of data bytes done. 113 * @fifo_size: The size of the FIFO (for periodic IN endpoints) 114 * @fifo_load: The amount of data loaded into the FIFO (periodic IN) 115 * @last_load: The offset of data for the last start of request. 116 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN 117 * 118 * This is the driver's state for each registered enpoint, allowing it 119 * to keep track of transactions that need doing. Each endpoint has a 120 * lock to protect the state, to try and avoid using an overall lock 121 * for the host controller as much as possible. 122 * 123 * For periodic IN endpoints, we have fifo_size and fifo_load to try 124 * and keep track of the amount of data in the periodic FIFO for each 125 * of these as we don't have a status register that tells us how much 126 * is in each of them. (note, this may actually be useless information 127 * as in shared-fifo mode periodic in acts like a single-frame packet 128 * buffer than a fifo) 129 */ 130 struct s3c_hsotg_ep { 131 struct usb_ep ep; 132 struct list_head queue; 133 struct s3c_hsotg *parent; 134 struct s3c_hsotg_req *req; 135 struct dentry *debugfs; 136 137 unsigned long total_data; 138 unsigned int size_loaded; 139 unsigned int last_load; 140 unsigned int fifo_load; 141 unsigned short fifo_size; 142 143 unsigned char dir_in; 144 unsigned char index; 145 unsigned char mc; 146 unsigned char interval; 147 148 unsigned int halted:1; 149 unsigned int periodic:1; 150 unsigned int isochronous:1; 151 unsigned int sent_zlp:1; 152 153 char name[10]; 154 }; 155 156 /** 157 * struct s3c_hsotg - driver state. 158 * @dev: The parent device supplied to the probe function 159 * @driver: USB gadget driver 160 * @phy: The otg phy transceiver structure for phy control. 161 * @uphy: The otg phy transceiver structure for old USB phy control. 162 * @plat: The platform specific configuration data. This can be removed once 163 * all SoCs support usb transceiver. 164 * @regs: The memory area mapped for accessing registers. 165 * @irq: The IRQ number we are using 166 * @supplies: Definition of USB power supplies 167 * @phyif: PHY interface width 168 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 169 * @num_of_eps: Number of available EPs (excluding EP0) 170 * @debug_root: root directrory for debugfs. 171 * @debug_file: main status file for debugfs. 172 * @debug_fifo: FIFO status file for debugfs. 173 * @ep0_reply: Request used for ep0 reply. 174 * @ep0_buff: Buffer for EP0 reply data, if needed. 175 * @ctrl_buff: Buffer for EP0 control requests. 176 * @ctrl_req: Request for EP0 control packets. 177 * @setup: NAK management for EP0 SETUP 178 * @last_rst: Time of last reset 179 * @eps: The endpoints being supplied to the gadget framework 180 */ 181 struct s3c_hsotg { 182 struct device *dev; 183 struct usb_gadget_driver *driver; 184 struct phy *phy; 185 struct usb_phy *uphy; 186 struct s3c_hsotg_plat *plat; 187 188 spinlock_t lock; 189 190 void __iomem *regs; 191 int irq; 192 struct clk *clk; 193 194 struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsotg_supply_names)]; 195 196 u32 phyif; 197 unsigned int dedicated_fifos:1; 198 unsigned char num_of_eps; 199 200 struct dentry *debug_root; 201 struct dentry *debug_file; 202 struct dentry *debug_fifo; 203 204 struct usb_request *ep0_reply; 205 struct usb_request *ctrl_req; 206 u8 ep0_buff[8]; 207 u8 ctrl_buff[8]; 208 209 struct usb_gadget gadget; 210 unsigned int setup; 211 unsigned long last_rst; 212 struct s3c_hsotg_ep *eps; 213 }; 214 215 /** 216 * struct s3c_hsotg_req - data transfer request 217 * @req: The USB gadget request 218 * @queue: The list of requests for the endpoint this is queued for. 219 * @in_progress: Has already had size/packets written to core 220 * @mapped: DMA buffer for this request has been mapped via dma_map_single(). 221 */ 222 struct s3c_hsotg_req { 223 struct usb_request req; 224 struct list_head queue; 225 unsigned char in_progress; 226 unsigned char mapped; 227 }; 228 229 #define call_gadget(_hs, _entry) \ 230 do { \ 231 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ 232 (_hs)->driver && (_hs)->driver->_entry) { \ 233 spin_unlock(&_hs->lock); \ 234 (_hs)->driver->_entry(&(_hs)->gadget); \ 235 spin_lock(&_hs->lock); \ 236 } \ 237 } while (0) 238 239 struct dwc2_hsotg; 240 struct dwc2_host_chan; 241 242 /* Device States */ 243 enum dwc2_lx_state { 244 DWC2_L0, /* On state */ 245 DWC2_L1, /* LPM sleep state */ 246 DWC2_L2, /* USB suspend state */ 247 DWC2_L3, /* Off state */ 248 }; 249 250 /** 251 * struct dwc2_core_params - Parameters for configuring the core 252 * 253 * @otg_cap: Specifies the OTG capabilities. 254 * 0 - HNP and SRP capable 255 * 1 - SRP Only capable 256 * 2 - No HNP/SRP capable (always available) 257 * Defaults to best available option (0, 1, then 2) 258 * @otg_ver: OTG version supported 259 * 0 - 1.3 (default) 260 * 1 - 2.0 261 * @dma_enable: Specifies whether to use slave or DMA mode for accessing 262 * the data FIFOs. The driver will automatically detect the 263 * value for this parameter if none is specified. 264 * 0 - Slave (always available) 265 * 1 - DMA (default, if available) 266 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 267 * address DMA mode or descriptor DMA mode for accessing 268 * the data FIFOs. The driver will automatically detect the 269 * value for this if none is specified. 270 * 0 - Address DMA 271 * 1 - Descriptor DMA (default, if available) 272 * @speed: Specifies the maximum speed of operation in host and 273 * device mode. The actual speed depends on the speed of 274 * the attached device and the value of phy_type. 275 * 0 - High Speed 276 * (default when phy_type is UTMI+ or ULPI) 277 * 1 - Full Speed 278 * (default when phy_type is Full Speed) 279 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 280 * 1 - Allow dynamic FIFO sizing (default, if available) 281 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 282 * are enabled 283 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 284 * dynamic FIFO sizing is enabled 285 * 16 to 32768 286 * Actual maximum value is autodetected and also 287 * the default. 288 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 289 * in host mode when dynamic FIFO sizing is enabled 290 * 16 to 32768 291 * Actual maximum value is autodetected and also 292 * the default. 293 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 294 * host mode when dynamic FIFO sizing is enabled 295 * 16 to 32768 296 * Actual maximum value is autodetected and also 297 * the default. 298 * @max_transfer_size: The maximum transfer size supported, in bytes 299 * 2047 to 65,535 300 * Actual maximum value is autodetected and also 301 * the default. 302 * @max_packet_count: The maximum number of packets in a transfer 303 * 15 to 511 304 * Actual maximum value is autodetected and also 305 * the default. 306 * @host_channels: The number of host channel registers to use 307 * 1 to 16 308 * Actual maximum value is autodetected and also 309 * the default. 310 * @phy_type: Specifies the type of PHY interface to use. By default, 311 * the driver will automatically detect the phy_type. 312 * 0 - Full Speed Phy 313 * 1 - UTMI+ Phy 314 * 2 - ULPI Phy 315 * Defaults to best available option (2, 1, then 0) 316 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 317 * is applicable for a phy_type of UTMI+ or ULPI. (For a 318 * ULPI phy_type, this parameter indicates the data width 319 * between the MAC and the ULPI Wrapper.) Also, this 320 * parameter is applicable only if the OTG_HSPHY_WIDTH cC 321 * parameter was set to "8 and 16 bits", meaning that the 322 * core has been configured to work at either data path 323 * width. 324 * 8 or 16 (default 16 if available) 325 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 326 * data rate. This parameter is only applicable if phy_type 327 * is ULPI. 328 * 0 - single data rate ULPI interface with 8 bit wide 329 * data bus (default) 330 * 1 - double data rate ULPI interface with 4 bit wide 331 * data bus 332 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 333 * external supply to drive the VBus 334 * 0 - Internal supply (default) 335 * 1 - External supply 336 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 337 * speed PHY. This parameter is only applicable if phy_type 338 * is FS. 339 * 0 - No (default) 340 * 1 - Yes 341 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 342 * 0 - No (default) 343 * 1 - Yes 344 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 345 * when attached to a Full Speed or Low Speed device in 346 * host mode. 347 * 0 - Don't support low power mode (default) 348 * 1 - Support low power mode 349 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 350 * when connected to a Low Speed device in host 351 * mode. This parameter is applicable only if 352 * host_support_fs_ls_low_power is enabled. 353 * 0 - 48 MHz 354 * (default when phy_type is UTMI+ or ULPI) 355 * 1 - 6 MHz 356 * (default when phy_type is Full Speed) 357 * @ts_dline: Enable Term Select Dline pulsing 358 * 0 - No (default) 359 * 1 - Yes 360 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 361 * 0 - No (default for core < 2.92a) 362 * 1 - Yes (default for core >= 2.92a) 363 * @ahbcfg: This field allows the default value of the GAHBCFG 364 * register to be overridden 365 * -1 - GAHBCFG value will be set to 0x06 366 * (INCR4, default) 367 * all others - GAHBCFG value will be overridden with 368 * this value 369 * Not all bits can be controlled like this, the 370 * bits defined by GAHBCFG_CTRL_MASK are controlled 371 * by the driver and are ignored in this 372 * configuration value. 373 * @uframe_sched: True to enable the microframe scheduler 374 * 375 * The following parameters may be specified when starting the module. These 376 * parameters define how the DWC_otg controller should be configured. A 377 * value of -1 (or any other out of range value) for any parameter means 378 * to read the value from hardware (if possible) or use the builtin 379 * default described above. 380 */ 381 struct dwc2_core_params { 382 /* 383 * Don't add any non-int members here, this will break 384 * dwc2_set_all_params! 385 */ 386 int otg_cap; 387 int otg_ver; 388 int dma_enable; 389 int dma_desc_enable; 390 int speed; 391 int enable_dynamic_fifo; 392 int en_multiple_tx_fifo; 393 int host_rx_fifo_size; 394 int host_nperio_tx_fifo_size; 395 int host_perio_tx_fifo_size; 396 int max_transfer_size; 397 int max_packet_count; 398 int host_channels; 399 int phy_type; 400 int phy_utmi_width; 401 int phy_ulpi_ddr; 402 int phy_ulpi_ext_vbus; 403 int i2c_enable; 404 int ulpi_fs_ls; 405 int host_support_fs_ls_low_power; 406 int host_ls_low_power_phy_clk; 407 int ts_dline; 408 int reload_ctl; 409 int ahbcfg; 410 int uframe_sched; 411 }; 412 413 /** 414 * struct dwc2_hw_params - Autodetected parameters. 415 * 416 * These parameters are the various parameters read from hardware 417 * registers during initialization. They typically contain the best 418 * supported or maximum value that can be configured in the 419 * corresponding dwc2_core_params value. 420 * 421 * The values that are not in dwc2_core_params are documented below. 422 * 423 * @op_mode Mode of Operation 424 * 0 - HNP- and SRP-Capable OTG (Host & Device) 425 * 1 - SRP-Capable OTG (Host & Device) 426 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 427 * 3 - SRP-Capable Device 428 * 4 - Non-OTG Device 429 * 5 - SRP-Capable Host 430 * 6 - Non-OTG Host 431 * @arch Architecture 432 * 0 - Slave only 433 * 1 - External DMA 434 * 2 - Internal DMA 435 * @power_optimized Are power optimizations enabled? 436 * @num_dev_ep Number of device endpoints available 437 * @num_dev_perio_in_ep Number of device periodic IN endpoints 438 * avaialable 439 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue 440 * Depth 441 * 0 to 30 442 * @host_perio_tx_q_depth 443 * Host Mode Periodic Request Queue Depth 444 * 2, 4 or 8 445 * @nperio_tx_q_depth 446 * Non-Periodic Request Queue Depth 447 * 2, 4 or 8 448 * @hs_phy_type High-speed PHY interface type 449 * 0 - High-speed interface not supported 450 * 1 - UTMI+ 451 * 2 - ULPI 452 * 3 - UTMI+ and ULPI 453 * @fs_phy_type Full-speed PHY interface type 454 * 0 - Full speed interface not supported 455 * 1 - Dedicated full speed interface 456 * 2 - FS pins shared with UTMI+ pins 457 * 3 - FS pins shared with ULPI pins 458 * @total_fifo_size: Total internal RAM for FIFOs (bytes) 459 * @utmi_phy_data_width UTMI+ PHY data width 460 * 0 - 8 bits 461 * 1 - 16 bits 462 * 2 - 8 or 16 bits 463 * @snpsid: Value from SNPSID register 464 */ 465 struct dwc2_hw_params { 466 unsigned op_mode:3; 467 unsigned arch:2; 468 unsigned dma_desc_enable:1; 469 unsigned enable_dynamic_fifo:1; 470 unsigned en_multiple_tx_fifo:1; 471 unsigned host_rx_fifo_size:16; 472 unsigned host_nperio_tx_fifo_size:16; 473 unsigned host_perio_tx_fifo_size:16; 474 unsigned nperio_tx_q_depth:3; 475 unsigned host_perio_tx_q_depth:3; 476 unsigned dev_token_q_depth:5; 477 unsigned max_transfer_size:26; 478 unsigned max_packet_count:11; 479 unsigned host_channels:5; 480 unsigned hs_phy_type:2; 481 unsigned fs_phy_type:2; 482 unsigned i2c_enable:1; 483 unsigned num_dev_ep:4; 484 unsigned num_dev_perio_in_ep:4; 485 unsigned total_fifo_size:16; 486 unsigned power_optimized:1; 487 unsigned utmi_phy_data_width:2; 488 u32 snpsid; 489 }; 490 491 /** 492 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 493 * and periodic schedules 494 * 495 * @dev: The struct device pointer 496 * @regs: Pointer to controller regs 497 * @core_params: Parameters that define how the core should be configured 498 * @hw_params: Parameters that were autodetected from the 499 * hardware registers 500 * @op_state: The operational State, during transitions (a_host=> 501 * a_peripheral and b_device=>b_host) this may not match 502 * the core, but allows the software to determine 503 * transitions 504 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 505 * transfer are in process of being queued 506 * @srp_success: Stores status of SRP request in the case of a FS PHY 507 * with an I2C interface 508 * @wq_otg: Workqueue object used for handling of some interrupts 509 * @wf_otg: Work object for handling Connector ID Status Change 510 * interrupt 511 * @wkp_timer: Timer object for handling Wakeup Detected interrupt 512 * @lx_state: Lx state of connected device 513 * @flags: Flags for handling root port state changes 514 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 515 * Transfers associated with these QHs are not currently 516 * assigned to a host channel. 517 * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 518 * Transfers associated with these QHs are currently 519 * assigned to a host channel. 520 * @non_periodic_qh_ptr: Pointer to next QH to process in the active 521 * non-periodic schedule 522 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 523 * list of QHs for periodic transfers that are _not_ 524 * scheduled for the next frame. Each QH in the list has an 525 * interval counter that determines when it needs to be 526 * scheduled for execution. This scheduling mechanism 527 * allows only a simple calculation for periodic bandwidth 528 * used (i.e. must assume that all periodic transfers may 529 * need to execute in the same frame). However, it greatly 530 * simplifies scheduling and should be sufficient for the 531 * vast majority of OTG hosts, which need to connect to a 532 * small number of peripherals at one time. Items move from 533 * this list to periodic_sched_ready when the QH interval 534 * counter is 0 at SOF. 535 * @periodic_sched_ready: List of periodic QHs that are ready for execution in 536 * the next frame, but have not yet been assigned to host 537 * channels. Items move from this list to 538 * periodic_sched_assigned as host channels become 539 * available during the current frame. 540 * @periodic_sched_assigned: List of periodic QHs to be executed in the next 541 * frame that are assigned to host channels. Items move 542 * from this list to periodic_sched_queued as the 543 * transactions for the QH are queued to the DWC_otg 544 * controller. 545 * @periodic_sched_queued: List of periodic QHs that have been queued for 546 * execution. Items move from this list to either 547 * periodic_sched_inactive or periodic_sched_ready when the 548 * channel associated with the transfer is released. If the 549 * interval for the QH is 1, the item moves to 550 * periodic_sched_ready because it must be rescheduled for 551 * the next frame. Otherwise, the item moves to 552 * periodic_sched_inactive. 553 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 554 * This value is in microseconds per (micro)frame. The 555 * assumption is that all periodic transfers may occur in 556 * the same (micro)frame. 557 * @frame_usecs: Internal variable used by the microframe scheduler 558 * @frame_number: Frame number read from the core at SOF. The value ranges 559 * from 0 to HFNUM_MAX_FRNUM. 560 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 561 * SOF enable/disable. 562 * @free_hc_list: Free host channels in the controller. This is a list of 563 * struct dwc2_host_chan items. 564 * @periodic_channels: Number of host channels assigned to periodic transfers. 565 * Currently assuming that there is a dedicated host 566 * channel for each periodic transaction and at least one 567 * host channel is available for non-periodic transactions. 568 * @non_periodic_channels: Number of host channels assigned to non-periodic 569 * transfers 570 * @available_host_channels Number of host channels available for the microframe 571 * scheduler to use 572 * @hc_ptr_array: Array of pointers to the host channel descriptors. 573 * Allows accessing a host channel descriptor given the 574 * host channel number. This is useful in interrupt 575 * handlers. 576 * @status_buf: Buffer used for data received during the status phase of 577 * a control transfer. 578 * @status_buf_dma: DMA address for status_buf 579 * @start_work: Delayed work for handling host A-cable connection 580 * @reset_work: Delayed work for handling a port reset 581 * @lock: Spinlock that protects all the driver data structures 582 * @priv: Stores a pointer to the struct usb_hcd 583 * @otg_port: OTG port number 584 * @frame_list: Frame list 585 * @frame_list_dma: Frame list DMA address 586 */ 587 struct dwc2_hsotg { 588 struct device *dev; 589 void __iomem *regs; 590 /** Params detected from hardware */ 591 struct dwc2_hw_params hw_params; 592 /** Params to actually use */ 593 struct dwc2_core_params *core_params; 594 enum usb_otg_state op_state; 595 596 unsigned int queuing_high_bandwidth:1; 597 unsigned int srp_success:1; 598 599 struct workqueue_struct *wq_otg; 600 struct work_struct wf_otg; 601 struct timer_list wkp_timer; 602 enum dwc2_lx_state lx_state; 603 604 union dwc2_hcd_internal_flags { 605 u32 d32; 606 struct { 607 unsigned port_connect_status_change:1; 608 unsigned port_connect_status:1; 609 unsigned port_reset_change:1; 610 unsigned port_enable_change:1; 611 unsigned port_suspend_change:1; 612 unsigned port_over_current_change:1; 613 unsigned port_l1_change:1; 614 unsigned reserved:26; 615 } b; 616 } flags; 617 618 struct list_head non_periodic_sched_inactive; 619 struct list_head non_periodic_sched_active; 620 struct list_head *non_periodic_qh_ptr; 621 struct list_head periodic_sched_inactive; 622 struct list_head periodic_sched_ready; 623 struct list_head periodic_sched_assigned; 624 struct list_head periodic_sched_queued; 625 u16 periodic_usecs; 626 u16 frame_usecs[8]; 627 u16 frame_number; 628 u16 periodic_qh_count; 629 630 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 631 #define FRAME_NUM_ARRAY_SIZE 1000 632 u16 last_frame_num; 633 u16 *frame_num_array; 634 u16 *last_frame_num_array; 635 int frame_num_idx; 636 int dumped_frame_num_array; 637 #endif 638 639 struct list_head free_hc_list; 640 int periodic_channels; 641 int non_periodic_channels; 642 int available_host_channels; 643 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 644 u8 *status_buf; 645 dma_addr_t status_buf_dma; 646 #define DWC2_HCD_STATUS_BUF_SIZE 64 647 648 struct delayed_work start_work; 649 struct delayed_work reset_work; 650 spinlock_t lock; 651 void *priv; 652 u8 otg_port; 653 u32 *frame_list; 654 dma_addr_t frame_list_dma; 655 656 /* DWC OTG HW Release versions */ 657 #define DWC2_CORE_REV_2_71a 0x4f54271a 658 #define DWC2_CORE_REV_2_90a 0x4f54290a 659 #define DWC2_CORE_REV_2_92a 0x4f54292a 660 #define DWC2_CORE_REV_2_94a 0x4f54294a 661 #define DWC2_CORE_REV_3_00a 0x4f54300a 662 663 #ifdef DEBUG 664 u32 frrem_samples; 665 u64 frrem_accum; 666 667 u32 hfnum_7_samples_a; 668 u64 hfnum_7_frrem_accum_a; 669 u32 hfnum_0_samples_a; 670 u64 hfnum_0_frrem_accum_a; 671 u32 hfnum_other_samples_a; 672 u64 hfnum_other_frrem_accum_a; 673 674 u32 hfnum_7_samples_b; 675 u64 hfnum_7_frrem_accum_b; 676 u32 hfnum_0_samples_b; 677 u64 hfnum_0_frrem_accum_b; 678 u32 hfnum_other_samples_b; 679 u64 hfnum_other_frrem_accum_b; 680 #endif 681 }; 682 683 /* Reasons for halting a host channel */ 684 enum dwc2_halt_status { 685 DWC2_HC_XFER_NO_HALT_STATUS, 686 DWC2_HC_XFER_COMPLETE, 687 DWC2_HC_XFER_URB_COMPLETE, 688 DWC2_HC_XFER_ACK, 689 DWC2_HC_XFER_NAK, 690 DWC2_HC_XFER_NYET, 691 DWC2_HC_XFER_STALL, 692 DWC2_HC_XFER_XACT_ERR, 693 DWC2_HC_XFER_FRAME_OVERRUN, 694 DWC2_HC_XFER_BABBLE_ERR, 695 DWC2_HC_XFER_DATA_TOGGLE_ERR, 696 DWC2_HC_XFER_AHB_ERR, 697 DWC2_HC_XFER_PERIODIC_INCOMPLETE, 698 DWC2_HC_XFER_URB_DEQUEUE, 699 }; 700 701 /* 702 * The following functions support initialization of the core driver component 703 * and the DWC_otg controller 704 */ 705 extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg); 706 707 /* 708 * Host core Functions. 709 * The following functions support managing the DWC_otg controller in host 710 * mode. 711 */ 712 extern void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan); 713 extern void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 714 enum dwc2_halt_status halt_status); 715 extern void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, 716 struct dwc2_host_chan *chan); 717 extern void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 718 struct dwc2_host_chan *chan); 719 extern void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 720 struct dwc2_host_chan *chan); 721 extern int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 722 struct dwc2_host_chan *chan); 723 extern void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, 724 struct dwc2_host_chan *chan); 725 extern void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg); 726 extern void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg); 727 728 extern u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg); 729 extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 730 731 /* 732 * Common core Functions. 733 * The following functions support managing the DWC_otg controller in either 734 * device or host mode. 735 */ 736 extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 737 extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 738 extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 739 740 extern int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq); 741 extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 742 extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 743 744 /* This function should be called on every hardware interrupt. */ 745 extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 746 747 /* OTG Core Parameters */ 748 749 /* 750 * Specifies the OTG capabilities. The driver will automatically 751 * detect the value for this parameter if none is specified. 752 * 0 - HNP and SRP capable (default) 753 * 1 - SRP Only capable 754 * 2 - No HNP/SRP capable 755 */ 756 extern void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val); 757 #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 758 #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 759 #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 760 761 /* 762 * Specifies whether to use slave or DMA mode for accessing the data 763 * FIFOs. The driver will automatically detect the value for this 764 * parameter if none is specified. 765 * 0 - Slave 766 * 1 - DMA (default, if available) 767 */ 768 extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val); 769 770 /* 771 * When DMA mode is enabled specifies whether to use 772 * address DMA or DMA Descritor mode for accessing the data 773 * FIFOs in device mode. The driver will automatically detect 774 * the value for this parameter if none is specified. 775 * 0 - address DMA 776 * 1 - DMA Descriptor(default, if available) 777 */ 778 extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val); 779 780 /* 781 * Specifies the maximum speed of operation in host and device mode. 782 * The actual speed depends on the speed of the attached device and 783 * the value of phy_type. The actual speed depends on the speed of the 784 * attached device. 785 * 0 - High Speed (default) 786 * 1 - Full Speed 787 */ 788 extern void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val); 789 #define DWC2_SPEED_PARAM_HIGH 0 790 #define DWC2_SPEED_PARAM_FULL 1 791 792 /* 793 * Specifies whether low power mode is supported when attached 794 * to a Full Speed or Low Speed device in host mode. 795 * 796 * 0 - Don't support low power mode (default) 797 * 1 - Support low power mode 798 */ 799 extern void dwc2_set_param_host_support_fs_ls_low_power( 800 struct dwc2_hsotg *hsotg, int val); 801 802 /* 803 * Specifies the PHY clock rate in low power mode when connected to a 804 * Low Speed device in host mode. This parameter is applicable only if 805 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS 806 * then defaults to 6 MHZ otherwise 48 MHZ. 807 * 808 * 0 - 48 MHz 809 * 1 - 6 MHz 810 */ 811 extern void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, 812 int val); 813 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 814 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 815 816 /* 817 * 0 - Use cC FIFO size parameters 818 * 1 - Allow dynamic FIFO sizing (default) 819 */ 820 extern void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, 821 int val); 822 823 /* 824 * Number of 4-byte words in the Rx FIFO in host mode when dynamic 825 * FIFO sizing is enabled. 826 * 16 to 32768 (default 1024) 827 */ 828 extern void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val); 829 830 /* 831 * Number of 4-byte words in the non-periodic Tx FIFO in host mode 832 * when Dynamic FIFO sizing is enabled in the core. 833 * 16 to 32768 (default 256) 834 */ 835 extern void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, 836 int val); 837 838 /* 839 * Number of 4-byte words in the host periodic Tx FIFO when dynamic 840 * FIFO sizing is enabled. 841 * 16 to 32768 (default 256) 842 */ 843 extern void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, 844 int val); 845 846 /* 847 * The maximum transfer size supported in bytes. 848 * 2047 to 65,535 (default 65,535) 849 */ 850 extern void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val); 851 852 /* 853 * The maximum number of packets in a transfer. 854 * 15 to 511 (default 511) 855 */ 856 extern void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val); 857 858 /* 859 * The number of host channel registers to use. 860 * 1 to 16 (default 11) 861 * Note: The FPGA configuration supports a maximum of 11 host channels. 862 */ 863 extern void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val); 864 865 /* 866 * Specifies the type of PHY interface to use. By default, the driver 867 * will automatically detect the phy_type. 868 * 869 * 0 - Full Speed PHY 870 * 1 - UTMI+ (default) 871 * 2 - ULPI 872 */ 873 extern void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val); 874 #define DWC2_PHY_TYPE_PARAM_FS 0 875 #define DWC2_PHY_TYPE_PARAM_UTMI 1 876 #define DWC2_PHY_TYPE_PARAM_ULPI 2 877 878 /* 879 * Specifies the UTMI+ Data Width. This parameter is 880 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI 881 * PHY_TYPE, this parameter indicates the data width between 882 * the MAC and the ULPI Wrapper.) Also, this parameter is 883 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set 884 * to "8 and 16 bits", meaning that the core has been 885 * configured to work at either data path width. 886 * 887 * 8 or 16 bits (default 16) 888 */ 889 extern void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val); 890 891 /* 892 * Specifies whether the ULPI operates at double or single 893 * data rate. This parameter is only applicable if PHY_TYPE is 894 * ULPI. 895 * 896 * 0 - single data rate ULPI interface with 8 bit wide data 897 * bus (default) 898 * 1 - double data rate ULPI interface with 4 bit wide data 899 * bus 900 */ 901 extern void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val); 902 903 /* 904 * Specifies whether to use the internal or external supply to 905 * drive the vbus with a ULPI phy. 906 */ 907 extern void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val); 908 #define DWC2_PHY_ULPI_INTERNAL_VBUS 0 909 #define DWC2_PHY_ULPI_EXTERNAL_VBUS 1 910 911 /* 912 * Specifies whether to use the I2Cinterface for full speed PHY. This 913 * parameter is only applicable if PHY_TYPE is FS. 914 * 0 - No (default) 915 * 1 - Yes 916 */ 917 extern void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val); 918 919 extern void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val); 920 921 extern void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val); 922 923 /* 924 * Specifies whether dedicated transmit FIFOs are 925 * enabled for non periodic IN endpoints in device mode 926 * 0 - No 927 * 1 - Yes 928 */ 929 extern void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, 930 int val); 931 932 extern void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val); 933 934 extern void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val); 935 936 extern void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val); 937 938 /* 939 * Dump core registers and SPRAM 940 */ 941 extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 942 extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 943 extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 944 945 /* 946 * Return OTG version - either 1.3 or 2.0 947 */ 948 extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg); 949 950 #endif /* __DWC2_CORE_H__ */ 951