1 /* 2 * core.h - DesignWare HS OTG Controller common declarations 3 * 4 * Copyright (C) 2004-2013 Synopsys, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The names of the above-listed copyright holders may not be used 16 * to endorse or promote products derived from this software without 17 * specific prior written permission. 18 * 19 * ALTERNATIVELY, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") as published by the Free Software 21 * Foundation; either version 2 of the License, or (at your option) any 22 * later version. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #ifndef __DWC2_CORE_H__ 38 #define __DWC2_CORE_H__ 39 40 #include <linux/phy/phy.h> 41 #include <linux/regulator/consumer.h> 42 #include <linux/usb/gadget.h> 43 #include <linux/usb/otg.h> 44 #include <linux/usb/phy.h> 45 #include "hw.h" 46 47 static inline u32 dwc2_readl(const void __iomem *addr) 48 { 49 u32 value = __raw_readl(addr); 50 51 /* In order to preserve endianness __raw_* operation is used. Therefore 52 * a barrier is needed to ensure IO access is not re-ordered across 53 * reads or writes 54 */ 55 mb(); 56 return value; 57 } 58 59 static inline void dwc2_writel(u32 value, void __iomem *addr) 60 { 61 __raw_writel(value, addr); 62 63 /* 64 * In order to preserve endianness __raw_* operation is used. Therefore 65 * a barrier is needed to ensure IO access is not re-ordered across 66 * reads or writes 67 */ 68 mb(); 69 #ifdef DWC2_LOG_WRITES 70 pr_info("INFO:: wrote %08x to %p\n", value, addr); 71 #endif 72 } 73 74 /* Maximum number of Endpoints/HostChannels */ 75 #define MAX_EPS_CHANNELS 16 76 77 /* dwc2-hsotg declarations */ 78 static const char * const dwc2_hsotg_supply_names[] = { 79 "vusb_d", /* digital USB supply, 1.2V */ 80 "vusb_a", /* analog USB supply, 1.1V */ 81 }; 82 83 /* 84 * EP0_MPS_LIMIT 85 * 86 * Unfortunately there seems to be a limit of the amount of data that can 87 * be transferred by IN transactions on EP0. This is either 127 bytes or 3 88 * packets (which practically means 1 packet and 63 bytes of data) when the 89 * MPS is set to 64. 90 * 91 * This means if we are wanting to move >127 bytes of data, we need to 92 * split the transactions up, but just doing one packet at a time does 93 * not work (this may be an implicit DATA0 PID on first packet of the 94 * transaction) and doing 2 packets is outside the controller's limits. 95 * 96 * If we try to lower the MPS size for EP0, then no transfers work properly 97 * for EP0, and the system will fail basic enumeration. As no cause for this 98 * has currently been found, we cannot support any large IN transfers for 99 * EP0. 100 */ 101 #define EP0_MPS_LIMIT 64 102 103 struct dwc2_hsotg; 104 struct dwc2_hsotg_req; 105 106 /** 107 * struct dwc2_hsotg_ep - driver endpoint definition. 108 * @ep: The gadget layer representation of the endpoint. 109 * @name: The driver generated name for the endpoint. 110 * @queue: Queue of requests for this endpoint. 111 * @parent: Reference back to the parent device structure. 112 * @req: The current request that the endpoint is processing. This is 113 * used to indicate an request has been loaded onto the endpoint 114 * and has yet to be completed (maybe due to data move, or simply 115 * awaiting an ack from the core all the data has been completed). 116 * @debugfs: File entry for debugfs file for this endpoint. 117 * @lock: State lock to protect contents of endpoint. 118 * @dir_in: Set to true if this endpoint is of the IN direction, which 119 * means that it is sending data to the Host. 120 * @index: The index for the endpoint registers. 121 * @mc: Multi Count - number of transactions per microframe 122 * @interval - Interval for periodic endpoints 123 * @name: The name array passed to the USB core. 124 * @halted: Set if the endpoint has been halted. 125 * @periodic: Set if this is a periodic ep, such as Interrupt 126 * @isochronous: Set if this is a isochronous ep 127 * @send_zlp: Set if we need to send a zero-length packet. 128 * @total_data: The total number of data bytes done. 129 * @fifo_size: The size of the FIFO (for periodic IN endpoints) 130 * @fifo_load: The amount of data loaded into the FIFO (periodic IN) 131 * @last_load: The offset of data for the last start of request. 132 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN 133 * 134 * This is the driver's state for each registered enpoint, allowing it 135 * to keep track of transactions that need doing. Each endpoint has a 136 * lock to protect the state, to try and avoid using an overall lock 137 * for the host controller as much as possible. 138 * 139 * For periodic IN endpoints, we have fifo_size and fifo_load to try 140 * and keep track of the amount of data in the periodic FIFO for each 141 * of these as we don't have a status register that tells us how much 142 * is in each of them. (note, this may actually be useless information 143 * as in shared-fifo mode periodic in acts like a single-frame packet 144 * buffer than a fifo) 145 */ 146 struct dwc2_hsotg_ep { 147 struct usb_ep ep; 148 struct list_head queue; 149 struct dwc2_hsotg *parent; 150 struct dwc2_hsotg_req *req; 151 struct dentry *debugfs; 152 153 unsigned long total_data; 154 unsigned int size_loaded; 155 unsigned int last_load; 156 unsigned int fifo_load; 157 unsigned short fifo_size; 158 unsigned short fifo_index; 159 160 unsigned char dir_in; 161 unsigned char index; 162 unsigned char mc; 163 unsigned char interval; 164 165 unsigned int halted:1; 166 unsigned int periodic:1; 167 unsigned int isochronous:1; 168 unsigned int send_zlp:1; 169 unsigned int has_correct_parity:1; 170 171 char name[10]; 172 }; 173 174 /** 175 * struct dwc2_hsotg_req - data transfer request 176 * @req: The USB gadget request 177 * @queue: The list of requests for the endpoint this is queued for. 178 * @saved_req_buf: variable to save req.buf when bounce buffers are used. 179 */ 180 struct dwc2_hsotg_req { 181 struct usb_request req; 182 struct list_head queue; 183 void *saved_req_buf; 184 }; 185 186 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 187 #define call_gadget(_hs, _entry) \ 188 do { \ 189 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ 190 (_hs)->driver && (_hs)->driver->_entry) { \ 191 spin_unlock(&_hs->lock); \ 192 (_hs)->driver->_entry(&(_hs)->gadget); \ 193 spin_lock(&_hs->lock); \ 194 } \ 195 } while (0) 196 #else 197 #define call_gadget(_hs, _entry) do {} while (0) 198 #endif 199 200 struct dwc2_hsotg; 201 struct dwc2_host_chan; 202 203 /* Device States */ 204 enum dwc2_lx_state { 205 DWC2_L0, /* On state */ 206 DWC2_L1, /* LPM sleep state */ 207 DWC2_L2, /* USB suspend state */ 208 DWC2_L3, /* Off state */ 209 }; 210 211 /* 212 * Gadget periodic tx fifo sizes as used by legacy driver 213 * EP0 is not included 214 */ 215 #define DWC2_G_P_LEGACY_TX_FIFO_SIZE {256, 256, 256, 256, 768, 768, 768, \ 216 768, 0, 0, 0, 0, 0, 0, 0} 217 218 /* Gadget ep0 states */ 219 enum dwc2_ep0_state { 220 DWC2_EP0_SETUP, 221 DWC2_EP0_DATA_IN, 222 DWC2_EP0_DATA_OUT, 223 DWC2_EP0_STATUS_IN, 224 DWC2_EP0_STATUS_OUT, 225 }; 226 227 /** 228 * struct dwc2_core_params - Parameters for configuring the core 229 * 230 * @otg_cap: Specifies the OTG capabilities. 231 * 0 - HNP and SRP capable 232 * 1 - SRP Only capable 233 * 2 - No HNP/SRP capable (always available) 234 * Defaults to best available option (0, 1, then 2) 235 * @otg_ver: OTG version supported 236 * 0 - 1.3 (default) 237 * 1 - 2.0 238 * @dma_enable: Specifies whether to use slave or DMA mode for accessing 239 * the data FIFOs. The driver will automatically detect the 240 * value for this parameter if none is specified. 241 * 0 - Slave (always available) 242 * 1 - DMA (default, if available) 243 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 244 * address DMA mode or descriptor DMA mode for accessing 245 * the data FIFOs. The driver will automatically detect the 246 * value for this if none is specified. 247 * 0 - Address DMA 248 * 1 - Descriptor DMA (default, if available) 249 * @speed: Specifies the maximum speed of operation in host and 250 * device mode. The actual speed depends on the speed of 251 * the attached device and the value of phy_type. 252 * 0 - High Speed 253 * (default when phy_type is UTMI+ or ULPI) 254 * 1 - Full Speed 255 * (default when phy_type is Full Speed) 256 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 257 * 1 - Allow dynamic FIFO sizing (default, if available) 258 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 259 * are enabled 260 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 261 * dynamic FIFO sizing is enabled 262 * 16 to 32768 263 * Actual maximum value is autodetected and also 264 * the default. 265 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 266 * in host mode when dynamic FIFO sizing is enabled 267 * 16 to 32768 268 * Actual maximum value is autodetected and also 269 * the default. 270 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 271 * host mode when dynamic FIFO sizing is enabled 272 * 16 to 32768 273 * Actual maximum value is autodetected and also 274 * the default. 275 * @max_transfer_size: The maximum transfer size supported, in bytes 276 * 2047 to 65,535 277 * Actual maximum value is autodetected and also 278 * the default. 279 * @max_packet_count: The maximum number of packets in a transfer 280 * 15 to 511 281 * Actual maximum value is autodetected and also 282 * the default. 283 * @host_channels: The number of host channel registers to use 284 * 1 to 16 285 * Actual maximum value is autodetected and also 286 * the default. 287 * @phy_type: Specifies the type of PHY interface to use. By default, 288 * the driver will automatically detect the phy_type. 289 * 0 - Full Speed Phy 290 * 1 - UTMI+ Phy 291 * 2 - ULPI Phy 292 * Defaults to best available option (2, 1, then 0) 293 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 294 * is applicable for a phy_type of UTMI+ or ULPI. (For a 295 * ULPI phy_type, this parameter indicates the data width 296 * between the MAC and the ULPI Wrapper.) Also, this 297 * parameter is applicable only if the OTG_HSPHY_WIDTH cC 298 * parameter was set to "8 and 16 bits", meaning that the 299 * core has been configured to work at either data path 300 * width. 301 * 8 or 16 (default 16 if available) 302 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 303 * data rate. This parameter is only applicable if phy_type 304 * is ULPI. 305 * 0 - single data rate ULPI interface with 8 bit wide 306 * data bus (default) 307 * 1 - double data rate ULPI interface with 4 bit wide 308 * data bus 309 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 310 * external supply to drive the VBus 311 * 0 - Internal supply (default) 312 * 1 - External supply 313 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 314 * speed PHY. This parameter is only applicable if phy_type 315 * is FS. 316 * 0 - No (default) 317 * 1 - Yes 318 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 319 * 0 - No (default) 320 * 1 - Yes 321 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 322 * when attached to a Full Speed or Low Speed device in 323 * host mode. 324 * 0 - Don't support low power mode (default) 325 * 1 - Support low power mode 326 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 327 * when connected to a Low Speed device in host 328 * mode. This parameter is applicable only if 329 * host_support_fs_ls_low_power is enabled. 330 * 0 - 48 MHz 331 * (default when phy_type is UTMI+ or ULPI) 332 * 1 - 6 MHz 333 * (default when phy_type is Full Speed) 334 * @ts_dline: Enable Term Select Dline pulsing 335 * 0 - No (default) 336 * 1 - Yes 337 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 338 * 0 - No (default for core < 2.92a) 339 * 1 - Yes (default for core >= 2.92a) 340 * @ahbcfg: This field allows the default value of the GAHBCFG 341 * register to be overridden 342 * -1 - GAHBCFG value will be set to 0x06 343 * (INCR4, default) 344 * all others - GAHBCFG value will be overridden with 345 * this value 346 * Not all bits can be controlled like this, the 347 * bits defined by GAHBCFG_CTRL_MASK are controlled 348 * by the driver and are ignored in this 349 * configuration value. 350 * @uframe_sched: True to enable the microframe scheduler 351 * @external_id_pin_ctl: Specifies whether ID pin is handled externally. 352 * Disable CONIDSTSCHNG controller interrupt in such 353 * case. 354 * 0 - No (default) 355 * 1 - Yes 356 * @hibernation: Specifies whether the controller support hibernation. 357 * If hibernation is enabled, the controller will enter 358 * hibernation in both peripheral and host mode when 359 * needed. 360 * 0 - No (default) 361 * 1 - Yes 362 * 363 * The following parameters may be specified when starting the module. These 364 * parameters define how the DWC_otg controller should be configured. A 365 * value of -1 (or any other out of range value) for any parameter means 366 * to read the value from hardware (if possible) or use the builtin 367 * default described above. 368 */ 369 struct dwc2_core_params { 370 /* 371 * Don't add any non-int members here, this will break 372 * dwc2_set_all_params! 373 */ 374 int otg_cap; 375 int otg_ver; 376 int dma_enable; 377 int dma_desc_enable; 378 int speed; 379 int enable_dynamic_fifo; 380 int en_multiple_tx_fifo; 381 int host_rx_fifo_size; 382 int host_nperio_tx_fifo_size; 383 int host_perio_tx_fifo_size; 384 int max_transfer_size; 385 int max_packet_count; 386 int host_channels; 387 int phy_type; 388 int phy_utmi_width; 389 int phy_ulpi_ddr; 390 int phy_ulpi_ext_vbus; 391 int i2c_enable; 392 int ulpi_fs_ls; 393 int host_support_fs_ls_low_power; 394 int host_ls_low_power_phy_clk; 395 int ts_dline; 396 int reload_ctl; 397 int ahbcfg; 398 int uframe_sched; 399 int external_id_pin_ctl; 400 int hibernation; 401 }; 402 403 /** 404 * struct dwc2_hw_params - Autodetected parameters. 405 * 406 * These parameters are the various parameters read from hardware 407 * registers during initialization. They typically contain the best 408 * supported or maximum value that can be configured in the 409 * corresponding dwc2_core_params value. 410 * 411 * The values that are not in dwc2_core_params are documented below. 412 * 413 * @op_mode Mode of Operation 414 * 0 - HNP- and SRP-Capable OTG (Host & Device) 415 * 1 - SRP-Capable OTG (Host & Device) 416 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 417 * 3 - SRP-Capable Device 418 * 4 - Non-OTG Device 419 * 5 - SRP-Capable Host 420 * 6 - Non-OTG Host 421 * @arch Architecture 422 * 0 - Slave only 423 * 1 - External DMA 424 * 2 - Internal DMA 425 * @power_optimized Are power optimizations enabled? 426 * @num_dev_ep Number of device endpoints available 427 * @num_dev_perio_in_ep Number of device periodic IN endpoints 428 * available 429 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue 430 * Depth 431 * 0 to 30 432 * @host_perio_tx_q_depth 433 * Host Mode Periodic Request Queue Depth 434 * 2, 4 or 8 435 * @nperio_tx_q_depth 436 * Non-Periodic Request Queue Depth 437 * 2, 4 or 8 438 * @hs_phy_type High-speed PHY interface type 439 * 0 - High-speed interface not supported 440 * 1 - UTMI+ 441 * 2 - ULPI 442 * 3 - UTMI+ and ULPI 443 * @fs_phy_type Full-speed PHY interface type 444 * 0 - Full speed interface not supported 445 * 1 - Dedicated full speed interface 446 * 2 - FS pins shared with UTMI+ pins 447 * 3 - FS pins shared with ULPI pins 448 * @total_fifo_size: Total internal RAM for FIFOs (bytes) 449 * @utmi_phy_data_width UTMI+ PHY data width 450 * 0 - 8 bits 451 * 1 - 16 bits 452 * 2 - 8 or 16 bits 453 * @snpsid: Value from SNPSID register 454 */ 455 struct dwc2_hw_params { 456 unsigned op_mode:3; 457 unsigned arch:2; 458 unsigned dma_desc_enable:1; 459 unsigned enable_dynamic_fifo:1; 460 unsigned en_multiple_tx_fifo:1; 461 unsigned host_rx_fifo_size:16; 462 unsigned host_nperio_tx_fifo_size:16; 463 unsigned host_perio_tx_fifo_size:16; 464 unsigned nperio_tx_q_depth:3; 465 unsigned host_perio_tx_q_depth:3; 466 unsigned dev_token_q_depth:5; 467 unsigned max_transfer_size:26; 468 unsigned max_packet_count:11; 469 unsigned host_channels:5; 470 unsigned hs_phy_type:2; 471 unsigned fs_phy_type:2; 472 unsigned i2c_enable:1; 473 unsigned num_dev_ep:4; 474 unsigned num_dev_perio_in_ep:4; 475 unsigned total_fifo_size:16; 476 unsigned power_optimized:1; 477 unsigned utmi_phy_data_width:2; 478 u32 snpsid; 479 }; 480 481 /* Size of control and EP0 buffers */ 482 #define DWC2_CTRL_BUFF_SIZE 8 483 484 /** 485 * struct dwc2_gregs_backup - Holds global registers state before entering partial 486 * power down 487 * @gotgctl: Backup of GOTGCTL register 488 * @gintmsk: Backup of GINTMSK register 489 * @gahbcfg: Backup of GAHBCFG register 490 * @gusbcfg: Backup of GUSBCFG register 491 * @grxfsiz: Backup of GRXFSIZ register 492 * @gnptxfsiz: Backup of GNPTXFSIZ register 493 * @gi2cctl: Backup of GI2CCTL register 494 * @hptxfsiz: Backup of HPTXFSIZ register 495 * @gdfifocfg: Backup of GDFIFOCFG register 496 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 497 * @gpwrdn: Backup of GPWRDN register 498 */ 499 struct dwc2_gregs_backup { 500 u32 gotgctl; 501 u32 gintmsk; 502 u32 gahbcfg; 503 u32 gusbcfg; 504 u32 grxfsiz; 505 u32 gnptxfsiz; 506 u32 gi2cctl; 507 u32 hptxfsiz; 508 u32 pcgcctl; 509 u32 gdfifocfg; 510 u32 dtxfsiz[MAX_EPS_CHANNELS]; 511 u32 gpwrdn; 512 bool valid; 513 }; 514 515 /** 516 * struct dwc2_dregs_backup - Holds device registers state before entering partial 517 * power down 518 * @dcfg: Backup of DCFG register 519 * @dctl: Backup of DCTL register 520 * @daintmsk: Backup of DAINTMSK register 521 * @diepmsk: Backup of DIEPMSK register 522 * @doepmsk: Backup of DOEPMSK register 523 * @diepctl: Backup of DIEPCTL register 524 * @dieptsiz: Backup of DIEPTSIZ register 525 * @diepdma: Backup of DIEPDMA register 526 * @doepctl: Backup of DOEPCTL register 527 * @doeptsiz: Backup of DOEPTSIZ register 528 * @doepdma: Backup of DOEPDMA register 529 */ 530 struct dwc2_dregs_backup { 531 u32 dcfg; 532 u32 dctl; 533 u32 daintmsk; 534 u32 diepmsk; 535 u32 doepmsk; 536 u32 diepctl[MAX_EPS_CHANNELS]; 537 u32 dieptsiz[MAX_EPS_CHANNELS]; 538 u32 diepdma[MAX_EPS_CHANNELS]; 539 u32 doepctl[MAX_EPS_CHANNELS]; 540 u32 doeptsiz[MAX_EPS_CHANNELS]; 541 u32 doepdma[MAX_EPS_CHANNELS]; 542 bool valid; 543 }; 544 545 /** 546 * struct dwc2_hregs_backup - Holds host registers state before entering partial 547 * power down 548 * @hcfg: Backup of HCFG register 549 * @haintmsk: Backup of HAINTMSK register 550 * @hcintmsk: Backup of HCINTMSK register 551 * @hptr0: Backup of HPTR0 register 552 * @hfir: Backup of HFIR register 553 */ 554 struct dwc2_hregs_backup { 555 u32 hcfg; 556 u32 haintmsk; 557 u32 hcintmsk[MAX_EPS_CHANNELS]; 558 u32 hprt0; 559 u32 hfir; 560 bool valid; 561 }; 562 563 /** 564 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 565 * and periodic schedules 566 * 567 * These are common for both host and peripheral modes: 568 * 569 * @dev: The struct device pointer 570 * @regs: Pointer to controller regs 571 * @hw_params: Parameters that were autodetected from the 572 * hardware registers 573 * @core_params: Parameters that define how the core should be configured 574 * @op_state: The operational State, during transitions (a_host=> 575 * a_peripheral and b_device=>b_host) this may not match 576 * the core, but allows the software to determine 577 * transitions 578 * @dr_mode: Requested mode of operation, one of following: 579 * - USB_DR_MODE_PERIPHERAL 580 * - USB_DR_MODE_HOST 581 * - USB_DR_MODE_OTG 582 * @hcd_enabled Host mode sub-driver initialization indicator. 583 * @gadget_enabled Peripheral mode sub-driver initialization indicator. 584 * @ll_hw_enabled Status of low-level hardware resources. 585 * @phy: The otg phy transceiver structure for phy control. 586 * @uphy: The otg phy transceiver structure for old USB phy control. 587 * @plat: The platform specific configuration data. This can be removed once 588 * all SoCs support usb transceiver. 589 * @supplies: Definition of USB power supplies 590 * @phyif: PHY interface width 591 * @lock: Spinlock that protects all the driver data structures 592 * @priv: Stores a pointer to the struct usb_hcd 593 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 594 * transfer are in process of being queued 595 * @srp_success: Stores status of SRP request in the case of a FS PHY 596 * with an I2C interface 597 * @wq_otg: Workqueue object used for handling of some interrupts 598 * @wf_otg: Work object for handling Connector ID Status Change 599 * interrupt 600 * @wkp_timer: Timer object for handling Wakeup Detected interrupt 601 * @lx_state: Lx state of connected device 602 * @gregs_backup: Backup of global registers during suspend 603 * @dregs_backup: Backup of device registers during suspend 604 * @hregs_backup: Backup of host registers during suspend 605 * 606 * These are for host mode: 607 * 608 * @flags: Flags for handling root port state changes 609 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 610 * Transfers associated with these QHs are not currently 611 * assigned to a host channel. 612 * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 613 * Transfers associated with these QHs are currently 614 * assigned to a host channel. 615 * @non_periodic_qh_ptr: Pointer to next QH to process in the active 616 * non-periodic schedule 617 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 618 * list of QHs for periodic transfers that are _not_ 619 * scheduled for the next frame. Each QH in the list has an 620 * interval counter that determines when it needs to be 621 * scheduled for execution. This scheduling mechanism 622 * allows only a simple calculation for periodic bandwidth 623 * used (i.e. must assume that all periodic transfers may 624 * need to execute in the same frame). However, it greatly 625 * simplifies scheduling and should be sufficient for the 626 * vast majority of OTG hosts, which need to connect to a 627 * small number of peripherals at one time. Items move from 628 * this list to periodic_sched_ready when the QH interval 629 * counter is 0 at SOF. 630 * @periodic_sched_ready: List of periodic QHs that are ready for execution in 631 * the next frame, but have not yet been assigned to host 632 * channels. Items move from this list to 633 * periodic_sched_assigned as host channels become 634 * available during the current frame. 635 * @periodic_sched_assigned: List of periodic QHs to be executed in the next 636 * frame that are assigned to host channels. Items move 637 * from this list to periodic_sched_queued as the 638 * transactions for the QH are queued to the DWC_otg 639 * controller. 640 * @periodic_sched_queued: List of periodic QHs that have been queued for 641 * execution. Items move from this list to either 642 * periodic_sched_inactive or periodic_sched_ready when the 643 * channel associated with the transfer is released. If the 644 * interval for the QH is 1, the item moves to 645 * periodic_sched_ready because it must be rescheduled for 646 * the next frame. Otherwise, the item moves to 647 * periodic_sched_inactive. 648 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 649 * This value is in microseconds per (micro)frame. The 650 * assumption is that all periodic transfers may occur in 651 * the same (micro)frame. 652 * @frame_usecs: Internal variable used by the microframe scheduler 653 * @frame_number: Frame number read from the core at SOF. The value ranges 654 * from 0 to HFNUM_MAX_FRNUM. 655 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 656 * SOF enable/disable. 657 * @free_hc_list: Free host channels in the controller. This is a list of 658 * struct dwc2_host_chan items. 659 * @periodic_channels: Number of host channels assigned to periodic transfers. 660 * Currently assuming that there is a dedicated host 661 * channel for each periodic transaction and at least one 662 * host channel is available for non-periodic transactions. 663 * @non_periodic_channels: Number of host channels assigned to non-periodic 664 * transfers 665 * @available_host_channels Number of host channels available for the microframe 666 * scheduler to use 667 * @hc_ptr_array: Array of pointers to the host channel descriptors. 668 * Allows accessing a host channel descriptor given the 669 * host channel number. This is useful in interrupt 670 * handlers. 671 * @status_buf: Buffer used for data received during the status phase of 672 * a control transfer. 673 * @status_buf_dma: DMA address for status_buf 674 * @start_work: Delayed work for handling host A-cable connection 675 * @reset_work: Delayed work for handling a port reset 676 * @otg_port: OTG port number 677 * @frame_list: Frame list 678 * @frame_list_dma: Frame list DMA address 679 * 680 * These are for peripheral mode: 681 * 682 * @driver: USB gadget driver 683 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 684 * @num_of_eps: Number of available EPs (excluding EP0) 685 * @debug_root: Root directrory for debugfs. 686 * @debug_file: Main status file for debugfs. 687 * @debug_testmode: Testmode status file for debugfs. 688 * @debug_fifo: FIFO status file for debugfs. 689 * @ep0_reply: Request used for ep0 reply. 690 * @ep0_buff: Buffer for EP0 reply data, if needed. 691 * @ctrl_buff: Buffer for EP0 control requests. 692 * @ctrl_req: Request for EP0 control packets. 693 * @ep0_state: EP0 control transfers state 694 * @test_mode: USB test mode requested by the host 695 * @eps: The endpoints being supplied to the gadget framework 696 * @g_using_dma: Indicate if dma usage is enabled 697 * @g_rx_fifo_sz: Contains rx fifo size value 698 * @g_np_g_tx_fifo_sz: Contains Non-Periodic tx fifo size value 699 * @g_tx_fifo_sz: Contains tx fifo size value per endpoints 700 */ 701 struct dwc2_hsotg { 702 struct device *dev; 703 void __iomem *regs; 704 /** Params detected from hardware */ 705 struct dwc2_hw_params hw_params; 706 /** Params to actually use */ 707 struct dwc2_core_params *core_params; 708 enum usb_otg_state op_state; 709 enum usb_dr_mode dr_mode; 710 unsigned int hcd_enabled:1; 711 unsigned int gadget_enabled:1; 712 unsigned int ll_hw_enabled:1; 713 714 struct phy *phy; 715 struct usb_phy *uphy; 716 struct dwc2_hsotg_plat *plat; 717 struct regulator_bulk_data supplies[ARRAY_SIZE(dwc2_hsotg_supply_names)]; 718 u32 phyif; 719 720 spinlock_t lock; 721 void *priv; 722 int irq; 723 struct clk *clk; 724 725 unsigned int queuing_high_bandwidth:1; 726 unsigned int srp_success:1; 727 728 struct workqueue_struct *wq_otg; 729 struct work_struct wf_otg; 730 struct timer_list wkp_timer; 731 enum dwc2_lx_state lx_state; 732 struct dwc2_gregs_backup gr_backup; 733 struct dwc2_dregs_backup dr_backup; 734 struct dwc2_hregs_backup hr_backup; 735 736 struct dentry *debug_root; 737 struct debugfs_regset32 *regset; 738 739 /* DWC OTG HW Release versions */ 740 #define DWC2_CORE_REV_2_71a 0x4f54271a 741 #define DWC2_CORE_REV_2_90a 0x4f54290a 742 #define DWC2_CORE_REV_2_92a 0x4f54292a 743 #define DWC2_CORE_REV_2_94a 0x4f54294a 744 #define DWC2_CORE_REV_3_00a 0x4f54300a 745 746 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 747 union dwc2_hcd_internal_flags { 748 u32 d32; 749 struct { 750 unsigned port_connect_status_change:1; 751 unsigned port_connect_status:1; 752 unsigned port_reset_change:1; 753 unsigned port_enable_change:1; 754 unsigned port_suspend_change:1; 755 unsigned port_over_current_change:1; 756 unsigned port_l1_change:1; 757 unsigned reserved:25; 758 } b; 759 } flags; 760 761 struct list_head non_periodic_sched_inactive; 762 struct list_head non_periodic_sched_active; 763 struct list_head *non_periodic_qh_ptr; 764 struct list_head periodic_sched_inactive; 765 struct list_head periodic_sched_ready; 766 struct list_head periodic_sched_assigned; 767 struct list_head periodic_sched_queued; 768 u16 periodic_usecs; 769 u16 frame_usecs[8]; 770 u16 frame_number; 771 u16 periodic_qh_count; 772 bool bus_suspended; 773 774 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 775 #define FRAME_NUM_ARRAY_SIZE 1000 776 u16 last_frame_num; 777 u16 *frame_num_array; 778 u16 *last_frame_num_array; 779 int frame_num_idx; 780 int dumped_frame_num_array; 781 #endif 782 783 struct list_head free_hc_list; 784 int periodic_channels; 785 int non_periodic_channels; 786 int available_host_channels; 787 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 788 u8 *status_buf; 789 dma_addr_t status_buf_dma; 790 #define DWC2_HCD_STATUS_BUF_SIZE 64 791 792 struct delayed_work start_work; 793 struct delayed_work reset_work; 794 u8 otg_port; 795 u32 *frame_list; 796 dma_addr_t frame_list_dma; 797 798 #ifdef DEBUG 799 u32 frrem_samples; 800 u64 frrem_accum; 801 802 u32 hfnum_7_samples_a; 803 u64 hfnum_7_frrem_accum_a; 804 u32 hfnum_0_samples_a; 805 u64 hfnum_0_frrem_accum_a; 806 u32 hfnum_other_samples_a; 807 u64 hfnum_other_frrem_accum_a; 808 809 u32 hfnum_7_samples_b; 810 u64 hfnum_7_frrem_accum_b; 811 u32 hfnum_0_samples_b; 812 u64 hfnum_0_frrem_accum_b; 813 u32 hfnum_other_samples_b; 814 u64 hfnum_other_frrem_accum_b; 815 #endif 816 #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ 817 818 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 819 /* Gadget structures */ 820 struct usb_gadget_driver *driver; 821 int fifo_mem; 822 unsigned int dedicated_fifos:1; 823 unsigned char num_of_eps; 824 u32 fifo_map; 825 826 struct usb_request *ep0_reply; 827 struct usb_request *ctrl_req; 828 void *ep0_buff; 829 void *ctrl_buff; 830 enum dwc2_ep0_state ep0_state; 831 u8 test_mode; 832 833 struct usb_gadget gadget; 834 unsigned int enabled:1; 835 unsigned int connected:1; 836 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS]; 837 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS]; 838 u32 g_using_dma; 839 u32 g_rx_fifo_sz; 840 u32 g_np_g_tx_fifo_sz; 841 u32 g_tx_fifo_sz[MAX_EPS_CHANNELS]; 842 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 843 }; 844 845 /* Reasons for halting a host channel */ 846 enum dwc2_halt_status { 847 DWC2_HC_XFER_NO_HALT_STATUS, 848 DWC2_HC_XFER_COMPLETE, 849 DWC2_HC_XFER_URB_COMPLETE, 850 DWC2_HC_XFER_ACK, 851 DWC2_HC_XFER_NAK, 852 DWC2_HC_XFER_NYET, 853 DWC2_HC_XFER_STALL, 854 DWC2_HC_XFER_XACT_ERR, 855 DWC2_HC_XFER_FRAME_OVERRUN, 856 DWC2_HC_XFER_BABBLE_ERR, 857 DWC2_HC_XFER_DATA_TOGGLE_ERR, 858 DWC2_HC_XFER_AHB_ERR, 859 DWC2_HC_XFER_PERIODIC_INCOMPLETE, 860 DWC2_HC_XFER_URB_DEQUEUE, 861 }; 862 863 /* 864 * The following functions support initialization of the core driver component 865 * and the DWC_otg controller 866 */ 867 extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg); 868 extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg); 869 extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore); 870 871 /* 872 * Host core Functions. 873 * The following functions support managing the DWC_otg controller in host 874 * mode. 875 */ 876 extern void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan); 877 extern void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 878 enum dwc2_halt_status halt_status); 879 extern void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, 880 struct dwc2_host_chan *chan); 881 extern void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 882 struct dwc2_host_chan *chan); 883 extern void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 884 struct dwc2_host_chan *chan); 885 extern int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 886 struct dwc2_host_chan *chan); 887 extern void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, 888 struct dwc2_host_chan *chan); 889 extern void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg); 890 extern void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg); 891 892 extern u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg); 893 extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 894 895 /* 896 * Common core Functions. 897 * The following functions support managing the DWC_otg controller in either 898 * device or host mode. 899 */ 900 extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 901 extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 902 extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 903 904 extern int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq); 905 extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 906 extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 907 908 /* This function should be called on every hardware interrupt. */ 909 extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 910 911 /* OTG Core Parameters */ 912 913 /* 914 * Specifies the OTG capabilities. The driver will automatically 915 * detect the value for this parameter if none is specified. 916 * 0 - HNP and SRP capable (default) 917 * 1 - SRP Only capable 918 * 2 - No HNP/SRP capable 919 */ 920 extern void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val); 921 #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 922 #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 923 #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 924 925 /* 926 * Specifies whether to use slave or DMA mode for accessing the data 927 * FIFOs. The driver will automatically detect the value for this 928 * parameter if none is specified. 929 * 0 - Slave 930 * 1 - DMA (default, if available) 931 */ 932 extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val); 933 934 /* 935 * When DMA mode is enabled specifies whether to use 936 * address DMA or DMA Descritor mode for accessing the data 937 * FIFOs in device mode. The driver will automatically detect 938 * the value for this parameter if none is specified. 939 * 0 - address DMA 940 * 1 - DMA Descriptor(default, if available) 941 */ 942 extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val); 943 944 /* 945 * Specifies the maximum speed of operation in host and device mode. 946 * The actual speed depends on the speed of the attached device and 947 * the value of phy_type. The actual speed depends on the speed of the 948 * attached device. 949 * 0 - High Speed (default) 950 * 1 - Full Speed 951 */ 952 extern void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val); 953 #define DWC2_SPEED_PARAM_HIGH 0 954 #define DWC2_SPEED_PARAM_FULL 1 955 956 /* 957 * Specifies whether low power mode is supported when attached 958 * to a Full Speed or Low Speed device in host mode. 959 * 960 * 0 - Don't support low power mode (default) 961 * 1 - Support low power mode 962 */ 963 extern void dwc2_set_param_host_support_fs_ls_low_power( 964 struct dwc2_hsotg *hsotg, int val); 965 966 /* 967 * Specifies the PHY clock rate in low power mode when connected to a 968 * Low Speed device in host mode. This parameter is applicable only if 969 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS 970 * then defaults to 6 MHZ otherwise 48 MHZ. 971 * 972 * 0 - 48 MHz 973 * 1 - 6 MHz 974 */ 975 extern void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, 976 int val); 977 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 978 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 979 980 /* 981 * 0 - Use cC FIFO size parameters 982 * 1 - Allow dynamic FIFO sizing (default) 983 */ 984 extern void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, 985 int val); 986 987 /* 988 * Number of 4-byte words in the Rx FIFO in host mode when dynamic 989 * FIFO sizing is enabled. 990 * 16 to 32768 (default 1024) 991 */ 992 extern void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val); 993 994 /* 995 * Number of 4-byte words in the non-periodic Tx FIFO in host mode 996 * when Dynamic FIFO sizing is enabled in the core. 997 * 16 to 32768 (default 256) 998 */ 999 extern void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, 1000 int val); 1001 1002 /* 1003 * Number of 4-byte words in the host periodic Tx FIFO when dynamic 1004 * FIFO sizing is enabled. 1005 * 16 to 32768 (default 256) 1006 */ 1007 extern void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, 1008 int val); 1009 1010 /* 1011 * The maximum transfer size supported in bytes. 1012 * 2047 to 65,535 (default 65,535) 1013 */ 1014 extern void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val); 1015 1016 /* 1017 * The maximum number of packets in a transfer. 1018 * 15 to 511 (default 511) 1019 */ 1020 extern void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val); 1021 1022 /* 1023 * The number of host channel registers to use. 1024 * 1 to 16 (default 11) 1025 * Note: The FPGA configuration supports a maximum of 11 host channels. 1026 */ 1027 extern void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val); 1028 1029 /* 1030 * Specifies the type of PHY interface to use. By default, the driver 1031 * will automatically detect the phy_type. 1032 * 1033 * 0 - Full Speed PHY 1034 * 1 - UTMI+ (default) 1035 * 2 - ULPI 1036 */ 1037 extern void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val); 1038 #define DWC2_PHY_TYPE_PARAM_FS 0 1039 #define DWC2_PHY_TYPE_PARAM_UTMI 1 1040 #define DWC2_PHY_TYPE_PARAM_ULPI 2 1041 1042 /* 1043 * Specifies the UTMI+ Data Width. This parameter is 1044 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI 1045 * PHY_TYPE, this parameter indicates the data width between 1046 * the MAC and the ULPI Wrapper.) Also, this parameter is 1047 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set 1048 * to "8 and 16 bits", meaning that the core has been 1049 * configured to work at either data path width. 1050 * 1051 * 8 or 16 bits (default 16) 1052 */ 1053 extern void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val); 1054 1055 /* 1056 * Specifies whether the ULPI operates at double or single 1057 * data rate. This parameter is only applicable if PHY_TYPE is 1058 * ULPI. 1059 * 1060 * 0 - single data rate ULPI interface with 8 bit wide data 1061 * bus (default) 1062 * 1 - double data rate ULPI interface with 4 bit wide data 1063 * bus 1064 */ 1065 extern void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val); 1066 1067 /* 1068 * Specifies whether to use the internal or external supply to 1069 * drive the vbus with a ULPI phy. 1070 */ 1071 extern void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val); 1072 #define DWC2_PHY_ULPI_INTERNAL_VBUS 0 1073 #define DWC2_PHY_ULPI_EXTERNAL_VBUS 1 1074 1075 /* 1076 * Specifies whether to use the I2Cinterface for full speed PHY. This 1077 * parameter is only applicable if PHY_TYPE is FS. 1078 * 0 - No (default) 1079 * 1 - Yes 1080 */ 1081 extern void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val); 1082 1083 extern void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val); 1084 1085 extern void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val); 1086 1087 /* 1088 * Specifies whether dedicated transmit FIFOs are 1089 * enabled for non periodic IN endpoints in device mode 1090 * 0 - No 1091 * 1 - Yes 1092 */ 1093 extern void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, 1094 int val); 1095 1096 extern void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val); 1097 1098 extern void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val); 1099 1100 extern void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val); 1101 1102 extern void dwc2_set_parameters(struct dwc2_hsotg *hsotg, 1103 const struct dwc2_core_params *params); 1104 1105 extern void dwc2_set_all_params(struct dwc2_core_params *params, int value); 1106 1107 extern int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); 1108 1109 extern int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg); 1110 extern int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg); 1111 1112 /* 1113 * Dump core registers and SPRAM 1114 */ 1115 extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 1116 extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 1117 extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 1118 1119 /* 1120 * Return OTG version - either 1.3 or 2.0 1121 */ 1122 extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg); 1123 1124 /* Gadget defines */ 1125 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1126 extern int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg); 1127 extern int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2); 1128 extern int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2); 1129 extern int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq); 1130 extern void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1131 bool reset); 1132 extern void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg); 1133 extern void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2); 1134 extern int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode); 1135 #define dwc2_is_device_connected(hsotg) (hsotg->connected) 1136 #else 1137 static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2) 1138 { return 0; } 1139 static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2) 1140 { return 0; } 1141 static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2) 1142 { return 0; } 1143 static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) 1144 { return 0; } 1145 static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1146 bool reset) {} 1147 static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} 1148 static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} 1149 static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, 1150 int testmode) 1151 { return 0; } 1152 #define dwc2_is_device_connected(hsotg) (0) 1153 #endif 1154 1155 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1156 extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 1157 extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg); 1158 extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 1159 #else 1160 static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1161 { return 0; } 1162 static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg) {} 1163 static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} 1164 static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} 1165 static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) 1166 { return 0; } 1167 #endif 1168 1169 #endif /* __DWC2_CORE_H__ */ 1170