1 /* 2 * core.h - DesignWare HS OTG Controller common declarations 3 * 4 * Copyright (C) 2004-2013 Synopsys, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The names of the above-listed copyright holders may not be used 16 * to endorse or promote products derived from this software without 17 * specific prior written permission. 18 * 19 * ALTERNATIVELY, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") as published by the Free Software 21 * Foundation; either version 2 of the License, or (at your option) any 22 * later version. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #ifndef __DWC2_CORE_H__ 38 #define __DWC2_CORE_H__ 39 40 #include <linux/phy/phy.h> 41 #include <linux/regulator/consumer.h> 42 #include <linux/usb/gadget.h> 43 #include <linux/usb/otg.h> 44 #include <linux/usb/phy.h> 45 #include "hw.h" 46 47 #ifdef DWC2_LOG_WRITES 48 static inline void do_write(u32 value, void *addr) 49 { 50 writel(value, addr); 51 pr_info("INFO:: wrote %08x to %p\n", value, addr); 52 } 53 54 #undef writel 55 #define writel(v, a) do_write(v, a) 56 #endif 57 58 /* Maximum number of Endpoints/HostChannels */ 59 #define MAX_EPS_CHANNELS 16 60 61 /* s3c-hsotg declarations */ 62 static const char * const s3c_hsotg_supply_names[] = { 63 "vusb_d", /* digital USB supply, 1.2V */ 64 "vusb_a", /* analog USB supply, 1.1V */ 65 }; 66 67 /* 68 * EP0_MPS_LIMIT 69 * 70 * Unfortunately there seems to be a limit of the amount of data that can 71 * be transferred by IN transactions on EP0. This is either 127 bytes or 3 72 * packets (which practically means 1 packet and 63 bytes of data) when the 73 * MPS is set to 64. 74 * 75 * This means if we are wanting to move >127 bytes of data, we need to 76 * split the transactions up, but just doing one packet at a time does 77 * not work (this may be an implicit DATA0 PID on first packet of the 78 * transaction) and doing 2 packets is outside the controller's limits. 79 * 80 * If we try to lower the MPS size for EP0, then no transfers work properly 81 * for EP0, and the system will fail basic enumeration. As no cause for this 82 * has currently been found, we cannot support any large IN transfers for 83 * EP0. 84 */ 85 #define EP0_MPS_LIMIT 64 86 87 struct dwc2_hsotg; 88 struct s3c_hsotg_req; 89 90 /** 91 * struct s3c_hsotg_ep - driver endpoint definition. 92 * @ep: The gadget layer representation of the endpoint. 93 * @name: The driver generated name for the endpoint. 94 * @queue: Queue of requests for this endpoint. 95 * @parent: Reference back to the parent device structure. 96 * @req: The current request that the endpoint is processing. This is 97 * used to indicate an request has been loaded onto the endpoint 98 * and has yet to be completed (maybe due to data move, or simply 99 * awaiting an ack from the core all the data has been completed). 100 * @debugfs: File entry for debugfs file for this endpoint. 101 * @lock: State lock to protect contents of endpoint. 102 * @dir_in: Set to true if this endpoint is of the IN direction, which 103 * means that it is sending data to the Host. 104 * @index: The index for the endpoint registers. 105 * @mc: Multi Count - number of transactions per microframe 106 * @interval - Interval for periodic endpoints 107 * @name: The name array passed to the USB core. 108 * @halted: Set if the endpoint has been halted. 109 * @periodic: Set if this is a periodic ep, such as Interrupt 110 * @isochronous: Set if this is a isochronous ep 111 * @sent_zlp: Set if we've sent a zero-length packet. 112 * @total_data: The total number of data bytes done. 113 * @fifo_size: The size of the FIFO (for periodic IN endpoints) 114 * @fifo_load: The amount of data loaded into the FIFO (periodic IN) 115 * @last_load: The offset of data for the last start of request. 116 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN 117 * 118 * This is the driver's state for each registered enpoint, allowing it 119 * to keep track of transactions that need doing. Each endpoint has a 120 * lock to protect the state, to try and avoid using an overall lock 121 * for the host controller as much as possible. 122 * 123 * For periodic IN endpoints, we have fifo_size and fifo_load to try 124 * and keep track of the amount of data in the periodic FIFO for each 125 * of these as we don't have a status register that tells us how much 126 * is in each of them. (note, this may actually be useless information 127 * as in shared-fifo mode periodic in acts like a single-frame packet 128 * buffer than a fifo) 129 */ 130 struct s3c_hsotg_ep { 131 struct usb_ep ep; 132 struct list_head queue; 133 struct dwc2_hsotg *parent; 134 struct s3c_hsotg_req *req; 135 struct dentry *debugfs; 136 137 unsigned long total_data; 138 unsigned int size_loaded; 139 unsigned int last_load; 140 unsigned int fifo_load; 141 unsigned short fifo_size; 142 unsigned short fifo_index; 143 144 unsigned char dir_in; 145 unsigned char index; 146 unsigned char mc; 147 unsigned char interval; 148 149 unsigned int halted:1; 150 unsigned int periodic:1; 151 unsigned int isochronous:1; 152 unsigned int sent_zlp:1; 153 154 char name[10]; 155 }; 156 157 /** 158 * struct s3c_hsotg_req - data transfer request 159 * @req: The USB gadget request 160 * @queue: The list of requests for the endpoint this is queued for. 161 * @in_progress: Has already had size/packets written to core 162 * @mapped: DMA buffer for this request has been mapped via dma_map_single(). 163 */ 164 struct s3c_hsotg_req { 165 struct usb_request req; 166 struct list_head queue; 167 unsigned char in_progress; 168 unsigned char mapped; 169 }; 170 171 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 172 #define call_gadget(_hs, _entry) \ 173 do { \ 174 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ 175 (_hs)->driver && (_hs)->driver->_entry) { \ 176 spin_unlock(&_hs->lock); \ 177 (_hs)->driver->_entry(&(_hs)->gadget); \ 178 spin_lock(&_hs->lock); \ 179 } \ 180 } while (0) 181 #else 182 #define call_gadget(_hs, _entry) do {} while (0) 183 #endif 184 185 struct dwc2_hsotg; 186 struct dwc2_host_chan; 187 188 /* Device States */ 189 enum dwc2_lx_state { 190 DWC2_L0, /* On state */ 191 DWC2_L1, /* LPM sleep state */ 192 DWC2_L2, /* USB suspend state */ 193 DWC2_L3, /* Off state */ 194 }; 195 196 /** 197 * struct dwc2_core_params - Parameters for configuring the core 198 * 199 * @otg_cap: Specifies the OTG capabilities. 200 * 0 - HNP and SRP capable 201 * 1 - SRP Only capable 202 * 2 - No HNP/SRP capable (always available) 203 * Defaults to best available option (0, 1, then 2) 204 * @otg_ver: OTG version supported 205 * 0 - 1.3 (default) 206 * 1 - 2.0 207 * @dma_enable: Specifies whether to use slave or DMA mode for accessing 208 * the data FIFOs. The driver will automatically detect the 209 * value for this parameter if none is specified. 210 * 0 - Slave (always available) 211 * 1 - DMA (default, if available) 212 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 213 * address DMA mode or descriptor DMA mode for accessing 214 * the data FIFOs. The driver will automatically detect the 215 * value for this if none is specified. 216 * 0 - Address DMA 217 * 1 - Descriptor DMA (default, if available) 218 * @speed: Specifies the maximum speed of operation in host and 219 * device mode. The actual speed depends on the speed of 220 * the attached device and the value of phy_type. 221 * 0 - High Speed 222 * (default when phy_type is UTMI+ or ULPI) 223 * 1 - Full Speed 224 * (default when phy_type is Full Speed) 225 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 226 * 1 - Allow dynamic FIFO sizing (default, if available) 227 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 228 * are enabled 229 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 230 * dynamic FIFO sizing is enabled 231 * 16 to 32768 232 * Actual maximum value is autodetected and also 233 * the default. 234 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 235 * in host mode when dynamic FIFO sizing is enabled 236 * 16 to 32768 237 * Actual maximum value is autodetected and also 238 * the default. 239 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 240 * host mode when dynamic FIFO sizing is enabled 241 * 16 to 32768 242 * Actual maximum value is autodetected and also 243 * the default. 244 * @max_transfer_size: The maximum transfer size supported, in bytes 245 * 2047 to 65,535 246 * Actual maximum value is autodetected and also 247 * the default. 248 * @max_packet_count: The maximum number of packets in a transfer 249 * 15 to 511 250 * Actual maximum value is autodetected and also 251 * the default. 252 * @host_channels: The number of host channel registers to use 253 * 1 to 16 254 * Actual maximum value is autodetected and also 255 * the default. 256 * @phy_type: Specifies the type of PHY interface to use. By default, 257 * the driver will automatically detect the phy_type. 258 * 0 - Full Speed Phy 259 * 1 - UTMI+ Phy 260 * 2 - ULPI Phy 261 * Defaults to best available option (2, 1, then 0) 262 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 263 * is applicable for a phy_type of UTMI+ or ULPI. (For a 264 * ULPI phy_type, this parameter indicates the data width 265 * between the MAC and the ULPI Wrapper.) Also, this 266 * parameter is applicable only if the OTG_HSPHY_WIDTH cC 267 * parameter was set to "8 and 16 bits", meaning that the 268 * core has been configured to work at either data path 269 * width. 270 * 8 or 16 (default 16 if available) 271 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 272 * data rate. This parameter is only applicable if phy_type 273 * is ULPI. 274 * 0 - single data rate ULPI interface with 8 bit wide 275 * data bus (default) 276 * 1 - double data rate ULPI interface with 4 bit wide 277 * data bus 278 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 279 * external supply to drive the VBus 280 * 0 - Internal supply (default) 281 * 1 - External supply 282 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 283 * speed PHY. This parameter is only applicable if phy_type 284 * is FS. 285 * 0 - No (default) 286 * 1 - Yes 287 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 288 * 0 - No (default) 289 * 1 - Yes 290 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 291 * when attached to a Full Speed or Low Speed device in 292 * host mode. 293 * 0 - Don't support low power mode (default) 294 * 1 - Support low power mode 295 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 296 * when connected to a Low Speed device in host 297 * mode. This parameter is applicable only if 298 * host_support_fs_ls_low_power is enabled. 299 * 0 - 48 MHz 300 * (default when phy_type is UTMI+ or ULPI) 301 * 1 - 6 MHz 302 * (default when phy_type is Full Speed) 303 * @ts_dline: Enable Term Select Dline pulsing 304 * 0 - No (default) 305 * 1 - Yes 306 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 307 * 0 - No (default for core < 2.92a) 308 * 1 - Yes (default for core >= 2.92a) 309 * @ahbcfg: This field allows the default value of the GAHBCFG 310 * register to be overridden 311 * -1 - GAHBCFG value will be set to 0x06 312 * (INCR4, default) 313 * all others - GAHBCFG value will be overridden with 314 * this value 315 * Not all bits can be controlled like this, the 316 * bits defined by GAHBCFG_CTRL_MASK are controlled 317 * by the driver and are ignored in this 318 * configuration value. 319 * @uframe_sched: True to enable the microframe scheduler 320 * 321 * The following parameters may be specified when starting the module. These 322 * parameters define how the DWC_otg controller should be configured. A 323 * value of -1 (or any other out of range value) for any parameter means 324 * to read the value from hardware (if possible) or use the builtin 325 * default described above. 326 */ 327 struct dwc2_core_params { 328 /* 329 * Don't add any non-int members here, this will break 330 * dwc2_set_all_params! 331 */ 332 int otg_cap; 333 int otg_ver; 334 int dma_enable; 335 int dma_desc_enable; 336 int speed; 337 int enable_dynamic_fifo; 338 int en_multiple_tx_fifo; 339 int host_rx_fifo_size; 340 int host_nperio_tx_fifo_size; 341 int host_perio_tx_fifo_size; 342 int max_transfer_size; 343 int max_packet_count; 344 int host_channels; 345 int phy_type; 346 int phy_utmi_width; 347 int phy_ulpi_ddr; 348 int phy_ulpi_ext_vbus; 349 int i2c_enable; 350 int ulpi_fs_ls; 351 int host_support_fs_ls_low_power; 352 int host_ls_low_power_phy_clk; 353 int ts_dline; 354 int reload_ctl; 355 int ahbcfg; 356 int uframe_sched; 357 }; 358 359 /** 360 * struct dwc2_hw_params - Autodetected parameters. 361 * 362 * These parameters are the various parameters read from hardware 363 * registers during initialization. They typically contain the best 364 * supported or maximum value that can be configured in the 365 * corresponding dwc2_core_params value. 366 * 367 * The values that are not in dwc2_core_params are documented below. 368 * 369 * @op_mode Mode of Operation 370 * 0 - HNP- and SRP-Capable OTG (Host & Device) 371 * 1 - SRP-Capable OTG (Host & Device) 372 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 373 * 3 - SRP-Capable Device 374 * 4 - Non-OTG Device 375 * 5 - SRP-Capable Host 376 * 6 - Non-OTG Host 377 * @arch Architecture 378 * 0 - Slave only 379 * 1 - External DMA 380 * 2 - Internal DMA 381 * @power_optimized Are power optimizations enabled? 382 * @num_dev_ep Number of device endpoints available 383 * @num_dev_perio_in_ep Number of device periodic IN endpoints 384 * avaialable 385 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue 386 * Depth 387 * 0 to 30 388 * @host_perio_tx_q_depth 389 * Host Mode Periodic Request Queue Depth 390 * 2, 4 or 8 391 * @nperio_tx_q_depth 392 * Non-Periodic Request Queue Depth 393 * 2, 4 or 8 394 * @hs_phy_type High-speed PHY interface type 395 * 0 - High-speed interface not supported 396 * 1 - UTMI+ 397 * 2 - ULPI 398 * 3 - UTMI+ and ULPI 399 * @fs_phy_type Full-speed PHY interface type 400 * 0 - Full speed interface not supported 401 * 1 - Dedicated full speed interface 402 * 2 - FS pins shared with UTMI+ pins 403 * 3 - FS pins shared with ULPI pins 404 * @total_fifo_size: Total internal RAM for FIFOs (bytes) 405 * @utmi_phy_data_width UTMI+ PHY data width 406 * 0 - 8 bits 407 * 1 - 16 bits 408 * 2 - 8 or 16 bits 409 * @snpsid: Value from SNPSID register 410 */ 411 struct dwc2_hw_params { 412 unsigned op_mode:3; 413 unsigned arch:2; 414 unsigned dma_desc_enable:1; 415 unsigned enable_dynamic_fifo:1; 416 unsigned en_multiple_tx_fifo:1; 417 unsigned host_rx_fifo_size:16; 418 unsigned host_nperio_tx_fifo_size:16; 419 unsigned host_perio_tx_fifo_size:16; 420 unsigned nperio_tx_q_depth:3; 421 unsigned host_perio_tx_q_depth:3; 422 unsigned dev_token_q_depth:5; 423 unsigned max_transfer_size:26; 424 unsigned max_packet_count:11; 425 unsigned host_channels:5; 426 unsigned hs_phy_type:2; 427 unsigned fs_phy_type:2; 428 unsigned i2c_enable:1; 429 unsigned num_dev_ep:4; 430 unsigned num_dev_perio_in_ep:4; 431 unsigned total_fifo_size:16; 432 unsigned power_optimized:1; 433 unsigned utmi_phy_data_width:2; 434 u32 snpsid; 435 }; 436 437 /** 438 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 439 * and periodic schedules 440 * 441 * These are common for both host and peripheral modes: 442 * 443 * @dev: The struct device pointer 444 * @regs: Pointer to controller regs 445 * @hw_params: Parameters that were autodetected from the 446 * hardware registers 447 * @core_params: Parameters that define how the core should be configured 448 * @op_state: The operational State, during transitions (a_host=> 449 * a_peripheral and b_device=>b_host) this may not match 450 * the core, but allows the software to determine 451 * transitions 452 * @dr_mode: Requested mode of operation, one of following: 453 * - USB_DR_MODE_PERIPHERAL 454 * - USB_DR_MODE_HOST 455 * - USB_DR_MODE_OTG 456 * @lock: Spinlock that protects all the driver data structures 457 * @priv: Stores a pointer to the struct usb_hcd 458 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 459 * transfer are in process of being queued 460 * @srp_success: Stores status of SRP request in the case of a FS PHY 461 * with an I2C interface 462 * @wq_otg: Workqueue object used for handling of some interrupts 463 * @wf_otg: Work object for handling Connector ID Status Change 464 * interrupt 465 * @wkp_timer: Timer object for handling Wakeup Detected interrupt 466 * @lx_state: Lx state of connected device 467 * 468 * These are for host mode: 469 * 470 * @flags: Flags for handling root port state changes 471 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 472 * Transfers associated with these QHs are not currently 473 * assigned to a host channel. 474 * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 475 * Transfers associated with these QHs are currently 476 * assigned to a host channel. 477 * @non_periodic_qh_ptr: Pointer to next QH to process in the active 478 * non-periodic schedule 479 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 480 * list of QHs for periodic transfers that are _not_ 481 * scheduled for the next frame. Each QH in the list has an 482 * interval counter that determines when it needs to be 483 * scheduled for execution. This scheduling mechanism 484 * allows only a simple calculation for periodic bandwidth 485 * used (i.e. must assume that all periodic transfers may 486 * need to execute in the same frame). However, it greatly 487 * simplifies scheduling and should be sufficient for the 488 * vast majority of OTG hosts, which need to connect to a 489 * small number of peripherals at one time. Items move from 490 * this list to periodic_sched_ready when the QH interval 491 * counter is 0 at SOF. 492 * @periodic_sched_ready: List of periodic QHs that are ready for execution in 493 * the next frame, but have not yet been assigned to host 494 * channels. Items move from this list to 495 * periodic_sched_assigned as host channels become 496 * available during the current frame. 497 * @periodic_sched_assigned: List of periodic QHs to be executed in the next 498 * frame that are assigned to host channels. Items move 499 * from this list to periodic_sched_queued as the 500 * transactions for the QH are queued to the DWC_otg 501 * controller. 502 * @periodic_sched_queued: List of periodic QHs that have been queued for 503 * execution. Items move from this list to either 504 * periodic_sched_inactive or periodic_sched_ready when the 505 * channel associated with the transfer is released. If the 506 * interval for the QH is 1, the item moves to 507 * periodic_sched_ready because it must be rescheduled for 508 * the next frame. Otherwise, the item moves to 509 * periodic_sched_inactive. 510 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 511 * This value is in microseconds per (micro)frame. The 512 * assumption is that all periodic transfers may occur in 513 * the same (micro)frame. 514 * @frame_usecs: Internal variable used by the microframe scheduler 515 * @frame_number: Frame number read from the core at SOF. The value ranges 516 * from 0 to HFNUM_MAX_FRNUM. 517 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 518 * SOF enable/disable. 519 * @free_hc_list: Free host channels in the controller. This is a list of 520 * struct dwc2_host_chan items. 521 * @periodic_channels: Number of host channels assigned to periodic transfers. 522 * Currently assuming that there is a dedicated host 523 * channel for each periodic transaction and at least one 524 * host channel is available for non-periodic transactions. 525 * @non_periodic_channels: Number of host channels assigned to non-periodic 526 * transfers 527 * @available_host_channels Number of host channels available for the microframe 528 * scheduler to use 529 * @hc_ptr_array: Array of pointers to the host channel descriptors. 530 * Allows accessing a host channel descriptor given the 531 * host channel number. This is useful in interrupt 532 * handlers. 533 * @status_buf: Buffer used for data received during the status phase of 534 * a control transfer. 535 * @status_buf_dma: DMA address for status_buf 536 * @start_work: Delayed work for handling host A-cable connection 537 * @reset_work: Delayed work for handling a port reset 538 * @otg_port: OTG port number 539 * @frame_list: Frame list 540 * @frame_list_dma: Frame list DMA address 541 * 542 * These are for peripheral mode: 543 * 544 * @driver: USB gadget driver 545 * @phy: The otg phy transceiver structure for phy control. 546 * @uphy: The otg phy transceiver structure for old USB phy control. 547 * @plat: The platform specific configuration data. This can be removed once 548 * all SoCs support usb transceiver. 549 * @supplies: Definition of USB power supplies 550 * @phyif: PHY interface width 551 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 552 * @num_of_eps: Number of available EPs (excluding EP0) 553 * @debug_root: Root directrory for debugfs. 554 * @debug_file: Main status file for debugfs. 555 * @debug_fifo: FIFO status file for debugfs. 556 * @ep0_reply: Request used for ep0 reply. 557 * @ep0_buff: Buffer for EP0 reply data, if needed. 558 * @ctrl_buff: Buffer for EP0 control requests. 559 * @ctrl_req: Request for EP0 control packets. 560 * @setup: NAK management for EP0 SETUP 561 * @last_rst: Time of last reset 562 * @eps: The endpoints being supplied to the gadget framework 563 */ 564 struct dwc2_hsotg { 565 struct device *dev; 566 void __iomem *regs; 567 /** Params detected from hardware */ 568 struct dwc2_hw_params hw_params; 569 /** Params to actually use */ 570 struct dwc2_core_params *core_params; 571 enum usb_otg_state op_state; 572 enum usb_dr_mode dr_mode; 573 574 struct phy *phy; 575 struct usb_phy *uphy; 576 struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsotg_supply_names)]; 577 578 spinlock_t lock; 579 struct mutex init_mutex; 580 void *priv; 581 int irq; 582 struct clk *clk; 583 584 unsigned int queuing_high_bandwidth:1; 585 unsigned int srp_success:1; 586 587 struct workqueue_struct *wq_otg; 588 struct work_struct wf_otg; 589 struct timer_list wkp_timer; 590 enum dwc2_lx_state lx_state; 591 592 struct dentry *debug_root; 593 struct dentry *debug_file; 594 struct dentry *debug_fifo; 595 596 /* DWC OTG HW Release versions */ 597 #define DWC2_CORE_REV_2_71a 0x4f54271a 598 #define DWC2_CORE_REV_2_90a 0x4f54290a 599 #define DWC2_CORE_REV_2_92a 0x4f54292a 600 #define DWC2_CORE_REV_2_94a 0x4f54294a 601 #define DWC2_CORE_REV_3_00a 0x4f54300a 602 603 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 604 union dwc2_hcd_internal_flags { 605 u32 d32; 606 struct { 607 unsigned port_connect_status_change:1; 608 unsigned port_connect_status:1; 609 unsigned port_reset_change:1; 610 unsigned port_enable_change:1; 611 unsigned port_suspend_change:1; 612 unsigned port_over_current_change:1; 613 unsigned port_l1_change:1; 614 unsigned reserved:25; 615 } b; 616 } flags; 617 618 struct list_head non_periodic_sched_inactive; 619 struct list_head non_periodic_sched_active; 620 struct list_head *non_periodic_qh_ptr; 621 struct list_head periodic_sched_inactive; 622 struct list_head periodic_sched_ready; 623 struct list_head periodic_sched_assigned; 624 struct list_head periodic_sched_queued; 625 u16 periodic_usecs; 626 u16 frame_usecs[8]; 627 u16 frame_number; 628 u16 periodic_qh_count; 629 630 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 631 #define FRAME_NUM_ARRAY_SIZE 1000 632 u16 last_frame_num; 633 u16 *frame_num_array; 634 u16 *last_frame_num_array; 635 int frame_num_idx; 636 int dumped_frame_num_array; 637 #endif 638 639 struct list_head free_hc_list; 640 int periodic_channels; 641 int non_periodic_channels; 642 int available_host_channels; 643 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 644 u8 *status_buf; 645 dma_addr_t status_buf_dma; 646 #define DWC2_HCD_STATUS_BUF_SIZE 64 647 648 struct delayed_work start_work; 649 struct delayed_work reset_work; 650 u8 otg_port; 651 u32 *frame_list; 652 dma_addr_t frame_list_dma; 653 654 #ifdef DEBUG 655 u32 frrem_samples; 656 u64 frrem_accum; 657 658 u32 hfnum_7_samples_a; 659 u64 hfnum_7_frrem_accum_a; 660 u32 hfnum_0_samples_a; 661 u64 hfnum_0_frrem_accum_a; 662 u32 hfnum_other_samples_a; 663 u64 hfnum_other_frrem_accum_a; 664 665 u32 hfnum_7_samples_b; 666 u64 hfnum_7_frrem_accum_b; 667 u32 hfnum_0_samples_b; 668 u64 hfnum_0_frrem_accum_b; 669 u32 hfnum_other_samples_b; 670 u64 hfnum_other_frrem_accum_b; 671 #endif 672 #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ 673 674 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 675 /* Gadget structures */ 676 struct usb_gadget_driver *driver; 677 struct s3c_hsotg_plat *plat; 678 679 u32 phyif; 680 int fifo_mem; 681 unsigned int dedicated_fifos:1; 682 unsigned char num_of_eps; 683 u32 fifo_map; 684 685 struct usb_request *ep0_reply; 686 struct usb_request *ctrl_req; 687 u8 ep0_buff[8]; 688 u8 ctrl_buff[8]; 689 690 struct usb_gadget gadget; 691 unsigned int enabled:1; 692 unsigned int connected:1; 693 unsigned int setup:1; 694 unsigned long last_rst; 695 struct s3c_hsotg_ep *eps; 696 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 697 }; 698 699 /* Reasons for halting a host channel */ 700 enum dwc2_halt_status { 701 DWC2_HC_XFER_NO_HALT_STATUS, 702 DWC2_HC_XFER_COMPLETE, 703 DWC2_HC_XFER_URB_COMPLETE, 704 DWC2_HC_XFER_ACK, 705 DWC2_HC_XFER_NAK, 706 DWC2_HC_XFER_NYET, 707 DWC2_HC_XFER_STALL, 708 DWC2_HC_XFER_XACT_ERR, 709 DWC2_HC_XFER_FRAME_OVERRUN, 710 DWC2_HC_XFER_BABBLE_ERR, 711 DWC2_HC_XFER_DATA_TOGGLE_ERR, 712 DWC2_HC_XFER_AHB_ERR, 713 DWC2_HC_XFER_PERIODIC_INCOMPLETE, 714 DWC2_HC_XFER_URB_DEQUEUE, 715 }; 716 717 /* 718 * The following functions support initialization of the core driver component 719 * and the DWC_otg controller 720 */ 721 extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg); 722 723 /* 724 * Host core Functions. 725 * The following functions support managing the DWC_otg controller in host 726 * mode. 727 */ 728 extern void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan); 729 extern void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 730 enum dwc2_halt_status halt_status); 731 extern void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, 732 struct dwc2_host_chan *chan); 733 extern void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 734 struct dwc2_host_chan *chan); 735 extern void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 736 struct dwc2_host_chan *chan); 737 extern int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 738 struct dwc2_host_chan *chan); 739 extern void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, 740 struct dwc2_host_chan *chan); 741 extern void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg); 742 extern void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg); 743 744 extern u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg); 745 extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 746 747 /* 748 * Common core Functions. 749 * The following functions support managing the DWC_otg controller in either 750 * device or host mode. 751 */ 752 extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 753 extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 754 extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 755 756 extern int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq); 757 extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 758 extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 759 760 /* This function should be called on every hardware interrupt. */ 761 extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 762 763 /* OTG Core Parameters */ 764 765 /* 766 * Specifies the OTG capabilities. The driver will automatically 767 * detect the value for this parameter if none is specified. 768 * 0 - HNP and SRP capable (default) 769 * 1 - SRP Only capable 770 * 2 - No HNP/SRP capable 771 */ 772 extern void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val); 773 #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 774 #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 775 #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 776 777 /* 778 * Specifies whether to use slave or DMA mode for accessing the data 779 * FIFOs. The driver will automatically detect the value for this 780 * parameter if none is specified. 781 * 0 - Slave 782 * 1 - DMA (default, if available) 783 */ 784 extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val); 785 786 /* 787 * When DMA mode is enabled specifies whether to use 788 * address DMA or DMA Descritor mode for accessing the data 789 * FIFOs in device mode. The driver will automatically detect 790 * the value for this parameter if none is specified. 791 * 0 - address DMA 792 * 1 - DMA Descriptor(default, if available) 793 */ 794 extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val); 795 796 /* 797 * Specifies the maximum speed of operation in host and device mode. 798 * The actual speed depends on the speed of the attached device and 799 * the value of phy_type. The actual speed depends on the speed of the 800 * attached device. 801 * 0 - High Speed (default) 802 * 1 - Full Speed 803 */ 804 extern void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val); 805 #define DWC2_SPEED_PARAM_HIGH 0 806 #define DWC2_SPEED_PARAM_FULL 1 807 808 /* 809 * Specifies whether low power mode is supported when attached 810 * to a Full Speed or Low Speed device in host mode. 811 * 812 * 0 - Don't support low power mode (default) 813 * 1 - Support low power mode 814 */ 815 extern void dwc2_set_param_host_support_fs_ls_low_power( 816 struct dwc2_hsotg *hsotg, int val); 817 818 /* 819 * Specifies the PHY clock rate in low power mode when connected to a 820 * Low Speed device in host mode. This parameter is applicable only if 821 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS 822 * then defaults to 6 MHZ otherwise 48 MHZ. 823 * 824 * 0 - 48 MHz 825 * 1 - 6 MHz 826 */ 827 extern void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, 828 int val); 829 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 830 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 831 832 /* 833 * 0 - Use cC FIFO size parameters 834 * 1 - Allow dynamic FIFO sizing (default) 835 */ 836 extern void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, 837 int val); 838 839 /* 840 * Number of 4-byte words in the Rx FIFO in host mode when dynamic 841 * FIFO sizing is enabled. 842 * 16 to 32768 (default 1024) 843 */ 844 extern void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val); 845 846 /* 847 * Number of 4-byte words in the non-periodic Tx FIFO in host mode 848 * when Dynamic FIFO sizing is enabled in the core. 849 * 16 to 32768 (default 256) 850 */ 851 extern void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, 852 int val); 853 854 /* 855 * Number of 4-byte words in the host periodic Tx FIFO when dynamic 856 * FIFO sizing is enabled. 857 * 16 to 32768 (default 256) 858 */ 859 extern void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, 860 int val); 861 862 /* 863 * The maximum transfer size supported in bytes. 864 * 2047 to 65,535 (default 65,535) 865 */ 866 extern void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val); 867 868 /* 869 * The maximum number of packets in a transfer. 870 * 15 to 511 (default 511) 871 */ 872 extern void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val); 873 874 /* 875 * The number of host channel registers to use. 876 * 1 to 16 (default 11) 877 * Note: The FPGA configuration supports a maximum of 11 host channels. 878 */ 879 extern void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val); 880 881 /* 882 * Specifies the type of PHY interface to use. By default, the driver 883 * will automatically detect the phy_type. 884 * 885 * 0 - Full Speed PHY 886 * 1 - UTMI+ (default) 887 * 2 - ULPI 888 */ 889 extern void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val); 890 #define DWC2_PHY_TYPE_PARAM_FS 0 891 #define DWC2_PHY_TYPE_PARAM_UTMI 1 892 #define DWC2_PHY_TYPE_PARAM_ULPI 2 893 894 /* 895 * Specifies the UTMI+ Data Width. This parameter is 896 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI 897 * PHY_TYPE, this parameter indicates the data width between 898 * the MAC and the ULPI Wrapper.) Also, this parameter is 899 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set 900 * to "8 and 16 bits", meaning that the core has been 901 * configured to work at either data path width. 902 * 903 * 8 or 16 bits (default 16) 904 */ 905 extern void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val); 906 907 /* 908 * Specifies whether the ULPI operates at double or single 909 * data rate. This parameter is only applicable if PHY_TYPE is 910 * ULPI. 911 * 912 * 0 - single data rate ULPI interface with 8 bit wide data 913 * bus (default) 914 * 1 - double data rate ULPI interface with 4 bit wide data 915 * bus 916 */ 917 extern void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val); 918 919 /* 920 * Specifies whether to use the internal or external supply to 921 * drive the vbus with a ULPI phy. 922 */ 923 extern void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val); 924 #define DWC2_PHY_ULPI_INTERNAL_VBUS 0 925 #define DWC2_PHY_ULPI_EXTERNAL_VBUS 1 926 927 /* 928 * Specifies whether to use the I2Cinterface for full speed PHY. This 929 * parameter is only applicable if PHY_TYPE is FS. 930 * 0 - No (default) 931 * 1 - Yes 932 */ 933 extern void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val); 934 935 extern void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val); 936 937 extern void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val); 938 939 /* 940 * Specifies whether dedicated transmit FIFOs are 941 * enabled for non periodic IN endpoints in device mode 942 * 0 - No 943 * 1 - Yes 944 */ 945 extern void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, 946 int val); 947 948 extern void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val); 949 950 extern void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val); 951 952 extern void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val); 953 954 /* 955 * Dump core registers and SPRAM 956 */ 957 extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 958 extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 959 extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 960 961 /* 962 * Return OTG version - either 1.3 or 2.0 963 */ 964 extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg); 965 966 /* Gadget defines */ 967 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 968 extern int s3c_hsotg_remove(struct dwc2_hsotg *hsotg); 969 extern int s3c_hsotg_suspend(struct dwc2_hsotg *dwc2); 970 extern int s3c_hsotg_resume(struct dwc2_hsotg *dwc2); 971 extern int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq); 972 extern void s3c_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2); 973 extern void s3c_hsotg_core_connect(struct dwc2_hsotg *hsotg); 974 extern void s3c_hsotg_disconnect(struct dwc2_hsotg *dwc2); 975 #else 976 static inline int s3c_hsotg_remove(struct dwc2_hsotg *dwc2) 977 { return 0; } 978 static inline int s3c_hsotg_suspend(struct dwc2_hsotg *dwc2) 979 { return 0; } 980 static inline int s3c_hsotg_resume(struct dwc2_hsotg *dwc2) 981 { return 0; } 982 static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) 983 { return 0; } 984 static inline void s3c_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2) {} 985 static inline void s3c_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} 986 static inline void s3c_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} 987 #endif 988 989 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 990 extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 991 extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg); 992 extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 993 #else 994 static inline void dwc2_set_all_params(struct dwc2_core_params *params, int value) {} 995 static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 996 { return 0; } 997 static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg) {} 998 static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} 999 static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} 1000 static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq, 1001 const struct dwc2_core_params *params) 1002 { return 0; } 1003 #endif 1004 1005 #endif /* __DWC2_CORE_H__ */ 1006