1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2 /* 3 * core.h - DesignWare HS OTG Controller common declarations 4 * 5 * Copyright (C) 2004-2013 Synopsys, Inc. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The names of the above-listed copyright holders may not be used 17 * to endorse or promote products derived from this software without 18 * specific prior written permission. 19 * 20 * ALTERNATIVELY, this software may be distributed under the terms of the 21 * GNU General Public License ("GPL") as published by the Free Software 22 * Foundation; either version 2 of the License, or (at your option) any 23 * later version. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef __DWC2_CORE_H__ 39 #define __DWC2_CORE_H__ 40 41 #include <linux/acpi.h> 42 #include <linux/phy/phy.h> 43 #include <linux/regulator/consumer.h> 44 #include <linux/usb/gadget.h> 45 #include <linux/usb/otg.h> 46 #include <linux/usb/phy.h> 47 #include "hw.h" 48 49 /* 50 * Suggested defines for tracers: 51 * - no_printk: Disable tracing 52 * - pr_info: Print this info to the console 53 * - trace_printk: Print this info to trace buffer (good for verbose logging) 54 */ 55 56 #define DWC2_TRACE_SCHEDULER no_printk 57 #define DWC2_TRACE_SCHEDULER_VB no_printk 58 59 /* Detailed scheduler tracing, but won't overwhelm console */ 60 #define dwc2_sch_dbg(hsotg, fmt, ...) \ 61 DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \ 62 dev_name(hsotg->dev), ##__VA_ARGS__) 63 64 /* Verbose scheduler tracing */ 65 #define dwc2_sch_vdbg(hsotg, fmt, ...) \ 66 DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \ 67 dev_name(hsotg->dev), ##__VA_ARGS__) 68 69 /* Maximum number of Endpoints/HostChannels */ 70 #define MAX_EPS_CHANNELS 16 71 72 /* dwc2-hsotg declarations */ 73 static const char * const dwc2_hsotg_supply_names[] = { 74 "vusb_d", /* digital USB supply, 1.2V */ 75 "vusb_a", /* analog USB supply, 1.1V */ 76 }; 77 78 #define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names) 79 80 /* 81 * EP0_MPS_LIMIT 82 * 83 * Unfortunately there seems to be a limit of the amount of data that can 84 * be transferred by IN transactions on EP0. This is either 127 bytes or 3 85 * packets (which practically means 1 packet and 63 bytes of data) when the 86 * MPS is set to 64. 87 * 88 * This means if we are wanting to move >127 bytes of data, we need to 89 * split the transactions up, but just doing one packet at a time does 90 * not work (this may be an implicit DATA0 PID on first packet of the 91 * transaction) and doing 2 packets is outside the controller's limits. 92 * 93 * If we try to lower the MPS size for EP0, then no transfers work properly 94 * for EP0, and the system will fail basic enumeration. As no cause for this 95 * has currently been found, we cannot support any large IN transfers for 96 * EP0. 97 */ 98 #define EP0_MPS_LIMIT 64 99 100 struct dwc2_hsotg; 101 struct dwc2_hsotg_req; 102 103 /** 104 * struct dwc2_hsotg_ep - driver endpoint definition. 105 * @ep: The gadget layer representation of the endpoint. 106 * @name: The driver generated name for the endpoint. 107 * @queue: Queue of requests for this endpoint. 108 * @parent: Reference back to the parent device structure. 109 * @req: The current request that the endpoint is processing. This is 110 * used to indicate an request has been loaded onto the endpoint 111 * and has yet to be completed (maybe due to data move, or simply 112 * awaiting an ack from the core all the data has been completed). 113 * @debugfs: File entry for debugfs file for this endpoint. 114 * @dir_in: Set to true if this endpoint is of the IN direction, which 115 * means that it is sending data to the Host. 116 * @index: The index for the endpoint registers. 117 * @mc: Multi Count - number of transactions per microframe 118 * @interval: Interval for periodic endpoints, in frames or microframes. 119 * @name: The name array passed to the USB core. 120 * @halted: Set if the endpoint has been halted. 121 * @periodic: Set if this is a periodic ep, such as Interrupt 122 * @isochronous: Set if this is a isochronous ep 123 * @send_zlp: Set if we need to send a zero-length packet. 124 * @desc_list_dma: The DMA address of descriptor chain currently in use. 125 * @desc_list: Pointer to descriptor DMA chain head currently in use. 126 * @desc_count: Count of entries within the DMA descriptor chain of EP. 127 * @next_desc: index of next free descriptor in the ISOC chain under SW control. 128 * @compl_desc: index of next descriptor to be completed by xFerComplete 129 * @total_data: The total number of data bytes done. 130 * @fifo_size: The size of the FIFO (for periodic IN endpoints) 131 * @fifo_index: For Dedicated FIFO operation, only FIFO0 can be used for EP0. 132 * @fifo_load: The amount of data loaded into the FIFO (periodic IN) 133 * @last_load: The offset of data for the last start of request. 134 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN 135 * @target_frame: Targeted frame num to setup next ISOC transfer 136 * @frame_overrun: Indicates SOF number overrun in DSTS 137 * 138 * This is the driver's state for each registered endpoint, allowing it 139 * to keep track of transactions that need doing. Each endpoint has a 140 * lock to protect the state, to try and avoid using an overall lock 141 * for the host controller as much as possible. 142 * 143 * For periodic IN endpoints, we have fifo_size and fifo_load to try 144 * and keep track of the amount of data in the periodic FIFO for each 145 * of these as we don't have a status register that tells us how much 146 * is in each of them. (note, this may actually be useless information 147 * as in shared-fifo mode periodic in acts like a single-frame packet 148 * buffer than a fifo) 149 */ 150 struct dwc2_hsotg_ep { 151 struct usb_ep ep; 152 struct list_head queue; 153 struct dwc2_hsotg *parent; 154 struct dwc2_hsotg_req *req; 155 struct dentry *debugfs; 156 157 unsigned long total_data; 158 unsigned int size_loaded; 159 unsigned int last_load; 160 unsigned int fifo_load; 161 unsigned short fifo_size; 162 unsigned short fifo_index; 163 164 unsigned char dir_in; 165 unsigned char index; 166 unsigned char mc; 167 u16 interval; 168 169 unsigned int halted:1; 170 unsigned int periodic:1; 171 unsigned int isochronous:1; 172 unsigned int send_zlp:1; 173 unsigned int target_frame; 174 #define TARGET_FRAME_INITIAL 0xFFFFFFFF 175 bool frame_overrun; 176 177 dma_addr_t desc_list_dma; 178 struct dwc2_dma_desc *desc_list; 179 u8 desc_count; 180 181 unsigned int next_desc; 182 unsigned int compl_desc; 183 184 char name[10]; 185 }; 186 187 /** 188 * struct dwc2_hsotg_req - data transfer request 189 * @req: The USB gadget request 190 * @queue: The list of requests for the endpoint this is queued for. 191 * @saved_req_buf: variable to save req.buf when bounce buffers are used. 192 */ 193 struct dwc2_hsotg_req { 194 struct usb_request req; 195 struct list_head queue; 196 void *saved_req_buf; 197 }; 198 199 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 200 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 201 #define call_gadget(_hs, _entry) \ 202 do { \ 203 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ 204 (_hs)->driver && (_hs)->driver->_entry) { \ 205 spin_unlock(&_hs->lock); \ 206 (_hs)->driver->_entry(&(_hs)->gadget); \ 207 spin_lock(&_hs->lock); \ 208 } \ 209 } while (0) 210 #else 211 #define call_gadget(_hs, _entry) do {} while (0) 212 #endif 213 214 struct dwc2_hsotg; 215 struct dwc2_host_chan; 216 217 /* Device States */ 218 enum dwc2_lx_state { 219 DWC2_L0, /* On state */ 220 DWC2_L1, /* LPM sleep state */ 221 DWC2_L2, /* USB suspend state */ 222 DWC2_L3, /* Off state */ 223 }; 224 225 /* Gadget ep0 states */ 226 enum dwc2_ep0_state { 227 DWC2_EP0_SETUP, 228 DWC2_EP0_DATA_IN, 229 DWC2_EP0_DATA_OUT, 230 DWC2_EP0_STATUS_IN, 231 DWC2_EP0_STATUS_OUT, 232 }; 233 234 /** 235 * struct dwc2_core_params - Parameters for configuring the core 236 * 237 * @otg_cap: Specifies the OTG capabilities. 238 * 0 - HNP and SRP capable 239 * 1 - SRP Only capable 240 * 2 - No HNP/SRP capable (always available) 241 * Defaults to best available option (0, 1, then 2) 242 * @host_dma: Specifies whether to use slave or DMA mode for accessing 243 * the data FIFOs. The driver will automatically detect the 244 * value for this parameter if none is specified. 245 * 0 - Slave (always available) 246 * 1 - DMA (default, if available) 247 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 248 * address DMA mode or descriptor DMA mode for accessing 249 * the data FIFOs. The driver will automatically detect the 250 * value for this if none is specified. 251 * 0 - Address DMA 252 * 1 - Descriptor DMA (default, if available) 253 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use 254 * address DMA mode or descriptor DMA mode for accessing 255 * the data FIFOs in Full Speed mode only. The driver 256 * will automatically detect the value for this if none is 257 * specified. 258 * 0 - Address DMA 259 * 1 - Descriptor DMA in FS (default, if available) 260 * @speed: Specifies the maximum speed of operation in host and 261 * device mode. The actual speed depends on the speed of 262 * the attached device and the value of phy_type. 263 * 0 - High Speed 264 * (default when phy_type is UTMI+ or ULPI) 265 * 1 - Full Speed 266 * (default when phy_type is Full Speed) 267 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 268 * 1 - Allow dynamic FIFO sizing (default, if available) 269 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 270 * are enabled for non-periodic IN endpoints in device 271 * mode. 272 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 273 * dynamic FIFO sizing is enabled 274 * 16 to 32768 275 * Actual maximum value is autodetected and also 276 * the default. 277 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 278 * in host mode when dynamic FIFO sizing is enabled 279 * 16 to 32768 280 * Actual maximum value is autodetected and also 281 * the default. 282 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 283 * host mode when dynamic FIFO sizing is enabled 284 * 16 to 32768 285 * Actual maximum value is autodetected and also 286 * the default. 287 * @max_transfer_size: The maximum transfer size supported, in bytes 288 * 2047 to 65,535 289 * Actual maximum value is autodetected and also 290 * the default. 291 * @max_packet_count: The maximum number of packets in a transfer 292 * 15 to 511 293 * Actual maximum value is autodetected and also 294 * the default. 295 * @host_channels: The number of host channel registers to use 296 * 1 to 16 297 * Actual maximum value is autodetected and also 298 * the default. 299 * @phy_type: Specifies the type of PHY interface to use. By default, 300 * the driver will automatically detect the phy_type. 301 * 0 - Full Speed Phy 302 * 1 - UTMI+ Phy 303 * 2 - ULPI Phy 304 * Defaults to best available option (2, 1, then 0) 305 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 306 * is applicable for a phy_type of UTMI+ or ULPI. (For a 307 * ULPI phy_type, this parameter indicates the data width 308 * between the MAC and the ULPI Wrapper.) Also, this 309 * parameter is applicable only if the OTG_HSPHY_WIDTH cC 310 * parameter was set to "8 and 16 bits", meaning that the 311 * core has been configured to work at either data path 312 * width. 313 * 8 or 16 (default 16 if available) 314 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 315 * data rate. This parameter is only applicable if phy_type 316 * is ULPI. 317 * 0 - single data rate ULPI interface with 8 bit wide 318 * data bus (default) 319 * 1 - double data rate ULPI interface with 4 bit wide 320 * data bus 321 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 322 * external supply to drive the VBus 323 * 0 - Internal supply (default) 324 * 1 - External supply 325 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 326 * speed PHY. This parameter is only applicable if phy_type 327 * is FS. 328 * 0 - No (default) 329 * 1 - Yes 330 * @ipg_isoc_en: Indicates the IPG supports is enabled or disabled. 331 * 0 - Disable (default) 332 * 1 - Enable 333 * @acg_enable: For enabling Active Clock Gating in the controller 334 * 0 - No 335 * 1 - Yes 336 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 337 * 0 - No (default) 338 * 1 - Yes 339 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 340 * when attached to a Full Speed or Low Speed device in 341 * host mode. 342 * 0 - Don't support low power mode (default) 343 * 1 - Support low power mode 344 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 345 * when connected to a Low Speed device in host 346 * mode. This parameter is applicable only if 347 * host_support_fs_ls_low_power is enabled. 348 * 0 - 48 MHz 349 * (default when phy_type is UTMI+ or ULPI) 350 * 1 - 6 MHz 351 * (default when phy_type is Full Speed) 352 * @oc_disable: Flag to disable overcurrent condition. 353 * 0 - Allow overcurrent condition to get detected 354 * 1 - Disable overcurrent condtion to get detected 355 * @ts_dline: Enable Term Select Dline pulsing 356 * 0 - No (default) 357 * 1 - Yes 358 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 359 * 0 - No (default for core < 2.92a) 360 * 1 - Yes (default for core >= 2.92a) 361 * @ahbcfg: This field allows the default value of the GAHBCFG 362 * register to be overridden 363 * -1 - GAHBCFG value will be set to 0x06 364 * (INCR, default) 365 * all others - GAHBCFG value will be overridden with 366 * this value 367 * Not all bits can be controlled like this, the 368 * bits defined by GAHBCFG_CTRL_MASK are controlled 369 * by the driver and are ignored in this 370 * configuration value. 371 * @uframe_sched: True to enable the microframe scheduler 372 * @external_id_pin_ctl: Specifies whether ID pin is handled externally. 373 * Disable CONIDSTSCHNG controller interrupt in such 374 * case. 375 * 0 - No (default) 376 * 1 - Yes 377 * @power_down: Specifies whether the controller support power_down. 378 * If power_down is enabled, the controller will enter 379 * power_down in both peripheral and host mode when 380 * needed. 381 * 0 - No (default) 382 * 1 - Partial power down 383 * 2 - Hibernation 384 * @lpm: Enable LPM support. 385 * 0 - No 386 * 1 - Yes 387 * @lpm_clock_gating: Enable core PHY clock gating. 388 * 0 - No 389 * 1 - Yes 390 * @besl: Enable LPM Errata support. 391 * 0 - No 392 * 1 - Yes 393 * @hird_threshold_en: HIRD or HIRD Threshold enable. 394 * 0 - No 395 * 1 - Yes 396 * @hird_threshold: Value of BESL or HIRD Threshold. 397 * @ref_clk_per: Indicates in terms of pico seconds the period 398 * of ref_clk. 399 * 62500 - 16MHz 400 * 58823 - 17MHz 401 * 52083 - 19.2MHz 402 * 50000 - 20MHz 403 * 41666 - 24MHz 404 * 33333 - 30MHz (default) 405 * 25000 - 40MHz 406 * @sof_cnt_wkup_alert: Indicates in term of number of SOF's after which 407 * the controller should generate an interrupt if the 408 * device had been in L1 state until that period. 409 * This is used by SW to initiate Remote WakeUp in the 410 * controller so as to sync to the uF number from the host. 411 * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO 412 * register. 413 * 0 - Deactivate the transceiver (default) 414 * 1 - Activate the transceiver 415 * @activate_stm_id_vb_detection: Activate external ID pin and Vbus level 416 * detection using GGPIO register. 417 * 0 - Deactivate the external level detection (default) 418 * 1 - Activate the external level detection 419 * @g_dma: Enables gadget dma usage (default: autodetect). 420 * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect). 421 * @g_rx_fifo_size: The periodic rx fifo size for the device, in 422 * DWORDS from 16-32768 (default: 2048 if 423 * possible, otherwise autodetect). 424 * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in 425 * DWORDS from 16-32768 (default: 1024 if 426 * possible, otherwise autodetect). 427 * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo 428 * mode. Each value corresponds to one EP 429 * starting from EP1 (max 15 values). Sizes are 430 * in DWORDS with possible values from 431 * 16-32768 (default: 256, 256, 256, 256, 768, 432 * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0). 433 * @change_speed_quirk: Change speed configuration to DWC2_SPEED_PARAM_FULL 434 * while full&low speed device connect. And change speed 435 * back to DWC2_SPEED_PARAM_HIGH while device is gone. 436 * 0 - No (default) 437 * 1 - Yes 438 * @service_interval: Enable service interval based scheduling. 439 * 0 - No 440 * 1 - Yes 441 * 442 * The following parameters may be specified when starting the module. These 443 * parameters define how the DWC_otg controller should be configured. A 444 * value of -1 (or any other out of range value) for any parameter means 445 * to read the value from hardware (if possible) or use the builtin 446 * default described above. 447 */ 448 struct dwc2_core_params { 449 u8 otg_cap; 450 #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 451 #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 452 #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 453 454 u8 phy_type; 455 #define DWC2_PHY_TYPE_PARAM_FS 0 456 #define DWC2_PHY_TYPE_PARAM_UTMI 1 457 #define DWC2_PHY_TYPE_PARAM_ULPI 2 458 459 u8 speed; 460 #define DWC2_SPEED_PARAM_HIGH 0 461 #define DWC2_SPEED_PARAM_FULL 1 462 #define DWC2_SPEED_PARAM_LOW 2 463 464 u8 phy_utmi_width; 465 bool phy_ulpi_ddr; 466 bool phy_ulpi_ext_vbus; 467 bool enable_dynamic_fifo; 468 bool en_multiple_tx_fifo; 469 bool i2c_enable; 470 bool acg_enable; 471 bool ulpi_fs_ls; 472 bool ts_dline; 473 bool reload_ctl; 474 bool uframe_sched; 475 bool external_id_pin_ctl; 476 477 int power_down; 478 #define DWC2_POWER_DOWN_PARAM_NONE 0 479 #define DWC2_POWER_DOWN_PARAM_PARTIAL 1 480 #define DWC2_POWER_DOWN_PARAM_HIBERNATION 2 481 482 bool lpm; 483 bool lpm_clock_gating; 484 bool besl; 485 bool hird_threshold_en; 486 bool service_interval; 487 u8 hird_threshold; 488 bool activate_stm_fs_transceiver; 489 bool activate_stm_id_vb_detection; 490 bool ipg_isoc_en; 491 u16 max_packet_count; 492 u32 max_transfer_size; 493 u32 ahbcfg; 494 495 /* GREFCLK parameters */ 496 u32 ref_clk_per; 497 u16 sof_cnt_wkup_alert; 498 499 /* Host parameters */ 500 bool host_dma; 501 bool dma_desc_enable; 502 bool dma_desc_fs_enable; 503 bool host_support_fs_ls_low_power; 504 bool host_ls_low_power_phy_clk; 505 bool oc_disable; 506 507 u8 host_channels; 508 u16 host_rx_fifo_size; 509 u16 host_nperio_tx_fifo_size; 510 u16 host_perio_tx_fifo_size; 511 512 /* Gadget parameters */ 513 bool g_dma; 514 bool g_dma_desc; 515 u32 g_rx_fifo_size; 516 u32 g_np_tx_fifo_size; 517 u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; 518 519 bool change_speed_quirk; 520 }; 521 522 /** 523 * struct dwc2_hw_params - Autodetected parameters. 524 * 525 * These parameters are the various parameters read from hardware 526 * registers during initialization. They typically contain the best 527 * supported or maximum value that can be configured in the 528 * corresponding dwc2_core_params value. 529 * 530 * The values that are not in dwc2_core_params are documented below. 531 * 532 * @op_mode: Mode of Operation 533 * 0 - HNP- and SRP-Capable OTG (Host & Device) 534 * 1 - SRP-Capable OTG (Host & Device) 535 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 536 * 3 - SRP-Capable Device 537 * 4 - Non-OTG Device 538 * 5 - SRP-Capable Host 539 * 6 - Non-OTG Host 540 * @arch: Architecture 541 * 0 - Slave only 542 * 1 - External DMA 543 * 2 - Internal DMA 544 * @ipg_isoc_en: This feature indicates that the controller supports 545 * the worst-case scenario of Rx followed by Rx 546 * Interpacket Gap (IPG) (32 bitTimes) as per the utmi 547 * specification for any token following ISOC OUT token. 548 * 0 - Don't support 549 * 1 - Support 550 * @power_optimized: Are power optimizations enabled? 551 * @num_dev_ep: Number of device endpoints available 552 * @num_dev_in_eps: Number of device IN endpoints available 553 * @num_dev_perio_in_ep: Number of device periodic IN endpoints 554 * available 555 * @dev_token_q_depth: Device Mode IN Token Sequence Learning Queue 556 * Depth 557 * 0 to 30 558 * @host_perio_tx_q_depth: 559 * Host Mode Periodic Request Queue Depth 560 * 2, 4 or 8 561 * @nperio_tx_q_depth: 562 * Non-Periodic Request Queue Depth 563 * 2, 4 or 8 564 * @hs_phy_type: High-speed PHY interface type 565 * 0 - High-speed interface not supported 566 * 1 - UTMI+ 567 * 2 - ULPI 568 * 3 - UTMI+ and ULPI 569 * @fs_phy_type: Full-speed PHY interface type 570 * 0 - Full speed interface not supported 571 * 1 - Dedicated full speed interface 572 * 2 - FS pins shared with UTMI+ pins 573 * 3 - FS pins shared with ULPI pins 574 * @total_fifo_size: Total internal RAM for FIFOs (bytes) 575 * @hibernation: Is hibernation enabled? 576 * @utmi_phy_data_width: UTMI+ PHY data width 577 * 0 - 8 bits 578 * 1 - 16 bits 579 * 2 - 8 or 16 bits 580 * @snpsid: Value from SNPSID register 581 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1) 582 * @g_tx_fifo_size: Power-on values of TxFIFO sizes 583 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 584 * address DMA mode or descriptor DMA mode for accessing 585 * the data FIFOs. The driver will automatically detect the 586 * value for this if none is specified. 587 * 0 - Address DMA 588 * 1 - Descriptor DMA (default, if available) 589 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 590 * 1 - Allow dynamic FIFO sizing (default, if available) 591 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 592 * are enabled for non-periodic IN endpoints in device 593 * mode. 594 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 595 * in host mode when dynamic FIFO sizing is enabled 596 * 16 to 32768 597 * Actual maximum value is autodetected and also 598 * the default. 599 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 600 * host mode when dynamic FIFO sizing is enabled 601 * 16 to 32768 602 * Actual maximum value is autodetected and also 603 * the default. 604 * @max_transfer_size: The maximum transfer size supported, in bytes 605 * 2047 to 65,535 606 * Actual maximum value is autodetected and also 607 * the default. 608 * @max_packet_count: The maximum number of packets in a transfer 609 * 15 to 511 610 * Actual maximum value is autodetected and also 611 * the default. 612 * @host_channels: The number of host channel registers to use 613 * 1 to 16 614 * Actual maximum value is autodetected and also 615 * the default. 616 * @dev_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 617 * in device mode when dynamic FIFO sizing is enabled 618 * 16 to 32768 619 * Actual maximum value is autodetected and also 620 * the default. 621 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 622 * speed PHY. This parameter is only applicable if phy_type 623 * is FS. 624 * 0 - No (default) 625 * 1 - Yes 626 * @acg_enable: For enabling Active Clock Gating in the controller 627 * 0 - Disable 628 * 1 - Enable 629 * @lpm_mode: For enabling Link Power Management in the controller 630 * 0 - Disable 631 * 1 - Enable 632 * @rx_fifo_size: Number of 4-byte words in the Rx FIFO when dynamic 633 * FIFO sizing is enabled 16 to 32768 634 * Actual maximum value is autodetected and also 635 * the default. 636 * @service_interval_mode: For enabling service interval based scheduling in the 637 * controller. 638 * 0 - Disable 639 * 1 - Enable 640 */ 641 struct dwc2_hw_params { 642 unsigned op_mode:3; 643 unsigned arch:2; 644 unsigned dma_desc_enable:1; 645 unsigned enable_dynamic_fifo:1; 646 unsigned en_multiple_tx_fifo:1; 647 unsigned rx_fifo_size:16; 648 unsigned host_nperio_tx_fifo_size:16; 649 unsigned dev_nperio_tx_fifo_size:16; 650 unsigned host_perio_tx_fifo_size:16; 651 unsigned nperio_tx_q_depth:3; 652 unsigned host_perio_tx_q_depth:3; 653 unsigned dev_token_q_depth:5; 654 unsigned max_transfer_size:26; 655 unsigned max_packet_count:11; 656 unsigned host_channels:5; 657 unsigned hs_phy_type:2; 658 unsigned fs_phy_type:2; 659 unsigned i2c_enable:1; 660 unsigned acg_enable:1; 661 unsigned num_dev_ep:4; 662 unsigned num_dev_in_eps : 4; 663 unsigned num_dev_perio_in_ep:4; 664 unsigned total_fifo_size:16; 665 unsigned power_optimized:1; 666 unsigned hibernation:1; 667 unsigned utmi_phy_data_width:2; 668 unsigned lpm_mode:1; 669 unsigned ipg_isoc_en:1; 670 unsigned service_interval_mode:1; 671 u32 snpsid; 672 u32 dev_ep_dirs; 673 u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; 674 }; 675 676 /* Size of control and EP0 buffers */ 677 #define DWC2_CTRL_BUFF_SIZE 8 678 679 /** 680 * struct dwc2_gregs_backup - Holds global registers state before 681 * entering partial power down 682 * @gotgctl: Backup of GOTGCTL register 683 * @gintmsk: Backup of GINTMSK register 684 * @gahbcfg: Backup of GAHBCFG register 685 * @gusbcfg: Backup of GUSBCFG register 686 * @grxfsiz: Backup of GRXFSIZ register 687 * @gnptxfsiz: Backup of GNPTXFSIZ register 688 * @gi2cctl: Backup of GI2CCTL register 689 * @glpmcfg: Backup of GLPMCFG register 690 * @gdfifocfg: Backup of GDFIFOCFG register 691 * @pcgcctl: Backup of PCGCCTL register 692 * @pcgcctl1: Backup of PCGCCTL1 register 693 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 694 * @gpwrdn: Backup of GPWRDN register 695 * @valid: True if registers values backuped. 696 */ 697 struct dwc2_gregs_backup { 698 u32 gotgctl; 699 u32 gintmsk; 700 u32 gahbcfg; 701 u32 gusbcfg; 702 u32 grxfsiz; 703 u32 gnptxfsiz; 704 u32 gi2cctl; 705 u32 glpmcfg; 706 u32 pcgcctl; 707 u32 pcgcctl1; 708 u32 gdfifocfg; 709 u32 gpwrdn; 710 bool valid; 711 }; 712 713 /** 714 * struct dwc2_dregs_backup - Holds device registers state before 715 * entering partial power down 716 * @dcfg: Backup of DCFG register 717 * @dctl: Backup of DCTL register 718 * @daintmsk: Backup of DAINTMSK register 719 * @diepmsk: Backup of DIEPMSK register 720 * @doepmsk: Backup of DOEPMSK register 721 * @diepctl: Backup of DIEPCTL register 722 * @dieptsiz: Backup of DIEPTSIZ register 723 * @diepdma: Backup of DIEPDMA register 724 * @doepctl: Backup of DOEPCTL register 725 * @doeptsiz: Backup of DOEPTSIZ register 726 * @doepdma: Backup of DOEPDMA register 727 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 728 * @valid: True if registers values backuped. 729 */ 730 struct dwc2_dregs_backup { 731 u32 dcfg; 732 u32 dctl; 733 u32 daintmsk; 734 u32 diepmsk; 735 u32 doepmsk; 736 u32 diepctl[MAX_EPS_CHANNELS]; 737 u32 dieptsiz[MAX_EPS_CHANNELS]; 738 u32 diepdma[MAX_EPS_CHANNELS]; 739 u32 doepctl[MAX_EPS_CHANNELS]; 740 u32 doeptsiz[MAX_EPS_CHANNELS]; 741 u32 doepdma[MAX_EPS_CHANNELS]; 742 u32 dtxfsiz[MAX_EPS_CHANNELS]; 743 bool valid; 744 }; 745 746 /** 747 * struct dwc2_hregs_backup - Holds host registers state before 748 * entering partial power down 749 * @hcfg: Backup of HCFG register 750 * @haintmsk: Backup of HAINTMSK register 751 * @hcintmsk: Backup of HCINTMSK register 752 * @hprt0: Backup of HPTR0 register 753 * @hfir: Backup of HFIR register 754 * @hptxfsiz: Backup of HPTXFSIZ register 755 * @valid: True if registers values backuped. 756 */ 757 struct dwc2_hregs_backup { 758 u32 hcfg; 759 u32 haintmsk; 760 u32 hcintmsk[MAX_EPS_CHANNELS]; 761 u32 hprt0; 762 u32 hfir; 763 u32 hptxfsiz; 764 bool valid; 765 }; 766 767 /* 768 * Constants related to high speed periodic scheduling 769 * 770 * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a 771 * reservation point of view it's assumed that the schedule goes right back to 772 * the beginning after the end of the schedule. 773 * 774 * What does that mean for scheduling things with a long interval? It means 775 * we'll reserve time for them in every possible microframe that they could 776 * ever be scheduled in. ...but we'll still only actually schedule them as 777 * often as they were requested. 778 * 779 * We keep our schedule in a "bitmap" structure. This simplifies having 780 * to keep track of and merge intervals: we just let the bitmap code do most 781 * of the heavy lifting. In a way scheduling is much like memory allocation. 782 * 783 * We schedule 100us per uframe or 80% of 125us (the maximum amount you're 784 * supposed to schedule for periodic transfers). That's according to spec. 785 * 786 * Note that though we only schedule 80% of each microframe, the bitmap that we 787 * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of 788 * space for each uFrame). 789 * 790 * Requirements: 791 * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1) 792 * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably 793 * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might 794 * be bugs). The 8 comes from the USB spec: number of microframes per frame. 795 */ 796 #define DWC2_US_PER_UFRAME 125 797 #define DWC2_HS_PERIODIC_US_PER_UFRAME 100 798 799 #define DWC2_HS_SCHEDULE_UFRAMES 8 800 #define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \ 801 DWC2_HS_PERIODIC_US_PER_UFRAME) 802 803 /* 804 * Constants related to low speed scheduling 805 * 806 * For high speed we schedule every 1us. For low speed that's a bit overkill, 807 * so we make up a unit called a "slice" that's worth 25us. There are 40 808 * slices in a full frame and we can schedule 36 of those (90%) for periodic 809 * transfers. 810 * 811 * Our low speed schedule can be as short as 1 frame or could be longer. When 812 * we only schedule 1 frame it means that we'll need to reserve a time every 813 * frame even for things that only transfer very rarely, so something that runs 814 * every 2048 frames will get time reserved in every frame. Our low speed 815 * schedule can be longer and we'll be able to handle more overlap, but that 816 * will come at increased memory cost and increased time to schedule. 817 * 818 * Note: one other advantage of a short low speed schedule is that if we mess 819 * up and miss scheduling we can jump in and use any of the slots that we 820 * happened to reserve. 821 * 822 * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for 823 * the schedule. There will be one schedule per TT. 824 * 825 * Requirements: 826 * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME. 827 */ 828 #define DWC2_US_PER_SLICE 25 829 #define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE) 830 831 #define DWC2_ROUND_US_TO_SLICE(us) \ 832 (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \ 833 DWC2_US_PER_SLICE) 834 835 #define DWC2_LS_PERIODIC_US_PER_FRAME \ 836 900 837 #define DWC2_LS_PERIODIC_SLICES_PER_FRAME \ 838 (DWC2_LS_PERIODIC_US_PER_FRAME / \ 839 DWC2_US_PER_SLICE) 840 841 #define DWC2_LS_SCHEDULE_FRAMES 1 842 #define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \ 843 DWC2_LS_PERIODIC_SLICES_PER_FRAME) 844 845 /** 846 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 847 * and periodic schedules 848 * 849 * These are common for both host and peripheral modes: 850 * 851 * @dev: The struct device pointer 852 * @regs: Pointer to controller regs 853 * @hw_params: Parameters that were autodetected from the 854 * hardware registers 855 * @params: Parameters that define how the core should be configured 856 * @op_state: The operational State, during transitions (a_host=> 857 * a_peripheral and b_device=>b_host) this may not match 858 * the core, but allows the software to determine 859 * transitions 860 * @dr_mode: Requested mode of operation, one of following: 861 * - USB_DR_MODE_PERIPHERAL 862 * - USB_DR_MODE_HOST 863 * - USB_DR_MODE_OTG 864 * @role_sw: usb_role_switch handle 865 * @hcd_enabled: Host mode sub-driver initialization indicator. 866 * @gadget_enabled: Peripheral mode sub-driver initialization indicator. 867 * @ll_hw_enabled: Status of low-level hardware resources. 868 * @hibernated: True if core is hibernated 869 * @in_ppd: True if core is partial power down mode. 870 * @bus_suspended: True if bus is suspended 871 * @reset_phy_on_wake: Quirk saying that we should assert PHY reset on a 872 * remote wakeup. 873 * @phy_off_for_suspend: Status of whether we turned the PHY off at suspend. 874 * @need_phy_for_wake: Quirk saying that we should keep the PHY on at 875 * suspend if we need USB to wake us up. 876 * @frame_number: Frame number read from the core. For both device 877 * and host modes. The value ranges are from 0 878 * to HFNUM_MAX_FRNUM. 879 * @phy: The otg phy transceiver structure for phy control. 880 * @uphy: The otg phy transceiver structure for old USB phy 881 * control. 882 * @plat: The platform specific configuration data. This can be 883 * removed once all SoCs support usb transceiver. 884 * @supplies: Definition of USB power supplies 885 * @vbus_supply: Regulator supplying vbus. 886 * @usb33d: Optional 3.3v regulator used on some stm32 devices to 887 * supply ID and VBUS detection hardware. 888 * @lock: Spinlock that protects all the driver data structures 889 * @priv: Stores a pointer to the struct usb_hcd 890 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 891 * transfer are in process of being queued 892 * @srp_success: Stores status of SRP request in the case of a FS PHY 893 * with an I2C interface 894 * @wq_otg: Workqueue object used for handling of some interrupts 895 * @wf_otg: Work object for handling Connector ID Status Change 896 * interrupt 897 * @wkp_timer: Timer object for handling Wakeup Detected interrupt 898 * @lx_state: Lx state of connected device 899 * @gr_backup: Backup of global registers during suspend 900 * @dr_backup: Backup of device registers during suspend 901 * @hr_backup: Backup of host registers during suspend 902 * @needs_byte_swap: Specifies whether the opposite endianness. 903 * 904 * These are for host mode: 905 * 906 * @flags: Flags for handling root port state changes 907 * @flags.d32: Contain all root port flags 908 * @flags.b: Separate root port flags from each other 909 * @flags.b.port_connect_status_change: True if root port connect status 910 * changed 911 * @flags.b.port_connect_status: True if device connected to root port 912 * @flags.b.port_reset_change: True if root port reset status changed 913 * @flags.b.port_enable_change: True if root port enable status changed 914 * @flags.b.port_suspend_change: True if root port suspend status changed 915 * @flags.b.port_over_current_change: True if root port over current state 916 * changed. 917 * @flags.b.port_l1_change: True if root port l1 status changed 918 * @flags.b.reserved: Reserved bits of root port register 919 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 920 * Transfers associated with these QHs are not currently 921 * assigned to a host channel. 922 * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 923 * Transfers associated with these QHs are currently 924 * assigned to a host channel. 925 * @non_periodic_qh_ptr: Pointer to next QH to process in the active 926 * non-periodic schedule 927 * @non_periodic_sched_waiting: Waiting QHs in the non-periodic schedule. 928 * Transfers associated with these QHs are not currently 929 * assigned to a host channel. 930 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 931 * list of QHs for periodic transfers that are _not_ 932 * scheduled for the next frame. Each QH in the list has an 933 * interval counter that determines when it needs to be 934 * scheduled for execution. This scheduling mechanism 935 * allows only a simple calculation for periodic bandwidth 936 * used (i.e. must assume that all periodic transfers may 937 * need to execute in the same frame). However, it greatly 938 * simplifies scheduling and should be sufficient for the 939 * vast majority of OTG hosts, which need to connect to a 940 * small number of peripherals at one time. Items move from 941 * this list to periodic_sched_ready when the QH interval 942 * counter is 0 at SOF. 943 * @periodic_sched_ready: List of periodic QHs that are ready for execution in 944 * the next frame, but have not yet been assigned to host 945 * channels. Items move from this list to 946 * periodic_sched_assigned as host channels become 947 * available during the current frame. 948 * @periodic_sched_assigned: List of periodic QHs to be executed in the next 949 * frame that are assigned to host channels. Items move 950 * from this list to periodic_sched_queued as the 951 * transactions for the QH are queued to the DWC_otg 952 * controller. 953 * @periodic_sched_queued: List of periodic QHs that have been queued for 954 * execution. Items move from this list to either 955 * periodic_sched_inactive or periodic_sched_ready when the 956 * channel associated with the transfer is released. If the 957 * interval for the QH is 1, the item moves to 958 * periodic_sched_ready because it must be rescheduled for 959 * the next frame. Otherwise, the item moves to 960 * periodic_sched_inactive. 961 * @split_order: List keeping track of channels doing splits, in order. 962 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 963 * This value is in microseconds per (micro)frame. The 964 * assumption is that all periodic transfers may occur in 965 * the same (micro)frame. 966 * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the 967 * host is in high speed mode; low speed schedules are 968 * stored elsewhere since we need one per TT. 969 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 970 * SOF enable/disable. 971 * @free_hc_list: Free host channels in the controller. This is a list of 972 * struct dwc2_host_chan items. 973 * @periodic_channels: Number of host channels assigned to periodic transfers. 974 * Currently assuming that there is a dedicated host 975 * channel for each periodic transaction and at least one 976 * host channel is available for non-periodic transactions. 977 * @non_periodic_channels: Number of host channels assigned to non-periodic 978 * transfers 979 * @available_host_channels: Number of host channels available for the 980 * microframe scheduler to use 981 * @hc_ptr_array: Array of pointers to the host channel descriptors. 982 * Allows accessing a host channel descriptor given the 983 * host channel number. This is useful in interrupt 984 * handlers. 985 * @status_buf: Buffer used for data received during the status phase of 986 * a control transfer. 987 * @status_buf_dma: DMA address for status_buf 988 * @start_work: Delayed work for handling host A-cable connection 989 * @reset_work: Delayed work for handling a port reset 990 * @phy_reset_work: Work structure for doing a PHY reset 991 * @otg_port: OTG port number 992 * @frame_list: Frame list 993 * @frame_list_dma: Frame list DMA address 994 * @frame_list_sz: Frame list size 995 * @desc_gen_cache: Kmem cache for generic descriptors 996 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors 997 * @unaligned_cache: Kmem cache for DMA mode to handle non-aligned buf 998 * 999 * These are for peripheral mode: 1000 * 1001 * @driver: USB gadget driver 1002 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 1003 * @num_of_eps: Number of available EPs (excluding EP0) 1004 * @debug_root: Root directrory for debugfs. 1005 * @ep0_reply: Request used for ep0 reply. 1006 * @ep0_buff: Buffer for EP0 reply data, if needed. 1007 * @ctrl_buff: Buffer for EP0 control requests. 1008 * @ctrl_req: Request for EP0 control packets. 1009 * @ep0_state: EP0 control transfers state 1010 * @delayed_status: true when gadget driver asks for delayed status 1011 * @test_mode: USB test mode requested by the host 1012 * @remote_wakeup_allowed: True if device is allowed to wake-up host by 1013 * remote-wakeup signalling 1014 * @setup_desc_dma: EP0 setup stage desc chain DMA address 1015 * @setup_desc: EP0 setup stage desc chain pointer 1016 * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address 1017 * @ctrl_in_desc: EP0 IN data phase desc chain pointer 1018 * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address 1019 * @ctrl_out_desc: EP0 OUT data phase desc chain pointer 1020 * @irq: Interrupt request line number 1021 * @clk: Pointer to otg clock 1022 * @reset: Pointer to dwc2 reset controller 1023 * @reset_ecc: Pointer to dwc2 optional reset controller in Stratix10. 1024 * @regset: A pointer to a struct debugfs_regset32, which contains 1025 * a pointer to an array of register definitions, the 1026 * array size and the base address where the register bank 1027 * is to be found. 1028 * @last_frame_num: Number of last frame. Range from 0 to 32768 1029 * @frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is 1030 * defined, for missed SOFs tracking. Array holds that 1031 * frame numbers, which not equal to last_frame_num +1 1032 * @last_frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is 1033 * defined, for missed SOFs tracking. 1034 * If current_frame_number != last_frame_num+1 1035 * then last_frame_num added to this array 1036 * @frame_num_idx: Actual size of frame_num_array and last_frame_num_array 1037 * @dumped_frame_num_array: 1 - if missed SOFs frame numbers dumbed 1038 * 0 - if missed SOFs frame numbers not dumbed 1039 * @fifo_mem: Total internal RAM for FIFOs (bytes) 1040 * @fifo_map: Each bit intend for concrete fifo. If that bit is set, 1041 * then that fifo is used 1042 * @gadget: Represents a usb gadget device 1043 * @connected: Used in slave mode. True if device connected with host 1044 * @eps_in: The IN endpoints being supplied to the gadget framework 1045 * @eps_out: The OUT endpoints being supplied to the gadget framework 1046 * @new_connection: Used in host mode. True if there are new connected 1047 * device 1048 * @enabled: Indicates the enabling state of controller 1049 * 1050 */ 1051 struct dwc2_hsotg { 1052 struct device *dev; 1053 void __iomem *regs; 1054 /** Params detected from hardware */ 1055 struct dwc2_hw_params hw_params; 1056 /** Params to actually use */ 1057 struct dwc2_core_params params; 1058 enum usb_otg_state op_state; 1059 enum usb_dr_mode dr_mode; 1060 struct usb_role_switch *role_sw; 1061 unsigned int hcd_enabled:1; 1062 unsigned int gadget_enabled:1; 1063 unsigned int ll_hw_enabled:1; 1064 unsigned int hibernated:1; 1065 unsigned int in_ppd:1; 1066 bool bus_suspended; 1067 unsigned int reset_phy_on_wake:1; 1068 unsigned int need_phy_for_wake:1; 1069 unsigned int phy_off_for_suspend:1; 1070 u16 frame_number; 1071 1072 struct phy *phy; 1073 struct usb_phy *uphy; 1074 struct dwc2_hsotg_plat *plat; 1075 struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES]; 1076 struct regulator *vbus_supply; 1077 struct regulator *usb33d; 1078 1079 spinlock_t lock; 1080 void *priv; 1081 int irq; 1082 struct clk *clk; 1083 struct reset_control *reset; 1084 struct reset_control *reset_ecc; 1085 1086 unsigned int queuing_high_bandwidth:1; 1087 unsigned int srp_success:1; 1088 1089 struct workqueue_struct *wq_otg; 1090 struct work_struct wf_otg; 1091 struct timer_list wkp_timer; 1092 enum dwc2_lx_state lx_state; 1093 struct dwc2_gregs_backup gr_backup; 1094 struct dwc2_dregs_backup dr_backup; 1095 struct dwc2_hregs_backup hr_backup; 1096 1097 struct dentry *debug_root; 1098 struct debugfs_regset32 *regset; 1099 bool needs_byte_swap; 1100 1101 /* DWC OTG HW Release versions */ 1102 #define DWC2_CORE_REV_2_71a 0x4f54271a 1103 #define DWC2_CORE_REV_2_72a 0x4f54272a 1104 #define DWC2_CORE_REV_2_80a 0x4f54280a 1105 #define DWC2_CORE_REV_2_90a 0x4f54290a 1106 #define DWC2_CORE_REV_2_91a 0x4f54291a 1107 #define DWC2_CORE_REV_2_92a 0x4f54292a 1108 #define DWC2_CORE_REV_2_94a 0x4f54294a 1109 #define DWC2_CORE_REV_3_00a 0x4f54300a 1110 #define DWC2_CORE_REV_3_10a 0x4f54310a 1111 #define DWC2_CORE_REV_4_00a 0x4f54400a 1112 #define DWC2_CORE_REV_4_20a 0x4f54420a 1113 #define DWC2_FS_IOT_REV_1_00a 0x5531100a 1114 #define DWC2_HS_IOT_REV_1_00a 0x5532100a 1115 #define DWC2_CORE_REV_MASK 0x0000ffff 1116 1117 /* DWC OTG HW Core ID */ 1118 #define DWC2_OTG_ID 0x4f540000 1119 #define DWC2_FS_IOT_ID 0x55310000 1120 #define DWC2_HS_IOT_ID 0x55320000 1121 1122 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1123 union dwc2_hcd_internal_flags { 1124 u32 d32; 1125 struct { 1126 unsigned port_connect_status_change:1; 1127 unsigned port_connect_status:1; 1128 unsigned port_reset_change:1; 1129 unsigned port_enable_change:1; 1130 unsigned port_suspend_change:1; 1131 unsigned port_over_current_change:1; 1132 unsigned port_l1_change:1; 1133 unsigned reserved:25; 1134 } b; 1135 } flags; 1136 1137 struct list_head non_periodic_sched_inactive; 1138 struct list_head non_periodic_sched_waiting; 1139 struct list_head non_periodic_sched_active; 1140 struct list_head *non_periodic_qh_ptr; 1141 struct list_head periodic_sched_inactive; 1142 struct list_head periodic_sched_ready; 1143 struct list_head periodic_sched_assigned; 1144 struct list_head periodic_sched_queued; 1145 struct list_head split_order; 1146 u16 periodic_usecs; 1147 unsigned long hs_periodic_bitmap[ 1148 DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)]; 1149 u16 periodic_qh_count; 1150 bool new_connection; 1151 1152 u16 last_frame_num; 1153 1154 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 1155 #define FRAME_NUM_ARRAY_SIZE 1000 1156 u16 *frame_num_array; 1157 u16 *last_frame_num_array; 1158 int frame_num_idx; 1159 int dumped_frame_num_array; 1160 #endif 1161 1162 struct list_head free_hc_list; 1163 int periodic_channels; 1164 int non_periodic_channels; 1165 int available_host_channels; 1166 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 1167 u8 *status_buf; 1168 dma_addr_t status_buf_dma; 1169 #define DWC2_HCD_STATUS_BUF_SIZE 64 1170 1171 struct delayed_work start_work; 1172 struct delayed_work reset_work; 1173 struct work_struct phy_reset_work; 1174 u8 otg_port; 1175 u32 *frame_list; 1176 dma_addr_t frame_list_dma; 1177 u32 frame_list_sz; 1178 struct kmem_cache *desc_gen_cache; 1179 struct kmem_cache *desc_hsisoc_cache; 1180 struct kmem_cache *unaligned_cache; 1181 #define DWC2_KMEM_UNALIGNED_BUF_SIZE 1024 1182 1183 #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ 1184 1185 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1186 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1187 /* Gadget structures */ 1188 struct usb_gadget_driver *driver; 1189 int fifo_mem; 1190 unsigned int dedicated_fifos:1; 1191 unsigned char num_of_eps; 1192 u32 fifo_map; 1193 1194 struct usb_request *ep0_reply; 1195 struct usb_request *ctrl_req; 1196 void *ep0_buff; 1197 void *ctrl_buff; 1198 enum dwc2_ep0_state ep0_state; 1199 unsigned delayed_status : 1; 1200 u8 test_mode; 1201 1202 dma_addr_t setup_desc_dma[2]; 1203 struct dwc2_dma_desc *setup_desc[2]; 1204 dma_addr_t ctrl_in_desc_dma; 1205 struct dwc2_dma_desc *ctrl_in_desc; 1206 dma_addr_t ctrl_out_desc_dma; 1207 struct dwc2_dma_desc *ctrl_out_desc; 1208 1209 struct usb_gadget gadget; 1210 unsigned int enabled:1; 1211 unsigned int connected:1; 1212 unsigned int remote_wakeup_allowed:1; 1213 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS]; 1214 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS]; 1215 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 1216 }; 1217 1218 /* Normal architectures just use readl/write */ 1219 static inline u32 dwc2_readl(struct dwc2_hsotg *hsotg, u32 offset) 1220 { 1221 u32 val; 1222 1223 val = readl(hsotg->regs + offset); 1224 if (hsotg->needs_byte_swap) 1225 return swab32(val); 1226 else 1227 return val; 1228 } 1229 1230 static inline void dwc2_writel(struct dwc2_hsotg *hsotg, u32 value, u32 offset) 1231 { 1232 if (hsotg->needs_byte_swap) 1233 writel(swab32(value), hsotg->regs + offset); 1234 else 1235 writel(value, hsotg->regs + offset); 1236 1237 #ifdef DWC2_LOG_WRITES 1238 pr_info("info:: wrote %08x to %p\n", value, hsotg->regs + offset); 1239 #endif 1240 } 1241 1242 static inline void dwc2_readl_rep(struct dwc2_hsotg *hsotg, u32 offset, 1243 void *buffer, unsigned int count) 1244 { 1245 if (count) { 1246 u32 *buf = buffer; 1247 1248 do { 1249 u32 x = dwc2_readl(hsotg, offset); 1250 *buf++ = x; 1251 } while (--count); 1252 } 1253 } 1254 1255 static inline void dwc2_writel_rep(struct dwc2_hsotg *hsotg, u32 offset, 1256 const void *buffer, unsigned int count) 1257 { 1258 if (count) { 1259 const u32 *buf = buffer; 1260 1261 do { 1262 dwc2_writel(hsotg, *buf++, offset); 1263 } while (--count); 1264 } 1265 } 1266 1267 /* Reasons for halting a host channel */ 1268 enum dwc2_halt_status { 1269 DWC2_HC_XFER_NO_HALT_STATUS, 1270 DWC2_HC_XFER_COMPLETE, 1271 DWC2_HC_XFER_URB_COMPLETE, 1272 DWC2_HC_XFER_ACK, 1273 DWC2_HC_XFER_NAK, 1274 DWC2_HC_XFER_NYET, 1275 DWC2_HC_XFER_STALL, 1276 DWC2_HC_XFER_XACT_ERR, 1277 DWC2_HC_XFER_FRAME_OVERRUN, 1278 DWC2_HC_XFER_BABBLE_ERR, 1279 DWC2_HC_XFER_DATA_TOGGLE_ERR, 1280 DWC2_HC_XFER_AHB_ERR, 1281 DWC2_HC_XFER_PERIODIC_INCOMPLETE, 1282 DWC2_HC_XFER_URB_DEQUEUE, 1283 }; 1284 1285 /* Core version information */ 1286 static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg) 1287 { 1288 return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000; 1289 } 1290 1291 static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg) 1292 { 1293 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000; 1294 } 1295 1296 static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg) 1297 { 1298 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000; 1299 } 1300 1301 /* 1302 * The following functions support initialization of the core driver component 1303 * and the DWC_otg controller 1304 */ 1305 int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait); 1306 int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg); 1307 int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, int rem_wakeup, 1308 bool restore); 1309 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host); 1310 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup, 1311 int reset, int is_host); 1312 void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg); 1313 int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy); 1314 1315 void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host); 1316 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg); 1317 1318 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 1319 1320 int dwc2_check_core_version(struct dwc2_hsotg *hsotg); 1321 1322 /* 1323 * Common core Functions. 1324 * The following functions support managing the DWC_otg controller in either 1325 * device or host mode. 1326 */ 1327 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 1328 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 1329 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 1330 1331 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 1332 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 1333 1334 void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup, 1335 int is_host); 1336 int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg); 1337 int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg); 1338 1339 void dwc2_enable_acg(struct dwc2_hsotg *hsotg); 1340 1341 /* This function should be called on every hardware interrupt. */ 1342 irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 1343 1344 /* The device ID match table */ 1345 extern const struct of_device_id dwc2_of_match_table[]; 1346 extern const struct acpi_device_id dwc2_acpi_match[]; 1347 1348 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg); 1349 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg); 1350 1351 /* Common polling functions */ 1352 int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit, 1353 u32 timeout); 1354 int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit, 1355 u32 timeout); 1356 /* Parameters */ 1357 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); 1358 int dwc2_init_params(struct dwc2_hsotg *hsotg); 1359 1360 /* 1361 * The following functions check the controller's OTG operation mode 1362 * capability (GHWCFG2.OTG_MODE). 1363 * 1364 * These functions can be used before the internal hsotg->hw_params 1365 * are read in and cached so they always read directly from the 1366 * GHWCFG2 register. 1367 */ 1368 unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg); 1369 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg); 1370 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg); 1371 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg); 1372 1373 /* 1374 * Returns the mode of operation, host or device 1375 */ 1376 static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) 1377 { 1378 return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) != 0; 1379 } 1380 1381 static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) 1382 { 1383 return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) == 0; 1384 } 1385 1386 int dwc2_drd_init(struct dwc2_hsotg *hsotg); 1387 void dwc2_drd_suspend(struct dwc2_hsotg *hsotg); 1388 void dwc2_drd_resume(struct dwc2_hsotg *hsotg); 1389 void dwc2_drd_exit(struct dwc2_hsotg *hsotg); 1390 1391 /* 1392 * Dump core registers and SPRAM 1393 */ 1394 void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 1395 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 1396 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 1397 1398 /* Gadget defines */ 1399 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1400 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1401 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg); 1402 int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2); 1403 int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2); 1404 int dwc2_gadget_init(struct dwc2_hsotg *hsotg); 1405 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1406 bool reset); 1407 void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg); 1408 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg); 1409 void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2); 1410 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode); 1411 #define dwc2_is_device_connected(hsotg) (hsotg->connected) 1412 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg); 1413 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup); 1414 int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg); 1415 int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, 1416 int rem_wakeup, int reset); 1417 int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg); 1418 int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg, 1419 bool restore); 1420 void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg); 1421 void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, 1422 int rem_wakeup); 1423 int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg); 1424 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg); 1425 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg); 1426 void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg); 1427 void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg); 1428 static inline void dwc2_clear_fifo_map(struct dwc2_hsotg *hsotg) 1429 { hsotg->fifo_map = 0; } 1430 #else 1431 static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2) 1432 { return 0; } 1433 static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2) 1434 { return 0; } 1435 static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2) 1436 { return 0; } 1437 static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg) 1438 { return 0; } 1439 static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1440 bool reset) {} 1441 static inline void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) {} 1442 static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} 1443 static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} 1444 static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, 1445 int testmode) 1446 { return 0; } 1447 #define dwc2_is_device_connected(hsotg) (0) 1448 static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) 1449 { return 0; } 1450 static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, 1451 int remote_wakeup) 1452 { return 0; } 1453 static inline int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg) 1454 { return 0; } 1455 static inline int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, 1456 int rem_wakeup, int reset) 1457 { return 0; } 1458 static inline int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg) 1459 { return 0; } 1460 static inline int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg, 1461 bool restore) 1462 { return 0; } 1463 static inline void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg) {} 1464 static inline void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, 1465 int rem_wakeup) {} 1466 static inline int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg) 1467 { return 0; } 1468 static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) 1469 { return 0; } 1470 static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg) 1471 { return 0; } 1472 static inline void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) {} 1473 static inline void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg) {} 1474 static inline void dwc2_clear_fifo_map(struct dwc2_hsotg *hsotg) {} 1475 #endif 1476 1477 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1478 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 1479 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us); 1480 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg); 1481 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force); 1482 void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 1483 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup); 1484 int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex); 1485 int dwc2_port_resume(struct dwc2_hsotg *hsotg); 1486 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg); 1487 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg); 1488 int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg); 1489 int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, 1490 int rem_wakeup, int reset); 1491 int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg); 1492 int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg, 1493 int rem_wakeup, bool restore); 1494 void dwc2_host_enter_clock_gating(struct dwc2_hsotg *hsotg); 1495 void dwc2_host_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup); 1496 bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2); 1497 static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) 1498 { schedule_work(&hsotg->phy_reset_work); } 1499 #else 1500 static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1501 { return 0; } 1502 static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, 1503 int us) 1504 { return 0; } 1505 static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {} 1506 static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {} 1507 static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} 1508 static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} 1509 static inline int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) 1510 { return 0; } 1511 static inline int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 1512 { return 0; } 1513 static inline int dwc2_port_resume(struct dwc2_hsotg *hsotg) 1514 { return 0; } 1515 static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg) 1516 { return 0; } 1517 static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 1518 { return 0; } 1519 static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 1520 { return 0; } 1521 static inline int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg) 1522 { return 0; } 1523 static inline int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, 1524 int rem_wakeup, int reset) 1525 { return 0; } 1526 static inline int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg) 1527 { return 0; } 1528 static inline int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg, 1529 int rem_wakeup, bool restore) 1530 { return 0; } 1531 static inline void dwc2_host_enter_clock_gating(struct dwc2_hsotg *hsotg) {} 1532 static inline void dwc2_host_exit_clock_gating(struct dwc2_hsotg *hsotg, 1533 int rem_wakeup) {} 1534 static inline bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2) 1535 { return false; } 1536 static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) {} 1537 1538 #endif 1539 1540 #endif /* __DWC2_CORE_H__ */ 1541