1 /* 2 * core.h - DesignWare HS OTG Controller common declarations 3 * 4 * Copyright (C) 2004-2013 Synopsys, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The names of the above-listed copyright holders may not be used 16 * to endorse or promote products derived from this software without 17 * specific prior written permission. 18 * 19 * ALTERNATIVELY, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") as published by the Free Software 21 * Foundation; either version 2 of the License, or (at your option) any 22 * later version. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #ifndef __DWC2_CORE_H__ 38 #define __DWC2_CORE_H__ 39 40 #include <linux/phy/phy.h> 41 #include <linux/regulator/consumer.h> 42 #include <linux/usb/gadget.h> 43 #include <linux/usb/otg.h> 44 #include <linux/usb/phy.h> 45 #include "hw.h" 46 47 #ifdef DWC2_LOG_WRITES 48 static inline void do_write(u32 value, void *addr) 49 { 50 writel(value, addr); 51 pr_info("INFO:: wrote %08x to %p\n", value, addr); 52 } 53 54 #undef writel 55 #define writel(v, a) do_write(v, a) 56 #endif 57 58 /* Maximum number of Endpoints/HostChannels */ 59 #define MAX_EPS_CHANNELS 16 60 61 /* s3c-hsotg declarations */ 62 static const char * const s3c_hsotg_supply_names[] = { 63 "vusb_d", /* digital USB supply, 1.2V */ 64 "vusb_a", /* analog USB supply, 1.1V */ 65 }; 66 67 /* 68 * EP0_MPS_LIMIT 69 * 70 * Unfortunately there seems to be a limit of the amount of data that can 71 * be transferred by IN transactions on EP0. This is either 127 bytes or 3 72 * packets (which practically means 1 packet and 63 bytes of data) when the 73 * MPS is set to 64. 74 * 75 * This means if we are wanting to move >127 bytes of data, we need to 76 * split the transactions up, but just doing one packet at a time does 77 * not work (this may be an implicit DATA0 PID on first packet of the 78 * transaction) and doing 2 packets is outside the controller's limits. 79 * 80 * If we try to lower the MPS size for EP0, then no transfers work properly 81 * for EP0, and the system will fail basic enumeration. As no cause for this 82 * has currently been found, we cannot support any large IN transfers for 83 * EP0. 84 */ 85 #define EP0_MPS_LIMIT 64 86 87 struct s3c_hsotg; 88 struct s3c_hsotg_req; 89 90 /** 91 * struct s3c_hsotg_ep - driver endpoint definition. 92 * @ep: The gadget layer representation of the endpoint. 93 * @name: The driver generated name for the endpoint. 94 * @queue: Queue of requests for this endpoint. 95 * @parent: Reference back to the parent device structure. 96 * @req: The current request that the endpoint is processing. This is 97 * used to indicate an request has been loaded onto the endpoint 98 * and has yet to be completed (maybe due to data move, or simply 99 * awaiting an ack from the core all the data has been completed). 100 * @debugfs: File entry for debugfs file for this endpoint. 101 * @lock: State lock to protect contents of endpoint. 102 * @dir_in: Set to true if this endpoint is of the IN direction, which 103 * means that it is sending data to the Host. 104 * @index: The index for the endpoint registers. 105 * @mc: Multi Count - number of transactions per microframe 106 * @interval - Interval for periodic endpoints 107 * @name: The name array passed to the USB core. 108 * @halted: Set if the endpoint has been halted. 109 * @periodic: Set if this is a periodic ep, such as Interrupt 110 * @isochronous: Set if this is a isochronous ep 111 * @sent_zlp: Set if we've sent a zero-length packet. 112 * @total_data: The total number of data bytes done. 113 * @fifo_size: The size of the FIFO (for periodic IN endpoints) 114 * @fifo_load: The amount of data loaded into the FIFO (periodic IN) 115 * @last_load: The offset of data for the last start of request. 116 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN 117 * 118 * This is the driver's state for each registered enpoint, allowing it 119 * to keep track of transactions that need doing. Each endpoint has a 120 * lock to protect the state, to try and avoid using an overall lock 121 * for the host controller as much as possible. 122 * 123 * For periodic IN endpoints, we have fifo_size and fifo_load to try 124 * and keep track of the amount of data in the periodic FIFO for each 125 * of these as we don't have a status register that tells us how much 126 * is in each of them. (note, this may actually be useless information 127 * as in shared-fifo mode periodic in acts like a single-frame packet 128 * buffer than a fifo) 129 */ 130 struct s3c_hsotg_ep { 131 struct usb_ep ep; 132 struct list_head queue; 133 struct s3c_hsotg *parent; 134 struct s3c_hsotg_req *req; 135 struct dentry *debugfs; 136 137 unsigned long total_data; 138 unsigned int size_loaded; 139 unsigned int last_load; 140 unsigned int fifo_load; 141 unsigned short fifo_size; 142 unsigned short fifo_index; 143 144 unsigned char dir_in; 145 unsigned char index; 146 unsigned char mc; 147 unsigned char interval; 148 149 unsigned int halted:1; 150 unsigned int periodic:1; 151 unsigned int isochronous:1; 152 unsigned int sent_zlp:1; 153 154 char name[10]; 155 }; 156 157 /** 158 * struct s3c_hsotg - driver state. 159 * @dev: The parent device supplied to the probe function 160 * @driver: USB gadget driver 161 * @phy: The otg phy transceiver structure for phy control. 162 * @uphy: The otg phy transceiver structure for old USB phy control. 163 * @plat: The platform specific configuration data. This can be removed once 164 * all SoCs support usb transceiver. 165 * @regs: The memory area mapped for accessing registers. 166 * @irq: The IRQ number we are using 167 * @supplies: Definition of USB power supplies 168 * @phyif: PHY interface width 169 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 170 * @num_of_eps: Number of available EPs (excluding EP0) 171 * @debug_root: root directrory for debugfs. 172 * @debug_file: main status file for debugfs. 173 * @debug_fifo: FIFO status file for debugfs. 174 * @ep0_reply: Request used for ep0 reply. 175 * @ep0_buff: Buffer for EP0 reply data, if needed. 176 * @ctrl_buff: Buffer for EP0 control requests. 177 * @ctrl_req: Request for EP0 control packets. 178 * @setup: NAK management for EP0 SETUP 179 * @last_rst: Time of last reset 180 * @eps: The endpoints being supplied to the gadget framework 181 */ 182 struct s3c_hsotg { 183 struct device *dev; 184 struct usb_gadget_driver *driver; 185 struct phy *phy; 186 struct usb_phy *uphy; 187 struct s3c_hsotg_plat *plat; 188 189 spinlock_t lock; 190 191 void __iomem *regs; 192 int irq; 193 struct clk *clk; 194 195 struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsotg_supply_names)]; 196 197 u32 phyif; 198 int fifo_mem; 199 unsigned int dedicated_fifos:1; 200 unsigned char num_of_eps; 201 u32 fifo_map; 202 203 struct dentry *debug_root; 204 struct dentry *debug_file; 205 struct dentry *debug_fifo; 206 207 struct usb_request *ep0_reply; 208 struct usb_request *ctrl_req; 209 u8 ep0_buff[8]; 210 u8 ctrl_buff[8]; 211 212 struct usb_gadget gadget; 213 unsigned int setup; 214 unsigned long last_rst; 215 struct s3c_hsotg_ep *eps; 216 }; 217 218 /** 219 * struct s3c_hsotg_req - data transfer request 220 * @req: The USB gadget request 221 * @queue: The list of requests for the endpoint this is queued for. 222 * @in_progress: Has already had size/packets written to core 223 * @mapped: DMA buffer for this request has been mapped via dma_map_single(). 224 */ 225 struct s3c_hsotg_req { 226 struct usb_request req; 227 struct list_head queue; 228 unsigned char in_progress; 229 unsigned char mapped; 230 }; 231 232 #define call_gadget(_hs, _entry) \ 233 do { \ 234 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ 235 (_hs)->driver && (_hs)->driver->_entry) { \ 236 spin_unlock(&_hs->lock); \ 237 (_hs)->driver->_entry(&(_hs)->gadget); \ 238 spin_lock(&_hs->lock); \ 239 } \ 240 } while (0) 241 242 struct dwc2_hsotg; 243 struct dwc2_host_chan; 244 245 /* Device States */ 246 enum dwc2_lx_state { 247 DWC2_L0, /* On state */ 248 DWC2_L1, /* LPM sleep state */ 249 DWC2_L2, /* USB suspend state */ 250 DWC2_L3, /* Off state */ 251 }; 252 253 /** 254 * struct dwc2_core_params - Parameters for configuring the core 255 * 256 * @otg_cap: Specifies the OTG capabilities. 257 * 0 - HNP and SRP capable 258 * 1 - SRP Only capable 259 * 2 - No HNP/SRP capable (always available) 260 * Defaults to best available option (0, 1, then 2) 261 * @otg_ver: OTG version supported 262 * 0 - 1.3 (default) 263 * 1 - 2.0 264 * @dma_enable: Specifies whether to use slave or DMA mode for accessing 265 * the data FIFOs. The driver will automatically detect the 266 * value for this parameter if none is specified. 267 * 0 - Slave (always available) 268 * 1 - DMA (default, if available) 269 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 270 * address DMA mode or descriptor DMA mode for accessing 271 * the data FIFOs. The driver will automatically detect the 272 * value for this if none is specified. 273 * 0 - Address DMA 274 * 1 - Descriptor DMA (default, if available) 275 * @speed: Specifies the maximum speed of operation in host and 276 * device mode. The actual speed depends on the speed of 277 * the attached device and the value of phy_type. 278 * 0 - High Speed 279 * (default when phy_type is UTMI+ or ULPI) 280 * 1 - Full Speed 281 * (default when phy_type is Full Speed) 282 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 283 * 1 - Allow dynamic FIFO sizing (default, if available) 284 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 285 * are enabled 286 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 287 * dynamic FIFO sizing is enabled 288 * 16 to 32768 289 * Actual maximum value is autodetected and also 290 * the default. 291 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 292 * in host mode when dynamic FIFO sizing is enabled 293 * 16 to 32768 294 * Actual maximum value is autodetected and also 295 * the default. 296 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 297 * host mode when dynamic FIFO sizing is enabled 298 * 16 to 32768 299 * Actual maximum value is autodetected and also 300 * the default. 301 * @max_transfer_size: The maximum transfer size supported, in bytes 302 * 2047 to 65,535 303 * Actual maximum value is autodetected and also 304 * the default. 305 * @max_packet_count: The maximum number of packets in a transfer 306 * 15 to 511 307 * Actual maximum value is autodetected and also 308 * the default. 309 * @host_channels: The number of host channel registers to use 310 * 1 to 16 311 * Actual maximum value is autodetected and also 312 * the default. 313 * @phy_type: Specifies the type of PHY interface to use. By default, 314 * the driver will automatically detect the phy_type. 315 * 0 - Full Speed Phy 316 * 1 - UTMI+ Phy 317 * 2 - ULPI Phy 318 * Defaults to best available option (2, 1, then 0) 319 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 320 * is applicable for a phy_type of UTMI+ or ULPI. (For a 321 * ULPI phy_type, this parameter indicates the data width 322 * between the MAC and the ULPI Wrapper.) Also, this 323 * parameter is applicable only if the OTG_HSPHY_WIDTH cC 324 * parameter was set to "8 and 16 bits", meaning that the 325 * core has been configured to work at either data path 326 * width. 327 * 8 or 16 (default 16 if available) 328 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 329 * data rate. This parameter is only applicable if phy_type 330 * is ULPI. 331 * 0 - single data rate ULPI interface with 8 bit wide 332 * data bus (default) 333 * 1 - double data rate ULPI interface with 4 bit wide 334 * data bus 335 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 336 * external supply to drive the VBus 337 * 0 - Internal supply (default) 338 * 1 - External supply 339 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 340 * speed PHY. This parameter is only applicable if phy_type 341 * is FS. 342 * 0 - No (default) 343 * 1 - Yes 344 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 345 * 0 - No (default) 346 * 1 - Yes 347 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 348 * when attached to a Full Speed or Low Speed device in 349 * host mode. 350 * 0 - Don't support low power mode (default) 351 * 1 - Support low power mode 352 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 353 * when connected to a Low Speed device in host 354 * mode. This parameter is applicable only if 355 * host_support_fs_ls_low_power is enabled. 356 * 0 - 48 MHz 357 * (default when phy_type is UTMI+ or ULPI) 358 * 1 - 6 MHz 359 * (default when phy_type is Full Speed) 360 * @ts_dline: Enable Term Select Dline pulsing 361 * 0 - No (default) 362 * 1 - Yes 363 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 364 * 0 - No (default for core < 2.92a) 365 * 1 - Yes (default for core >= 2.92a) 366 * @ahbcfg: This field allows the default value of the GAHBCFG 367 * register to be overridden 368 * -1 - GAHBCFG value will be set to 0x06 369 * (INCR4, default) 370 * all others - GAHBCFG value will be overridden with 371 * this value 372 * Not all bits can be controlled like this, the 373 * bits defined by GAHBCFG_CTRL_MASK are controlled 374 * by the driver and are ignored in this 375 * configuration value. 376 * @uframe_sched: True to enable the microframe scheduler 377 * 378 * The following parameters may be specified when starting the module. These 379 * parameters define how the DWC_otg controller should be configured. A 380 * value of -1 (or any other out of range value) for any parameter means 381 * to read the value from hardware (if possible) or use the builtin 382 * default described above. 383 */ 384 struct dwc2_core_params { 385 /* 386 * Don't add any non-int members here, this will break 387 * dwc2_set_all_params! 388 */ 389 int otg_cap; 390 int otg_ver; 391 int dma_enable; 392 int dma_desc_enable; 393 int speed; 394 int enable_dynamic_fifo; 395 int en_multiple_tx_fifo; 396 int host_rx_fifo_size; 397 int host_nperio_tx_fifo_size; 398 int host_perio_tx_fifo_size; 399 int max_transfer_size; 400 int max_packet_count; 401 int host_channels; 402 int phy_type; 403 int phy_utmi_width; 404 int phy_ulpi_ddr; 405 int phy_ulpi_ext_vbus; 406 int i2c_enable; 407 int ulpi_fs_ls; 408 int host_support_fs_ls_low_power; 409 int host_ls_low_power_phy_clk; 410 int ts_dline; 411 int reload_ctl; 412 int ahbcfg; 413 int uframe_sched; 414 }; 415 416 /** 417 * struct dwc2_hw_params - Autodetected parameters. 418 * 419 * These parameters are the various parameters read from hardware 420 * registers during initialization. They typically contain the best 421 * supported or maximum value that can be configured in the 422 * corresponding dwc2_core_params value. 423 * 424 * The values that are not in dwc2_core_params are documented below. 425 * 426 * @op_mode Mode of Operation 427 * 0 - HNP- and SRP-Capable OTG (Host & Device) 428 * 1 - SRP-Capable OTG (Host & Device) 429 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 430 * 3 - SRP-Capable Device 431 * 4 - Non-OTG Device 432 * 5 - SRP-Capable Host 433 * 6 - Non-OTG Host 434 * @arch Architecture 435 * 0 - Slave only 436 * 1 - External DMA 437 * 2 - Internal DMA 438 * @power_optimized Are power optimizations enabled? 439 * @num_dev_ep Number of device endpoints available 440 * @num_dev_perio_in_ep Number of device periodic IN endpoints 441 * avaialable 442 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue 443 * Depth 444 * 0 to 30 445 * @host_perio_tx_q_depth 446 * Host Mode Periodic Request Queue Depth 447 * 2, 4 or 8 448 * @nperio_tx_q_depth 449 * Non-Periodic Request Queue Depth 450 * 2, 4 or 8 451 * @hs_phy_type High-speed PHY interface type 452 * 0 - High-speed interface not supported 453 * 1 - UTMI+ 454 * 2 - ULPI 455 * 3 - UTMI+ and ULPI 456 * @fs_phy_type Full-speed PHY interface type 457 * 0 - Full speed interface not supported 458 * 1 - Dedicated full speed interface 459 * 2 - FS pins shared with UTMI+ pins 460 * 3 - FS pins shared with ULPI pins 461 * @total_fifo_size: Total internal RAM for FIFOs (bytes) 462 * @utmi_phy_data_width UTMI+ PHY data width 463 * 0 - 8 bits 464 * 1 - 16 bits 465 * 2 - 8 or 16 bits 466 * @snpsid: Value from SNPSID register 467 */ 468 struct dwc2_hw_params { 469 unsigned op_mode:3; 470 unsigned arch:2; 471 unsigned dma_desc_enable:1; 472 unsigned enable_dynamic_fifo:1; 473 unsigned en_multiple_tx_fifo:1; 474 unsigned host_rx_fifo_size:16; 475 unsigned host_nperio_tx_fifo_size:16; 476 unsigned host_perio_tx_fifo_size:16; 477 unsigned nperio_tx_q_depth:3; 478 unsigned host_perio_tx_q_depth:3; 479 unsigned dev_token_q_depth:5; 480 unsigned max_transfer_size:26; 481 unsigned max_packet_count:11; 482 unsigned host_channels:5; 483 unsigned hs_phy_type:2; 484 unsigned fs_phy_type:2; 485 unsigned i2c_enable:1; 486 unsigned num_dev_ep:4; 487 unsigned num_dev_perio_in_ep:4; 488 unsigned total_fifo_size:16; 489 unsigned power_optimized:1; 490 unsigned utmi_phy_data_width:2; 491 u32 snpsid; 492 }; 493 494 /** 495 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 496 * and periodic schedules 497 * 498 * @dev: The struct device pointer 499 * @regs: Pointer to controller regs 500 * @core_params: Parameters that define how the core should be configured 501 * @hw_params: Parameters that were autodetected from the 502 * hardware registers 503 * @op_state: The operational State, during transitions (a_host=> 504 * a_peripheral and b_device=>b_host) this may not match 505 * the core, but allows the software to determine 506 * transitions 507 * @dr_mode: Requested mode of operation, one of following: 508 * - USB_DR_MODE_PERIPHERAL 509 * - USB_DR_MODE_HOST 510 * - USB_DR_MODE_OTG 511 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 512 * transfer are in process of being queued 513 * @srp_success: Stores status of SRP request in the case of a FS PHY 514 * with an I2C interface 515 * @wq_otg: Workqueue object used for handling of some interrupts 516 * @wf_otg: Work object for handling Connector ID Status Change 517 * interrupt 518 * @wkp_timer: Timer object for handling Wakeup Detected interrupt 519 * @lx_state: Lx state of connected device 520 * @flags: Flags for handling root port state changes 521 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 522 * Transfers associated with these QHs are not currently 523 * assigned to a host channel. 524 * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 525 * Transfers associated with these QHs are currently 526 * assigned to a host channel. 527 * @non_periodic_qh_ptr: Pointer to next QH to process in the active 528 * non-periodic schedule 529 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 530 * list of QHs for periodic transfers that are _not_ 531 * scheduled for the next frame. Each QH in the list has an 532 * interval counter that determines when it needs to be 533 * scheduled for execution. This scheduling mechanism 534 * allows only a simple calculation for periodic bandwidth 535 * used (i.e. must assume that all periodic transfers may 536 * need to execute in the same frame). However, it greatly 537 * simplifies scheduling and should be sufficient for the 538 * vast majority of OTG hosts, which need to connect to a 539 * small number of peripherals at one time. Items move from 540 * this list to periodic_sched_ready when the QH interval 541 * counter is 0 at SOF. 542 * @periodic_sched_ready: List of periodic QHs that are ready for execution in 543 * the next frame, but have not yet been assigned to host 544 * channels. Items move from this list to 545 * periodic_sched_assigned as host channels become 546 * available during the current frame. 547 * @periodic_sched_assigned: List of periodic QHs to be executed in the next 548 * frame that are assigned to host channels. Items move 549 * from this list to periodic_sched_queued as the 550 * transactions for the QH are queued to the DWC_otg 551 * controller. 552 * @periodic_sched_queued: List of periodic QHs that have been queued for 553 * execution. Items move from this list to either 554 * periodic_sched_inactive or periodic_sched_ready when the 555 * channel associated with the transfer is released. If the 556 * interval for the QH is 1, the item moves to 557 * periodic_sched_ready because it must be rescheduled for 558 * the next frame. Otherwise, the item moves to 559 * periodic_sched_inactive. 560 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 561 * This value is in microseconds per (micro)frame. The 562 * assumption is that all periodic transfers may occur in 563 * the same (micro)frame. 564 * @frame_usecs: Internal variable used by the microframe scheduler 565 * @frame_number: Frame number read from the core at SOF. The value ranges 566 * from 0 to HFNUM_MAX_FRNUM. 567 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 568 * SOF enable/disable. 569 * @free_hc_list: Free host channels in the controller. This is a list of 570 * struct dwc2_host_chan items. 571 * @periodic_channels: Number of host channels assigned to periodic transfers. 572 * Currently assuming that there is a dedicated host 573 * channel for each periodic transaction and at least one 574 * host channel is available for non-periodic transactions. 575 * @non_periodic_channels: Number of host channels assigned to non-periodic 576 * transfers 577 * @available_host_channels Number of host channels available for the microframe 578 * scheduler to use 579 * @hc_ptr_array: Array of pointers to the host channel descriptors. 580 * Allows accessing a host channel descriptor given the 581 * host channel number. This is useful in interrupt 582 * handlers. 583 * @status_buf: Buffer used for data received during the status phase of 584 * a control transfer. 585 * @status_buf_dma: DMA address for status_buf 586 * @start_work: Delayed work for handling host A-cable connection 587 * @reset_work: Delayed work for handling a port reset 588 * @lock: Spinlock that protects all the driver data structures 589 * @priv: Stores a pointer to the struct usb_hcd 590 * @otg_port: OTG port number 591 * @frame_list: Frame list 592 * @frame_list_dma: Frame list DMA address 593 */ 594 struct dwc2_hsotg { 595 struct device *dev; 596 void __iomem *regs; 597 /** Params detected from hardware */ 598 struct dwc2_hw_params hw_params; 599 /** Params to actually use */ 600 struct dwc2_core_params *core_params; 601 enum usb_otg_state op_state; 602 enum usb_dr_mode dr_mode; 603 604 unsigned int queuing_high_bandwidth:1; 605 unsigned int srp_success:1; 606 607 struct workqueue_struct *wq_otg; 608 struct work_struct wf_otg; 609 struct timer_list wkp_timer; 610 enum dwc2_lx_state lx_state; 611 612 union dwc2_hcd_internal_flags { 613 u32 d32; 614 struct { 615 unsigned port_connect_status_change:1; 616 unsigned port_connect_status:1; 617 unsigned port_reset_change:1; 618 unsigned port_enable_change:1; 619 unsigned port_suspend_change:1; 620 unsigned port_over_current_change:1; 621 unsigned port_l1_change:1; 622 unsigned reserved:25; 623 } b; 624 } flags; 625 626 struct list_head non_periodic_sched_inactive; 627 struct list_head non_periodic_sched_active; 628 struct list_head *non_periodic_qh_ptr; 629 struct list_head periodic_sched_inactive; 630 struct list_head periodic_sched_ready; 631 struct list_head periodic_sched_assigned; 632 struct list_head periodic_sched_queued; 633 u16 periodic_usecs; 634 u16 frame_usecs[8]; 635 u16 frame_number; 636 u16 periodic_qh_count; 637 638 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 639 #define FRAME_NUM_ARRAY_SIZE 1000 640 u16 last_frame_num; 641 u16 *frame_num_array; 642 u16 *last_frame_num_array; 643 int frame_num_idx; 644 int dumped_frame_num_array; 645 #endif 646 647 struct list_head free_hc_list; 648 int periodic_channels; 649 int non_periodic_channels; 650 int available_host_channels; 651 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 652 u8 *status_buf; 653 dma_addr_t status_buf_dma; 654 #define DWC2_HCD_STATUS_BUF_SIZE 64 655 656 struct delayed_work start_work; 657 struct delayed_work reset_work; 658 spinlock_t lock; 659 void *priv; 660 u8 otg_port; 661 u32 *frame_list; 662 dma_addr_t frame_list_dma; 663 664 /* DWC OTG HW Release versions */ 665 #define DWC2_CORE_REV_2_71a 0x4f54271a 666 #define DWC2_CORE_REV_2_90a 0x4f54290a 667 #define DWC2_CORE_REV_2_92a 0x4f54292a 668 #define DWC2_CORE_REV_2_94a 0x4f54294a 669 #define DWC2_CORE_REV_3_00a 0x4f54300a 670 671 #ifdef DEBUG 672 u32 frrem_samples; 673 u64 frrem_accum; 674 675 u32 hfnum_7_samples_a; 676 u64 hfnum_7_frrem_accum_a; 677 u32 hfnum_0_samples_a; 678 u64 hfnum_0_frrem_accum_a; 679 u32 hfnum_other_samples_a; 680 u64 hfnum_other_frrem_accum_a; 681 682 u32 hfnum_7_samples_b; 683 u64 hfnum_7_frrem_accum_b; 684 u32 hfnum_0_samples_b; 685 u64 hfnum_0_frrem_accum_b; 686 u32 hfnum_other_samples_b; 687 u64 hfnum_other_frrem_accum_b; 688 #endif 689 }; 690 691 /* Reasons for halting a host channel */ 692 enum dwc2_halt_status { 693 DWC2_HC_XFER_NO_HALT_STATUS, 694 DWC2_HC_XFER_COMPLETE, 695 DWC2_HC_XFER_URB_COMPLETE, 696 DWC2_HC_XFER_ACK, 697 DWC2_HC_XFER_NAK, 698 DWC2_HC_XFER_NYET, 699 DWC2_HC_XFER_STALL, 700 DWC2_HC_XFER_XACT_ERR, 701 DWC2_HC_XFER_FRAME_OVERRUN, 702 DWC2_HC_XFER_BABBLE_ERR, 703 DWC2_HC_XFER_DATA_TOGGLE_ERR, 704 DWC2_HC_XFER_AHB_ERR, 705 DWC2_HC_XFER_PERIODIC_INCOMPLETE, 706 DWC2_HC_XFER_URB_DEQUEUE, 707 }; 708 709 /* 710 * The following functions support initialization of the core driver component 711 * and the DWC_otg controller 712 */ 713 extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg); 714 715 /* 716 * Host core Functions. 717 * The following functions support managing the DWC_otg controller in host 718 * mode. 719 */ 720 extern void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan); 721 extern void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 722 enum dwc2_halt_status halt_status); 723 extern void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, 724 struct dwc2_host_chan *chan); 725 extern void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 726 struct dwc2_host_chan *chan); 727 extern void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 728 struct dwc2_host_chan *chan); 729 extern int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 730 struct dwc2_host_chan *chan); 731 extern void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, 732 struct dwc2_host_chan *chan); 733 extern void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg); 734 extern void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg); 735 736 extern u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg); 737 extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 738 739 /* 740 * Common core Functions. 741 * The following functions support managing the DWC_otg controller in either 742 * device or host mode. 743 */ 744 extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 745 extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 746 extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 747 748 extern int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq); 749 extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 750 extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 751 752 /* This function should be called on every hardware interrupt. */ 753 extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 754 755 /* OTG Core Parameters */ 756 757 /* 758 * Specifies the OTG capabilities. The driver will automatically 759 * detect the value for this parameter if none is specified. 760 * 0 - HNP and SRP capable (default) 761 * 1 - SRP Only capable 762 * 2 - No HNP/SRP capable 763 */ 764 extern void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val); 765 #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 766 #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 767 #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 768 769 /* 770 * Specifies whether to use slave or DMA mode for accessing the data 771 * FIFOs. The driver will automatically detect the value for this 772 * parameter if none is specified. 773 * 0 - Slave 774 * 1 - DMA (default, if available) 775 */ 776 extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val); 777 778 /* 779 * When DMA mode is enabled specifies whether to use 780 * address DMA or DMA Descritor mode for accessing the data 781 * FIFOs in device mode. The driver will automatically detect 782 * the value for this parameter if none is specified. 783 * 0 - address DMA 784 * 1 - DMA Descriptor(default, if available) 785 */ 786 extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val); 787 788 /* 789 * Specifies the maximum speed of operation in host and device mode. 790 * The actual speed depends on the speed of the attached device and 791 * the value of phy_type. The actual speed depends on the speed of the 792 * attached device. 793 * 0 - High Speed (default) 794 * 1 - Full Speed 795 */ 796 extern void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val); 797 #define DWC2_SPEED_PARAM_HIGH 0 798 #define DWC2_SPEED_PARAM_FULL 1 799 800 /* 801 * Specifies whether low power mode is supported when attached 802 * to a Full Speed or Low Speed device in host mode. 803 * 804 * 0 - Don't support low power mode (default) 805 * 1 - Support low power mode 806 */ 807 extern void dwc2_set_param_host_support_fs_ls_low_power( 808 struct dwc2_hsotg *hsotg, int val); 809 810 /* 811 * Specifies the PHY clock rate in low power mode when connected to a 812 * Low Speed device in host mode. This parameter is applicable only if 813 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS 814 * then defaults to 6 MHZ otherwise 48 MHZ. 815 * 816 * 0 - 48 MHz 817 * 1 - 6 MHz 818 */ 819 extern void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, 820 int val); 821 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 822 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 823 824 /* 825 * 0 - Use cC FIFO size parameters 826 * 1 - Allow dynamic FIFO sizing (default) 827 */ 828 extern void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, 829 int val); 830 831 /* 832 * Number of 4-byte words in the Rx FIFO in host mode when dynamic 833 * FIFO sizing is enabled. 834 * 16 to 32768 (default 1024) 835 */ 836 extern void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val); 837 838 /* 839 * Number of 4-byte words in the non-periodic Tx FIFO in host mode 840 * when Dynamic FIFO sizing is enabled in the core. 841 * 16 to 32768 (default 256) 842 */ 843 extern void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, 844 int val); 845 846 /* 847 * Number of 4-byte words in the host periodic Tx FIFO when dynamic 848 * FIFO sizing is enabled. 849 * 16 to 32768 (default 256) 850 */ 851 extern void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, 852 int val); 853 854 /* 855 * The maximum transfer size supported in bytes. 856 * 2047 to 65,535 (default 65,535) 857 */ 858 extern void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val); 859 860 /* 861 * The maximum number of packets in a transfer. 862 * 15 to 511 (default 511) 863 */ 864 extern void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val); 865 866 /* 867 * The number of host channel registers to use. 868 * 1 to 16 (default 11) 869 * Note: The FPGA configuration supports a maximum of 11 host channels. 870 */ 871 extern void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val); 872 873 /* 874 * Specifies the type of PHY interface to use. By default, the driver 875 * will automatically detect the phy_type. 876 * 877 * 0 - Full Speed PHY 878 * 1 - UTMI+ (default) 879 * 2 - ULPI 880 */ 881 extern void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val); 882 #define DWC2_PHY_TYPE_PARAM_FS 0 883 #define DWC2_PHY_TYPE_PARAM_UTMI 1 884 #define DWC2_PHY_TYPE_PARAM_ULPI 2 885 886 /* 887 * Specifies the UTMI+ Data Width. This parameter is 888 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI 889 * PHY_TYPE, this parameter indicates the data width between 890 * the MAC and the ULPI Wrapper.) Also, this parameter is 891 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set 892 * to "8 and 16 bits", meaning that the core has been 893 * configured to work at either data path width. 894 * 895 * 8 or 16 bits (default 16) 896 */ 897 extern void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val); 898 899 /* 900 * Specifies whether the ULPI operates at double or single 901 * data rate. This parameter is only applicable if PHY_TYPE is 902 * ULPI. 903 * 904 * 0 - single data rate ULPI interface with 8 bit wide data 905 * bus (default) 906 * 1 - double data rate ULPI interface with 4 bit wide data 907 * bus 908 */ 909 extern void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val); 910 911 /* 912 * Specifies whether to use the internal or external supply to 913 * drive the vbus with a ULPI phy. 914 */ 915 extern void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val); 916 #define DWC2_PHY_ULPI_INTERNAL_VBUS 0 917 #define DWC2_PHY_ULPI_EXTERNAL_VBUS 1 918 919 /* 920 * Specifies whether to use the I2Cinterface for full speed PHY. This 921 * parameter is only applicable if PHY_TYPE is FS. 922 * 0 - No (default) 923 * 1 - Yes 924 */ 925 extern void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val); 926 927 extern void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val); 928 929 extern void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val); 930 931 /* 932 * Specifies whether dedicated transmit FIFOs are 933 * enabled for non periodic IN endpoints in device mode 934 * 0 - No 935 * 1 - Yes 936 */ 937 extern void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, 938 int val); 939 940 extern void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val); 941 942 extern void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val); 943 944 extern void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val); 945 946 /* 947 * Dump core registers and SPRAM 948 */ 949 extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 950 extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 951 extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 952 953 /* 954 * Return OTG version - either 1.3 or 2.0 955 */ 956 extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg); 957 958 #endif /* __DWC2_CORE_H__ */ 959