1 /* 2 * core.h - DesignWare HS OTG Controller common declarations 3 * 4 * Copyright (C) 2004-2013 Synopsys, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The names of the above-listed copyright holders may not be used 16 * to endorse or promote products derived from this software without 17 * specific prior written permission. 18 * 19 * ALTERNATIVELY, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") as published by the Free Software 21 * Foundation; either version 2 of the License, or (at your option) any 22 * later version. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #ifndef __DWC2_CORE_H__ 38 #define __DWC2_CORE_H__ 39 40 #include <linux/phy/phy.h> 41 #include <linux/regulator/consumer.h> 42 #include <linux/usb/gadget.h> 43 #include <linux/usb/otg.h> 44 #include <linux/usb/phy.h> 45 #include "hw.h" 46 47 #ifdef DWC2_LOG_WRITES 48 static inline void do_write(u32 value, void *addr) 49 { 50 writel(value, addr); 51 pr_info("INFO:: wrote %08x to %p\n", value, addr); 52 } 53 54 #undef writel 55 #define writel(v, a) do_write(v, a) 56 #endif 57 58 /* Maximum number of Endpoints/HostChannels */ 59 #define MAX_EPS_CHANNELS 16 60 61 /* s3c-hsotg declarations */ 62 static const char * const s3c_hsotg_supply_names[] = { 63 "vusb_d", /* digital USB supply, 1.2V */ 64 "vusb_a", /* analog USB supply, 1.1V */ 65 }; 66 67 /* 68 * EP0_MPS_LIMIT 69 * 70 * Unfortunately there seems to be a limit of the amount of data that can 71 * be transferred by IN transactions on EP0. This is either 127 bytes or 3 72 * packets (which practically means 1 packet and 63 bytes of data) when the 73 * MPS is set to 64. 74 * 75 * This means if we are wanting to move >127 bytes of data, we need to 76 * split the transactions up, but just doing one packet at a time does 77 * not work (this may be an implicit DATA0 PID on first packet of the 78 * transaction) and doing 2 packets is outside the controller's limits. 79 * 80 * If we try to lower the MPS size for EP0, then no transfers work properly 81 * for EP0, and the system will fail basic enumeration. As no cause for this 82 * has currently been found, we cannot support any large IN transfers for 83 * EP0. 84 */ 85 #define EP0_MPS_LIMIT 64 86 87 struct dwc2_hsotg; 88 struct s3c_hsotg_req; 89 90 /** 91 * struct s3c_hsotg_ep - driver endpoint definition. 92 * @ep: The gadget layer representation of the endpoint. 93 * @name: The driver generated name for the endpoint. 94 * @queue: Queue of requests for this endpoint. 95 * @parent: Reference back to the parent device structure. 96 * @req: The current request that the endpoint is processing. This is 97 * used to indicate an request has been loaded onto the endpoint 98 * and has yet to be completed (maybe due to data move, or simply 99 * awaiting an ack from the core all the data has been completed). 100 * @debugfs: File entry for debugfs file for this endpoint. 101 * @lock: State lock to protect contents of endpoint. 102 * @dir_in: Set to true if this endpoint is of the IN direction, which 103 * means that it is sending data to the Host. 104 * @index: The index for the endpoint registers. 105 * @mc: Multi Count - number of transactions per microframe 106 * @interval - Interval for periodic endpoints 107 * @name: The name array passed to the USB core. 108 * @halted: Set if the endpoint has been halted. 109 * @periodic: Set if this is a periodic ep, such as Interrupt 110 * @isochronous: Set if this is a isochronous ep 111 * @send_zlp: Set if we need to send a zero-length packet. 112 * @total_data: The total number of data bytes done. 113 * @fifo_size: The size of the FIFO (for periodic IN endpoints) 114 * @fifo_load: The amount of data loaded into the FIFO (periodic IN) 115 * @last_load: The offset of data for the last start of request. 116 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN 117 * 118 * This is the driver's state for each registered enpoint, allowing it 119 * to keep track of transactions that need doing. Each endpoint has a 120 * lock to protect the state, to try and avoid using an overall lock 121 * for the host controller as much as possible. 122 * 123 * For periodic IN endpoints, we have fifo_size and fifo_load to try 124 * and keep track of the amount of data in the periodic FIFO for each 125 * of these as we don't have a status register that tells us how much 126 * is in each of them. (note, this may actually be useless information 127 * as in shared-fifo mode periodic in acts like a single-frame packet 128 * buffer than a fifo) 129 */ 130 struct s3c_hsotg_ep { 131 struct usb_ep ep; 132 struct list_head queue; 133 struct dwc2_hsotg *parent; 134 struct s3c_hsotg_req *req; 135 struct dentry *debugfs; 136 137 unsigned long total_data; 138 unsigned int size_loaded; 139 unsigned int last_load; 140 unsigned int fifo_load; 141 unsigned short fifo_size; 142 unsigned short fifo_index; 143 144 unsigned char dir_in; 145 unsigned char index; 146 unsigned char mc; 147 unsigned char interval; 148 149 unsigned int halted:1; 150 unsigned int periodic:1; 151 unsigned int isochronous:1; 152 unsigned int send_zlp:1; 153 154 char name[10]; 155 }; 156 157 /** 158 * struct s3c_hsotg_req - data transfer request 159 * @req: The USB gadget request 160 * @queue: The list of requests for the endpoint this is queued for. 161 * @saved_req_buf: variable to save req.buf when bounce buffers are used. 162 */ 163 struct s3c_hsotg_req { 164 struct usb_request req; 165 struct list_head queue; 166 void *saved_req_buf; 167 }; 168 169 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 170 #define call_gadget(_hs, _entry) \ 171 do { \ 172 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ 173 (_hs)->driver && (_hs)->driver->_entry) { \ 174 spin_unlock(&_hs->lock); \ 175 (_hs)->driver->_entry(&(_hs)->gadget); \ 176 spin_lock(&_hs->lock); \ 177 } \ 178 } while (0) 179 #else 180 #define call_gadget(_hs, _entry) do {} while (0) 181 #endif 182 183 struct dwc2_hsotg; 184 struct dwc2_host_chan; 185 186 /* Device States */ 187 enum dwc2_lx_state { 188 DWC2_L0, /* On state */ 189 DWC2_L1, /* LPM sleep state */ 190 DWC2_L2, /* USB suspend state */ 191 DWC2_L3, /* Off state */ 192 }; 193 194 /* 195 * Gadget periodic tx fifo sizes as used by legacy driver 196 * EP0 is not included 197 */ 198 #define DWC2_G_P_LEGACY_TX_FIFO_SIZE {256, 256, 256, 256, 768, 768, 768, \ 199 768, 0, 0, 0, 0, 0, 0, 0} 200 201 /* Gadget ep0 states */ 202 enum dwc2_ep0_state { 203 DWC2_EP0_SETUP, 204 DWC2_EP0_DATA_IN, 205 DWC2_EP0_DATA_OUT, 206 DWC2_EP0_STATUS_IN, 207 DWC2_EP0_STATUS_OUT, 208 }; 209 210 /** 211 * struct dwc2_core_params - Parameters for configuring the core 212 * 213 * @otg_cap: Specifies the OTG capabilities. 214 * 0 - HNP and SRP capable 215 * 1 - SRP Only capable 216 * 2 - No HNP/SRP capable (always available) 217 * Defaults to best available option (0, 1, then 2) 218 * @otg_ver: OTG version supported 219 * 0 - 1.3 (default) 220 * 1 - 2.0 221 * @dma_enable: Specifies whether to use slave or DMA mode for accessing 222 * the data FIFOs. The driver will automatically detect the 223 * value for this parameter if none is specified. 224 * 0 - Slave (always available) 225 * 1 - DMA (default, if available) 226 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 227 * address DMA mode or descriptor DMA mode for accessing 228 * the data FIFOs. The driver will automatically detect the 229 * value for this if none is specified. 230 * 0 - Address DMA 231 * 1 - Descriptor DMA (default, if available) 232 * @speed: Specifies the maximum speed of operation in host and 233 * device mode. The actual speed depends on the speed of 234 * the attached device and the value of phy_type. 235 * 0 - High Speed 236 * (default when phy_type is UTMI+ or ULPI) 237 * 1 - Full Speed 238 * (default when phy_type is Full Speed) 239 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 240 * 1 - Allow dynamic FIFO sizing (default, if available) 241 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 242 * are enabled 243 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 244 * dynamic FIFO sizing is enabled 245 * 16 to 32768 246 * Actual maximum value is autodetected and also 247 * the default. 248 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 249 * in host mode when dynamic FIFO sizing is enabled 250 * 16 to 32768 251 * Actual maximum value is autodetected and also 252 * the default. 253 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 254 * host mode when dynamic FIFO sizing is enabled 255 * 16 to 32768 256 * Actual maximum value is autodetected and also 257 * the default. 258 * @max_transfer_size: The maximum transfer size supported, in bytes 259 * 2047 to 65,535 260 * Actual maximum value is autodetected and also 261 * the default. 262 * @max_packet_count: The maximum number of packets in a transfer 263 * 15 to 511 264 * Actual maximum value is autodetected and also 265 * the default. 266 * @host_channels: The number of host channel registers to use 267 * 1 to 16 268 * Actual maximum value is autodetected and also 269 * the default. 270 * @phy_type: Specifies the type of PHY interface to use. By default, 271 * the driver will automatically detect the phy_type. 272 * 0 - Full Speed Phy 273 * 1 - UTMI+ Phy 274 * 2 - ULPI Phy 275 * Defaults to best available option (2, 1, then 0) 276 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 277 * is applicable for a phy_type of UTMI+ or ULPI. (For a 278 * ULPI phy_type, this parameter indicates the data width 279 * between the MAC and the ULPI Wrapper.) Also, this 280 * parameter is applicable only if the OTG_HSPHY_WIDTH cC 281 * parameter was set to "8 and 16 bits", meaning that the 282 * core has been configured to work at either data path 283 * width. 284 * 8 or 16 (default 16 if available) 285 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 286 * data rate. This parameter is only applicable if phy_type 287 * is ULPI. 288 * 0 - single data rate ULPI interface with 8 bit wide 289 * data bus (default) 290 * 1 - double data rate ULPI interface with 4 bit wide 291 * data bus 292 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 293 * external supply to drive the VBus 294 * 0 - Internal supply (default) 295 * 1 - External supply 296 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 297 * speed PHY. This parameter is only applicable if phy_type 298 * is FS. 299 * 0 - No (default) 300 * 1 - Yes 301 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 302 * 0 - No (default) 303 * 1 - Yes 304 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 305 * when attached to a Full Speed or Low Speed device in 306 * host mode. 307 * 0 - Don't support low power mode (default) 308 * 1 - Support low power mode 309 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 310 * when connected to a Low Speed device in host 311 * mode. This parameter is applicable only if 312 * host_support_fs_ls_low_power is enabled. 313 * 0 - 48 MHz 314 * (default when phy_type is UTMI+ or ULPI) 315 * 1 - 6 MHz 316 * (default when phy_type is Full Speed) 317 * @ts_dline: Enable Term Select Dline pulsing 318 * 0 - No (default) 319 * 1 - Yes 320 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 321 * 0 - No (default for core < 2.92a) 322 * 1 - Yes (default for core >= 2.92a) 323 * @ahbcfg: This field allows the default value of the GAHBCFG 324 * register to be overridden 325 * -1 - GAHBCFG value will be set to 0x06 326 * (INCR4, default) 327 * all others - GAHBCFG value will be overridden with 328 * this value 329 * Not all bits can be controlled like this, the 330 * bits defined by GAHBCFG_CTRL_MASK are controlled 331 * by the driver and are ignored in this 332 * configuration value. 333 * @uframe_sched: True to enable the microframe scheduler 334 * 335 * The following parameters may be specified when starting the module. These 336 * parameters define how the DWC_otg controller should be configured. A 337 * value of -1 (or any other out of range value) for any parameter means 338 * to read the value from hardware (if possible) or use the builtin 339 * default described above. 340 */ 341 struct dwc2_core_params { 342 /* 343 * Don't add any non-int members here, this will break 344 * dwc2_set_all_params! 345 */ 346 int otg_cap; 347 int otg_ver; 348 int dma_enable; 349 int dma_desc_enable; 350 int speed; 351 int enable_dynamic_fifo; 352 int en_multiple_tx_fifo; 353 int host_rx_fifo_size; 354 int host_nperio_tx_fifo_size; 355 int host_perio_tx_fifo_size; 356 int max_transfer_size; 357 int max_packet_count; 358 int host_channels; 359 int phy_type; 360 int phy_utmi_width; 361 int phy_ulpi_ddr; 362 int phy_ulpi_ext_vbus; 363 int i2c_enable; 364 int ulpi_fs_ls; 365 int host_support_fs_ls_low_power; 366 int host_ls_low_power_phy_clk; 367 int ts_dline; 368 int reload_ctl; 369 int ahbcfg; 370 int uframe_sched; 371 }; 372 373 /** 374 * struct dwc2_hw_params - Autodetected parameters. 375 * 376 * These parameters are the various parameters read from hardware 377 * registers during initialization. They typically contain the best 378 * supported or maximum value that can be configured in the 379 * corresponding dwc2_core_params value. 380 * 381 * The values that are not in dwc2_core_params are documented below. 382 * 383 * @op_mode Mode of Operation 384 * 0 - HNP- and SRP-Capable OTG (Host & Device) 385 * 1 - SRP-Capable OTG (Host & Device) 386 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 387 * 3 - SRP-Capable Device 388 * 4 - Non-OTG Device 389 * 5 - SRP-Capable Host 390 * 6 - Non-OTG Host 391 * @arch Architecture 392 * 0 - Slave only 393 * 1 - External DMA 394 * 2 - Internal DMA 395 * @power_optimized Are power optimizations enabled? 396 * @num_dev_ep Number of device endpoints available 397 * @num_dev_perio_in_ep Number of device periodic IN endpoints 398 * available 399 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue 400 * Depth 401 * 0 to 30 402 * @host_perio_tx_q_depth 403 * Host Mode Periodic Request Queue Depth 404 * 2, 4 or 8 405 * @nperio_tx_q_depth 406 * Non-Periodic Request Queue Depth 407 * 2, 4 or 8 408 * @hs_phy_type High-speed PHY interface type 409 * 0 - High-speed interface not supported 410 * 1 - UTMI+ 411 * 2 - ULPI 412 * 3 - UTMI+ and ULPI 413 * @fs_phy_type Full-speed PHY interface type 414 * 0 - Full speed interface not supported 415 * 1 - Dedicated full speed interface 416 * 2 - FS pins shared with UTMI+ pins 417 * 3 - FS pins shared with ULPI pins 418 * @total_fifo_size: Total internal RAM for FIFOs (bytes) 419 * @utmi_phy_data_width UTMI+ PHY data width 420 * 0 - 8 bits 421 * 1 - 16 bits 422 * 2 - 8 or 16 bits 423 * @snpsid: Value from SNPSID register 424 */ 425 struct dwc2_hw_params { 426 unsigned op_mode:3; 427 unsigned arch:2; 428 unsigned dma_desc_enable:1; 429 unsigned enable_dynamic_fifo:1; 430 unsigned en_multiple_tx_fifo:1; 431 unsigned host_rx_fifo_size:16; 432 unsigned host_nperio_tx_fifo_size:16; 433 unsigned host_perio_tx_fifo_size:16; 434 unsigned nperio_tx_q_depth:3; 435 unsigned host_perio_tx_q_depth:3; 436 unsigned dev_token_q_depth:5; 437 unsigned max_transfer_size:26; 438 unsigned max_packet_count:11; 439 unsigned host_channels:5; 440 unsigned hs_phy_type:2; 441 unsigned fs_phy_type:2; 442 unsigned i2c_enable:1; 443 unsigned num_dev_ep:4; 444 unsigned num_dev_perio_in_ep:4; 445 unsigned total_fifo_size:16; 446 unsigned power_optimized:1; 447 unsigned utmi_phy_data_width:2; 448 u32 snpsid; 449 }; 450 451 /* Size of control and EP0 buffers */ 452 #define DWC2_CTRL_BUFF_SIZE 8 453 454 /** 455 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 456 * and periodic schedules 457 * 458 * These are common for both host and peripheral modes: 459 * 460 * @dev: The struct device pointer 461 * @regs: Pointer to controller regs 462 * @hw_params: Parameters that were autodetected from the 463 * hardware registers 464 * @core_params: Parameters that define how the core should be configured 465 * @op_state: The operational State, during transitions (a_host=> 466 * a_peripheral and b_device=>b_host) this may not match 467 * the core, but allows the software to determine 468 * transitions 469 * @dr_mode: Requested mode of operation, one of following: 470 * - USB_DR_MODE_PERIPHERAL 471 * - USB_DR_MODE_HOST 472 * - USB_DR_MODE_OTG 473 * @lock: Spinlock that protects all the driver data structures 474 * @priv: Stores a pointer to the struct usb_hcd 475 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 476 * transfer are in process of being queued 477 * @srp_success: Stores status of SRP request in the case of a FS PHY 478 * with an I2C interface 479 * @wq_otg: Workqueue object used for handling of some interrupts 480 * @wf_otg: Work object for handling Connector ID Status Change 481 * interrupt 482 * @wkp_timer: Timer object for handling Wakeup Detected interrupt 483 * @lx_state: Lx state of connected device 484 * 485 * These are for host mode: 486 * 487 * @flags: Flags for handling root port state changes 488 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 489 * Transfers associated with these QHs are not currently 490 * assigned to a host channel. 491 * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 492 * Transfers associated with these QHs are currently 493 * assigned to a host channel. 494 * @non_periodic_qh_ptr: Pointer to next QH to process in the active 495 * non-periodic schedule 496 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 497 * list of QHs for periodic transfers that are _not_ 498 * scheduled for the next frame. Each QH in the list has an 499 * interval counter that determines when it needs to be 500 * scheduled for execution. This scheduling mechanism 501 * allows only a simple calculation for periodic bandwidth 502 * used (i.e. must assume that all periodic transfers may 503 * need to execute in the same frame). However, it greatly 504 * simplifies scheduling and should be sufficient for the 505 * vast majority of OTG hosts, which need to connect to a 506 * small number of peripherals at one time. Items move from 507 * this list to periodic_sched_ready when the QH interval 508 * counter is 0 at SOF. 509 * @periodic_sched_ready: List of periodic QHs that are ready for execution in 510 * the next frame, but have not yet been assigned to host 511 * channels. Items move from this list to 512 * periodic_sched_assigned as host channels become 513 * available during the current frame. 514 * @periodic_sched_assigned: List of periodic QHs to be executed in the next 515 * frame that are assigned to host channels. Items move 516 * from this list to periodic_sched_queued as the 517 * transactions for the QH are queued to the DWC_otg 518 * controller. 519 * @periodic_sched_queued: List of periodic QHs that have been queued for 520 * execution. Items move from this list to either 521 * periodic_sched_inactive or periodic_sched_ready when the 522 * channel associated with the transfer is released. If the 523 * interval for the QH is 1, the item moves to 524 * periodic_sched_ready because it must be rescheduled for 525 * the next frame. Otherwise, the item moves to 526 * periodic_sched_inactive. 527 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 528 * This value is in microseconds per (micro)frame. The 529 * assumption is that all periodic transfers may occur in 530 * the same (micro)frame. 531 * @frame_usecs: Internal variable used by the microframe scheduler 532 * @frame_number: Frame number read from the core at SOF. The value ranges 533 * from 0 to HFNUM_MAX_FRNUM. 534 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 535 * SOF enable/disable. 536 * @free_hc_list: Free host channels in the controller. This is a list of 537 * struct dwc2_host_chan items. 538 * @periodic_channels: Number of host channels assigned to periodic transfers. 539 * Currently assuming that there is a dedicated host 540 * channel for each periodic transaction and at least one 541 * host channel is available for non-periodic transactions. 542 * @non_periodic_channels: Number of host channels assigned to non-periodic 543 * transfers 544 * @available_host_channels Number of host channels available for the microframe 545 * scheduler to use 546 * @hc_ptr_array: Array of pointers to the host channel descriptors. 547 * Allows accessing a host channel descriptor given the 548 * host channel number. This is useful in interrupt 549 * handlers. 550 * @status_buf: Buffer used for data received during the status phase of 551 * a control transfer. 552 * @status_buf_dma: DMA address for status_buf 553 * @start_work: Delayed work for handling host A-cable connection 554 * @reset_work: Delayed work for handling a port reset 555 * @otg_port: OTG port number 556 * @frame_list: Frame list 557 * @frame_list_dma: Frame list DMA address 558 * 559 * These are for peripheral mode: 560 * 561 * @driver: USB gadget driver 562 * @phy: The otg phy transceiver structure for phy control. 563 * @uphy: The otg phy transceiver structure for old USB phy control. 564 * @plat: The platform specific configuration data. This can be removed once 565 * all SoCs support usb transceiver. 566 * @supplies: Definition of USB power supplies 567 * @phyif: PHY interface width 568 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 569 * @num_of_eps: Number of available EPs (excluding EP0) 570 * @debug_root: Root directrory for debugfs. 571 * @debug_file: Main status file for debugfs. 572 * @debug_testmode: Testmode status file for debugfs. 573 * @debug_fifo: FIFO status file for debugfs. 574 * @ep0_reply: Request used for ep0 reply. 575 * @ep0_buff: Buffer for EP0 reply data, if needed. 576 * @ctrl_buff: Buffer for EP0 control requests. 577 * @ctrl_req: Request for EP0 control packets. 578 * @ep0_state: EP0 control transfers state 579 * @test_mode: USB test mode requested by the host 580 * @last_rst: Time of last reset 581 * @eps: The endpoints being supplied to the gadget framework 582 * @g_using_dma: Indicate if dma usage is enabled 583 * @g_rx_fifo_sz: Contains rx fifo size value 584 * @g_np_g_tx_fifo_sz: Contains Non-Periodic tx fifo size value 585 * @g_tx_fifo_sz: Contains tx fifo size value per endpoints 586 */ 587 struct dwc2_hsotg { 588 struct device *dev; 589 void __iomem *regs; 590 /** Params detected from hardware */ 591 struct dwc2_hw_params hw_params; 592 /** Params to actually use */ 593 struct dwc2_core_params *core_params; 594 enum usb_otg_state op_state; 595 enum usb_dr_mode dr_mode; 596 unsigned int hcd_enabled:1; 597 unsigned int gadget_enabled:1; 598 599 struct phy *phy; 600 struct usb_phy *uphy; 601 struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsotg_supply_names)]; 602 603 spinlock_t lock; 604 struct mutex init_mutex; 605 void *priv; 606 int irq; 607 struct clk *clk; 608 609 unsigned int queuing_high_bandwidth:1; 610 unsigned int srp_success:1; 611 612 struct workqueue_struct *wq_otg; 613 struct work_struct wf_otg; 614 struct timer_list wkp_timer; 615 enum dwc2_lx_state lx_state; 616 617 struct dentry *debug_root; 618 struct dentry *debug_file; 619 struct dentry *debug_testmode; 620 struct dentry *debug_fifo; 621 622 /* DWC OTG HW Release versions */ 623 #define DWC2_CORE_REV_2_71a 0x4f54271a 624 #define DWC2_CORE_REV_2_90a 0x4f54290a 625 #define DWC2_CORE_REV_2_92a 0x4f54292a 626 #define DWC2_CORE_REV_2_94a 0x4f54294a 627 #define DWC2_CORE_REV_3_00a 0x4f54300a 628 629 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 630 union dwc2_hcd_internal_flags { 631 u32 d32; 632 struct { 633 unsigned port_connect_status_change:1; 634 unsigned port_connect_status:1; 635 unsigned port_reset_change:1; 636 unsigned port_enable_change:1; 637 unsigned port_suspend_change:1; 638 unsigned port_over_current_change:1; 639 unsigned port_l1_change:1; 640 unsigned reserved:25; 641 } b; 642 } flags; 643 644 struct list_head non_periodic_sched_inactive; 645 struct list_head non_periodic_sched_active; 646 struct list_head *non_periodic_qh_ptr; 647 struct list_head periodic_sched_inactive; 648 struct list_head periodic_sched_ready; 649 struct list_head periodic_sched_assigned; 650 struct list_head periodic_sched_queued; 651 u16 periodic_usecs; 652 u16 frame_usecs[8]; 653 u16 frame_number; 654 u16 periodic_qh_count; 655 656 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 657 #define FRAME_NUM_ARRAY_SIZE 1000 658 u16 last_frame_num; 659 u16 *frame_num_array; 660 u16 *last_frame_num_array; 661 int frame_num_idx; 662 int dumped_frame_num_array; 663 #endif 664 665 struct list_head free_hc_list; 666 int periodic_channels; 667 int non_periodic_channels; 668 int available_host_channels; 669 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 670 u8 *status_buf; 671 dma_addr_t status_buf_dma; 672 #define DWC2_HCD_STATUS_BUF_SIZE 64 673 674 struct delayed_work start_work; 675 struct delayed_work reset_work; 676 u8 otg_port; 677 u32 *frame_list; 678 dma_addr_t frame_list_dma; 679 680 #ifdef DEBUG 681 u32 frrem_samples; 682 u64 frrem_accum; 683 684 u32 hfnum_7_samples_a; 685 u64 hfnum_7_frrem_accum_a; 686 u32 hfnum_0_samples_a; 687 u64 hfnum_0_frrem_accum_a; 688 u32 hfnum_other_samples_a; 689 u64 hfnum_other_frrem_accum_a; 690 691 u32 hfnum_7_samples_b; 692 u64 hfnum_7_frrem_accum_b; 693 u32 hfnum_0_samples_b; 694 u64 hfnum_0_frrem_accum_b; 695 u32 hfnum_other_samples_b; 696 u64 hfnum_other_frrem_accum_b; 697 #endif 698 #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ 699 700 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 701 /* Gadget structures */ 702 struct usb_gadget_driver *driver; 703 struct s3c_hsotg_plat *plat; 704 705 u32 phyif; 706 int fifo_mem; 707 unsigned int dedicated_fifos:1; 708 unsigned char num_of_eps; 709 u32 fifo_map; 710 711 struct usb_request *ep0_reply; 712 struct usb_request *ctrl_req; 713 void *ep0_buff; 714 void *ctrl_buff; 715 enum dwc2_ep0_state ep0_state; 716 u8 test_mode; 717 718 struct usb_gadget gadget; 719 unsigned int enabled:1; 720 unsigned int connected:1; 721 unsigned long last_rst; 722 struct s3c_hsotg_ep *eps_in[MAX_EPS_CHANNELS]; 723 struct s3c_hsotg_ep *eps_out[MAX_EPS_CHANNELS]; 724 u32 g_using_dma; 725 u32 g_rx_fifo_sz; 726 u32 g_np_g_tx_fifo_sz; 727 u32 g_tx_fifo_sz[MAX_EPS_CHANNELS]; 728 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 729 }; 730 731 /* Reasons for halting a host channel */ 732 enum dwc2_halt_status { 733 DWC2_HC_XFER_NO_HALT_STATUS, 734 DWC2_HC_XFER_COMPLETE, 735 DWC2_HC_XFER_URB_COMPLETE, 736 DWC2_HC_XFER_ACK, 737 DWC2_HC_XFER_NAK, 738 DWC2_HC_XFER_NYET, 739 DWC2_HC_XFER_STALL, 740 DWC2_HC_XFER_XACT_ERR, 741 DWC2_HC_XFER_FRAME_OVERRUN, 742 DWC2_HC_XFER_BABBLE_ERR, 743 DWC2_HC_XFER_DATA_TOGGLE_ERR, 744 DWC2_HC_XFER_AHB_ERR, 745 DWC2_HC_XFER_PERIODIC_INCOMPLETE, 746 DWC2_HC_XFER_URB_DEQUEUE, 747 }; 748 749 /* 750 * The following functions support initialization of the core driver component 751 * and the DWC_otg controller 752 */ 753 extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg); 754 755 /* 756 * Host core Functions. 757 * The following functions support managing the DWC_otg controller in host 758 * mode. 759 */ 760 extern void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan); 761 extern void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 762 enum dwc2_halt_status halt_status); 763 extern void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, 764 struct dwc2_host_chan *chan); 765 extern void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 766 struct dwc2_host_chan *chan); 767 extern void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 768 struct dwc2_host_chan *chan); 769 extern int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 770 struct dwc2_host_chan *chan); 771 extern void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, 772 struct dwc2_host_chan *chan); 773 extern void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg); 774 extern void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg); 775 776 extern u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg); 777 extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 778 779 /* 780 * Common core Functions. 781 * The following functions support managing the DWC_otg controller in either 782 * device or host mode. 783 */ 784 extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 785 extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 786 extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 787 788 extern int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq); 789 extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 790 extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 791 792 /* This function should be called on every hardware interrupt. */ 793 extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 794 795 /* OTG Core Parameters */ 796 797 /* 798 * Specifies the OTG capabilities. The driver will automatically 799 * detect the value for this parameter if none is specified. 800 * 0 - HNP and SRP capable (default) 801 * 1 - SRP Only capable 802 * 2 - No HNP/SRP capable 803 */ 804 extern void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val); 805 #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 806 #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 807 #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 808 809 /* 810 * Specifies whether to use slave or DMA mode for accessing the data 811 * FIFOs. The driver will automatically detect the value for this 812 * parameter if none is specified. 813 * 0 - Slave 814 * 1 - DMA (default, if available) 815 */ 816 extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val); 817 818 /* 819 * When DMA mode is enabled specifies whether to use 820 * address DMA or DMA Descritor mode for accessing the data 821 * FIFOs in device mode. The driver will automatically detect 822 * the value for this parameter if none is specified. 823 * 0 - address DMA 824 * 1 - DMA Descriptor(default, if available) 825 */ 826 extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val); 827 828 /* 829 * Specifies the maximum speed of operation in host and device mode. 830 * The actual speed depends on the speed of the attached device and 831 * the value of phy_type. The actual speed depends on the speed of the 832 * attached device. 833 * 0 - High Speed (default) 834 * 1 - Full Speed 835 */ 836 extern void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val); 837 #define DWC2_SPEED_PARAM_HIGH 0 838 #define DWC2_SPEED_PARAM_FULL 1 839 840 /* 841 * Specifies whether low power mode is supported when attached 842 * to a Full Speed or Low Speed device in host mode. 843 * 844 * 0 - Don't support low power mode (default) 845 * 1 - Support low power mode 846 */ 847 extern void dwc2_set_param_host_support_fs_ls_low_power( 848 struct dwc2_hsotg *hsotg, int val); 849 850 /* 851 * Specifies the PHY clock rate in low power mode when connected to a 852 * Low Speed device in host mode. This parameter is applicable only if 853 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS 854 * then defaults to 6 MHZ otherwise 48 MHZ. 855 * 856 * 0 - 48 MHz 857 * 1 - 6 MHz 858 */ 859 extern void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, 860 int val); 861 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 862 #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 863 864 /* 865 * 0 - Use cC FIFO size parameters 866 * 1 - Allow dynamic FIFO sizing (default) 867 */ 868 extern void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, 869 int val); 870 871 /* 872 * Number of 4-byte words in the Rx FIFO in host mode when dynamic 873 * FIFO sizing is enabled. 874 * 16 to 32768 (default 1024) 875 */ 876 extern void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val); 877 878 /* 879 * Number of 4-byte words in the non-periodic Tx FIFO in host mode 880 * when Dynamic FIFO sizing is enabled in the core. 881 * 16 to 32768 (default 256) 882 */ 883 extern void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, 884 int val); 885 886 /* 887 * Number of 4-byte words in the host periodic Tx FIFO when dynamic 888 * FIFO sizing is enabled. 889 * 16 to 32768 (default 256) 890 */ 891 extern void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, 892 int val); 893 894 /* 895 * The maximum transfer size supported in bytes. 896 * 2047 to 65,535 (default 65,535) 897 */ 898 extern void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val); 899 900 /* 901 * The maximum number of packets in a transfer. 902 * 15 to 511 (default 511) 903 */ 904 extern void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val); 905 906 /* 907 * The number of host channel registers to use. 908 * 1 to 16 (default 11) 909 * Note: The FPGA configuration supports a maximum of 11 host channels. 910 */ 911 extern void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val); 912 913 /* 914 * Specifies the type of PHY interface to use. By default, the driver 915 * will automatically detect the phy_type. 916 * 917 * 0 - Full Speed PHY 918 * 1 - UTMI+ (default) 919 * 2 - ULPI 920 */ 921 extern void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val); 922 #define DWC2_PHY_TYPE_PARAM_FS 0 923 #define DWC2_PHY_TYPE_PARAM_UTMI 1 924 #define DWC2_PHY_TYPE_PARAM_ULPI 2 925 926 /* 927 * Specifies the UTMI+ Data Width. This parameter is 928 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI 929 * PHY_TYPE, this parameter indicates the data width between 930 * the MAC and the ULPI Wrapper.) Also, this parameter is 931 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set 932 * to "8 and 16 bits", meaning that the core has been 933 * configured to work at either data path width. 934 * 935 * 8 or 16 bits (default 16) 936 */ 937 extern void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val); 938 939 /* 940 * Specifies whether the ULPI operates at double or single 941 * data rate. This parameter is only applicable if PHY_TYPE is 942 * ULPI. 943 * 944 * 0 - single data rate ULPI interface with 8 bit wide data 945 * bus (default) 946 * 1 - double data rate ULPI interface with 4 bit wide data 947 * bus 948 */ 949 extern void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val); 950 951 /* 952 * Specifies whether to use the internal or external supply to 953 * drive the vbus with a ULPI phy. 954 */ 955 extern void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val); 956 #define DWC2_PHY_ULPI_INTERNAL_VBUS 0 957 #define DWC2_PHY_ULPI_EXTERNAL_VBUS 1 958 959 /* 960 * Specifies whether to use the I2Cinterface for full speed PHY. This 961 * parameter is only applicable if PHY_TYPE is FS. 962 * 0 - No (default) 963 * 1 - Yes 964 */ 965 extern void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val); 966 967 extern void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val); 968 969 extern void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val); 970 971 /* 972 * Specifies whether dedicated transmit FIFOs are 973 * enabled for non periodic IN endpoints in device mode 974 * 0 - No 975 * 1 - Yes 976 */ 977 extern void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, 978 int val); 979 980 extern void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val); 981 982 extern void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val); 983 984 extern void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val); 985 986 /* 987 * Dump core registers and SPRAM 988 */ 989 extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 990 extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 991 extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 992 993 /* 994 * Return OTG version - either 1.3 or 2.0 995 */ 996 extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg); 997 998 /* Gadget defines */ 999 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1000 extern int s3c_hsotg_remove(struct dwc2_hsotg *hsotg); 1001 extern int s3c_hsotg_suspend(struct dwc2_hsotg *dwc2); 1002 extern int s3c_hsotg_resume(struct dwc2_hsotg *dwc2); 1003 extern int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq); 1004 extern void s3c_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1005 bool reset); 1006 extern void s3c_hsotg_core_connect(struct dwc2_hsotg *hsotg); 1007 extern void s3c_hsotg_disconnect(struct dwc2_hsotg *dwc2); 1008 #else 1009 static inline int s3c_hsotg_remove(struct dwc2_hsotg *dwc2) 1010 { return 0; } 1011 static inline int s3c_hsotg_suspend(struct dwc2_hsotg *dwc2) 1012 { return 0; } 1013 static inline int s3c_hsotg_resume(struct dwc2_hsotg *dwc2) 1014 { return 0; } 1015 static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) 1016 { return 0; } 1017 static inline void s3c_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1018 bool reset) {} 1019 static inline void s3c_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} 1020 static inline void s3c_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} 1021 #endif 1022 1023 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1024 extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 1025 extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg); 1026 extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 1027 #else 1028 static inline void dwc2_set_all_params(struct dwc2_core_params *params, int value) {} 1029 static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1030 { return 0; } 1031 static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg) {} 1032 static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} 1033 static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} 1034 static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq, 1035 const struct dwc2_core_params *params) 1036 { return 0; } 1037 #endif 1038 1039 #endif /* __DWC2_CORE_H__ */ 1040