1 /* 2 * core.h - DesignWare HS OTG Controller common declarations 3 * 4 * Copyright (C) 2004-2013 Synopsys, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The names of the above-listed copyright holders may not be used 16 * to endorse or promote products derived from this software without 17 * specific prior written permission. 18 * 19 * ALTERNATIVELY, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") as published by the Free Software 21 * Foundation; either version 2 of the License, or (at your option) any 22 * later version. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #ifndef __DWC2_CORE_H__ 38 #define __DWC2_CORE_H__ 39 40 #include <linux/phy/phy.h> 41 #include <linux/regulator/consumer.h> 42 #include <linux/usb/gadget.h> 43 #include <linux/usb/otg.h> 44 #include <linux/usb/phy.h> 45 #include "hw.h" 46 47 /* 48 * Suggested defines for tracers: 49 * - no_printk: Disable tracing 50 * - pr_info: Print this info to the console 51 * - trace_printk: Print this info to trace buffer (good for verbose logging) 52 */ 53 54 #define DWC2_TRACE_SCHEDULER no_printk 55 #define DWC2_TRACE_SCHEDULER_VB no_printk 56 57 /* Detailed scheduler tracing, but won't overwhelm console */ 58 #define dwc2_sch_dbg(hsotg, fmt, ...) \ 59 DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \ 60 dev_name(hsotg->dev), ##__VA_ARGS__) 61 62 /* Verbose scheduler tracing */ 63 #define dwc2_sch_vdbg(hsotg, fmt, ...) \ 64 DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \ 65 dev_name(hsotg->dev), ##__VA_ARGS__) 66 67 #ifdef CONFIG_MIPS 68 /* 69 * There are some MIPS machines that can run in either big-endian 70 * or little-endian mode and that use the dwc2 register without 71 * a byteswap in both ways. 72 * Unlike other architectures, MIPS apparently does not require a 73 * barrier before the __raw_writel() to synchronize with DMA but does 74 * require the barrier after the __raw_writel() to serialize a set of 75 * writes. This set of operations was added specifically for MIPS and 76 * should only be used there. 77 */ 78 static inline u32 dwc2_readl(const void __iomem *addr) 79 { 80 u32 value = __raw_readl(addr); 81 82 /* In order to preserve endianness __raw_* operation is used. Therefore 83 * a barrier is needed to ensure IO access is not re-ordered across 84 * reads or writes 85 */ 86 mb(); 87 return value; 88 } 89 90 static inline void dwc2_writel(u32 value, void __iomem *addr) 91 { 92 __raw_writel(value, addr); 93 94 /* 95 * In order to preserve endianness __raw_* operation is used. Therefore 96 * a barrier is needed to ensure IO access is not re-ordered across 97 * reads or writes 98 */ 99 mb(); 100 #ifdef DWC2_LOG_WRITES 101 pr_info("INFO:: wrote %08x to %p\n", value, addr); 102 #endif 103 } 104 #else 105 /* Normal architectures just use readl/write */ 106 static inline u32 dwc2_readl(const void __iomem *addr) 107 { 108 return readl(addr); 109 } 110 111 static inline void dwc2_writel(u32 value, void __iomem *addr) 112 { 113 writel(value, addr); 114 115 #ifdef DWC2_LOG_WRITES 116 pr_info("info:: wrote %08x to %p\n", value, addr); 117 #endif 118 } 119 #endif 120 121 /* Maximum number of Endpoints/HostChannels */ 122 #define MAX_EPS_CHANNELS 16 123 124 /* dwc2-hsotg declarations */ 125 static const char * const dwc2_hsotg_supply_names[] = { 126 "vusb_d", /* digital USB supply, 1.2V */ 127 "vusb_a", /* analog USB supply, 1.1V */ 128 }; 129 130 #define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names) 131 132 /* 133 * EP0_MPS_LIMIT 134 * 135 * Unfortunately there seems to be a limit of the amount of data that can 136 * be transferred by IN transactions on EP0. This is either 127 bytes or 3 137 * packets (which practically means 1 packet and 63 bytes of data) when the 138 * MPS is set to 64. 139 * 140 * This means if we are wanting to move >127 bytes of data, we need to 141 * split the transactions up, but just doing one packet at a time does 142 * not work (this may be an implicit DATA0 PID on first packet of the 143 * transaction) and doing 2 packets is outside the controller's limits. 144 * 145 * If we try to lower the MPS size for EP0, then no transfers work properly 146 * for EP0, and the system will fail basic enumeration. As no cause for this 147 * has currently been found, we cannot support any large IN transfers for 148 * EP0. 149 */ 150 #define EP0_MPS_LIMIT 64 151 152 struct dwc2_hsotg; 153 struct dwc2_hsotg_req; 154 155 /** 156 * struct dwc2_hsotg_ep - driver endpoint definition. 157 * @ep: The gadget layer representation of the endpoint. 158 * @name: The driver generated name for the endpoint. 159 * @queue: Queue of requests for this endpoint. 160 * @parent: Reference back to the parent device structure. 161 * @req: The current request that the endpoint is processing. This is 162 * used to indicate an request has been loaded onto the endpoint 163 * and has yet to be completed (maybe due to data move, or simply 164 * awaiting an ack from the core all the data has been completed). 165 * @debugfs: File entry for debugfs file for this endpoint. 166 * @lock: State lock to protect contents of endpoint. 167 * @dir_in: Set to true if this endpoint is of the IN direction, which 168 * means that it is sending data to the Host. 169 * @index: The index for the endpoint registers. 170 * @mc: Multi Count - number of transactions per microframe 171 * @interval - Interval for periodic endpoints, in frames or microframes. 172 * @name: The name array passed to the USB core. 173 * @halted: Set if the endpoint has been halted. 174 * @periodic: Set if this is a periodic ep, such as Interrupt 175 * @isochronous: Set if this is a isochronous ep 176 * @send_zlp: Set if we need to send a zero-length packet. 177 * @desc_list_dma: The DMA address of descriptor chain currently in use. 178 * @desc_list: Pointer to descriptor DMA chain head currently in use. 179 * @desc_count: Count of entries within the DMA descriptor chain of EP. 180 * @isoc_chain_num: Number of ISOC chain currently in use - either 0 or 1. 181 * @next_desc: index of next free descriptor in the ISOC chain under SW control. 182 * @total_data: The total number of data bytes done. 183 * @fifo_size: The size of the FIFO (for periodic IN endpoints) 184 * @fifo_load: The amount of data loaded into the FIFO (periodic IN) 185 * @last_load: The offset of data for the last start of request. 186 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN 187 * @target_frame: Targeted frame num to setup next ISOC transfer 188 * @frame_overrun: Indicates SOF number overrun in DSTS 189 * 190 * This is the driver's state for each registered enpoint, allowing it 191 * to keep track of transactions that need doing. Each endpoint has a 192 * lock to protect the state, to try and avoid using an overall lock 193 * for the host controller as much as possible. 194 * 195 * For periodic IN endpoints, we have fifo_size and fifo_load to try 196 * and keep track of the amount of data in the periodic FIFO for each 197 * of these as we don't have a status register that tells us how much 198 * is in each of them. (note, this may actually be useless information 199 * as in shared-fifo mode periodic in acts like a single-frame packet 200 * buffer than a fifo) 201 */ 202 struct dwc2_hsotg_ep { 203 struct usb_ep ep; 204 struct list_head queue; 205 struct dwc2_hsotg *parent; 206 struct dwc2_hsotg_req *req; 207 struct dentry *debugfs; 208 209 unsigned long total_data; 210 unsigned int size_loaded; 211 unsigned int last_load; 212 unsigned int fifo_load; 213 unsigned short fifo_size; 214 unsigned short fifo_index; 215 216 unsigned char dir_in; 217 unsigned char index; 218 unsigned char mc; 219 unsigned char interval; 220 221 unsigned int halted:1; 222 unsigned int periodic:1; 223 unsigned int isochronous:1; 224 unsigned int send_zlp:1; 225 unsigned int target_frame; 226 #define TARGET_FRAME_INITIAL 0xFFFFFFFF 227 bool frame_overrun; 228 229 dma_addr_t desc_list_dma; 230 struct dwc2_dma_desc *desc_list; 231 u8 desc_count; 232 233 unsigned char isoc_chain_num; 234 unsigned int next_desc; 235 236 char name[10]; 237 }; 238 239 /** 240 * struct dwc2_hsotg_req - data transfer request 241 * @req: The USB gadget request 242 * @queue: The list of requests for the endpoint this is queued for. 243 * @saved_req_buf: variable to save req.buf when bounce buffers are used. 244 */ 245 struct dwc2_hsotg_req { 246 struct usb_request req; 247 struct list_head queue; 248 void *saved_req_buf; 249 }; 250 251 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 252 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 253 #define call_gadget(_hs, _entry) \ 254 do { \ 255 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ 256 (_hs)->driver && (_hs)->driver->_entry) { \ 257 spin_unlock(&_hs->lock); \ 258 (_hs)->driver->_entry(&(_hs)->gadget); \ 259 spin_lock(&_hs->lock); \ 260 } \ 261 } while (0) 262 #else 263 #define call_gadget(_hs, _entry) do {} while (0) 264 #endif 265 266 struct dwc2_hsotg; 267 struct dwc2_host_chan; 268 269 /* Device States */ 270 enum dwc2_lx_state { 271 DWC2_L0, /* On state */ 272 DWC2_L1, /* LPM sleep state */ 273 DWC2_L2, /* USB suspend state */ 274 DWC2_L3, /* Off state */ 275 }; 276 277 /* Gadget ep0 states */ 278 enum dwc2_ep0_state { 279 DWC2_EP0_SETUP, 280 DWC2_EP0_DATA_IN, 281 DWC2_EP0_DATA_OUT, 282 DWC2_EP0_STATUS_IN, 283 DWC2_EP0_STATUS_OUT, 284 }; 285 286 /** 287 * struct dwc2_core_params - Parameters for configuring the core 288 * 289 * @otg_cap: Specifies the OTG capabilities. 290 * 0 - HNP and SRP capable 291 * 1 - SRP Only capable 292 * 2 - No HNP/SRP capable (always available) 293 * Defaults to best available option (0, 1, then 2) 294 * @host_dma: Specifies whether to use slave or DMA mode for accessing 295 * the data FIFOs. The driver will automatically detect the 296 * value for this parameter if none is specified. 297 * 0 - Slave (always available) 298 * 1 - DMA (default, if available) 299 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 300 * address DMA mode or descriptor DMA mode for accessing 301 * the data FIFOs. The driver will automatically detect the 302 * value for this if none is specified. 303 * 0 - Address DMA 304 * 1 - Descriptor DMA (default, if available) 305 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use 306 * address DMA mode or descriptor DMA mode for accessing 307 * the data FIFOs in Full Speed mode only. The driver 308 * will automatically detect the value for this if none is 309 * specified. 310 * 0 - Address DMA 311 * 1 - Descriptor DMA in FS (default, if available) 312 * @speed: Specifies the maximum speed of operation in host and 313 * device mode. The actual speed depends on the speed of 314 * the attached device and the value of phy_type. 315 * 0 - High Speed 316 * (default when phy_type is UTMI+ or ULPI) 317 * 1 - Full Speed 318 * (default when phy_type is Full Speed) 319 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 320 * 1 - Allow dynamic FIFO sizing (default, if available) 321 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 322 * are enabled for non-periodic IN endpoints in device 323 * mode. 324 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 325 * dynamic FIFO sizing is enabled 326 * 16 to 32768 327 * Actual maximum value is autodetected and also 328 * the default. 329 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 330 * in host mode when dynamic FIFO sizing is enabled 331 * 16 to 32768 332 * Actual maximum value is autodetected and also 333 * the default. 334 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 335 * host mode when dynamic FIFO sizing is enabled 336 * 16 to 32768 337 * Actual maximum value is autodetected and also 338 * the default. 339 * @max_transfer_size: The maximum transfer size supported, in bytes 340 * 2047 to 65,535 341 * Actual maximum value is autodetected and also 342 * the default. 343 * @max_packet_count: The maximum number of packets in a transfer 344 * 15 to 511 345 * Actual maximum value is autodetected and also 346 * the default. 347 * @host_channels: The number of host channel registers to use 348 * 1 to 16 349 * Actual maximum value is autodetected and also 350 * the default. 351 * @phy_type: Specifies the type of PHY interface to use. By default, 352 * the driver will automatically detect the phy_type. 353 * 0 - Full Speed Phy 354 * 1 - UTMI+ Phy 355 * 2 - ULPI Phy 356 * Defaults to best available option (2, 1, then 0) 357 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 358 * is applicable for a phy_type of UTMI+ or ULPI. (For a 359 * ULPI phy_type, this parameter indicates the data width 360 * between the MAC and the ULPI Wrapper.) Also, this 361 * parameter is applicable only if the OTG_HSPHY_WIDTH cC 362 * parameter was set to "8 and 16 bits", meaning that the 363 * core has been configured to work at either data path 364 * width. 365 * 8 or 16 (default 16 if available) 366 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 367 * data rate. This parameter is only applicable if phy_type 368 * is ULPI. 369 * 0 - single data rate ULPI interface with 8 bit wide 370 * data bus (default) 371 * 1 - double data rate ULPI interface with 4 bit wide 372 * data bus 373 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 374 * external supply to drive the VBus 375 * 0 - Internal supply (default) 376 * 1 - External supply 377 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 378 * speed PHY. This parameter is only applicable if phy_type 379 * is FS. 380 * 0 - No (default) 381 * 1 - Yes 382 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 383 * 0 - No (default) 384 * 1 - Yes 385 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 386 * when attached to a Full Speed or Low Speed device in 387 * host mode. 388 * 0 - Don't support low power mode (default) 389 * 1 - Support low power mode 390 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 391 * when connected to a Low Speed device in host 392 * mode. This parameter is applicable only if 393 * host_support_fs_ls_low_power is enabled. 394 * 0 - 48 MHz 395 * (default when phy_type is UTMI+ or ULPI) 396 * 1 - 6 MHz 397 * (default when phy_type is Full Speed) 398 * @ts_dline: Enable Term Select Dline pulsing 399 * 0 - No (default) 400 * 1 - Yes 401 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 402 * 0 - No (default for core < 2.92a) 403 * 1 - Yes (default for core >= 2.92a) 404 * @ahbcfg: This field allows the default value of the GAHBCFG 405 * register to be overridden 406 * -1 - GAHBCFG value will be set to 0x06 407 * (INCR4, default) 408 * all others - GAHBCFG value will be overridden with 409 * this value 410 * Not all bits can be controlled like this, the 411 * bits defined by GAHBCFG_CTRL_MASK are controlled 412 * by the driver and are ignored in this 413 * configuration value. 414 * @uframe_sched: True to enable the microframe scheduler 415 * @external_id_pin_ctl: Specifies whether ID pin is handled externally. 416 * Disable CONIDSTSCHNG controller interrupt in such 417 * case. 418 * 0 - No (default) 419 * 1 - Yes 420 * @hibernation: Specifies whether the controller support hibernation. 421 * If hibernation is enabled, the controller will enter 422 * hibernation in both peripheral and host mode when 423 * needed. 424 * 0 - No (default) 425 * 1 - Yes 426 * @g_dma: Enables gadget dma usage (default: autodetect). 427 * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect). 428 * @g_rx_fifo_size: The periodic rx fifo size for the device, in 429 * DWORDS from 16-32768 (default: 2048 if 430 * possible, otherwise autodetect). 431 * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in 432 * DWORDS from 16-32768 (default: 1024 if 433 * possible, otherwise autodetect). 434 * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo 435 * mode. Each value corresponds to one EP 436 * starting from EP1 (max 15 values). Sizes are 437 * in DWORDS with possible values from from 438 * 16-32768 (default: 256, 256, 256, 256, 768, 439 * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0). 440 * @change_speed_quirk: Change speed configuration to DWC2_SPEED_PARAM_FULL 441 * while full&low speed device connect. And change speed 442 * back to DWC2_SPEED_PARAM_HIGH while device is gone. 443 * 0 - No (default) 444 * 1 - Yes 445 * 446 * The following parameters may be specified when starting the module. These 447 * parameters define how the DWC_otg controller should be configured. A 448 * value of -1 (or any other out of range value) for any parameter means 449 * to read the value from hardware (if possible) or use the builtin 450 * default described above. 451 */ 452 struct dwc2_core_params { 453 u8 otg_cap; 454 #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 455 #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 456 #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 457 458 u8 phy_type; 459 #define DWC2_PHY_TYPE_PARAM_FS 0 460 #define DWC2_PHY_TYPE_PARAM_UTMI 1 461 #define DWC2_PHY_TYPE_PARAM_ULPI 2 462 463 u8 speed; 464 #define DWC2_SPEED_PARAM_HIGH 0 465 #define DWC2_SPEED_PARAM_FULL 1 466 #define DWC2_SPEED_PARAM_LOW 2 467 468 u8 phy_utmi_width; 469 bool phy_ulpi_ddr; 470 bool phy_ulpi_ext_vbus; 471 bool enable_dynamic_fifo; 472 bool en_multiple_tx_fifo; 473 bool i2c_enable; 474 bool ulpi_fs_ls; 475 bool ts_dline; 476 bool reload_ctl; 477 bool uframe_sched; 478 bool external_id_pin_ctl; 479 bool hibernation; 480 u16 max_packet_count; 481 u32 max_transfer_size; 482 u32 ahbcfg; 483 484 /* Host parameters */ 485 bool host_dma; 486 bool dma_desc_enable; 487 bool dma_desc_fs_enable; 488 bool host_support_fs_ls_low_power; 489 bool host_ls_low_power_phy_clk; 490 491 u8 host_channels; 492 u16 host_rx_fifo_size; 493 u16 host_nperio_tx_fifo_size; 494 u16 host_perio_tx_fifo_size; 495 496 /* Gadget parameters */ 497 bool g_dma; 498 bool g_dma_desc; 499 u32 g_rx_fifo_size; 500 u32 g_np_tx_fifo_size; 501 u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; 502 503 bool change_speed_quirk; 504 }; 505 506 /** 507 * struct dwc2_hw_params - Autodetected parameters. 508 * 509 * These parameters are the various parameters read from hardware 510 * registers during initialization. They typically contain the best 511 * supported or maximum value that can be configured in the 512 * corresponding dwc2_core_params value. 513 * 514 * The values that are not in dwc2_core_params are documented below. 515 * 516 * @op_mode Mode of Operation 517 * 0 - HNP- and SRP-Capable OTG (Host & Device) 518 * 1 - SRP-Capable OTG (Host & Device) 519 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 520 * 3 - SRP-Capable Device 521 * 4 - Non-OTG Device 522 * 5 - SRP-Capable Host 523 * 6 - Non-OTG Host 524 * @arch Architecture 525 * 0 - Slave only 526 * 1 - External DMA 527 * 2 - Internal DMA 528 * @power_optimized Are power optimizations enabled? 529 * @num_dev_ep Number of device endpoints available 530 * @num_dev_perio_in_ep Number of device periodic IN endpoints 531 * available 532 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue 533 * Depth 534 * 0 to 30 535 * @host_perio_tx_q_depth 536 * Host Mode Periodic Request Queue Depth 537 * 2, 4 or 8 538 * @nperio_tx_q_depth 539 * Non-Periodic Request Queue Depth 540 * 2, 4 or 8 541 * @hs_phy_type High-speed PHY interface type 542 * 0 - High-speed interface not supported 543 * 1 - UTMI+ 544 * 2 - ULPI 545 * 3 - UTMI+ and ULPI 546 * @fs_phy_type Full-speed PHY interface type 547 * 0 - Full speed interface not supported 548 * 1 - Dedicated full speed interface 549 * 2 - FS pins shared with UTMI+ pins 550 * 3 - FS pins shared with ULPI pins 551 * @total_fifo_size: Total internal RAM for FIFOs (bytes) 552 * @utmi_phy_data_width UTMI+ PHY data width 553 * 0 - 8 bits 554 * 1 - 16 bits 555 * 2 - 8 or 16 bits 556 * @snpsid: Value from SNPSID register 557 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1) 558 */ 559 struct dwc2_hw_params { 560 unsigned op_mode:3; 561 unsigned arch:2; 562 unsigned dma_desc_enable:1; 563 unsigned enable_dynamic_fifo:1; 564 unsigned en_multiple_tx_fifo:1; 565 unsigned rx_fifo_size:16; 566 unsigned host_nperio_tx_fifo_size:16; 567 unsigned dev_nperio_tx_fifo_size:16; 568 unsigned host_perio_tx_fifo_size:16; 569 unsigned nperio_tx_q_depth:3; 570 unsigned host_perio_tx_q_depth:3; 571 unsigned dev_token_q_depth:5; 572 unsigned max_transfer_size:26; 573 unsigned max_packet_count:11; 574 unsigned host_channels:5; 575 unsigned hs_phy_type:2; 576 unsigned fs_phy_type:2; 577 unsigned i2c_enable:1; 578 unsigned num_dev_ep:4; 579 unsigned num_dev_perio_in_ep:4; 580 unsigned total_fifo_size:16; 581 unsigned power_optimized:1; 582 unsigned utmi_phy_data_width:2; 583 u32 snpsid; 584 u32 dev_ep_dirs; 585 }; 586 587 /* Size of control and EP0 buffers */ 588 #define DWC2_CTRL_BUFF_SIZE 8 589 590 /** 591 * struct dwc2_gregs_backup - Holds global registers state before 592 * entering partial power down 593 * @gotgctl: Backup of GOTGCTL register 594 * @gintmsk: Backup of GINTMSK register 595 * @gahbcfg: Backup of GAHBCFG register 596 * @gusbcfg: Backup of GUSBCFG register 597 * @grxfsiz: Backup of GRXFSIZ register 598 * @gnptxfsiz: Backup of GNPTXFSIZ register 599 * @gi2cctl: Backup of GI2CCTL register 600 * @hptxfsiz: Backup of HPTXFSIZ register 601 * @gdfifocfg: Backup of GDFIFOCFG register 602 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 603 * @gpwrdn: Backup of GPWRDN register 604 */ 605 struct dwc2_gregs_backup { 606 u32 gotgctl; 607 u32 gintmsk; 608 u32 gahbcfg; 609 u32 gusbcfg; 610 u32 grxfsiz; 611 u32 gnptxfsiz; 612 u32 gi2cctl; 613 u32 hptxfsiz; 614 u32 pcgcctl; 615 u32 gdfifocfg; 616 u32 dtxfsiz[MAX_EPS_CHANNELS]; 617 u32 gpwrdn; 618 bool valid; 619 }; 620 621 /** 622 * struct dwc2_dregs_backup - Holds device registers state before 623 * entering partial power down 624 * @dcfg: Backup of DCFG register 625 * @dctl: Backup of DCTL register 626 * @daintmsk: Backup of DAINTMSK register 627 * @diepmsk: Backup of DIEPMSK register 628 * @doepmsk: Backup of DOEPMSK register 629 * @diepctl: Backup of DIEPCTL register 630 * @dieptsiz: Backup of DIEPTSIZ register 631 * @diepdma: Backup of DIEPDMA register 632 * @doepctl: Backup of DOEPCTL register 633 * @doeptsiz: Backup of DOEPTSIZ register 634 * @doepdma: Backup of DOEPDMA register 635 */ 636 struct dwc2_dregs_backup { 637 u32 dcfg; 638 u32 dctl; 639 u32 daintmsk; 640 u32 diepmsk; 641 u32 doepmsk; 642 u32 diepctl[MAX_EPS_CHANNELS]; 643 u32 dieptsiz[MAX_EPS_CHANNELS]; 644 u32 diepdma[MAX_EPS_CHANNELS]; 645 u32 doepctl[MAX_EPS_CHANNELS]; 646 u32 doeptsiz[MAX_EPS_CHANNELS]; 647 u32 doepdma[MAX_EPS_CHANNELS]; 648 bool valid; 649 }; 650 651 /** 652 * struct dwc2_hregs_backup - Holds host registers state before 653 * entering partial power down 654 * @hcfg: Backup of HCFG register 655 * @haintmsk: Backup of HAINTMSK register 656 * @hcintmsk: Backup of HCINTMSK register 657 * @hptr0: Backup of HPTR0 register 658 * @hfir: Backup of HFIR register 659 */ 660 struct dwc2_hregs_backup { 661 u32 hcfg; 662 u32 haintmsk; 663 u32 hcintmsk[MAX_EPS_CHANNELS]; 664 u32 hprt0; 665 u32 hfir; 666 bool valid; 667 }; 668 669 /* 670 * Constants related to high speed periodic scheduling 671 * 672 * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a 673 * reservation point of view it's assumed that the schedule goes right back to 674 * the beginning after the end of the schedule. 675 * 676 * What does that mean for scheduling things with a long interval? It means 677 * we'll reserve time for them in every possible microframe that they could 678 * ever be scheduled in. ...but we'll still only actually schedule them as 679 * often as they were requested. 680 * 681 * We keep our schedule in a "bitmap" structure. This simplifies having 682 * to keep track of and merge intervals: we just let the bitmap code do most 683 * of the heavy lifting. In a way scheduling is much like memory allocation. 684 * 685 * We schedule 100us per uframe or 80% of 125us (the maximum amount you're 686 * supposed to schedule for periodic transfers). That's according to spec. 687 * 688 * Note that though we only schedule 80% of each microframe, the bitmap that we 689 * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of 690 * space for each uFrame). 691 * 692 * Requirements: 693 * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1) 694 * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably 695 * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might 696 * be bugs). The 8 comes from the USB spec: number of microframes per frame. 697 */ 698 #define DWC2_US_PER_UFRAME 125 699 #define DWC2_HS_PERIODIC_US_PER_UFRAME 100 700 701 #define DWC2_HS_SCHEDULE_UFRAMES 8 702 #define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \ 703 DWC2_HS_PERIODIC_US_PER_UFRAME) 704 705 /* 706 * Constants related to low speed scheduling 707 * 708 * For high speed we schedule every 1us. For low speed that's a bit overkill, 709 * so we make up a unit called a "slice" that's worth 25us. There are 40 710 * slices in a full frame and we can schedule 36 of those (90%) for periodic 711 * transfers. 712 * 713 * Our low speed schedule can be as short as 1 frame or could be longer. When 714 * we only schedule 1 frame it means that we'll need to reserve a time every 715 * frame even for things that only transfer very rarely, so something that runs 716 * every 2048 frames will get time reserved in every frame. Our low speed 717 * schedule can be longer and we'll be able to handle more overlap, but that 718 * will come at increased memory cost and increased time to schedule. 719 * 720 * Note: one other advantage of a short low speed schedule is that if we mess 721 * up and miss scheduling we can jump in and use any of the slots that we 722 * happened to reserve. 723 * 724 * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for 725 * the schedule. There will be one schedule per TT. 726 * 727 * Requirements: 728 * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME. 729 */ 730 #define DWC2_US_PER_SLICE 25 731 #define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE) 732 733 #define DWC2_ROUND_US_TO_SLICE(us) \ 734 (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \ 735 DWC2_US_PER_SLICE) 736 737 #define DWC2_LS_PERIODIC_US_PER_FRAME \ 738 900 739 #define DWC2_LS_PERIODIC_SLICES_PER_FRAME \ 740 (DWC2_LS_PERIODIC_US_PER_FRAME / \ 741 DWC2_US_PER_SLICE) 742 743 #define DWC2_LS_SCHEDULE_FRAMES 1 744 #define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \ 745 DWC2_LS_PERIODIC_SLICES_PER_FRAME) 746 747 /** 748 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 749 * and periodic schedules 750 * 751 * These are common for both host and peripheral modes: 752 * 753 * @dev: The struct device pointer 754 * @regs: Pointer to controller regs 755 * @hw_params: Parameters that were autodetected from the 756 * hardware registers 757 * @core_params: Parameters that define how the core should be configured 758 * @op_state: The operational State, during transitions (a_host=> 759 * a_peripheral and b_device=>b_host) this may not match 760 * the core, but allows the software to determine 761 * transitions 762 * @dr_mode: Requested mode of operation, one of following: 763 * - USB_DR_MODE_PERIPHERAL 764 * - USB_DR_MODE_HOST 765 * - USB_DR_MODE_OTG 766 * @hcd_enabled Host mode sub-driver initialization indicator. 767 * @gadget_enabled Peripheral mode sub-driver initialization indicator. 768 * @ll_hw_enabled Status of low-level hardware resources. 769 * @phy: The otg phy transceiver structure for phy control. 770 * @uphy: The otg phy transceiver structure for old USB phy 771 * control. 772 * @plat: The platform specific configuration data. This can be 773 * removed once all SoCs support usb transceiver. 774 * @supplies: Definition of USB power supplies 775 * @phyif: PHY interface width 776 * @lock: Spinlock that protects all the driver data structures 777 * @priv: Stores a pointer to the struct usb_hcd 778 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 779 * transfer are in process of being queued 780 * @srp_success: Stores status of SRP request in the case of a FS PHY 781 * with an I2C interface 782 * @wq_otg: Workqueue object used for handling of some interrupts 783 * @wf_otg: Work object for handling Connector ID Status Change 784 * interrupt 785 * @wkp_timer: Timer object for handling Wakeup Detected interrupt 786 * @lx_state: Lx state of connected device 787 * @gregs_backup: Backup of global registers during suspend 788 * @dregs_backup: Backup of device registers during suspend 789 * @hregs_backup: Backup of host registers during suspend 790 * 791 * These are for host mode: 792 * 793 * @flags: Flags for handling root port state changes 794 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 795 * Transfers associated with these QHs are not currently 796 * assigned to a host channel. 797 * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 798 * Transfers associated with these QHs are currently 799 * assigned to a host channel. 800 * @non_periodic_qh_ptr: Pointer to next QH to process in the active 801 * non-periodic schedule 802 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 803 * list of QHs for periodic transfers that are _not_ 804 * scheduled for the next frame. Each QH in the list has an 805 * interval counter that determines when it needs to be 806 * scheduled for execution. This scheduling mechanism 807 * allows only a simple calculation for periodic bandwidth 808 * used (i.e. must assume that all periodic transfers may 809 * need to execute in the same frame). However, it greatly 810 * simplifies scheduling and should be sufficient for the 811 * vast majority of OTG hosts, which need to connect to a 812 * small number of peripherals at one time. Items move from 813 * this list to periodic_sched_ready when the QH interval 814 * counter is 0 at SOF. 815 * @periodic_sched_ready: List of periodic QHs that are ready for execution in 816 * the next frame, but have not yet been assigned to host 817 * channels. Items move from this list to 818 * periodic_sched_assigned as host channels become 819 * available during the current frame. 820 * @periodic_sched_assigned: List of periodic QHs to be executed in the next 821 * frame that are assigned to host channels. Items move 822 * from this list to periodic_sched_queued as the 823 * transactions for the QH are queued to the DWC_otg 824 * controller. 825 * @periodic_sched_queued: List of periodic QHs that have been queued for 826 * execution. Items move from this list to either 827 * periodic_sched_inactive or periodic_sched_ready when the 828 * channel associated with the transfer is released. If the 829 * interval for the QH is 1, the item moves to 830 * periodic_sched_ready because it must be rescheduled for 831 * the next frame. Otherwise, the item moves to 832 * periodic_sched_inactive. 833 * @split_order: List keeping track of channels doing splits, in order. 834 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 835 * This value is in microseconds per (micro)frame. The 836 * assumption is that all periodic transfers may occur in 837 * the same (micro)frame. 838 * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the 839 * host is in high speed mode; low speed schedules are 840 * stored elsewhere since we need one per TT. 841 * @frame_number: Frame number read from the core at SOF. The value ranges 842 * from 0 to HFNUM_MAX_FRNUM. 843 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 844 * SOF enable/disable. 845 * @free_hc_list: Free host channels in the controller. This is a list of 846 * struct dwc2_host_chan items. 847 * @periodic_channels: Number of host channels assigned to periodic transfers. 848 * Currently assuming that there is a dedicated host 849 * channel for each periodic transaction and at least one 850 * host channel is available for non-periodic transactions. 851 * @non_periodic_channels: Number of host channels assigned to non-periodic 852 * transfers 853 * @available_host_channels Number of host channels available for the microframe 854 * scheduler to use 855 * @hc_ptr_array: Array of pointers to the host channel descriptors. 856 * Allows accessing a host channel descriptor given the 857 * host channel number. This is useful in interrupt 858 * handlers. 859 * @status_buf: Buffer used for data received during the status phase of 860 * a control transfer. 861 * @status_buf_dma: DMA address for status_buf 862 * @start_work: Delayed work for handling host A-cable connection 863 * @reset_work: Delayed work for handling a port reset 864 * @otg_port: OTG port number 865 * @frame_list: Frame list 866 * @frame_list_dma: Frame list DMA address 867 * @frame_list_sz: Frame list size 868 * @desc_gen_cache: Kmem cache for generic descriptors 869 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors 870 * 871 * These are for peripheral mode: 872 * 873 * @driver: USB gadget driver 874 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 875 * @num_of_eps: Number of available EPs (excluding EP0) 876 * @debug_root: Root directrory for debugfs. 877 * @debug_file: Main status file for debugfs. 878 * @debug_testmode: Testmode status file for debugfs. 879 * @debug_fifo: FIFO status file for debugfs. 880 * @ep0_reply: Request used for ep0 reply. 881 * @ep0_buff: Buffer for EP0 reply data, if needed. 882 * @ctrl_buff: Buffer for EP0 control requests. 883 * @ctrl_req: Request for EP0 control packets. 884 * @ep0_state: EP0 control transfers state 885 * @test_mode: USB test mode requested by the host 886 * @setup_desc_dma: EP0 setup stage desc chain DMA address 887 * @setup_desc: EP0 setup stage desc chain pointer 888 * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address 889 * @ctrl_in_desc: EP0 IN data phase desc chain pointer 890 * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address 891 * @ctrl_out_desc: EP0 OUT data phase desc chain pointer 892 * @eps: The endpoints being supplied to the gadget framework 893 */ 894 struct dwc2_hsotg { 895 struct device *dev; 896 void __iomem *regs; 897 /** Params detected from hardware */ 898 struct dwc2_hw_params hw_params; 899 /** Params to actually use */ 900 struct dwc2_core_params params; 901 enum usb_otg_state op_state; 902 enum usb_dr_mode dr_mode; 903 unsigned int hcd_enabled:1; 904 unsigned int gadget_enabled:1; 905 unsigned int ll_hw_enabled:1; 906 907 struct phy *phy; 908 struct usb_phy *uphy; 909 struct dwc2_hsotg_plat *plat; 910 struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES]; 911 u32 phyif; 912 913 spinlock_t lock; 914 void *priv; 915 int irq; 916 struct clk *clk; 917 struct reset_control *reset; 918 919 unsigned int queuing_high_bandwidth:1; 920 unsigned int srp_success:1; 921 922 struct workqueue_struct *wq_otg; 923 struct work_struct wf_otg; 924 struct timer_list wkp_timer; 925 enum dwc2_lx_state lx_state; 926 struct dwc2_gregs_backup gr_backup; 927 struct dwc2_dregs_backup dr_backup; 928 struct dwc2_hregs_backup hr_backup; 929 930 struct dentry *debug_root; 931 struct debugfs_regset32 *regset; 932 933 /* DWC OTG HW Release versions */ 934 #define DWC2_CORE_REV_2_71a 0x4f54271a 935 #define DWC2_CORE_REV_2_90a 0x4f54290a 936 #define DWC2_CORE_REV_2_91a 0x4f54291a 937 #define DWC2_CORE_REV_2_92a 0x4f54292a 938 #define DWC2_CORE_REV_2_94a 0x4f54294a 939 #define DWC2_CORE_REV_3_00a 0x4f54300a 940 #define DWC2_CORE_REV_3_10a 0x4f54310a 941 #define DWC2_FS_IOT_REV_1_00a 0x5531100a 942 #define DWC2_HS_IOT_REV_1_00a 0x5532100a 943 944 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 945 union dwc2_hcd_internal_flags { 946 u32 d32; 947 struct { 948 unsigned port_connect_status_change:1; 949 unsigned port_connect_status:1; 950 unsigned port_reset_change:1; 951 unsigned port_enable_change:1; 952 unsigned port_suspend_change:1; 953 unsigned port_over_current_change:1; 954 unsigned port_l1_change:1; 955 unsigned reserved:25; 956 } b; 957 } flags; 958 959 struct list_head non_periodic_sched_inactive; 960 struct list_head non_periodic_sched_active; 961 struct list_head *non_periodic_qh_ptr; 962 struct list_head periodic_sched_inactive; 963 struct list_head periodic_sched_ready; 964 struct list_head periodic_sched_assigned; 965 struct list_head periodic_sched_queued; 966 struct list_head split_order; 967 u16 periodic_usecs; 968 unsigned long hs_periodic_bitmap[ 969 DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)]; 970 u16 frame_number; 971 u16 periodic_qh_count; 972 bool bus_suspended; 973 bool new_connection; 974 975 u16 last_frame_num; 976 977 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 978 #define FRAME_NUM_ARRAY_SIZE 1000 979 u16 *frame_num_array; 980 u16 *last_frame_num_array; 981 int frame_num_idx; 982 int dumped_frame_num_array; 983 #endif 984 985 struct list_head free_hc_list; 986 int periodic_channels; 987 int non_periodic_channels; 988 int available_host_channels; 989 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 990 u8 *status_buf; 991 dma_addr_t status_buf_dma; 992 #define DWC2_HCD_STATUS_BUF_SIZE 64 993 994 struct delayed_work start_work; 995 struct delayed_work reset_work; 996 u8 otg_port; 997 u32 *frame_list; 998 dma_addr_t frame_list_dma; 999 u32 frame_list_sz; 1000 struct kmem_cache *desc_gen_cache; 1001 struct kmem_cache *desc_hsisoc_cache; 1002 1003 #ifdef DEBUG 1004 u32 frrem_samples; 1005 u64 frrem_accum; 1006 1007 u32 hfnum_7_samples_a; 1008 u64 hfnum_7_frrem_accum_a; 1009 u32 hfnum_0_samples_a; 1010 u64 hfnum_0_frrem_accum_a; 1011 u32 hfnum_other_samples_a; 1012 u64 hfnum_other_frrem_accum_a; 1013 1014 u32 hfnum_7_samples_b; 1015 u64 hfnum_7_frrem_accum_b; 1016 u32 hfnum_0_samples_b; 1017 u64 hfnum_0_frrem_accum_b; 1018 u32 hfnum_other_samples_b; 1019 u64 hfnum_other_frrem_accum_b; 1020 #endif 1021 #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ 1022 1023 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1024 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1025 /* Gadget structures */ 1026 struct usb_gadget_driver *driver; 1027 int fifo_mem; 1028 unsigned int dedicated_fifos:1; 1029 unsigned char num_of_eps; 1030 u32 fifo_map; 1031 1032 struct usb_request *ep0_reply; 1033 struct usb_request *ctrl_req; 1034 void *ep0_buff; 1035 void *ctrl_buff; 1036 enum dwc2_ep0_state ep0_state; 1037 u8 test_mode; 1038 1039 dma_addr_t setup_desc_dma[2]; 1040 struct dwc2_dma_desc *setup_desc[2]; 1041 dma_addr_t ctrl_in_desc_dma; 1042 struct dwc2_dma_desc *ctrl_in_desc; 1043 dma_addr_t ctrl_out_desc_dma; 1044 struct dwc2_dma_desc *ctrl_out_desc; 1045 1046 struct usb_gadget gadget; 1047 unsigned int enabled:1; 1048 unsigned int connected:1; 1049 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS]; 1050 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS]; 1051 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 1052 }; 1053 1054 /* Reasons for halting a host channel */ 1055 enum dwc2_halt_status { 1056 DWC2_HC_XFER_NO_HALT_STATUS, 1057 DWC2_HC_XFER_COMPLETE, 1058 DWC2_HC_XFER_URB_COMPLETE, 1059 DWC2_HC_XFER_ACK, 1060 DWC2_HC_XFER_NAK, 1061 DWC2_HC_XFER_NYET, 1062 DWC2_HC_XFER_STALL, 1063 DWC2_HC_XFER_XACT_ERR, 1064 DWC2_HC_XFER_FRAME_OVERRUN, 1065 DWC2_HC_XFER_BABBLE_ERR, 1066 DWC2_HC_XFER_DATA_TOGGLE_ERR, 1067 DWC2_HC_XFER_AHB_ERR, 1068 DWC2_HC_XFER_PERIODIC_INCOMPLETE, 1069 DWC2_HC_XFER_URB_DEQUEUE, 1070 }; 1071 1072 /* Core version information */ 1073 static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg) 1074 { 1075 return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000; 1076 } 1077 1078 static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg) 1079 { 1080 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000; 1081 } 1082 1083 static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg) 1084 { 1085 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000; 1086 } 1087 1088 /* 1089 * The following functions support initialization of the core driver component 1090 * and the DWC_otg controller 1091 */ 1092 int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait); 1093 int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg); 1094 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg); 1095 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore); 1096 1097 bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host); 1098 void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg); 1099 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg); 1100 1101 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 1102 1103 /* 1104 * Common core Functions. 1105 * The following functions support managing the DWC_otg controller in either 1106 * device or host mode. 1107 */ 1108 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 1109 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 1110 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 1111 1112 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 1113 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 1114 1115 /* This function should be called on every hardware interrupt. */ 1116 irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 1117 1118 /* The device ID match table */ 1119 extern const struct of_device_id dwc2_of_match_table[]; 1120 1121 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg); 1122 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg); 1123 1124 /* Parameters */ 1125 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); 1126 int dwc2_init_params(struct dwc2_hsotg *hsotg); 1127 1128 /* 1129 * The following functions check the controller's OTG operation mode 1130 * capability (GHWCFG2.OTG_MODE). 1131 * 1132 * These functions can be used before the internal hsotg->hw_params 1133 * are read in and cached so they always read directly from the 1134 * GHWCFG2 register. 1135 */ 1136 unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg); 1137 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg); 1138 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg); 1139 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg); 1140 1141 /* 1142 * Returns the mode of operation, host or device 1143 */ 1144 static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) 1145 { 1146 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0; 1147 } 1148 1149 static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) 1150 { 1151 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0; 1152 } 1153 1154 /* 1155 * Dump core registers and SPRAM 1156 */ 1157 void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 1158 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 1159 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 1160 1161 /* Gadget defines */ 1162 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1163 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1164 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg); 1165 int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2); 1166 int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2); 1167 int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq); 1168 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1169 bool reset); 1170 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg); 1171 void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2); 1172 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode); 1173 #define dwc2_is_device_connected(hsotg) (hsotg->connected) 1174 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg); 1175 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg); 1176 int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg); 1177 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg); 1178 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg); 1179 #else 1180 static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2) 1181 { return 0; } 1182 static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2) 1183 { return 0; } 1184 static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2) 1185 { return 0; } 1186 static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) 1187 { return 0; } 1188 static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1189 bool reset) {} 1190 static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} 1191 static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} 1192 static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, 1193 int testmode) 1194 { return 0; } 1195 #define dwc2_is_device_connected(hsotg) (0) 1196 static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) 1197 { return 0; } 1198 static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg) 1199 { return 0; } 1200 static inline int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg) 1201 { return 0; } 1202 static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) 1203 { return 0; } 1204 static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg) 1205 { return 0; } 1206 #endif 1207 1208 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1209 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 1210 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us); 1211 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg); 1212 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force); 1213 void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 1214 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg); 1215 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg); 1216 #else 1217 static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1218 { return 0; } 1219 static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, 1220 int us) 1221 { return 0; } 1222 static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {} 1223 static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {} 1224 static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} 1225 static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} 1226 static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg) 1227 { return 0; } 1228 static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 1229 { return 0; } 1230 static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 1231 { return 0; } 1232 1233 #endif 1234 1235 #endif /* __DWC2_CORE_H__ */ 1236