15fd54aceSGreg Kroah-Hartman // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2197ba5f4SPaul Zimmerman /* 3197ba5f4SPaul Zimmerman * core.h - DesignWare HS OTG Controller common declarations 4197ba5f4SPaul Zimmerman * 5197ba5f4SPaul Zimmerman * Copyright (C) 2004-2013 Synopsys, Inc. 6197ba5f4SPaul Zimmerman * 7197ba5f4SPaul Zimmerman * Redistribution and use in source and binary forms, with or without 8197ba5f4SPaul Zimmerman * modification, are permitted provided that the following conditions 9197ba5f4SPaul Zimmerman * are met: 10197ba5f4SPaul Zimmerman * 1. Redistributions of source code must retain the above copyright 11197ba5f4SPaul Zimmerman * notice, this list of conditions, and the following disclaimer, 12197ba5f4SPaul Zimmerman * without modification. 13197ba5f4SPaul Zimmerman * 2. Redistributions in binary form must reproduce the above copyright 14197ba5f4SPaul Zimmerman * notice, this list of conditions and the following disclaimer in the 15197ba5f4SPaul Zimmerman * documentation and/or other materials provided with the distribution. 16197ba5f4SPaul Zimmerman * 3. The names of the above-listed copyright holders may not be used 17197ba5f4SPaul Zimmerman * to endorse or promote products derived from this software without 18197ba5f4SPaul Zimmerman * specific prior written permission. 19197ba5f4SPaul Zimmerman * 20197ba5f4SPaul Zimmerman * ALTERNATIVELY, this software may be distributed under the terms of the 21197ba5f4SPaul Zimmerman * GNU General Public License ("GPL") as published by the Free Software 22197ba5f4SPaul Zimmerman * Foundation; either version 2 of the License, or (at your option) any 23197ba5f4SPaul Zimmerman * later version. 24197ba5f4SPaul Zimmerman * 25197ba5f4SPaul Zimmerman * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 26197ba5f4SPaul Zimmerman * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 27197ba5f4SPaul Zimmerman * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28197ba5f4SPaul Zimmerman * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 29197ba5f4SPaul Zimmerman * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 30197ba5f4SPaul Zimmerman * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 31197ba5f4SPaul Zimmerman * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32197ba5f4SPaul Zimmerman * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 33197ba5f4SPaul Zimmerman * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 34197ba5f4SPaul Zimmerman * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 35197ba5f4SPaul Zimmerman * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36197ba5f4SPaul Zimmerman */ 37197ba5f4SPaul Zimmerman 38197ba5f4SPaul Zimmerman #ifndef __DWC2_CORE_H__ 39197ba5f4SPaul Zimmerman #define __DWC2_CORE_H__ 40197ba5f4SPaul Zimmerman 41f7c0b143SDinh Nguyen #include <linux/phy/phy.h> 42f7c0b143SDinh Nguyen #include <linux/regulator/consumer.h> 43f7c0b143SDinh Nguyen #include <linux/usb/gadget.h> 44f7c0b143SDinh Nguyen #include <linux/usb/otg.h> 45197ba5f4SPaul Zimmerman #include <linux/usb/phy.h> 46197ba5f4SPaul Zimmerman #include "hw.h" 47197ba5f4SPaul Zimmerman 4874fc4a75SDouglas Anderson /* 4974fc4a75SDouglas Anderson * Suggested defines for tracers: 5074fc4a75SDouglas Anderson * - no_printk: Disable tracing 5174fc4a75SDouglas Anderson * - pr_info: Print this info to the console 5274fc4a75SDouglas Anderson * - trace_printk: Print this info to trace buffer (good for verbose logging) 5374fc4a75SDouglas Anderson */ 5474fc4a75SDouglas Anderson 5574fc4a75SDouglas Anderson #define DWC2_TRACE_SCHEDULER no_printk 5674fc4a75SDouglas Anderson #define DWC2_TRACE_SCHEDULER_VB no_printk 5774fc4a75SDouglas Anderson 5874fc4a75SDouglas Anderson /* Detailed scheduler tracing, but won't overwhelm console */ 5974fc4a75SDouglas Anderson #define dwc2_sch_dbg(hsotg, fmt, ...) \ 6074fc4a75SDouglas Anderson DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \ 6174fc4a75SDouglas Anderson dev_name(hsotg->dev), ##__VA_ARGS__) 6274fc4a75SDouglas Anderson 6374fc4a75SDouglas Anderson /* Verbose scheduler tracing */ 6474fc4a75SDouglas Anderson #define dwc2_sch_vdbg(hsotg, fmt, ...) \ 6574fc4a75SDouglas Anderson DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \ 6674fc4a75SDouglas Anderson dev_name(hsotg->dev), ##__VA_ARGS__) 6774fc4a75SDouglas Anderson 68197ba5f4SPaul Zimmerman /* Maximum number of Endpoints/HostChannels */ 69197ba5f4SPaul Zimmerman #define MAX_EPS_CHANNELS 16 70197ba5f4SPaul Zimmerman 711f91b4ccSFelipe Balbi /* dwc2-hsotg declarations */ 721f91b4ccSFelipe Balbi static const char * const dwc2_hsotg_supply_names[] = { 73f7c0b143SDinh Nguyen "vusb_d", /* digital USB supply, 1.2V */ 74f7c0b143SDinh Nguyen "vusb_a", /* analog USB supply, 1.1V */ 75f7c0b143SDinh Nguyen }; 76f7c0b143SDinh Nguyen 77b98866c2SJohn Youn #define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names) 78b98866c2SJohn Youn 79f7c0b143SDinh Nguyen /* 80f7c0b143SDinh Nguyen * EP0_MPS_LIMIT 81f7c0b143SDinh Nguyen * 82f7c0b143SDinh Nguyen * Unfortunately there seems to be a limit of the amount of data that can 83f7c0b143SDinh Nguyen * be transferred by IN transactions on EP0. This is either 127 bytes or 3 84f7c0b143SDinh Nguyen * packets (which practically means 1 packet and 63 bytes of data) when the 85f7c0b143SDinh Nguyen * MPS is set to 64. 86f7c0b143SDinh Nguyen * 87f7c0b143SDinh Nguyen * This means if we are wanting to move >127 bytes of data, we need to 88f7c0b143SDinh Nguyen * split the transactions up, but just doing one packet at a time does 89f7c0b143SDinh Nguyen * not work (this may be an implicit DATA0 PID on first packet of the 90f7c0b143SDinh Nguyen * transaction) and doing 2 packets is outside the controller's limits. 91f7c0b143SDinh Nguyen * 92f7c0b143SDinh Nguyen * If we try to lower the MPS size for EP0, then no transfers work properly 93f7c0b143SDinh Nguyen * for EP0, and the system will fail basic enumeration. As no cause for this 94f7c0b143SDinh Nguyen * has currently been found, we cannot support any large IN transfers for 95f7c0b143SDinh Nguyen * EP0. 96f7c0b143SDinh Nguyen */ 97f7c0b143SDinh Nguyen #define EP0_MPS_LIMIT 64 98f7c0b143SDinh Nguyen 99941fcce4SDinh Nguyen struct dwc2_hsotg; 1001f91b4ccSFelipe Balbi struct dwc2_hsotg_req; 101f7c0b143SDinh Nguyen 102f7c0b143SDinh Nguyen /** 1031f91b4ccSFelipe Balbi * struct dwc2_hsotg_ep - driver endpoint definition. 104f7c0b143SDinh Nguyen * @ep: The gadget layer representation of the endpoint. 105f7c0b143SDinh Nguyen * @name: The driver generated name for the endpoint. 106f7c0b143SDinh Nguyen * @queue: Queue of requests for this endpoint. 107f7c0b143SDinh Nguyen * @parent: Reference back to the parent device structure. 108f7c0b143SDinh Nguyen * @req: The current request that the endpoint is processing. This is 109f7c0b143SDinh Nguyen * used to indicate an request has been loaded onto the endpoint 110f7c0b143SDinh Nguyen * and has yet to be completed (maybe due to data move, or simply 111f7c0b143SDinh Nguyen * awaiting an ack from the core all the data has been completed). 112f7c0b143SDinh Nguyen * @debugfs: File entry for debugfs file for this endpoint. 113f7c0b143SDinh Nguyen * @dir_in: Set to true if this endpoint is of the IN direction, which 114f7c0b143SDinh Nguyen * means that it is sending data to the Host. 115f7c0b143SDinh Nguyen * @index: The index for the endpoint registers. 116f7c0b143SDinh Nguyen * @mc: Multi Count - number of transactions per microframe 1176fb914d7SGrigor Tovmasyan * @interval: Interval for periodic endpoints, in frames or microframes. 118f7c0b143SDinh Nguyen * @name: The name array passed to the USB core. 119f7c0b143SDinh Nguyen * @halted: Set if the endpoint has been halted. 120f7c0b143SDinh Nguyen * @periodic: Set if this is a periodic ep, such as Interrupt 121f7c0b143SDinh Nguyen * @isochronous: Set if this is a isochronous ep 1228a20fa45SMian Yousaf Kaukab * @send_zlp: Set if we need to send a zero-length packet. 1235f54c54bSVahram Aharonyan * @desc_list_dma: The DMA address of descriptor chain currently in use. 1245f54c54bSVahram Aharonyan * @desc_list: Pointer to descriptor DMA chain head currently in use. 1255f54c54bSVahram Aharonyan * @desc_count: Count of entries within the DMA descriptor chain of EP. 126ab7d2192SVahram Aharonyan * @next_desc: index of next free descriptor in the ISOC chain under SW control. 127729cac69SMinas Harutyunyan * @compl_desc: index of next descriptor to be completed by xFerComplete 128f7c0b143SDinh Nguyen * @total_data: The total number of data bytes done. 129f7c0b143SDinh Nguyen * @fifo_size: The size of the FIFO (for periodic IN endpoints) 1306fb914d7SGrigor Tovmasyan * @fifo_index: For Dedicated FIFO operation, only FIFO0 can be used for EP0. 131f7c0b143SDinh Nguyen * @fifo_load: The amount of data loaded into the FIFO (periodic IN) 132f7c0b143SDinh Nguyen * @last_load: The offset of data for the last start of request. 133f7c0b143SDinh Nguyen * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN 13492d1635dSVardan Mikayelyan * @target_frame: Targeted frame num to setup next ISOC transfer 13592d1635dSVardan Mikayelyan * @frame_overrun: Indicates SOF number overrun in DSTS 136f7c0b143SDinh Nguyen * 137f7c0b143SDinh Nguyen * This is the driver's state for each registered enpoint, allowing it 138f7c0b143SDinh Nguyen * to keep track of transactions that need doing. Each endpoint has a 139f7c0b143SDinh Nguyen * lock to protect the state, to try and avoid using an overall lock 140f7c0b143SDinh Nguyen * for the host controller as much as possible. 141f7c0b143SDinh Nguyen * 142f7c0b143SDinh Nguyen * For periodic IN endpoints, we have fifo_size and fifo_load to try 143f7c0b143SDinh Nguyen * and keep track of the amount of data in the periodic FIFO for each 144f7c0b143SDinh Nguyen * of these as we don't have a status register that tells us how much 145f7c0b143SDinh Nguyen * is in each of them. (note, this may actually be useless information 146f7c0b143SDinh Nguyen * as in shared-fifo mode periodic in acts like a single-frame packet 147f7c0b143SDinh Nguyen * buffer than a fifo) 148f7c0b143SDinh Nguyen */ 1491f91b4ccSFelipe Balbi struct dwc2_hsotg_ep { 150f7c0b143SDinh Nguyen struct usb_ep ep; 151f7c0b143SDinh Nguyen struct list_head queue; 152941fcce4SDinh Nguyen struct dwc2_hsotg *parent; 1531f91b4ccSFelipe Balbi struct dwc2_hsotg_req *req; 154f7c0b143SDinh Nguyen struct dentry *debugfs; 155f7c0b143SDinh Nguyen 156f7c0b143SDinh Nguyen unsigned long total_data; 157f7c0b143SDinh Nguyen unsigned int size_loaded; 158f7c0b143SDinh Nguyen unsigned int last_load; 159f7c0b143SDinh Nguyen unsigned int fifo_load; 160f7c0b143SDinh Nguyen unsigned short fifo_size; 161b203d0a2SRobert Baldyga unsigned short fifo_index; 162f7c0b143SDinh Nguyen 163f7c0b143SDinh Nguyen unsigned char dir_in; 164f7c0b143SDinh Nguyen unsigned char index; 165f7c0b143SDinh Nguyen unsigned char mc; 16612814a3fSGrigor Tovmasyan u16 interval; 167f7c0b143SDinh Nguyen 168f7c0b143SDinh Nguyen unsigned int halted:1; 169f7c0b143SDinh Nguyen unsigned int periodic:1; 170f7c0b143SDinh Nguyen unsigned int isochronous:1; 1718a20fa45SMian Yousaf Kaukab unsigned int send_zlp:1; 17292d1635dSVardan Mikayelyan unsigned int target_frame; 17392d1635dSVardan Mikayelyan #define TARGET_FRAME_INITIAL 0xFFFFFFFF 17492d1635dSVardan Mikayelyan bool frame_overrun; 175f7c0b143SDinh Nguyen 1765f54c54bSVahram Aharonyan dma_addr_t desc_list_dma; 1775f54c54bSVahram Aharonyan struct dwc2_dma_desc *desc_list; 1785f54c54bSVahram Aharonyan u8 desc_count; 1795f54c54bSVahram Aharonyan 180ab7d2192SVahram Aharonyan unsigned int next_desc; 181729cac69SMinas Harutyunyan unsigned int compl_desc; 182ab7d2192SVahram Aharonyan 183f7c0b143SDinh Nguyen char name[10]; 184f7c0b143SDinh Nguyen }; 185f7c0b143SDinh Nguyen 186f7c0b143SDinh Nguyen /** 1871f91b4ccSFelipe Balbi * struct dwc2_hsotg_req - data transfer request 188f7c0b143SDinh Nguyen * @req: The USB gadget request 189f7c0b143SDinh Nguyen * @queue: The list of requests for the endpoint this is queued for. 1907d24c1b5SMian Yousaf Kaukab * @saved_req_buf: variable to save req.buf when bounce buffers are used. 191f7c0b143SDinh Nguyen */ 1921f91b4ccSFelipe Balbi struct dwc2_hsotg_req { 193f7c0b143SDinh Nguyen struct usb_request req; 194f7c0b143SDinh Nguyen struct list_head queue; 1957d24c1b5SMian Yousaf Kaukab void *saved_req_buf; 196f7c0b143SDinh Nguyen }; 197f7c0b143SDinh Nguyen 198b98866c2SJohn Youn #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 199b98866c2SJohn Youn IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 200f7c0b143SDinh Nguyen #define call_gadget(_hs, _entry) \ 201f7c0b143SDinh Nguyen do { \ 202f7c0b143SDinh Nguyen if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ 203f7c0b143SDinh Nguyen (_hs)->driver && (_hs)->driver->_entry) { \ 204f7c0b143SDinh Nguyen spin_unlock(&_hs->lock); \ 205f7c0b143SDinh Nguyen (_hs)->driver->_entry(&(_hs)->gadget); \ 206f7c0b143SDinh Nguyen spin_lock(&_hs->lock); \ 207f7c0b143SDinh Nguyen } \ 208f7c0b143SDinh Nguyen } while (0) 209941fcce4SDinh Nguyen #else 210941fcce4SDinh Nguyen #define call_gadget(_hs, _entry) do {} while (0) 211941fcce4SDinh Nguyen #endif 212f7c0b143SDinh Nguyen 213197ba5f4SPaul Zimmerman struct dwc2_hsotg; 214197ba5f4SPaul Zimmerman struct dwc2_host_chan; 215197ba5f4SPaul Zimmerman 216197ba5f4SPaul Zimmerman /* Device States */ 217197ba5f4SPaul Zimmerman enum dwc2_lx_state { 218197ba5f4SPaul Zimmerman DWC2_L0, /* On state */ 219197ba5f4SPaul Zimmerman DWC2_L1, /* LPM sleep state */ 220197ba5f4SPaul Zimmerman DWC2_L2, /* USB suspend state */ 221197ba5f4SPaul Zimmerman DWC2_L3, /* Off state */ 222197ba5f4SPaul Zimmerman }; 223197ba5f4SPaul Zimmerman 224fe0b94abSMian Yousaf Kaukab /* Gadget ep0 states */ 225fe0b94abSMian Yousaf Kaukab enum dwc2_ep0_state { 226fe0b94abSMian Yousaf Kaukab DWC2_EP0_SETUP, 227fe0b94abSMian Yousaf Kaukab DWC2_EP0_DATA_IN, 228fe0b94abSMian Yousaf Kaukab DWC2_EP0_DATA_OUT, 229fe0b94abSMian Yousaf Kaukab DWC2_EP0_STATUS_IN, 230fe0b94abSMian Yousaf Kaukab DWC2_EP0_STATUS_OUT, 231fe0b94abSMian Yousaf Kaukab }; 232fe0b94abSMian Yousaf Kaukab 233197ba5f4SPaul Zimmerman /** 234197ba5f4SPaul Zimmerman * struct dwc2_core_params - Parameters for configuring the core 235197ba5f4SPaul Zimmerman * 236197ba5f4SPaul Zimmerman * @otg_cap: Specifies the OTG capabilities. 237197ba5f4SPaul Zimmerman * 0 - HNP and SRP capable 238197ba5f4SPaul Zimmerman * 1 - SRP Only capable 239197ba5f4SPaul Zimmerman * 2 - No HNP/SRP capable (always available) 240197ba5f4SPaul Zimmerman * Defaults to best available option (0, 1, then 2) 241e7839f99SJohn Youn * @host_dma: Specifies whether to use slave or DMA mode for accessing 242197ba5f4SPaul Zimmerman * the data FIFOs. The driver will automatically detect the 243197ba5f4SPaul Zimmerman * value for this parameter if none is specified. 244197ba5f4SPaul Zimmerman * 0 - Slave (always available) 245197ba5f4SPaul Zimmerman * 1 - DMA (default, if available) 246197ba5f4SPaul Zimmerman * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 247197ba5f4SPaul Zimmerman * address DMA mode or descriptor DMA mode for accessing 248197ba5f4SPaul Zimmerman * the data FIFOs. The driver will automatically detect the 249197ba5f4SPaul Zimmerman * value for this if none is specified. 250197ba5f4SPaul Zimmerman * 0 - Address DMA 251197ba5f4SPaul Zimmerman * 1 - Descriptor DMA (default, if available) 252fbb9e22bSMian Yousaf Kaukab * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use 253fbb9e22bSMian Yousaf Kaukab * address DMA mode or descriptor DMA mode for accessing 254fbb9e22bSMian Yousaf Kaukab * the data FIFOs in Full Speed mode only. The driver 255fbb9e22bSMian Yousaf Kaukab * will automatically detect the value for this if none is 256fbb9e22bSMian Yousaf Kaukab * specified. 257fbb9e22bSMian Yousaf Kaukab * 0 - Address DMA 258fbb9e22bSMian Yousaf Kaukab * 1 - Descriptor DMA in FS (default, if available) 259197ba5f4SPaul Zimmerman * @speed: Specifies the maximum speed of operation in host and 260197ba5f4SPaul Zimmerman * device mode. The actual speed depends on the speed of 261197ba5f4SPaul Zimmerman * the attached device and the value of phy_type. 262197ba5f4SPaul Zimmerman * 0 - High Speed 263197ba5f4SPaul Zimmerman * (default when phy_type is UTMI+ or ULPI) 264197ba5f4SPaul Zimmerman * 1 - Full Speed 265197ba5f4SPaul Zimmerman * (default when phy_type is Full Speed) 266197ba5f4SPaul Zimmerman * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 267197ba5f4SPaul Zimmerman * 1 - Allow dynamic FIFO sizing (default, if available) 268197ba5f4SPaul Zimmerman * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 269c1d286cfSJohn Youn * are enabled for non-periodic IN endpoints in device 270c1d286cfSJohn Youn * mode. 271197ba5f4SPaul Zimmerman * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 272197ba5f4SPaul Zimmerman * dynamic FIFO sizing is enabled 273197ba5f4SPaul Zimmerman * 16 to 32768 274197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 275197ba5f4SPaul Zimmerman * the default. 276197ba5f4SPaul Zimmerman * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 277197ba5f4SPaul Zimmerman * in host mode when dynamic FIFO sizing is enabled 278197ba5f4SPaul Zimmerman * 16 to 32768 279197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 280197ba5f4SPaul Zimmerman * the default. 281197ba5f4SPaul Zimmerman * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 282197ba5f4SPaul Zimmerman * host mode when dynamic FIFO sizing is enabled 283197ba5f4SPaul Zimmerman * 16 to 32768 284197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 285197ba5f4SPaul Zimmerman * the default. 286197ba5f4SPaul Zimmerman * @max_transfer_size: The maximum transfer size supported, in bytes 287197ba5f4SPaul Zimmerman * 2047 to 65,535 288197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 289197ba5f4SPaul Zimmerman * the default. 290197ba5f4SPaul Zimmerman * @max_packet_count: The maximum number of packets in a transfer 291197ba5f4SPaul Zimmerman * 15 to 511 292197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 293197ba5f4SPaul Zimmerman * the default. 294197ba5f4SPaul Zimmerman * @host_channels: The number of host channel registers to use 295197ba5f4SPaul Zimmerman * 1 to 16 296197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 297197ba5f4SPaul Zimmerman * the default. 298197ba5f4SPaul Zimmerman * @phy_type: Specifies the type of PHY interface to use. By default, 299197ba5f4SPaul Zimmerman * the driver will automatically detect the phy_type. 300197ba5f4SPaul Zimmerman * 0 - Full Speed Phy 301197ba5f4SPaul Zimmerman * 1 - UTMI+ Phy 302197ba5f4SPaul Zimmerman * 2 - ULPI Phy 303197ba5f4SPaul Zimmerman * Defaults to best available option (2, 1, then 0) 304197ba5f4SPaul Zimmerman * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 305197ba5f4SPaul Zimmerman * is applicable for a phy_type of UTMI+ or ULPI. (For a 306197ba5f4SPaul Zimmerman * ULPI phy_type, this parameter indicates the data width 307197ba5f4SPaul Zimmerman * between the MAC and the ULPI Wrapper.) Also, this 308197ba5f4SPaul Zimmerman * parameter is applicable only if the OTG_HSPHY_WIDTH cC 309197ba5f4SPaul Zimmerman * parameter was set to "8 and 16 bits", meaning that the 310197ba5f4SPaul Zimmerman * core has been configured to work at either data path 311197ba5f4SPaul Zimmerman * width. 312197ba5f4SPaul Zimmerman * 8 or 16 (default 16 if available) 313197ba5f4SPaul Zimmerman * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 314197ba5f4SPaul Zimmerman * data rate. This parameter is only applicable if phy_type 315197ba5f4SPaul Zimmerman * is ULPI. 316197ba5f4SPaul Zimmerman * 0 - single data rate ULPI interface with 8 bit wide 317197ba5f4SPaul Zimmerman * data bus (default) 318197ba5f4SPaul Zimmerman * 1 - double data rate ULPI interface with 4 bit wide 319197ba5f4SPaul Zimmerman * data bus 320197ba5f4SPaul Zimmerman * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 321197ba5f4SPaul Zimmerman * external supply to drive the VBus 322197ba5f4SPaul Zimmerman * 0 - Internal supply (default) 323197ba5f4SPaul Zimmerman * 1 - External supply 324197ba5f4SPaul Zimmerman * @i2c_enable: Specifies whether to use the I2Cinterface for a full 325197ba5f4SPaul Zimmerman * speed PHY. This parameter is only applicable if phy_type 326197ba5f4SPaul Zimmerman * is FS. 327197ba5f4SPaul Zimmerman * 0 - No (default) 328197ba5f4SPaul Zimmerman * 1 - Yes 3296fb914d7SGrigor Tovmasyan * @ipg_isoc_en: Indicates the IPG supports is enabled or disabled. 330b43ebc96SGrigor Tovmasyan * 0 - Disable (default) 331b43ebc96SGrigor Tovmasyan * 1 - Enable 3326fb914d7SGrigor Tovmasyan * @acg_enable: For enabling Active Clock Gating in the controller 3336fb914d7SGrigor Tovmasyan * 0 - No 3346fb914d7SGrigor Tovmasyan * 1 - Yes 335197ba5f4SPaul Zimmerman * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 336197ba5f4SPaul Zimmerman * 0 - No (default) 337197ba5f4SPaul Zimmerman * 1 - Yes 338197ba5f4SPaul Zimmerman * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 339197ba5f4SPaul Zimmerman * when attached to a Full Speed or Low Speed device in 340197ba5f4SPaul Zimmerman * host mode. 341197ba5f4SPaul Zimmerman * 0 - Don't support low power mode (default) 342197ba5f4SPaul Zimmerman * 1 - Support low power mode 343197ba5f4SPaul Zimmerman * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 344197ba5f4SPaul Zimmerman * when connected to a Low Speed device in host 345197ba5f4SPaul Zimmerman * mode. This parameter is applicable only if 346197ba5f4SPaul Zimmerman * host_support_fs_ls_low_power is enabled. 347197ba5f4SPaul Zimmerman * 0 - 48 MHz 348197ba5f4SPaul Zimmerman * (default when phy_type is UTMI+ or ULPI) 349197ba5f4SPaul Zimmerman * 1 - 6 MHz 350197ba5f4SPaul Zimmerman * (default when phy_type is Full Speed) 351b11633c4SDinh Nguyen * @oc_disable: Flag to disable overcurrent condition. 352b11633c4SDinh Nguyen * 0 - Allow overcurrent condition to get detected 353b11633c4SDinh Nguyen * 1 - Disable overcurrent condtion to get detected 354197ba5f4SPaul Zimmerman * @ts_dline: Enable Term Select Dline pulsing 355197ba5f4SPaul Zimmerman * 0 - No (default) 356197ba5f4SPaul Zimmerman * 1 - Yes 357197ba5f4SPaul Zimmerman * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 358197ba5f4SPaul Zimmerman * 0 - No (default for core < 2.92a) 359197ba5f4SPaul Zimmerman * 1 - Yes (default for core >= 2.92a) 360197ba5f4SPaul Zimmerman * @ahbcfg: This field allows the default value of the GAHBCFG 361197ba5f4SPaul Zimmerman * register to be overridden 362197ba5f4SPaul Zimmerman * -1 - GAHBCFG value will be set to 0x06 3631b52d2faSRazmik Karapetyan * (INCR, default) 364197ba5f4SPaul Zimmerman * all others - GAHBCFG value will be overridden with 365197ba5f4SPaul Zimmerman * this value 366197ba5f4SPaul Zimmerman * Not all bits can be controlled like this, the 367197ba5f4SPaul Zimmerman * bits defined by GAHBCFG_CTRL_MASK are controlled 368197ba5f4SPaul Zimmerman * by the driver and are ignored in this 369197ba5f4SPaul Zimmerman * configuration value. 370197ba5f4SPaul Zimmerman * @uframe_sched: True to enable the microframe scheduler 371a6d249d8SGregory Herrero * @external_id_pin_ctl: Specifies whether ID pin is handled externally. 372a6d249d8SGregory Herrero * Disable CONIDSTSCHNG controller interrupt in such 373a6d249d8SGregory Herrero * case. 374a6d249d8SGregory Herrero * 0 - No (default) 375a6d249d8SGregory Herrero * 1 - Yes 37641ba9b9bSVardan Mikayelyan * @power_down: Specifies whether the controller support power_down. 37741ba9b9bSVardan Mikayelyan * If power_down is enabled, the controller will enter 37841ba9b9bSVardan Mikayelyan * power_down in both peripheral and host mode when 379285046aaSGregory Herrero * needed. 380285046aaSGregory Herrero * 0 - No (default) 381631a2310SVardan Mikayelyan * 1 - Partial power down 382631a2310SVardan Mikayelyan * 2 - Hibernation 3836f80b6deSSevak Arakelyan * @lpm: Enable LPM support. 3846f80b6deSSevak Arakelyan * 0 - No 3856f80b6deSSevak Arakelyan * 1 - Yes 3866f80b6deSSevak Arakelyan * @lpm_clock_gating: Enable core PHY clock gating. 3876f80b6deSSevak Arakelyan * 0 - No 3886f80b6deSSevak Arakelyan * 1 - Yes 3896f80b6deSSevak Arakelyan * @besl: Enable LPM Errata support. 3906f80b6deSSevak Arakelyan * 0 - No 3916f80b6deSSevak Arakelyan * 1 - Yes 3926f80b6deSSevak Arakelyan * @hird_threshold_en: HIRD or HIRD Threshold enable. 3936f80b6deSSevak Arakelyan * 0 - No 3946f80b6deSSevak Arakelyan * 1 - Yes 3956f80b6deSSevak Arakelyan * @hird_threshold: Value of BESL or HIRD Threshold. 396e35b1350SBruno Herrera * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO 397e35b1350SBruno Herrera * register. 398e35b1350SBruno Herrera * 0 - Deactivate the transceiver (default) 399e35b1350SBruno Herrera * 1 - Activate the transceiver 4009962b62fSJohn Youn * @g_dma: Enables gadget dma usage (default: autodetect). 401dec4b556SVahram Aharonyan * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect). 40205ee799fSJohn Youn * @g_rx_fifo_size: The periodic rx fifo size for the device, in 40305ee799fSJohn Youn * DWORDS from 16-32768 (default: 2048 if 40405ee799fSJohn Youn * possible, otherwise autodetect). 40505ee799fSJohn Youn * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in 40605ee799fSJohn Youn * DWORDS from 16-32768 (default: 1024 if 40705ee799fSJohn Youn * possible, otherwise autodetect). 40805ee799fSJohn Youn * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo 40905ee799fSJohn Youn * mode. Each value corresponds to one EP 41005ee799fSJohn Youn * starting from EP1 (max 15 values). Sizes are 41105ee799fSJohn Youn * in DWORDS with possible values from from 41205ee799fSJohn Youn * 16-32768 (default: 256, 256, 256, 256, 768, 41305ee799fSJohn Youn * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0). 414ca8b0332SChen Yu * @change_speed_quirk: Change speed configuration to DWC2_SPEED_PARAM_FULL 415ca8b0332SChen Yu * while full&low speed device connect. And change speed 416ca8b0332SChen Yu * back to DWC2_SPEED_PARAM_HIGH while device is gone. 417ca8b0332SChen Yu * 0 - No (default) 418ca8b0332SChen Yu * 1 - Yes 419197ba5f4SPaul Zimmerman * 420197ba5f4SPaul Zimmerman * The following parameters may be specified when starting the module. These 421197ba5f4SPaul Zimmerman * parameters define how the DWC_otg controller should be configured. A 422197ba5f4SPaul Zimmerman * value of -1 (or any other out of range value) for any parameter means 423197ba5f4SPaul Zimmerman * to read the value from hardware (if possible) or use the builtin 424197ba5f4SPaul Zimmerman * default described above. 425197ba5f4SPaul Zimmerman */ 426197ba5f4SPaul Zimmerman struct dwc2_core_params { 427d21bcc3fSJohn Youn u8 otg_cap; 428c1d286cfSJohn Youn #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 429c1d286cfSJohn Youn #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 430c1d286cfSJohn Youn #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 431c1d286cfSJohn Youn 432d21bcc3fSJohn Youn u8 phy_type; 433c1d286cfSJohn Youn #define DWC2_PHY_TYPE_PARAM_FS 0 434c1d286cfSJohn Youn #define DWC2_PHY_TYPE_PARAM_UTMI 1 435c1d286cfSJohn Youn #define DWC2_PHY_TYPE_PARAM_ULPI 2 436c1d286cfSJohn Youn 43757b8e235SJohn Youn u8 speed; 43857b8e235SJohn Youn #define DWC2_SPEED_PARAM_HIGH 0 43957b8e235SJohn Youn #define DWC2_SPEED_PARAM_FULL 1 44057b8e235SJohn Youn #define DWC2_SPEED_PARAM_LOW 2 44157b8e235SJohn Youn 442d21bcc3fSJohn Youn u8 phy_utmi_width; 443d21bcc3fSJohn Youn bool phy_ulpi_ddr; 444d21bcc3fSJohn Youn bool phy_ulpi_ext_vbus; 44557b8e235SJohn Youn bool enable_dynamic_fifo; 44657b8e235SJohn Youn bool en_multiple_tx_fifo; 447d21bcc3fSJohn Youn bool i2c_enable; 44866e77a24SRazmik Karapetyan bool acg_enable; 449d21bcc3fSJohn Youn bool ulpi_fs_ls; 45057b8e235SJohn Youn bool ts_dline; 45157b8e235SJohn Youn bool reload_ctl; 45257b8e235SJohn Youn bool uframe_sched; 45357b8e235SJohn Youn bool external_id_pin_ctl; 454631a2310SVardan Mikayelyan 455631a2310SVardan Mikayelyan int power_down; 456631a2310SVardan Mikayelyan #define DWC2_POWER_DOWN_PARAM_NONE 0 457631a2310SVardan Mikayelyan #define DWC2_POWER_DOWN_PARAM_PARTIAL 1 458631a2310SVardan Mikayelyan #define DWC2_POWER_DOWN_PARAM_HIBERNATION 2 459631a2310SVardan Mikayelyan 4606f80b6deSSevak Arakelyan bool lpm; 4616f80b6deSSevak Arakelyan bool lpm_clock_gating; 4626f80b6deSSevak Arakelyan bool besl; 4636f80b6deSSevak Arakelyan bool hird_threshold_en; 4646f80b6deSSevak Arakelyan u8 hird_threshold; 465e35b1350SBruno Herrera bool activate_stm_fs_transceiver; 466b43ebc96SGrigor Tovmasyan bool ipg_isoc_en; 46757b8e235SJohn Youn u16 max_packet_count; 46857b8e235SJohn Youn u32 max_transfer_size; 46957b8e235SJohn Youn u32 ahbcfg; 47057b8e235SJohn Youn 47157b8e235SJohn Youn /* Host parameters */ 47257b8e235SJohn Youn bool host_dma; 47357b8e235SJohn Youn bool dma_desc_enable; 47457b8e235SJohn Youn bool dma_desc_fs_enable; 475d21bcc3fSJohn Youn bool host_support_fs_ls_low_power; 476d21bcc3fSJohn Youn bool host_ls_low_power_phy_clk; 477b11633c4SDinh Nguyen bool oc_disable; 478c1d286cfSJohn Youn 47957b8e235SJohn Youn u8 host_channels; 48057b8e235SJohn Youn u16 host_rx_fifo_size; 48157b8e235SJohn Youn u16 host_nperio_tx_fifo_size; 48257b8e235SJohn Youn u16 host_perio_tx_fifo_size; 4836b66ce51SJohn Youn 4846b66ce51SJohn Youn /* Gadget parameters */ 48505ee799fSJohn Youn bool g_dma; 486dec4b556SVahram Aharonyan bool g_dma_desc; 48700c704ccSLeo Yan u32 g_rx_fifo_size; 48800c704ccSLeo Yan u32 g_np_tx_fifo_size; 48905ee799fSJohn Youn u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; 490ca8b0332SChen Yu 491ca8b0332SChen Yu bool change_speed_quirk; 492197ba5f4SPaul Zimmerman }; 493197ba5f4SPaul Zimmerman 494197ba5f4SPaul Zimmerman /** 495197ba5f4SPaul Zimmerman * struct dwc2_hw_params - Autodetected parameters. 496197ba5f4SPaul Zimmerman * 497197ba5f4SPaul Zimmerman * These parameters are the various parameters read from hardware 498197ba5f4SPaul Zimmerman * registers during initialization. They typically contain the best 499197ba5f4SPaul Zimmerman * supported or maximum value that can be configured in the 500197ba5f4SPaul Zimmerman * corresponding dwc2_core_params value. 501197ba5f4SPaul Zimmerman * 502197ba5f4SPaul Zimmerman * The values that are not in dwc2_core_params are documented below. 503197ba5f4SPaul Zimmerman * 5046fb914d7SGrigor Tovmasyan * @op_mode: Mode of Operation 505197ba5f4SPaul Zimmerman * 0 - HNP- and SRP-Capable OTG (Host & Device) 506197ba5f4SPaul Zimmerman * 1 - SRP-Capable OTG (Host & Device) 507197ba5f4SPaul Zimmerman * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 508197ba5f4SPaul Zimmerman * 3 - SRP-Capable Device 509197ba5f4SPaul Zimmerman * 4 - Non-OTG Device 510197ba5f4SPaul Zimmerman * 5 - SRP-Capable Host 511197ba5f4SPaul Zimmerman * 6 - Non-OTG Host 5126fb914d7SGrigor Tovmasyan * @arch: Architecture 513197ba5f4SPaul Zimmerman * 0 - Slave only 514197ba5f4SPaul Zimmerman * 1 - External DMA 515197ba5f4SPaul Zimmerman * 2 - Internal DMA 5166fb914d7SGrigor Tovmasyan * @ipg_isoc_en: This feature indicates that the controller supports 517b43ebc96SGrigor Tovmasyan * the worst-case scenario of Rx followed by Rx 518b43ebc96SGrigor Tovmasyan * Interpacket Gap (IPG) (32 bitTimes) as per the utmi 519b43ebc96SGrigor Tovmasyan * specification for any token following ISOC OUT token. 520b43ebc96SGrigor Tovmasyan * 0 - Don't support 521b43ebc96SGrigor Tovmasyan * 1 - Support 5226fb914d7SGrigor Tovmasyan * @power_optimized: Are power optimizations enabled? 5236fb914d7SGrigor Tovmasyan * @num_dev_ep: Number of device endpoints available 5246fb914d7SGrigor Tovmasyan * @num_dev_in_eps: Number of device IN endpoints available 5256fb914d7SGrigor Tovmasyan * @num_dev_perio_in_ep: Number of device periodic IN endpoints 526997f4f81SMickael Maison * available 5276fb914d7SGrigor Tovmasyan * @dev_token_q_depth: Device Mode IN Token Sequence Learning Queue 528197ba5f4SPaul Zimmerman * Depth 529197ba5f4SPaul Zimmerman * 0 to 30 5306fb914d7SGrigor Tovmasyan * @host_perio_tx_q_depth: 531197ba5f4SPaul Zimmerman * Host Mode Periodic Request Queue Depth 532197ba5f4SPaul Zimmerman * 2, 4 or 8 5336fb914d7SGrigor Tovmasyan * @nperio_tx_q_depth: 534197ba5f4SPaul Zimmerman * Non-Periodic Request Queue Depth 535197ba5f4SPaul Zimmerman * 2, 4 or 8 5366fb914d7SGrigor Tovmasyan * @hs_phy_type: High-speed PHY interface type 537197ba5f4SPaul Zimmerman * 0 - High-speed interface not supported 538197ba5f4SPaul Zimmerman * 1 - UTMI+ 539197ba5f4SPaul Zimmerman * 2 - ULPI 540197ba5f4SPaul Zimmerman * 3 - UTMI+ and ULPI 5416fb914d7SGrigor Tovmasyan * @fs_phy_type: Full-speed PHY interface type 542197ba5f4SPaul Zimmerman * 0 - Full speed interface not supported 543197ba5f4SPaul Zimmerman * 1 - Dedicated full speed interface 544197ba5f4SPaul Zimmerman * 2 - FS pins shared with UTMI+ pins 545197ba5f4SPaul Zimmerman * 3 - FS pins shared with ULPI pins 546197ba5f4SPaul Zimmerman * @total_fifo_size: Total internal RAM for FIFOs (bytes) 5476fb914d7SGrigor Tovmasyan * @hibernation: Is hibernation enabled? 5486fb914d7SGrigor Tovmasyan * @utmi_phy_data_width: UTMI+ PHY data width 549197ba5f4SPaul Zimmerman * 0 - 8 bits 550197ba5f4SPaul Zimmerman * 1 - 16 bits 551197ba5f4SPaul Zimmerman * 2 - 8 or 16 bits 552197ba5f4SPaul Zimmerman * @snpsid: Value from SNPSID register 55355e1040eSJohn Youn * @dev_ep_dirs: Direction of device endpoints (GHWCFG1) 5546fb914d7SGrigor Tovmasyan * @g_tx_fifo_size: Power-on values of TxFIFO sizes 5556fb914d7SGrigor Tovmasyan * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 5566fb914d7SGrigor Tovmasyan * address DMA mode or descriptor DMA mode for accessing 5576fb914d7SGrigor Tovmasyan * the data FIFOs. The driver will automatically detect the 5586fb914d7SGrigor Tovmasyan * value for this if none is specified. 5596fb914d7SGrigor Tovmasyan * 0 - Address DMA 5606fb914d7SGrigor Tovmasyan * 1 - Descriptor DMA (default, if available) 5616fb914d7SGrigor Tovmasyan * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 5626fb914d7SGrigor Tovmasyan * 1 - Allow dynamic FIFO sizing (default, if available) 5636fb914d7SGrigor Tovmasyan * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 5646fb914d7SGrigor Tovmasyan * are enabled for non-periodic IN endpoints in device 5656fb914d7SGrigor Tovmasyan * mode. 5666fb914d7SGrigor Tovmasyan * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 5676fb914d7SGrigor Tovmasyan * in host mode when dynamic FIFO sizing is enabled 5686fb914d7SGrigor Tovmasyan * 16 to 32768 5696fb914d7SGrigor Tovmasyan * Actual maximum value is autodetected and also 5706fb914d7SGrigor Tovmasyan * the default. 5716fb914d7SGrigor Tovmasyan * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 5726fb914d7SGrigor Tovmasyan * host mode when dynamic FIFO sizing is enabled 5736fb914d7SGrigor Tovmasyan * 16 to 32768 5746fb914d7SGrigor Tovmasyan * Actual maximum value is autodetected and also 5756fb914d7SGrigor Tovmasyan * the default. 5766fb914d7SGrigor Tovmasyan * @max_transfer_size: The maximum transfer size supported, in bytes 5776fb914d7SGrigor Tovmasyan * 2047 to 65,535 5786fb914d7SGrigor Tovmasyan * Actual maximum value is autodetected and also 5796fb914d7SGrigor Tovmasyan * the default. 5806fb914d7SGrigor Tovmasyan * @max_packet_count: The maximum number of packets in a transfer 5816fb914d7SGrigor Tovmasyan * 15 to 511 5826fb914d7SGrigor Tovmasyan * Actual maximum value is autodetected and also 5836fb914d7SGrigor Tovmasyan * the default. 5846fb914d7SGrigor Tovmasyan * @host_channels: The number of host channel registers to use 5856fb914d7SGrigor Tovmasyan * 1 to 16 5866fb914d7SGrigor Tovmasyan * Actual maximum value is autodetected and also 5876fb914d7SGrigor Tovmasyan * the default. 5886fb914d7SGrigor Tovmasyan * @dev_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 5896fb914d7SGrigor Tovmasyan * in device mode when dynamic FIFO sizing is enabled 5906fb914d7SGrigor Tovmasyan * 16 to 32768 5916fb914d7SGrigor Tovmasyan * Actual maximum value is autodetected and also 5926fb914d7SGrigor Tovmasyan * the default. 5936fb914d7SGrigor Tovmasyan * @i2c_enable: Specifies whether to use the I2Cinterface for a full 5946fb914d7SGrigor Tovmasyan * speed PHY. This parameter is only applicable if phy_type 5956fb914d7SGrigor Tovmasyan * is FS. 5966fb914d7SGrigor Tovmasyan * 0 - No (default) 5976fb914d7SGrigor Tovmasyan * 1 - Yes 5986fb914d7SGrigor Tovmasyan * @acg_enable: For enabling Active Clock Gating in the controller 5996fb914d7SGrigor Tovmasyan * 0 - Disable 6006fb914d7SGrigor Tovmasyan * 1 - Enable 6016fb914d7SGrigor Tovmasyan * @lpm_mode: For enabling Link Power Management in the controller 6026fb914d7SGrigor Tovmasyan * 0 - Disable 6036fb914d7SGrigor Tovmasyan * 1 - Enable 6046fb914d7SGrigor Tovmasyan * @rx_fifo_size: Number of 4-byte words in the Rx FIFO when dynamic 6056fb914d7SGrigor Tovmasyan * FIFO sizing is enabled 16 to 32768 6066fb914d7SGrigor Tovmasyan * Actual maximum value is autodetected and also 6076fb914d7SGrigor Tovmasyan * the default. 608197ba5f4SPaul Zimmerman */ 609197ba5f4SPaul Zimmerman struct dwc2_hw_params { 610197ba5f4SPaul Zimmerman unsigned op_mode:3; 611197ba5f4SPaul Zimmerman unsigned arch:2; 612197ba5f4SPaul Zimmerman unsigned dma_desc_enable:1; 613197ba5f4SPaul Zimmerman unsigned enable_dynamic_fifo:1; 614197ba5f4SPaul Zimmerman unsigned en_multiple_tx_fifo:1; 615d1531319SJohn Youn unsigned rx_fifo_size:16; 616197ba5f4SPaul Zimmerman unsigned host_nperio_tx_fifo_size:16; 61755e1040eSJohn Youn unsigned dev_nperio_tx_fifo_size:16; 618197ba5f4SPaul Zimmerman unsigned host_perio_tx_fifo_size:16; 619197ba5f4SPaul Zimmerman unsigned nperio_tx_q_depth:3; 620197ba5f4SPaul Zimmerman unsigned host_perio_tx_q_depth:3; 621197ba5f4SPaul Zimmerman unsigned dev_token_q_depth:5; 622197ba5f4SPaul Zimmerman unsigned max_transfer_size:26; 623197ba5f4SPaul Zimmerman unsigned max_packet_count:11; 624197ba5f4SPaul Zimmerman unsigned host_channels:5; 625197ba5f4SPaul Zimmerman unsigned hs_phy_type:2; 626197ba5f4SPaul Zimmerman unsigned fs_phy_type:2; 627197ba5f4SPaul Zimmerman unsigned i2c_enable:1; 62866e77a24SRazmik Karapetyan unsigned acg_enable:1; 629197ba5f4SPaul Zimmerman unsigned num_dev_ep:4; 6309273083aSMinas Harutyunyan unsigned num_dev_in_eps : 4; 631197ba5f4SPaul Zimmerman unsigned num_dev_perio_in_ep:4; 632197ba5f4SPaul Zimmerman unsigned total_fifo_size:16; 633197ba5f4SPaul Zimmerman unsigned power_optimized:1; 634631a2310SVardan Mikayelyan unsigned hibernation:1; 635197ba5f4SPaul Zimmerman unsigned utmi_phy_data_width:2; 6366f80b6deSSevak Arakelyan unsigned lpm_mode:1; 637b43ebc96SGrigor Tovmasyan unsigned ipg_isoc_en:1; 638197ba5f4SPaul Zimmerman u32 snpsid; 63955e1040eSJohn Youn u32 dev_ep_dirs; 6409273083aSMinas Harutyunyan u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; 641197ba5f4SPaul Zimmerman }; 642197ba5f4SPaul Zimmerman 6433f95001dSMian Yousaf Kaukab /* Size of control and EP0 buffers */ 6443f95001dSMian Yousaf Kaukab #define DWC2_CTRL_BUFF_SIZE 8 6453f95001dSMian Yousaf Kaukab 646197ba5f4SPaul Zimmerman /** 64738beaec6SJohn Youn * struct dwc2_gregs_backup - Holds global registers state before 64838beaec6SJohn Youn * entering partial power down 649d17ee77bSGregory Herrero * @gotgctl: Backup of GOTGCTL register 650d17ee77bSGregory Herrero * @gintmsk: Backup of GINTMSK register 651d17ee77bSGregory Herrero * @gahbcfg: Backup of GAHBCFG register 652d17ee77bSGregory Herrero * @gusbcfg: Backup of GUSBCFG register 653d17ee77bSGregory Herrero * @grxfsiz: Backup of GRXFSIZ register 654d17ee77bSGregory Herrero * @gnptxfsiz: Backup of GNPTXFSIZ register 655d17ee77bSGregory Herrero * @gi2cctl: Backup of GI2CCTL register 65666a36096SVardan Mikayelyan * @glpmcfg: Backup of GLPMCFG register 657d17ee77bSGregory Herrero * @gdfifocfg: Backup of GDFIFOCFG register 6586fb914d7SGrigor Tovmasyan * @pcgcctl: Backup of PCGCCTL register 6596fb914d7SGrigor Tovmasyan * @pcgcctl1: Backup of PCGCCTL1 register 6606fb914d7SGrigor Tovmasyan * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 661d17ee77bSGregory Herrero * @gpwrdn: Backup of GPWRDN register 6626fb914d7SGrigor Tovmasyan * @valid: True if registers values backuped. 663d17ee77bSGregory Herrero */ 664d17ee77bSGregory Herrero struct dwc2_gregs_backup { 665d17ee77bSGregory Herrero u32 gotgctl; 666d17ee77bSGregory Herrero u32 gintmsk; 667d17ee77bSGregory Herrero u32 gahbcfg; 668d17ee77bSGregory Herrero u32 gusbcfg; 669d17ee77bSGregory Herrero u32 grxfsiz; 670d17ee77bSGregory Herrero u32 gnptxfsiz; 671d17ee77bSGregory Herrero u32 gi2cctl; 67266a36096SVardan Mikayelyan u32 glpmcfg; 673d17ee77bSGregory Herrero u32 pcgcctl; 674600a490eSRazmik Karapetyan u32 pcgcctl1; 675d17ee77bSGregory Herrero u32 gdfifocfg; 676d17ee77bSGregory Herrero u32 gpwrdn; 677cc1e204cSMian Yousaf Kaukab bool valid; 678d17ee77bSGregory Herrero }; 679d17ee77bSGregory Herrero 680d17ee77bSGregory Herrero /** 68138beaec6SJohn Youn * struct dwc2_dregs_backup - Holds device registers state before 68238beaec6SJohn Youn * entering partial power down 683d17ee77bSGregory Herrero * @dcfg: Backup of DCFG register 684d17ee77bSGregory Herrero * @dctl: Backup of DCTL register 685d17ee77bSGregory Herrero * @daintmsk: Backup of DAINTMSK register 686d17ee77bSGregory Herrero * @diepmsk: Backup of DIEPMSK register 687d17ee77bSGregory Herrero * @doepmsk: Backup of DOEPMSK register 688d17ee77bSGregory Herrero * @diepctl: Backup of DIEPCTL register 689d17ee77bSGregory Herrero * @dieptsiz: Backup of DIEPTSIZ register 690d17ee77bSGregory Herrero * @diepdma: Backup of DIEPDMA register 691d17ee77bSGregory Herrero * @doepctl: Backup of DOEPCTL register 692d17ee77bSGregory Herrero * @doeptsiz: Backup of DOEPTSIZ register 693d17ee77bSGregory Herrero * @doepdma: Backup of DOEPDMA register 694af7c2bd3SVardan Mikayelyan * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 6956fb914d7SGrigor Tovmasyan * @valid: True if registers values backuped. 696d17ee77bSGregory Herrero */ 697d17ee77bSGregory Herrero struct dwc2_dregs_backup { 698d17ee77bSGregory Herrero u32 dcfg; 699d17ee77bSGregory Herrero u32 dctl; 700d17ee77bSGregory Herrero u32 daintmsk; 701d17ee77bSGregory Herrero u32 diepmsk; 702d17ee77bSGregory Herrero u32 doepmsk; 703d17ee77bSGregory Herrero u32 diepctl[MAX_EPS_CHANNELS]; 704d17ee77bSGregory Herrero u32 dieptsiz[MAX_EPS_CHANNELS]; 705d17ee77bSGregory Herrero u32 diepdma[MAX_EPS_CHANNELS]; 706d17ee77bSGregory Herrero u32 doepctl[MAX_EPS_CHANNELS]; 707d17ee77bSGregory Herrero u32 doeptsiz[MAX_EPS_CHANNELS]; 708d17ee77bSGregory Herrero u32 doepdma[MAX_EPS_CHANNELS]; 709af7c2bd3SVardan Mikayelyan u32 dtxfsiz[MAX_EPS_CHANNELS]; 710cc1e204cSMian Yousaf Kaukab bool valid; 711d17ee77bSGregory Herrero }; 712d17ee77bSGregory Herrero 713d17ee77bSGregory Herrero /** 71438beaec6SJohn Youn * struct dwc2_hregs_backup - Holds host registers state before 71538beaec6SJohn Youn * entering partial power down 716d17ee77bSGregory Herrero * @hcfg: Backup of HCFG register 717d17ee77bSGregory Herrero * @haintmsk: Backup of HAINTMSK register 718d17ee77bSGregory Herrero * @hcintmsk: Backup of HCINTMSK register 7196fb914d7SGrigor Tovmasyan * @hprt0: Backup of HPTR0 register 720d17ee77bSGregory Herrero * @hfir: Backup of HFIR register 72166a36096SVardan Mikayelyan * @hptxfsiz: Backup of HPTXFSIZ register 7226fb914d7SGrigor Tovmasyan * @valid: True if registers values backuped. 723d17ee77bSGregory Herrero */ 724d17ee77bSGregory Herrero struct dwc2_hregs_backup { 725d17ee77bSGregory Herrero u32 hcfg; 726d17ee77bSGregory Herrero u32 haintmsk; 727d17ee77bSGregory Herrero u32 hcintmsk[MAX_EPS_CHANNELS]; 728d17ee77bSGregory Herrero u32 hprt0; 729d17ee77bSGregory Herrero u32 hfir; 73066a36096SVardan Mikayelyan u32 hptxfsiz; 731cc1e204cSMian Yousaf Kaukab bool valid; 732d17ee77bSGregory Herrero }; 733d17ee77bSGregory Herrero 7349f9f09b0SDouglas Anderson /* 7359f9f09b0SDouglas Anderson * Constants related to high speed periodic scheduling 7369f9f09b0SDouglas Anderson * 7379f9f09b0SDouglas Anderson * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a 7389f9f09b0SDouglas Anderson * reservation point of view it's assumed that the schedule goes right back to 7399f9f09b0SDouglas Anderson * the beginning after the end of the schedule. 7409f9f09b0SDouglas Anderson * 7419f9f09b0SDouglas Anderson * What does that mean for scheduling things with a long interval? It means 7429f9f09b0SDouglas Anderson * we'll reserve time for them in every possible microframe that they could 7439f9f09b0SDouglas Anderson * ever be scheduled in. ...but we'll still only actually schedule them as 7449f9f09b0SDouglas Anderson * often as they were requested. 7459f9f09b0SDouglas Anderson * 7469f9f09b0SDouglas Anderson * We keep our schedule in a "bitmap" structure. This simplifies having 7479f9f09b0SDouglas Anderson * to keep track of and merge intervals: we just let the bitmap code do most 7489f9f09b0SDouglas Anderson * of the heavy lifting. In a way scheduling is much like memory allocation. 7499f9f09b0SDouglas Anderson * 7509f9f09b0SDouglas Anderson * We schedule 100us per uframe or 80% of 125us (the maximum amount you're 7519f9f09b0SDouglas Anderson * supposed to schedule for periodic transfers). That's according to spec. 7529f9f09b0SDouglas Anderson * 7539f9f09b0SDouglas Anderson * Note that though we only schedule 80% of each microframe, the bitmap that we 7549f9f09b0SDouglas Anderson * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of 7559f9f09b0SDouglas Anderson * space for each uFrame). 7569f9f09b0SDouglas Anderson * 7579f9f09b0SDouglas Anderson * Requirements: 7589f9f09b0SDouglas Anderson * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1) 7599f9f09b0SDouglas Anderson * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably 7609f9f09b0SDouglas Anderson * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might 7619f9f09b0SDouglas Anderson * be bugs). The 8 comes from the USB spec: number of microframes per frame. 7629f9f09b0SDouglas Anderson */ 7639f9f09b0SDouglas Anderson #define DWC2_US_PER_UFRAME 125 7649f9f09b0SDouglas Anderson #define DWC2_HS_PERIODIC_US_PER_UFRAME 100 7659f9f09b0SDouglas Anderson 7669f9f09b0SDouglas Anderson #define DWC2_HS_SCHEDULE_UFRAMES 8 7679f9f09b0SDouglas Anderson #define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \ 7689f9f09b0SDouglas Anderson DWC2_HS_PERIODIC_US_PER_UFRAME) 7699f9f09b0SDouglas Anderson 7709f9f09b0SDouglas Anderson /* 7719f9f09b0SDouglas Anderson * Constants related to low speed scheduling 7729f9f09b0SDouglas Anderson * 7739f9f09b0SDouglas Anderson * For high speed we schedule every 1us. For low speed that's a bit overkill, 7749f9f09b0SDouglas Anderson * so we make up a unit called a "slice" that's worth 25us. There are 40 7759f9f09b0SDouglas Anderson * slices in a full frame and we can schedule 36 of those (90%) for periodic 7769f9f09b0SDouglas Anderson * transfers. 7779f9f09b0SDouglas Anderson * 7789f9f09b0SDouglas Anderson * Our low speed schedule can be as short as 1 frame or could be longer. When 7799f9f09b0SDouglas Anderson * we only schedule 1 frame it means that we'll need to reserve a time every 7809f9f09b0SDouglas Anderson * frame even for things that only transfer very rarely, so something that runs 7819f9f09b0SDouglas Anderson * every 2048 frames will get time reserved in every frame. Our low speed 7829f9f09b0SDouglas Anderson * schedule can be longer and we'll be able to handle more overlap, but that 7839f9f09b0SDouglas Anderson * will come at increased memory cost and increased time to schedule. 7849f9f09b0SDouglas Anderson * 7859f9f09b0SDouglas Anderson * Note: one other advantage of a short low speed schedule is that if we mess 7869f9f09b0SDouglas Anderson * up and miss scheduling we can jump in and use any of the slots that we 7879f9f09b0SDouglas Anderson * happened to reserve. 7889f9f09b0SDouglas Anderson * 7899f9f09b0SDouglas Anderson * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for 7909f9f09b0SDouglas Anderson * the schedule. There will be one schedule per TT. 7919f9f09b0SDouglas Anderson * 7929f9f09b0SDouglas Anderson * Requirements: 7939f9f09b0SDouglas Anderson * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME. 7949f9f09b0SDouglas Anderson */ 7959f9f09b0SDouglas Anderson #define DWC2_US_PER_SLICE 25 7969f9f09b0SDouglas Anderson #define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE) 7979f9f09b0SDouglas Anderson 7989f9f09b0SDouglas Anderson #define DWC2_ROUND_US_TO_SLICE(us) \ 7999f9f09b0SDouglas Anderson (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \ 8009f9f09b0SDouglas Anderson DWC2_US_PER_SLICE) 8019f9f09b0SDouglas Anderson 8029f9f09b0SDouglas Anderson #define DWC2_LS_PERIODIC_US_PER_FRAME \ 8039f9f09b0SDouglas Anderson 900 8049f9f09b0SDouglas Anderson #define DWC2_LS_PERIODIC_SLICES_PER_FRAME \ 8059f9f09b0SDouglas Anderson (DWC2_LS_PERIODIC_US_PER_FRAME / \ 8069f9f09b0SDouglas Anderson DWC2_US_PER_SLICE) 8079f9f09b0SDouglas Anderson 8089f9f09b0SDouglas Anderson #define DWC2_LS_SCHEDULE_FRAMES 1 8099f9f09b0SDouglas Anderson #define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \ 8109f9f09b0SDouglas Anderson DWC2_LS_PERIODIC_SLICES_PER_FRAME) 8119f9f09b0SDouglas Anderson 812d17ee77bSGregory Herrero /** 813197ba5f4SPaul Zimmerman * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 814197ba5f4SPaul Zimmerman * and periodic schedules 815197ba5f4SPaul Zimmerman * 816941fcce4SDinh Nguyen * These are common for both host and peripheral modes: 817941fcce4SDinh Nguyen * 818197ba5f4SPaul Zimmerman * @dev: The struct device pointer 819197ba5f4SPaul Zimmerman * @regs: Pointer to controller regs 820197ba5f4SPaul Zimmerman * @hw_params: Parameters that were autodetected from the 821197ba5f4SPaul Zimmerman * hardware registers 8226fb914d7SGrigor Tovmasyan * @params: Parameters that define how the core should be configured 823197ba5f4SPaul Zimmerman * @op_state: The operational State, during transitions (a_host=> 824197ba5f4SPaul Zimmerman * a_peripheral and b_device=>b_host) this may not match 825197ba5f4SPaul Zimmerman * the core, but allows the software to determine 826197ba5f4SPaul Zimmerman * transitions 827c0155b9dSKever Yang * @dr_mode: Requested mode of operation, one of following: 828c0155b9dSKever Yang * - USB_DR_MODE_PERIPHERAL 829c0155b9dSKever Yang * - USB_DR_MODE_HOST 830c0155b9dSKever Yang * - USB_DR_MODE_OTG 8316fb914d7SGrigor Tovmasyan * @hcd_enabled: Host mode sub-driver initialization indicator. 8326fb914d7SGrigor Tovmasyan * @gadget_enabled: Peripheral mode sub-driver initialization indicator. 8336fb914d7SGrigor Tovmasyan * @ll_hw_enabled: Status of low-level hardware resources. 83420fe4409SVardan Mikayelyan * @hibernated: True if core is hibernated 835c7c24e7aSArtur Petrosyan * @frame_number: Frame number read from the core. For both device 836c7c24e7aSArtur Petrosyan * and host modes. The value ranges are from 0 837c7c24e7aSArtur Petrosyan * to HFNUM_MAX_FRNUM. 83809a75e85SMarek Szyprowski * @phy: The otg phy transceiver structure for phy control. 83938beaec6SJohn Youn * @uphy: The otg phy transceiver structure for old USB phy 84038beaec6SJohn Youn * control. 84138beaec6SJohn Youn * @plat: The platform specific configuration data. This can be 84238beaec6SJohn Youn * removed once all SoCs support usb transceiver. 84309a75e85SMarek Szyprowski * @supplies: Definition of USB power supplies 844531ef5ebSAmelie Delaunay * @vbus_supply: Regulator supplying vbus. 84509a75e85SMarek Szyprowski * @phyif: PHY interface width 846941fcce4SDinh Nguyen * @lock: Spinlock that protects all the driver data structures 847941fcce4SDinh Nguyen * @priv: Stores a pointer to the struct usb_hcd 848197ba5f4SPaul Zimmerman * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 849197ba5f4SPaul Zimmerman * transfer are in process of being queued 850197ba5f4SPaul Zimmerman * @srp_success: Stores status of SRP request in the case of a FS PHY 851197ba5f4SPaul Zimmerman * with an I2C interface 852197ba5f4SPaul Zimmerman * @wq_otg: Workqueue object used for handling of some interrupts 853197ba5f4SPaul Zimmerman * @wf_otg: Work object for handling Connector ID Status Change 854197ba5f4SPaul Zimmerman * interrupt 855197ba5f4SPaul Zimmerman * @wkp_timer: Timer object for handling Wakeup Detected interrupt 856197ba5f4SPaul Zimmerman * @lx_state: Lx state of connected device 8576fb914d7SGrigor Tovmasyan * @gr_backup: Backup of global registers during suspend 8586fb914d7SGrigor Tovmasyan * @dr_backup: Backup of device registers during suspend 8596fb914d7SGrigor Tovmasyan * @hr_backup: Backup of host registers during suspend 860941fcce4SDinh Nguyen * 861941fcce4SDinh Nguyen * These are for host mode: 862941fcce4SDinh Nguyen * 863197ba5f4SPaul Zimmerman * @flags: Flags for handling root port state changes 8646fb914d7SGrigor Tovmasyan * @flags.d32: Contain all root port flags 8656fb914d7SGrigor Tovmasyan * @flags.b: Separate root port flags from each other 8666fb914d7SGrigor Tovmasyan * @flags.b.port_connect_status_change: True if root port connect status 8676fb914d7SGrigor Tovmasyan * changed 8686fb914d7SGrigor Tovmasyan * @flags.b.port_connect_status: True if device connected to root port 8696fb914d7SGrigor Tovmasyan * @flags.b.port_reset_change: True if root port reset status changed 8706fb914d7SGrigor Tovmasyan * @flags.b.port_enable_change: True if root port enable status changed 8716fb914d7SGrigor Tovmasyan * @flags.b.port_suspend_change: True if root port suspend status changed 8726fb914d7SGrigor Tovmasyan * @flags.b.port_over_current_change: True if root port over current state 8736fb914d7SGrigor Tovmasyan * changed. 8746fb914d7SGrigor Tovmasyan * @flags.b.port_l1_change: True if root port l1 status changed 8756fb914d7SGrigor Tovmasyan * @flags.b.reserved: Reserved bits of root port register 876197ba5f4SPaul Zimmerman * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 877197ba5f4SPaul Zimmerman * Transfers associated with these QHs are not currently 878197ba5f4SPaul Zimmerman * assigned to a host channel. 879197ba5f4SPaul Zimmerman * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 880197ba5f4SPaul Zimmerman * Transfers associated with these QHs are currently 881197ba5f4SPaul Zimmerman * assigned to a host channel. 882197ba5f4SPaul Zimmerman * @non_periodic_qh_ptr: Pointer to next QH to process in the active 883197ba5f4SPaul Zimmerman * non-periodic schedule 8846fb914d7SGrigor Tovmasyan * @non_periodic_sched_waiting: Waiting QHs in the non-periodic schedule. 8856fb914d7SGrigor Tovmasyan * Transfers associated with these QHs are not currently 8866fb914d7SGrigor Tovmasyan * assigned to a host channel. 887197ba5f4SPaul Zimmerman * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 888197ba5f4SPaul Zimmerman * list of QHs for periodic transfers that are _not_ 889197ba5f4SPaul Zimmerman * scheduled for the next frame. Each QH in the list has an 890197ba5f4SPaul Zimmerman * interval counter that determines when it needs to be 891197ba5f4SPaul Zimmerman * scheduled for execution. This scheduling mechanism 892197ba5f4SPaul Zimmerman * allows only a simple calculation for periodic bandwidth 893197ba5f4SPaul Zimmerman * used (i.e. must assume that all periodic transfers may 894197ba5f4SPaul Zimmerman * need to execute in the same frame). However, it greatly 895197ba5f4SPaul Zimmerman * simplifies scheduling and should be sufficient for the 896197ba5f4SPaul Zimmerman * vast majority of OTG hosts, which need to connect to a 897197ba5f4SPaul Zimmerman * small number of peripherals at one time. Items move from 898197ba5f4SPaul Zimmerman * this list to periodic_sched_ready when the QH interval 899197ba5f4SPaul Zimmerman * counter is 0 at SOF. 900197ba5f4SPaul Zimmerman * @periodic_sched_ready: List of periodic QHs that are ready for execution in 901197ba5f4SPaul Zimmerman * the next frame, but have not yet been assigned to host 902197ba5f4SPaul Zimmerman * channels. Items move from this list to 903197ba5f4SPaul Zimmerman * periodic_sched_assigned as host channels become 904197ba5f4SPaul Zimmerman * available during the current frame. 905197ba5f4SPaul Zimmerman * @periodic_sched_assigned: List of periodic QHs to be executed in the next 906197ba5f4SPaul Zimmerman * frame that are assigned to host channels. Items move 907197ba5f4SPaul Zimmerman * from this list to periodic_sched_queued as the 908197ba5f4SPaul Zimmerman * transactions for the QH are queued to the DWC_otg 909197ba5f4SPaul Zimmerman * controller. 910197ba5f4SPaul Zimmerman * @periodic_sched_queued: List of periodic QHs that have been queued for 911197ba5f4SPaul Zimmerman * execution. Items move from this list to either 912197ba5f4SPaul Zimmerman * periodic_sched_inactive or periodic_sched_ready when the 913197ba5f4SPaul Zimmerman * channel associated with the transfer is released. If the 914197ba5f4SPaul Zimmerman * interval for the QH is 1, the item moves to 915197ba5f4SPaul Zimmerman * periodic_sched_ready because it must be rescheduled for 916197ba5f4SPaul Zimmerman * the next frame. Otherwise, the item moves to 917197ba5f4SPaul Zimmerman * periodic_sched_inactive. 918c9c8ac01SDouglas Anderson * @split_order: List keeping track of channels doing splits, in order. 919197ba5f4SPaul Zimmerman * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 920197ba5f4SPaul Zimmerman * This value is in microseconds per (micro)frame. The 921197ba5f4SPaul Zimmerman * assumption is that all periodic transfers may occur in 922197ba5f4SPaul Zimmerman * the same (micro)frame. 9239f9f09b0SDouglas Anderson * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the 9249f9f09b0SDouglas Anderson * host is in high speed mode; low speed schedules are 9259f9f09b0SDouglas Anderson * stored elsewhere since we need one per TT. 926197ba5f4SPaul Zimmerman * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 927197ba5f4SPaul Zimmerman * SOF enable/disable. 928197ba5f4SPaul Zimmerman * @free_hc_list: Free host channels in the controller. This is a list of 929197ba5f4SPaul Zimmerman * struct dwc2_host_chan items. 930197ba5f4SPaul Zimmerman * @periodic_channels: Number of host channels assigned to periodic transfers. 931197ba5f4SPaul Zimmerman * Currently assuming that there is a dedicated host 932197ba5f4SPaul Zimmerman * channel for each periodic transaction and at least one 933197ba5f4SPaul Zimmerman * host channel is available for non-periodic transactions. 934197ba5f4SPaul Zimmerman * @non_periodic_channels: Number of host channels assigned to non-periodic 935197ba5f4SPaul Zimmerman * transfers 9366fb914d7SGrigor Tovmasyan * @available_host_channels: Number of host channels available for the 9376fb914d7SGrigor Tovmasyan * microframe scheduler to use 938197ba5f4SPaul Zimmerman * @hc_ptr_array: Array of pointers to the host channel descriptors. 939197ba5f4SPaul Zimmerman * Allows accessing a host channel descriptor given the 940197ba5f4SPaul Zimmerman * host channel number. This is useful in interrupt 941197ba5f4SPaul Zimmerman * handlers. 942197ba5f4SPaul Zimmerman * @status_buf: Buffer used for data received during the status phase of 943197ba5f4SPaul Zimmerman * a control transfer. 944197ba5f4SPaul Zimmerman * @status_buf_dma: DMA address for status_buf 945197ba5f4SPaul Zimmerman * @start_work: Delayed work for handling host A-cable connection 946197ba5f4SPaul Zimmerman * @reset_work: Delayed work for handling a port reset 947197ba5f4SPaul Zimmerman * @otg_port: OTG port number 948197ba5f4SPaul Zimmerman * @frame_list: Frame list 949197ba5f4SPaul Zimmerman * @frame_list_dma: Frame list DMA address 95095105a99SGregory Herrero * @frame_list_sz: Frame list size 9513b5fcc9aSGregory Herrero * @desc_gen_cache: Kmem cache for generic descriptors 9523b5fcc9aSGregory Herrero * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors 953af424a41SWilliam Wu * @unaligned_cache: Kmem cache for DMA mode to handle non-aligned buf 954941fcce4SDinh Nguyen * 955941fcce4SDinh Nguyen * These are for peripheral mode: 956941fcce4SDinh Nguyen * 957941fcce4SDinh Nguyen * @driver: USB gadget driver 958941fcce4SDinh Nguyen * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 959941fcce4SDinh Nguyen * @num_of_eps: Number of available EPs (excluding EP0) 960941fcce4SDinh Nguyen * @debug_root: Root directrory for debugfs. 961941fcce4SDinh Nguyen * @ep0_reply: Request used for ep0 reply. 962941fcce4SDinh Nguyen * @ep0_buff: Buffer for EP0 reply data, if needed. 963941fcce4SDinh Nguyen * @ctrl_buff: Buffer for EP0 control requests. 964941fcce4SDinh Nguyen * @ctrl_req: Request for EP0 control packets. 965fe0b94abSMian Yousaf Kaukab * @ep0_state: EP0 control transfers state 9669e14d0a5SGregory Herrero * @test_mode: USB test mode requested by the host 967fa389a6dSVardan Mikayelyan * @remote_wakeup_allowed: True if device is allowed to wake-up host by 968fa389a6dSVardan Mikayelyan * remote-wakeup signalling 9690f6b80c0SVahram Aharonyan * @setup_desc_dma: EP0 setup stage desc chain DMA address 9700f6b80c0SVahram Aharonyan * @setup_desc: EP0 setup stage desc chain pointer 9710f6b80c0SVahram Aharonyan * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address 9720f6b80c0SVahram Aharonyan * @ctrl_in_desc: EP0 IN data phase desc chain pointer 9730f6b80c0SVahram Aharonyan * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address 9740f6b80c0SVahram Aharonyan * @ctrl_out_desc: EP0 OUT data phase desc chain pointer 9756fb914d7SGrigor Tovmasyan * @irq: Interrupt request line number 9766fb914d7SGrigor Tovmasyan * @clk: Pointer to otg clock 9776fb914d7SGrigor Tovmasyan * @reset: Pointer to dwc2 reset controller 9786fb914d7SGrigor Tovmasyan * @reset_ecc: Pointer to dwc2 optional reset controller in Stratix10. 9796fb914d7SGrigor Tovmasyan * @regset: A pointer to a struct debugfs_regset32, which contains 9806fb914d7SGrigor Tovmasyan * a pointer to an array of register definitions, the 9816fb914d7SGrigor Tovmasyan * array size and the base address where the register bank 9826fb914d7SGrigor Tovmasyan * is to be found. 9836fb914d7SGrigor Tovmasyan * @bus_suspended: True if bus is suspended 9846fb914d7SGrigor Tovmasyan * @last_frame_num: Number of last frame. Range from 0 to 32768 9856fb914d7SGrigor Tovmasyan * @frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is 9866fb914d7SGrigor Tovmasyan * defined, for missed SOFs tracking. Array holds that 9876fb914d7SGrigor Tovmasyan * frame numbers, which not equal to last_frame_num +1 9886fb914d7SGrigor Tovmasyan * @last_frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is 9896fb914d7SGrigor Tovmasyan * defined, for missed SOFs tracking. 9906fb914d7SGrigor Tovmasyan * If current_frame_number != last_frame_num+1 9916fb914d7SGrigor Tovmasyan * then last_frame_num added to this array 9926fb914d7SGrigor Tovmasyan * @frame_num_idx: Actual size of frame_num_array and last_frame_num_array 9936fb914d7SGrigor Tovmasyan * @dumped_frame_num_array: 1 - if missed SOFs frame numbers dumbed 9946fb914d7SGrigor Tovmasyan * 0 - if missed SOFs frame numbers not dumbed 9956fb914d7SGrigor Tovmasyan * @fifo_mem: Total internal RAM for FIFOs (bytes) 9966fb914d7SGrigor Tovmasyan * @fifo_map: Each bit intend for concrete fifo. If that bit is set, 9976fb914d7SGrigor Tovmasyan * then that fifo is used 9986fb914d7SGrigor Tovmasyan * @gadget: Represents a usb slave device 9996fb914d7SGrigor Tovmasyan * @connected: Used in slave mode. True if device connected with host 10006fb914d7SGrigor Tovmasyan * @eps_in: The IN endpoints being supplied to the gadget framework 10016fb914d7SGrigor Tovmasyan * @eps_out: The OUT endpoints being supplied to the gadget framework 10026fb914d7SGrigor Tovmasyan * @new_connection: Used in host mode. True if there are new connected 10036fb914d7SGrigor Tovmasyan * device 10046fb914d7SGrigor Tovmasyan * @enabled: Indicates the enabling state of controller 10056fb914d7SGrigor Tovmasyan * 1006197ba5f4SPaul Zimmerman */ 1007197ba5f4SPaul Zimmerman struct dwc2_hsotg { 1008197ba5f4SPaul Zimmerman struct device *dev; 1009197ba5f4SPaul Zimmerman void __iomem *regs; 1010197ba5f4SPaul Zimmerman /** Params detected from hardware */ 1011197ba5f4SPaul Zimmerman struct dwc2_hw_params hw_params; 1012197ba5f4SPaul Zimmerman /** Params to actually use */ 1013bea8e86cSJohn Youn struct dwc2_core_params params; 1014197ba5f4SPaul Zimmerman enum usb_otg_state op_state; 1015c0155b9dSKever Yang enum usb_dr_mode dr_mode; 1016e39af88fSMarek Szyprowski unsigned int hcd_enabled:1; 1017e39af88fSMarek Szyprowski unsigned int gadget_enabled:1; 101809a75e85SMarek Szyprowski unsigned int ll_hw_enabled:1; 101920fe4409SVardan Mikayelyan unsigned int hibernated:1; 1020c7c24e7aSArtur Petrosyan u16 frame_number; 1021197ba5f4SPaul Zimmerman 1022941fcce4SDinh Nguyen struct phy *phy; 1023941fcce4SDinh Nguyen struct usb_phy *uphy; 102409a75e85SMarek Szyprowski struct dwc2_hsotg_plat *plat; 1025b98866c2SJohn Youn struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES]; 1026531ef5ebSAmelie Delaunay struct regulator *vbus_supply; 102709a75e85SMarek Szyprowski u32 phyif; 1028941fcce4SDinh Nguyen 1029941fcce4SDinh Nguyen spinlock_t lock; 1030941fcce4SDinh Nguyen void *priv; 1031941fcce4SDinh Nguyen int irq; 1032941fcce4SDinh Nguyen struct clk *clk; 103383f8da56SDinh Nguyen struct reset_control *reset; 1034f2830ad4SDinh Nguyen struct reset_control *reset_ecc; 1035941fcce4SDinh Nguyen 1036197ba5f4SPaul Zimmerman unsigned int queuing_high_bandwidth:1; 1037197ba5f4SPaul Zimmerman unsigned int srp_success:1; 1038197ba5f4SPaul Zimmerman 1039197ba5f4SPaul Zimmerman struct workqueue_struct *wq_otg; 1040197ba5f4SPaul Zimmerman struct work_struct wf_otg; 1041197ba5f4SPaul Zimmerman struct timer_list wkp_timer; 1042197ba5f4SPaul Zimmerman enum dwc2_lx_state lx_state; 1043cc1e204cSMian Yousaf Kaukab struct dwc2_gregs_backup gr_backup; 1044cc1e204cSMian Yousaf Kaukab struct dwc2_dregs_backup dr_backup; 1045cc1e204cSMian Yousaf Kaukab struct dwc2_hregs_backup hr_backup; 1046197ba5f4SPaul Zimmerman 1047941fcce4SDinh Nguyen struct dentry *debug_root; 1048563cf017SMian Yousaf Kaukab struct debugfs_regset32 *regset; 1049941fcce4SDinh Nguyen 1050941fcce4SDinh Nguyen /* DWC OTG HW Release versions */ 1051941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_71a 0x4f54271a 10525295322aSArtur Petrosyan #define DWC2_CORE_REV_2_72a 0x4f54272a 10536f80b6deSSevak Arakelyan #define DWC2_CORE_REV_2_80a 0x4f54280a 1054941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_90a 0x4f54290a 1055e1f411d1SSevak Arakelyan #define DWC2_CORE_REV_2_91a 0x4f54291a 1056941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_92a 0x4f54292a 1057941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_94a 0x4f54294a 1058941fcce4SDinh Nguyen #define DWC2_CORE_REV_3_00a 0x4f54300a 1059fef6bc37SJohn Youn #define DWC2_CORE_REV_3_10a 0x4f54310a 10605295322aSArtur Petrosyan #define DWC2_CORE_REV_4_00a 0x4f54400a 10611e6b98ebSVardan Mikayelyan #define DWC2_FS_IOT_REV_1_00a 0x5531100a 10621e6b98ebSVardan Mikayelyan #define DWC2_HS_IOT_REV_1_00a 0x5532100a 1063941fcce4SDinh Nguyen 1064d14ccabaSGevorg Sahakyan /* DWC OTG HW Core ID */ 1065d14ccabaSGevorg Sahakyan #define DWC2_OTG_ID 0x4f540000 1066d14ccabaSGevorg Sahakyan #define DWC2_FS_IOT_ID 0x55310000 1067d14ccabaSGevorg Sahakyan #define DWC2_HS_IOT_ID 0x55320000 1068d14ccabaSGevorg Sahakyan 1069941fcce4SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1070197ba5f4SPaul Zimmerman union dwc2_hcd_internal_flags { 1071197ba5f4SPaul Zimmerman u32 d32; 1072197ba5f4SPaul Zimmerman struct { 1073197ba5f4SPaul Zimmerman unsigned port_connect_status_change:1; 1074197ba5f4SPaul Zimmerman unsigned port_connect_status:1; 1075197ba5f4SPaul Zimmerman unsigned port_reset_change:1; 1076197ba5f4SPaul Zimmerman unsigned port_enable_change:1; 1077197ba5f4SPaul Zimmerman unsigned port_suspend_change:1; 1078197ba5f4SPaul Zimmerman unsigned port_over_current_change:1; 1079197ba5f4SPaul Zimmerman unsigned port_l1_change:1; 1080fd4850cfSCharles Manning unsigned reserved:25; 1081197ba5f4SPaul Zimmerman } b; 1082197ba5f4SPaul Zimmerman } flags; 1083197ba5f4SPaul Zimmerman 1084197ba5f4SPaul Zimmerman struct list_head non_periodic_sched_inactive; 108538d2b5fbSDouglas Anderson struct list_head non_periodic_sched_waiting; 1086197ba5f4SPaul Zimmerman struct list_head non_periodic_sched_active; 1087197ba5f4SPaul Zimmerman struct list_head *non_periodic_qh_ptr; 1088197ba5f4SPaul Zimmerman struct list_head periodic_sched_inactive; 1089197ba5f4SPaul Zimmerman struct list_head periodic_sched_ready; 1090197ba5f4SPaul Zimmerman struct list_head periodic_sched_assigned; 1091197ba5f4SPaul Zimmerman struct list_head periodic_sched_queued; 1092c9c8ac01SDouglas Anderson struct list_head split_order; 1093197ba5f4SPaul Zimmerman u16 periodic_usecs; 10949f9f09b0SDouglas Anderson unsigned long hs_periodic_bitmap[ 10959f9f09b0SDouglas Anderson DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)]; 1096197ba5f4SPaul Zimmerman u16 periodic_qh_count; 1097734643dfSGregory Herrero bool bus_suspended; 1098fbb9e22bSMian Yousaf Kaukab bool new_connection; 1099197ba5f4SPaul Zimmerman 1100483bb254SDouglas Anderson u16 last_frame_num; 1101483bb254SDouglas Anderson 1102197ba5f4SPaul Zimmerman #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 1103197ba5f4SPaul Zimmerman #define FRAME_NUM_ARRAY_SIZE 1000 1104197ba5f4SPaul Zimmerman u16 *frame_num_array; 1105197ba5f4SPaul Zimmerman u16 *last_frame_num_array; 1106197ba5f4SPaul Zimmerman int frame_num_idx; 1107197ba5f4SPaul Zimmerman int dumped_frame_num_array; 1108197ba5f4SPaul Zimmerman #endif 1109197ba5f4SPaul Zimmerman 1110197ba5f4SPaul Zimmerman struct list_head free_hc_list; 1111197ba5f4SPaul Zimmerman int periodic_channels; 1112197ba5f4SPaul Zimmerman int non_periodic_channels; 1113197ba5f4SPaul Zimmerman int available_host_channels; 1114197ba5f4SPaul Zimmerman struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 1115197ba5f4SPaul Zimmerman u8 *status_buf; 1116197ba5f4SPaul Zimmerman dma_addr_t status_buf_dma; 1117197ba5f4SPaul Zimmerman #define DWC2_HCD_STATUS_BUF_SIZE 64 1118197ba5f4SPaul Zimmerman 1119197ba5f4SPaul Zimmerman struct delayed_work start_work; 1120197ba5f4SPaul Zimmerman struct delayed_work reset_work; 1121197ba5f4SPaul Zimmerman u8 otg_port; 1122197ba5f4SPaul Zimmerman u32 *frame_list; 1123197ba5f4SPaul Zimmerman dma_addr_t frame_list_dma; 112495105a99SGregory Herrero u32 frame_list_sz; 11253b5fcc9aSGregory Herrero struct kmem_cache *desc_gen_cache; 11263b5fcc9aSGregory Herrero struct kmem_cache *desc_hsisoc_cache; 1127af424a41SWilliam Wu struct kmem_cache *unaligned_cache; 1128af424a41SWilliam Wu #define DWC2_KMEM_UNALIGNED_BUF_SIZE 1024 1129197ba5f4SPaul Zimmerman 1130941fcce4SDinh Nguyen #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ 1131941fcce4SDinh Nguyen 1132b98866c2SJohn Youn #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1133b98866c2SJohn Youn IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1134941fcce4SDinh Nguyen /* Gadget structures */ 1135941fcce4SDinh Nguyen struct usb_gadget_driver *driver; 1136941fcce4SDinh Nguyen int fifo_mem; 1137941fcce4SDinh Nguyen unsigned int dedicated_fifos:1; 1138941fcce4SDinh Nguyen unsigned char num_of_eps; 1139941fcce4SDinh Nguyen u32 fifo_map; 1140941fcce4SDinh Nguyen 1141941fcce4SDinh Nguyen struct usb_request *ep0_reply; 1142941fcce4SDinh Nguyen struct usb_request *ctrl_req; 11433f95001dSMian Yousaf Kaukab void *ep0_buff; 11443f95001dSMian Yousaf Kaukab void *ctrl_buff; 1145fe0b94abSMian Yousaf Kaukab enum dwc2_ep0_state ep0_state; 11469e14d0a5SGregory Herrero u8 test_mode; 1147941fcce4SDinh Nguyen 11480f6b80c0SVahram Aharonyan dma_addr_t setup_desc_dma[2]; 11490f6b80c0SVahram Aharonyan struct dwc2_dma_desc *setup_desc[2]; 11500f6b80c0SVahram Aharonyan dma_addr_t ctrl_in_desc_dma; 11510f6b80c0SVahram Aharonyan struct dwc2_dma_desc *ctrl_in_desc; 11520f6b80c0SVahram Aharonyan dma_addr_t ctrl_out_desc_dma; 11530f6b80c0SVahram Aharonyan struct dwc2_dma_desc *ctrl_out_desc; 11540f6b80c0SVahram Aharonyan 1155941fcce4SDinh Nguyen struct usb_gadget gadget; 1156dc6e69e6SMarek Szyprowski unsigned int enabled:1; 11574ace06e8SMarek Szyprowski unsigned int connected:1; 1158fa389a6dSVardan Mikayelyan unsigned int remote_wakeup_allowed:1; 11591f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS]; 11601f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS]; 1161941fcce4SDinh Nguyen #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 1162197ba5f4SPaul Zimmerman }; 1163197ba5f4SPaul Zimmerman 11640f548098SGevorg Sahakyan #ifdef CONFIG_MIPS 11650f548098SGevorg Sahakyan /* 11660f548098SGevorg Sahakyan * There are some MIPS machines that can run in either big-endian 11670f548098SGevorg Sahakyan * or little-endian mode and that use the dwc2 register without 11680f548098SGevorg Sahakyan * a byteswap in both ways. 11690f548098SGevorg Sahakyan * Unlike other architectures, MIPS apparently does not require a 11700f548098SGevorg Sahakyan * barrier before the __raw_writel() to synchronize with DMA but does 11710f548098SGevorg Sahakyan * require the barrier after the __raw_writel() to serialize a set of 11720f548098SGevorg Sahakyan * writes. This set of operations was added specifically for MIPS and 11730f548098SGevorg Sahakyan * should only be used there. 11740f548098SGevorg Sahakyan */ 1175f25c42b8SGevorg Sahakyan static inline u32 dwc2_readl(struct dwc2_hsotg *hsotg, u32 offset) 11760f548098SGevorg Sahakyan { 1177f25c42b8SGevorg Sahakyan u32 value = __raw_readl(hsotg->regs + offset); 11780f548098SGevorg Sahakyan 11790f548098SGevorg Sahakyan /* In order to preserve endianness __raw_* operation is used. Therefore 11800f548098SGevorg Sahakyan * a barrier is needed to ensure IO access is not re-ordered across 11810f548098SGevorg Sahakyan * reads or writes 11820f548098SGevorg Sahakyan */ 11830f548098SGevorg Sahakyan mb(); 11840f548098SGevorg Sahakyan return value; 11850f548098SGevorg Sahakyan } 11860f548098SGevorg Sahakyan 1187f25c42b8SGevorg Sahakyan static inline void dwc2_writel(struct dwc2_hsotg *hsotg, u32 value, u32 offset) 11880f548098SGevorg Sahakyan { 1189f25c42b8SGevorg Sahakyan __raw_writel(value, hsotg->regs + offset); 11900f548098SGevorg Sahakyan 11910f548098SGevorg Sahakyan /* 11920f548098SGevorg Sahakyan * In order to preserve endianness __raw_* operation is used. Therefore 11930f548098SGevorg Sahakyan * a barrier is needed to ensure IO access is not re-ordered across 11940f548098SGevorg Sahakyan * reads or writes 11950f548098SGevorg Sahakyan */ 11960f548098SGevorg Sahakyan mb(); 11970f548098SGevorg Sahakyan #ifdef DWC2_LOG_WRITES 1198f25c42b8SGevorg Sahakyan pr_info("INFO:: wrote %08x to %p\n", value, hsotg->regs + offset); 11990f548098SGevorg Sahakyan #endif 12000f548098SGevorg Sahakyan } 12010f548098SGevorg Sahakyan #else 1202f25c42b8SGevorg Sahakyan 12030f548098SGevorg Sahakyan /* Normal architectures just use readl/write */ 1204f25c42b8SGevorg Sahakyan static inline u32 dwc2_readl(struct dwc2_hsotg *hsotg, u32 offset) 12050f548098SGevorg Sahakyan { 1206f25c42b8SGevorg Sahakyan return readl(hsotg->regs + offset); 12070f548098SGevorg Sahakyan } 12080f548098SGevorg Sahakyan 1209f25c42b8SGevorg Sahakyan static inline void dwc2_writel(struct dwc2_hsotg *hsotg, u32 value, u32 offset) 12100f548098SGevorg Sahakyan { 1211f25c42b8SGevorg Sahakyan writel(value, hsotg->regs + offset); 12120f548098SGevorg Sahakyan 12130f548098SGevorg Sahakyan #ifdef DWC2_LOG_WRITES 1214f25c42b8SGevorg Sahakyan pr_info("info:: wrote %08x to %p\n", value, hsotg->regs + offset); 12150f548098SGevorg Sahakyan #endif 12160f548098SGevorg Sahakyan } 12170f548098SGevorg Sahakyan #endif 12180f548098SGevorg Sahakyan 1219197ba5f4SPaul Zimmerman /* Reasons for halting a host channel */ 1220197ba5f4SPaul Zimmerman enum dwc2_halt_status { 1221197ba5f4SPaul Zimmerman DWC2_HC_XFER_NO_HALT_STATUS, 1222197ba5f4SPaul Zimmerman DWC2_HC_XFER_COMPLETE, 1223197ba5f4SPaul Zimmerman DWC2_HC_XFER_URB_COMPLETE, 1224197ba5f4SPaul Zimmerman DWC2_HC_XFER_ACK, 1225197ba5f4SPaul Zimmerman DWC2_HC_XFER_NAK, 1226197ba5f4SPaul Zimmerman DWC2_HC_XFER_NYET, 1227197ba5f4SPaul Zimmerman DWC2_HC_XFER_STALL, 1228197ba5f4SPaul Zimmerman DWC2_HC_XFER_XACT_ERR, 1229197ba5f4SPaul Zimmerman DWC2_HC_XFER_FRAME_OVERRUN, 1230197ba5f4SPaul Zimmerman DWC2_HC_XFER_BABBLE_ERR, 1231197ba5f4SPaul Zimmerman DWC2_HC_XFER_DATA_TOGGLE_ERR, 1232197ba5f4SPaul Zimmerman DWC2_HC_XFER_AHB_ERR, 1233197ba5f4SPaul Zimmerman DWC2_HC_XFER_PERIODIC_INCOMPLETE, 1234197ba5f4SPaul Zimmerman DWC2_HC_XFER_URB_DEQUEUE, 1235197ba5f4SPaul Zimmerman }; 1236197ba5f4SPaul Zimmerman 12371e6b98ebSVardan Mikayelyan /* Core version information */ 12381e6b98ebSVardan Mikayelyan static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg) 12391e6b98ebSVardan Mikayelyan { 12401e6b98ebSVardan Mikayelyan return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000; 12411e6b98ebSVardan Mikayelyan } 12421e6b98ebSVardan Mikayelyan 12431e6b98ebSVardan Mikayelyan static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg) 12441e6b98ebSVardan Mikayelyan { 12451e6b98ebSVardan Mikayelyan return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000; 12461e6b98ebSVardan Mikayelyan } 12471e6b98ebSVardan Mikayelyan 12481e6b98ebSVardan Mikayelyan static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg) 12491e6b98ebSVardan Mikayelyan { 12501e6b98ebSVardan Mikayelyan return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000; 12511e6b98ebSVardan Mikayelyan } 12521e6b98ebSVardan Mikayelyan 1253197ba5f4SPaul Zimmerman /* 1254197ba5f4SPaul Zimmerman * The following functions support initialization of the core driver component 1255197ba5f4SPaul Zimmerman * and the DWC_otg controller 1256197ba5f4SPaul Zimmerman */ 12576e6360b6SJohn Stultz int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait); 125841ba9b9bSVardan Mikayelyan int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg); 125941ba9b9bSVardan Mikayelyan int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, bool restore); 1260624815ceSVardan Mikayelyan int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host); 1261624815ceSVardan Mikayelyan int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup, 1262624815ceSVardan Mikayelyan int reset, int is_host); 1263197ba5f4SPaul Zimmerman 126413b1f8e2SVardan Mikayelyan void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host); 126509c96980SJohn Youn void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg); 126609c96980SJohn Youn 12679da51974SJohn Youn bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 1268197ba5f4SPaul Zimmerman 1269197ba5f4SPaul Zimmerman /* 1270197ba5f4SPaul Zimmerman * Common core Functions. 1271197ba5f4SPaul Zimmerman * The following functions support managing the DWC_otg controller in either 1272197ba5f4SPaul Zimmerman * device or host mode. 1273197ba5f4SPaul Zimmerman */ 12749da51974SJohn Youn void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 12759da51974SJohn Youn void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 12769da51974SJohn Youn void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 1277197ba5f4SPaul Zimmerman 12789da51974SJohn Youn void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 12799da51974SJohn Youn void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 1280197ba5f4SPaul Zimmerman 128194d2666cSVardan Mikayelyan void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup, 128294d2666cSVardan Mikayelyan int is_host); 1283c5c403dcSVardan Mikayelyan int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg); 1284c5c403dcSVardan Mikayelyan int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg); 128594d2666cSVardan Mikayelyan 128666e77a24SRazmik Karapetyan void dwc2_enable_acg(struct dwc2_hsotg *hsotg); 128766e77a24SRazmik Karapetyan 1288197ba5f4SPaul Zimmerman /* This function should be called on every hardware interrupt. */ 12899da51974SJohn Youn irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 1290197ba5f4SPaul Zimmerman 1291323230efSJohn Youn /* The device ID match table */ 1292323230efSJohn Youn extern const struct of_device_id dwc2_of_match_table[]; 1293323230efSJohn Youn 12949da51974SJohn Youn int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg); 12959da51974SJohn Youn int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg); 1296ecb176c6SMian Yousaf Kaukab 129779d6b8c5SSevak Arakelyan /* Common polling functions */ 129879d6b8c5SSevak Arakelyan int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit, 129979d6b8c5SSevak Arakelyan u32 timeout); 130079d6b8c5SSevak Arakelyan int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit, 130179d6b8c5SSevak Arakelyan u32 timeout); 1302334bbd4eSJohn Youn /* Parameters */ 1303c1d286cfSJohn Youn int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); 1304334bbd4eSJohn Youn int dwc2_init_params(struct dwc2_hsotg *hsotg); 1305334bbd4eSJohn Youn 1306197ba5f4SPaul Zimmerman /* 13076bea9620SJohn Youn * The following functions check the controller's OTG operation mode 13086bea9620SJohn Youn * capability (GHWCFG2.OTG_MODE). 13096bea9620SJohn Youn * 13106bea9620SJohn Youn * These functions can be used before the internal hsotg->hw_params 13116bea9620SJohn Youn * are read in and cached so they always read directly from the 13126bea9620SJohn Youn * GHWCFG2 register. 13136bea9620SJohn Youn */ 13149da51974SJohn Youn unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg); 13156bea9620SJohn Youn bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg); 13166bea9620SJohn Youn bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg); 13176bea9620SJohn Youn bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg); 13186bea9620SJohn Youn 13196bea9620SJohn Youn /* 13201696d5abSJohn Youn * Returns the mode of operation, host or device 13211696d5abSJohn Youn */ 13221696d5abSJohn Youn static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) 13231696d5abSJohn Youn { 1324f25c42b8SGevorg Sahakyan return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) != 0; 13251696d5abSJohn Youn } 13269da51974SJohn Youn 13271696d5abSJohn Youn static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) 13281696d5abSJohn Youn { 1329f25c42b8SGevorg Sahakyan return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) == 0; 13301696d5abSJohn Youn } 13311696d5abSJohn Youn 13321696d5abSJohn Youn /* 1333197ba5f4SPaul Zimmerman * Dump core registers and SPRAM 1334197ba5f4SPaul Zimmerman */ 13359da51974SJohn Youn void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 13369da51974SJohn Youn void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 13379da51974SJohn Youn void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 1338197ba5f4SPaul Zimmerman 1339117777b2SDinh Nguyen /* Gadget defines */ 1340b98866c2SJohn Youn #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1341b98866c2SJohn Youn IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 13429da51974SJohn Youn int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg); 13439da51974SJohn Youn int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2); 13449da51974SJohn Youn int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2); 1345f3768997SVardan Mikayelyan int dwc2_gadget_init(struct dwc2_hsotg *hsotg); 13469da51974SJohn Youn void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1347643cc4deSGregory Herrero bool reset); 13489da51974SJohn Youn void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg); 13499da51974SJohn Youn void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2); 13509da51974SJohn Youn int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode); 1351f81f46e1SGregory Herrero #define dwc2_is_device_connected(hsotg) (hsotg->connected) 135258e52ff6SJohn Youn int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg); 13539a5d2816SVardan Mikayelyan int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup); 1354c5c403dcSVardan Mikayelyan int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg); 1355c5c403dcSVardan Mikayelyan int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, 1356c5c403dcSVardan Mikayelyan int rem_wakeup, int reset); 1357c138ecfaSSevak Arakelyan int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg); 1358c138ecfaSSevak Arakelyan int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg); 1359c138ecfaSSevak Arakelyan int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg); 136021b03405SSevak Arakelyan void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg); 1361117777b2SDinh Nguyen #else 13621f91b4ccSFelipe Balbi static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2) 1363117777b2SDinh Nguyen { return 0; } 13641f91b4ccSFelipe Balbi static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2) 1365117777b2SDinh Nguyen { return 0; } 13661f91b4ccSFelipe Balbi static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2) 1367117777b2SDinh Nguyen { return 0; } 1368f3768997SVardan Mikayelyan static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg) 1369117777b2SDinh Nguyen { return 0; } 13701f91b4ccSFelipe Balbi static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1371643cc4deSGregory Herrero bool reset) {} 13721f91b4ccSFelipe Balbi static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} 13731f91b4ccSFelipe Balbi static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} 13741f91b4ccSFelipe Balbi static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, 1375f91eea44SMian Yousaf Kaukab int testmode) 1376f91eea44SMian Yousaf Kaukab { return 0; } 1377f81f46e1SGregory Herrero #define dwc2_is_device_connected(hsotg) (0) 137858e52ff6SJohn Youn static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) 137958e52ff6SJohn Youn { return 0; } 13809a5d2816SVardan Mikayelyan static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, 13819a5d2816SVardan Mikayelyan int remote_wakeup) 138258e52ff6SJohn Youn { return 0; } 1383c5c403dcSVardan Mikayelyan static inline int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg) 1384c5c403dcSVardan Mikayelyan { return 0; } 1385c5c403dcSVardan Mikayelyan static inline int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, 1386c5c403dcSVardan Mikayelyan int rem_wakeup, int reset) 1387c5c403dcSVardan Mikayelyan { return 0; } 1388c138ecfaSSevak Arakelyan static inline int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg) 1389c138ecfaSSevak Arakelyan { return 0; } 1390c138ecfaSSevak Arakelyan static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) 1391c138ecfaSSevak Arakelyan { return 0; } 1392c138ecfaSSevak Arakelyan static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg) 1393c138ecfaSSevak Arakelyan { return 0; } 139421b03405SSevak Arakelyan static inline void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) {} 1395117777b2SDinh Nguyen #endif 1396117777b2SDinh Nguyen 1397117777b2SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 13989da51974SJohn Youn int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 13999da51974SJohn Youn int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us); 14009da51974SJohn Youn void dwc2_hcd_connect(struct dwc2_hsotg *hsotg); 14019da51974SJohn Youn void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force); 14029da51974SJohn Youn void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 140365c9c4c6SVardan Mikayelyan int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup); 140458e52ff6SJohn Youn int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg); 140558e52ff6SJohn Youn int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg); 1406c5c403dcSVardan Mikayelyan int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg); 1407c5c403dcSVardan Mikayelyan int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, 1408c5c403dcSVardan Mikayelyan int rem_wakeup, int reset); 1409117777b2SDinh Nguyen #else 1410117777b2SDinh Nguyen static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1411117777b2SDinh Nguyen { return 0; } 1412fae4e826SDouglas Anderson static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, 1413fae4e826SDouglas Anderson int us) 1414fae4e826SDouglas Anderson { return 0; } 14156a659531SDouglas Anderson static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {} 14166a659531SDouglas Anderson static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {} 1417117777b2SDinh Nguyen static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} 1418117777b2SDinh Nguyen static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} 141965c9c4c6SVardan Mikayelyan static inline int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) 142065c9c4c6SVardan Mikayelyan { return 0; } 14214fe160d5SHeiner Kallweit static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg) 1422117777b2SDinh Nguyen { return 0; } 142358e52ff6SJohn Youn static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 142458e52ff6SJohn Youn { return 0; } 142558e52ff6SJohn Youn static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 142658e52ff6SJohn Youn { return 0; } 1427c5c403dcSVardan Mikayelyan static inline int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg) 1428c5c403dcSVardan Mikayelyan { return 0; } 1429c5c403dcSVardan Mikayelyan static inline int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, 1430c5c403dcSVardan Mikayelyan int rem_wakeup, int reset) 1431c5c403dcSVardan Mikayelyan { return 0; } 143258e52ff6SJohn Youn 1433117777b2SDinh Nguyen #endif 1434117777b2SDinh Nguyen 1435197ba5f4SPaul Zimmerman #endif /* __DWC2_CORE_H__ */ 1436