1197ba5f4SPaul Zimmerman /* 2197ba5f4SPaul Zimmerman * core.h - DesignWare HS OTG Controller common declarations 3197ba5f4SPaul Zimmerman * 4197ba5f4SPaul Zimmerman * Copyright (C) 2004-2013 Synopsys, Inc. 5197ba5f4SPaul Zimmerman * 6197ba5f4SPaul Zimmerman * Redistribution and use in source and binary forms, with or without 7197ba5f4SPaul Zimmerman * modification, are permitted provided that the following conditions 8197ba5f4SPaul Zimmerman * are met: 9197ba5f4SPaul Zimmerman * 1. Redistributions of source code must retain the above copyright 10197ba5f4SPaul Zimmerman * notice, this list of conditions, and the following disclaimer, 11197ba5f4SPaul Zimmerman * without modification. 12197ba5f4SPaul Zimmerman * 2. Redistributions in binary form must reproduce the above copyright 13197ba5f4SPaul Zimmerman * notice, this list of conditions and the following disclaimer in the 14197ba5f4SPaul Zimmerman * documentation and/or other materials provided with the distribution. 15197ba5f4SPaul Zimmerman * 3. The names of the above-listed copyright holders may not be used 16197ba5f4SPaul Zimmerman * to endorse or promote products derived from this software without 17197ba5f4SPaul Zimmerman * specific prior written permission. 18197ba5f4SPaul Zimmerman * 19197ba5f4SPaul Zimmerman * ALTERNATIVELY, this software may be distributed under the terms of the 20197ba5f4SPaul Zimmerman * GNU General Public License ("GPL") as published by the Free Software 21197ba5f4SPaul Zimmerman * Foundation; either version 2 of the License, or (at your option) any 22197ba5f4SPaul Zimmerman * later version. 23197ba5f4SPaul Zimmerman * 24197ba5f4SPaul Zimmerman * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25197ba5f4SPaul Zimmerman * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26197ba5f4SPaul Zimmerman * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27197ba5f4SPaul Zimmerman * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28197ba5f4SPaul Zimmerman * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29197ba5f4SPaul Zimmerman * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30197ba5f4SPaul Zimmerman * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31197ba5f4SPaul Zimmerman * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32197ba5f4SPaul Zimmerman * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33197ba5f4SPaul Zimmerman * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34197ba5f4SPaul Zimmerman * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35197ba5f4SPaul Zimmerman */ 36197ba5f4SPaul Zimmerman 37197ba5f4SPaul Zimmerman #ifndef __DWC2_CORE_H__ 38197ba5f4SPaul Zimmerman #define __DWC2_CORE_H__ 39197ba5f4SPaul Zimmerman 40f7c0b143SDinh Nguyen #include <linux/phy/phy.h> 41f7c0b143SDinh Nguyen #include <linux/regulator/consumer.h> 42f7c0b143SDinh Nguyen #include <linux/usb/gadget.h> 43f7c0b143SDinh Nguyen #include <linux/usb/otg.h> 44197ba5f4SPaul Zimmerman #include <linux/usb/phy.h> 45197ba5f4SPaul Zimmerman #include "hw.h" 46197ba5f4SPaul Zimmerman 47197ba5f4SPaul Zimmerman #ifdef DWC2_LOG_WRITES 48197ba5f4SPaul Zimmerman static inline void do_write(u32 value, void *addr) 49197ba5f4SPaul Zimmerman { 50197ba5f4SPaul Zimmerman writel(value, addr); 51197ba5f4SPaul Zimmerman pr_info("INFO:: wrote %08x to %p\n", value, addr); 52197ba5f4SPaul Zimmerman } 53197ba5f4SPaul Zimmerman 54197ba5f4SPaul Zimmerman #undef writel 55197ba5f4SPaul Zimmerman #define writel(v, a) do_write(v, a) 56197ba5f4SPaul Zimmerman #endif 57197ba5f4SPaul Zimmerman 58197ba5f4SPaul Zimmerman /* Maximum number of Endpoints/HostChannels */ 59197ba5f4SPaul Zimmerman #define MAX_EPS_CHANNELS 16 60197ba5f4SPaul Zimmerman 61f7c0b143SDinh Nguyen /* s3c-hsotg declarations */ 62f7c0b143SDinh Nguyen static const char * const s3c_hsotg_supply_names[] = { 63f7c0b143SDinh Nguyen "vusb_d", /* digital USB supply, 1.2V */ 64f7c0b143SDinh Nguyen "vusb_a", /* analog USB supply, 1.1V */ 65f7c0b143SDinh Nguyen }; 66f7c0b143SDinh Nguyen 67f7c0b143SDinh Nguyen /* 68f7c0b143SDinh Nguyen * EP0_MPS_LIMIT 69f7c0b143SDinh Nguyen * 70f7c0b143SDinh Nguyen * Unfortunately there seems to be a limit of the amount of data that can 71f7c0b143SDinh Nguyen * be transferred by IN transactions on EP0. This is either 127 bytes or 3 72f7c0b143SDinh Nguyen * packets (which practically means 1 packet and 63 bytes of data) when the 73f7c0b143SDinh Nguyen * MPS is set to 64. 74f7c0b143SDinh Nguyen * 75f7c0b143SDinh Nguyen * This means if we are wanting to move >127 bytes of data, we need to 76f7c0b143SDinh Nguyen * split the transactions up, but just doing one packet at a time does 77f7c0b143SDinh Nguyen * not work (this may be an implicit DATA0 PID on first packet of the 78f7c0b143SDinh Nguyen * transaction) and doing 2 packets is outside the controller's limits. 79f7c0b143SDinh Nguyen * 80f7c0b143SDinh Nguyen * If we try to lower the MPS size for EP0, then no transfers work properly 81f7c0b143SDinh Nguyen * for EP0, and the system will fail basic enumeration. As no cause for this 82f7c0b143SDinh Nguyen * has currently been found, we cannot support any large IN transfers for 83f7c0b143SDinh Nguyen * EP0. 84f7c0b143SDinh Nguyen */ 85f7c0b143SDinh Nguyen #define EP0_MPS_LIMIT 64 86f7c0b143SDinh Nguyen 87941fcce4SDinh Nguyen struct dwc2_hsotg; 88f7c0b143SDinh Nguyen struct s3c_hsotg_req; 89f7c0b143SDinh Nguyen 90f7c0b143SDinh Nguyen /** 91f7c0b143SDinh Nguyen * struct s3c_hsotg_ep - driver endpoint definition. 92f7c0b143SDinh Nguyen * @ep: The gadget layer representation of the endpoint. 93f7c0b143SDinh Nguyen * @name: The driver generated name for the endpoint. 94f7c0b143SDinh Nguyen * @queue: Queue of requests for this endpoint. 95f7c0b143SDinh Nguyen * @parent: Reference back to the parent device structure. 96f7c0b143SDinh Nguyen * @req: The current request that the endpoint is processing. This is 97f7c0b143SDinh Nguyen * used to indicate an request has been loaded onto the endpoint 98f7c0b143SDinh Nguyen * and has yet to be completed (maybe due to data move, or simply 99f7c0b143SDinh Nguyen * awaiting an ack from the core all the data has been completed). 100f7c0b143SDinh Nguyen * @debugfs: File entry for debugfs file for this endpoint. 101f7c0b143SDinh Nguyen * @lock: State lock to protect contents of endpoint. 102f7c0b143SDinh Nguyen * @dir_in: Set to true if this endpoint is of the IN direction, which 103f7c0b143SDinh Nguyen * means that it is sending data to the Host. 104f7c0b143SDinh Nguyen * @index: The index for the endpoint registers. 105f7c0b143SDinh Nguyen * @mc: Multi Count - number of transactions per microframe 106f7c0b143SDinh Nguyen * @interval - Interval for periodic endpoints 107f7c0b143SDinh Nguyen * @name: The name array passed to the USB core. 108f7c0b143SDinh Nguyen * @halted: Set if the endpoint has been halted. 109f7c0b143SDinh Nguyen * @periodic: Set if this is a periodic ep, such as Interrupt 110f7c0b143SDinh Nguyen * @isochronous: Set if this is a isochronous ep 1118a20fa45SMian Yousaf Kaukab * @send_zlp: Set if we need to send a zero-length packet. 112f7c0b143SDinh Nguyen * @total_data: The total number of data bytes done. 113f7c0b143SDinh Nguyen * @fifo_size: The size of the FIFO (for periodic IN endpoints) 114f7c0b143SDinh Nguyen * @fifo_load: The amount of data loaded into the FIFO (periodic IN) 115f7c0b143SDinh Nguyen * @last_load: The offset of data for the last start of request. 116f7c0b143SDinh Nguyen * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN 117f7c0b143SDinh Nguyen * 118f7c0b143SDinh Nguyen * This is the driver's state for each registered enpoint, allowing it 119f7c0b143SDinh Nguyen * to keep track of transactions that need doing. Each endpoint has a 120f7c0b143SDinh Nguyen * lock to protect the state, to try and avoid using an overall lock 121f7c0b143SDinh Nguyen * for the host controller as much as possible. 122f7c0b143SDinh Nguyen * 123f7c0b143SDinh Nguyen * For periodic IN endpoints, we have fifo_size and fifo_load to try 124f7c0b143SDinh Nguyen * and keep track of the amount of data in the periodic FIFO for each 125f7c0b143SDinh Nguyen * of these as we don't have a status register that tells us how much 126f7c0b143SDinh Nguyen * is in each of them. (note, this may actually be useless information 127f7c0b143SDinh Nguyen * as in shared-fifo mode periodic in acts like a single-frame packet 128f7c0b143SDinh Nguyen * buffer than a fifo) 129f7c0b143SDinh Nguyen */ 130f7c0b143SDinh Nguyen struct s3c_hsotg_ep { 131f7c0b143SDinh Nguyen struct usb_ep ep; 132f7c0b143SDinh Nguyen struct list_head queue; 133941fcce4SDinh Nguyen struct dwc2_hsotg *parent; 134f7c0b143SDinh Nguyen struct s3c_hsotg_req *req; 135f7c0b143SDinh Nguyen struct dentry *debugfs; 136f7c0b143SDinh Nguyen 137f7c0b143SDinh Nguyen unsigned long total_data; 138f7c0b143SDinh Nguyen unsigned int size_loaded; 139f7c0b143SDinh Nguyen unsigned int last_load; 140f7c0b143SDinh Nguyen unsigned int fifo_load; 141f7c0b143SDinh Nguyen unsigned short fifo_size; 142b203d0a2SRobert Baldyga unsigned short fifo_index; 143f7c0b143SDinh Nguyen 144f7c0b143SDinh Nguyen unsigned char dir_in; 145f7c0b143SDinh Nguyen unsigned char index; 146f7c0b143SDinh Nguyen unsigned char mc; 147f7c0b143SDinh Nguyen unsigned char interval; 148f7c0b143SDinh Nguyen 149f7c0b143SDinh Nguyen unsigned int halted:1; 150f7c0b143SDinh Nguyen unsigned int periodic:1; 151f7c0b143SDinh Nguyen unsigned int isochronous:1; 1528a20fa45SMian Yousaf Kaukab unsigned int send_zlp:1; 153f7c0b143SDinh Nguyen 154f7c0b143SDinh Nguyen char name[10]; 155f7c0b143SDinh Nguyen }; 156f7c0b143SDinh Nguyen 157f7c0b143SDinh Nguyen /** 158f7c0b143SDinh Nguyen * struct s3c_hsotg_req - data transfer request 159f7c0b143SDinh Nguyen * @req: The USB gadget request 160f7c0b143SDinh Nguyen * @queue: The list of requests for the endpoint this is queued for. 1617d24c1b5SMian Yousaf Kaukab * @saved_req_buf: variable to save req.buf when bounce buffers are used. 162f7c0b143SDinh Nguyen */ 163f7c0b143SDinh Nguyen struct s3c_hsotg_req { 164f7c0b143SDinh Nguyen struct usb_request req; 165f7c0b143SDinh Nguyen struct list_head queue; 1667d24c1b5SMian Yousaf Kaukab void *saved_req_buf; 167f7c0b143SDinh Nguyen }; 168f7c0b143SDinh Nguyen 169941fcce4SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 170f7c0b143SDinh Nguyen #define call_gadget(_hs, _entry) \ 171f7c0b143SDinh Nguyen do { \ 172f7c0b143SDinh Nguyen if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ 173f7c0b143SDinh Nguyen (_hs)->driver && (_hs)->driver->_entry) { \ 174f7c0b143SDinh Nguyen spin_unlock(&_hs->lock); \ 175f7c0b143SDinh Nguyen (_hs)->driver->_entry(&(_hs)->gadget); \ 176f7c0b143SDinh Nguyen spin_lock(&_hs->lock); \ 177f7c0b143SDinh Nguyen } \ 178f7c0b143SDinh Nguyen } while (0) 179941fcce4SDinh Nguyen #else 180941fcce4SDinh Nguyen #define call_gadget(_hs, _entry) do {} while (0) 181941fcce4SDinh Nguyen #endif 182f7c0b143SDinh Nguyen 183197ba5f4SPaul Zimmerman struct dwc2_hsotg; 184197ba5f4SPaul Zimmerman struct dwc2_host_chan; 185197ba5f4SPaul Zimmerman 186197ba5f4SPaul Zimmerman /* Device States */ 187197ba5f4SPaul Zimmerman enum dwc2_lx_state { 188197ba5f4SPaul Zimmerman DWC2_L0, /* On state */ 189197ba5f4SPaul Zimmerman DWC2_L1, /* LPM sleep state */ 190197ba5f4SPaul Zimmerman DWC2_L2, /* USB suspend state */ 191197ba5f4SPaul Zimmerman DWC2_L3, /* Off state */ 192197ba5f4SPaul Zimmerman }; 193197ba5f4SPaul Zimmerman 1940a176279SGregory Herrero /* 1950a176279SGregory Herrero * Gadget periodic tx fifo sizes as used by legacy driver 1960a176279SGregory Herrero * EP0 is not included 1970a176279SGregory Herrero */ 1980a176279SGregory Herrero #define DWC2_G_P_LEGACY_TX_FIFO_SIZE {256, 256, 256, 256, 768, 768, 768, \ 1990a176279SGregory Herrero 768, 0, 0, 0, 0, 0, 0, 0} 2000a176279SGregory Herrero 201fe0b94abSMian Yousaf Kaukab /* Gadget ep0 states */ 202fe0b94abSMian Yousaf Kaukab enum dwc2_ep0_state { 203fe0b94abSMian Yousaf Kaukab DWC2_EP0_SETUP, 204fe0b94abSMian Yousaf Kaukab DWC2_EP0_DATA_IN, 205fe0b94abSMian Yousaf Kaukab DWC2_EP0_DATA_OUT, 206fe0b94abSMian Yousaf Kaukab DWC2_EP0_STATUS_IN, 207fe0b94abSMian Yousaf Kaukab DWC2_EP0_STATUS_OUT, 208fe0b94abSMian Yousaf Kaukab }; 209fe0b94abSMian Yousaf Kaukab 210197ba5f4SPaul Zimmerman /** 211197ba5f4SPaul Zimmerman * struct dwc2_core_params - Parameters for configuring the core 212197ba5f4SPaul Zimmerman * 213197ba5f4SPaul Zimmerman * @otg_cap: Specifies the OTG capabilities. 214197ba5f4SPaul Zimmerman * 0 - HNP and SRP capable 215197ba5f4SPaul Zimmerman * 1 - SRP Only capable 216197ba5f4SPaul Zimmerman * 2 - No HNP/SRP capable (always available) 217197ba5f4SPaul Zimmerman * Defaults to best available option (0, 1, then 2) 218197ba5f4SPaul Zimmerman * @otg_ver: OTG version supported 219197ba5f4SPaul Zimmerman * 0 - 1.3 (default) 220197ba5f4SPaul Zimmerman * 1 - 2.0 221197ba5f4SPaul Zimmerman * @dma_enable: Specifies whether to use slave or DMA mode for accessing 222197ba5f4SPaul Zimmerman * the data FIFOs. The driver will automatically detect the 223197ba5f4SPaul Zimmerman * value for this parameter if none is specified. 224197ba5f4SPaul Zimmerman * 0 - Slave (always available) 225197ba5f4SPaul Zimmerman * 1 - DMA (default, if available) 226197ba5f4SPaul Zimmerman * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 227197ba5f4SPaul Zimmerman * address DMA mode or descriptor DMA mode for accessing 228197ba5f4SPaul Zimmerman * the data FIFOs. The driver will automatically detect the 229197ba5f4SPaul Zimmerman * value for this if none is specified. 230197ba5f4SPaul Zimmerman * 0 - Address DMA 231197ba5f4SPaul Zimmerman * 1 - Descriptor DMA (default, if available) 232197ba5f4SPaul Zimmerman * @speed: Specifies the maximum speed of operation in host and 233197ba5f4SPaul Zimmerman * device mode. The actual speed depends on the speed of 234197ba5f4SPaul Zimmerman * the attached device and the value of phy_type. 235197ba5f4SPaul Zimmerman * 0 - High Speed 236197ba5f4SPaul Zimmerman * (default when phy_type is UTMI+ or ULPI) 237197ba5f4SPaul Zimmerman * 1 - Full Speed 238197ba5f4SPaul Zimmerman * (default when phy_type is Full Speed) 239197ba5f4SPaul Zimmerman * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 240197ba5f4SPaul Zimmerman * 1 - Allow dynamic FIFO sizing (default, if available) 241197ba5f4SPaul Zimmerman * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 242197ba5f4SPaul Zimmerman * are enabled 243197ba5f4SPaul Zimmerman * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 244197ba5f4SPaul Zimmerman * dynamic FIFO sizing is enabled 245197ba5f4SPaul Zimmerman * 16 to 32768 246197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 247197ba5f4SPaul Zimmerman * the default. 248197ba5f4SPaul Zimmerman * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 249197ba5f4SPaul Zimmerman * in host mode when dynamic FIFO sizing is enabled 250197ba5f4SPaul Zimmerman * 16 to 32768 251197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 252197ba5f4SPaul Zimmerman * the default. 253197ba5f4SPaul Zimmerman * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 254197ba5f4SPaul Zimmerman * host mode when dynamic FIFO sizing is enabled 255197ba5f4SPaul Zimmerman * 16 to 32768 256197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 257197ba5f4SPaul Zimmerman * the default. 258197ba5f4SPaul Zimmerman * @max_transfer_size: The maximum transfer size supported, in bytes 259197ba5f4SPaul Zimmerman * 2047 to 65,535 260197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 261197ba5f4SPaul Zimmerman * the default. 262197ba5f4SPaul Zimmerman * @max_packet_count: The maximum number of packets in a transfer 263197ba5f4SPaul Zimmerman * 15 to 511 264197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 265197ba5f4SPaul Zimmerman * the default. 266197ba5f4SPaul Zimmerman * @host_channels: The number of host channel registers to use 267197ba5f4SPaul Zimmerman * 1 to 16 268197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 269197ba5f4SPaul Zimmerman * the default. 270197ba5f4SPaul Zimmerman * @phy_type: Specifies the type of PHY interface to use. By default, 271197ba5f4SPaul Zimmerman * the driver will automatically detect the phy_type. 272197ba5f4SPaul Zimmerman * 0 - Full Speed Phy 273197ba5f4SPaul Zimmerman * 1 - UTMI+ Phy 274197ba5f4SPaul Zimmerman * 2 - ULPI Phy 275197ba5f4SPaul Zimmerman * Defaults to best available option (2, 1, then 0) 276197ba5f4SPaul Zimmerman * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 277197ba5f4SPaul Zimmerman * is applicable for a phy_type of UTMI+ or ULPI. (For a 278197ba5f4SPaul Zimmerman * ULPI phy_type, this parameter indicates the data width 279197ba5f4SPaul Zimmerman * between the MAC and the ULPI Wrapper.) Also, this 280197ba5f4SPaul Zimmerman * parameter is applicable only if the OTG_HSPHY_WIDTH cC 281197ba5f4SPaul Zimmerman * parameter was set to "8 and 16 bits", meaning that the 282197ba5f4SPaul Zimmerman * core has been configured to work at either data path 283197ba5f4SPaul Zimmerman * width. 284197ba5f4SPaul Zimmerman * 8 or 16 (default 16 if available) 285197ba5f4SPaul Zimmerman * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 286197ba5f4SPaul Zimmerman * data rate. This parameter is only applicable if phy_type 287197ba5f4SPaul Zimmerman * is ULPI. 288197ba5f4SPaul Zimmerman * 0 - single data rate ULPI interface with 8 bit wide 289197ba5f4SPaul Zimmerman * data bus (default) 290197ba5f4SPaul Zimmerman * 1 - double data rate ULPI interface with 4 bit wide 291197ba5f4SPaul Zimmerman * data bus 292197ba5f4SPaul Zimmerman * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 293197ba5f4SPaul Zimmerman * external supply to drive the VBus 294197ba5f4SPaul Zimmerman * 0 - Internal supply (default) 295197ba5f4SPaul Zimmerman * 1 - External supply 296197ba5f4SPaul Zimmerman * @i2c_enable: Specifies whether to use the I2Cinterface for a full 297197ba5f4SPaul Zimmerman * speed PHY. This parameter is only applicable if phy_type 298197ba5f4SPaul Zimmerman * is FS. 299197ba5f4SPaul Zimmerman * 0 - No (default) 300197ba5f4SPaul Zimmerman * 1 - Yes 301197ba5f4SPaul Zimmerman * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 302197ba5f4SPaul Zimmerman * 0 - No (default) 303197ba5f4SPaul Zimmerman * 1 - Yes 304197ba5f4SPaul Zimmerman * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 305197ba5f4SPaul Zimmerman * when attached to a Full Speed or Low Speed device in 306197ba5f4SPaul Zimmerman * host mode. 307197ba5f4SPaul Zimmerman * 0 - Don't support low power mode (default) 308197ba5f4SPaul Zimmerman * 1 - Support low power mode 309197ba5f4SPaul Zimmerman * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 310197ba5f4SPaul Zimmerman * when connected to a Low Speed device in host 311197ba5f4SPaul Zimmerman * mode. This parameter is applicable only if 312197ba5f4SPaul Zimmerman * host_support_fs_ls_low_power is enabled. 313197ba5f4SPaul Zimmerman * 0 - 48 MHz 314197ba5f4SPaul Zimmerman * (default when phy_type is UTMI+ or ULPI) 315197ba5f4SPaul Zimmerman * 1 - 6 MHz 316197ba5f4SPaul Zimmerman * (default when phy_type is Full Speed) 317197ba5f4SPaul Zimmerman * @ts_dline: Enable Term Select Dline pulsing 318197ba5f4SPaul Zimmerman * 0 - No (default) 319197ba5f4SPaul Zimmerman * 1 - Yes 320197ba5f4SPaul Zimmerman * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 321197ba5f4SPaul Zimmerman * 0 - No (default for core < 2.92a) 322197ba5f4SPaul Zimmerman * 1 - Yes (default for core >= 2.92a) 323197ba5f4SPaul Zimmerman * @ahbcfg: This field allows the default value of the GAHBCFG 324197ba5f4SPaul Zimmerman * register to be overridden 325197ba5f4SPaul Zimmerman * -1 - GAHBCFG value will be set to 0x06 326197ba5f4SPaul Zimmerman * (INCR4, default) 327197ba5f4SPaul Zimmerman * all others - GAHBCFG value will be overridden with 328197ba5f4SPaul Zimmerman * this value 329197ba5f4SPaul Zimmerman * Not all bits can be controlled like this, the 330197ba5f4SPaul Zimmerman * bits defined by GAHBCFG_CTRL_MASK are controlled 331197ba5f4SPaul Zimmerman * by the driver and are ignored in this 332197ba5f4SPaul Zimmerman * configuration value. 333197ba5f4SPaul Zimmerman * @uframe_sched: True to enable the microframe scheduler 334a6d249d8SGregory Herrero * @external_id_pin_ctl: Specifies whether ID pin is handled externally. 335a6d249d8SGregory Herrero * Disable CONIDSTSCHNG controller interrupt in such 336a6d249d8SGregory Herrero * case. 337a6d249d8SGregory Herrero * 0 - No (default) 338a6d249d8SGregory Herrero * 1 - Yes 339197ba5f4SPaul Zimmerman * 340197ba5f4SPaul Zimmerman * The following parameters may be specified when starting the module. These 341197ba5f4SPaul Zimmerman * parameters define how the DWC_otg controller should be configured. A 342197ba5f4SPaul Zimmerman * value of -1 (or any other out of range value) for any parameter means 343197ba5f4SPaul Zimmerman * to read the value from hardware (if possible) or use the builtin 344197ba5f4SPaul Zimmerman * default described above. 345197ba5f4SPaul Zimmerman */ 346197ba5f4SPaul Zimmerman struct dwc2_core_params { 347197ba5f4SPaul Zimmerman /* 348197ba5f4SPaul Zimmerman * Don't add any non-int members here, this will break 349197ba5f4SPaul Zimmerman * dwc2_set_all_params! 350197ba5f4SPaul Zimmerman */ 351197ba5f4SPaul Zimmerman int otg_cap; 352197ba5f4SPaul Zimmerman int otg_ver; 353197ba5f4SPaul Zimmerman int dma_enable; 354197ba5f4SPaul Zimmerman int dma_desc_enable; 355197ba5f4SPaul Zimmerman int speed; 356197ba5f4SPaul Zimmerman int enable_dynamic_fifo; 357197ba5f4SPaul Zimmerman int en_multiple_tx_fifo; 358197ba5f4SPaul Zimmerman int host_rx_fifo_size; 359197ba5f4SPaul Zimmerman int host_nperio_tx_fifo_size; 360197ba5f4SPaul Zimmerman int host_perio_tx_fifo_size; 361197ba5f4SPaul Zimmerman int max_transfer_size; 362197ba5f4SPaul Zimmerman int max_packet_count; 363197ba5f4SPaul Zimmerman int host_channels; 364197ba5f4SPaul Zimmerman int phy_type; 365197ba5f4SPaul Zimmerman int phy_utmi_width; 366197ba5f4SPaul Zimmerman int phy_ulpi_ddr; 367197ba5f4SPaul Zimmerman int phy_ulpi_ext_vbus; 368197ba5f4SPaul Zimmerman int i2c_enable; 369197ba5f4SPaul Zimmerman int ulpi_fs_ls; 370197ba5f4SPaul Zimmerman int host_support_fs_ls_low_power; 371197ba5f4SPaul Zimmerman int host_ls_low_power_phy_clk; 372197ba5f4SPaul Zimmerman int ts_dline; 373197ba5f4SPaul Zimmerman int reload_ctl; 374197ba5f4SPaul Zimmerman int ahbcfg; 375197ba5f4SPaul Zimmerman int uframe_sched; 376a6d249d8SGregory Herrero int external_id_pin_ctl; 377197ba5f4SPaul Zimmerman }; 378197ba5f4SPaul Zimmerman 379197ba5f4SPaul Zimmerman /** 380197ba5f4SPaul Zimmerman * struct dwc2_hw_params - Autodetected parameters. 381197ba5f4SPaul Zimmerman * 382197ba5f4SPaul Zimmerman * These parameters are the various parameters read from hardware 383197ba5f4SPaul Zimmerman * registers during initialization. They typically contain the best 384197ba5f4SPaul Zimmerman * supported or maximum value that can be configured in the 385197ba5f4SPaul Zimmerman * corresponding dwc2_core_params value. 386197ba5f4SPaul Zimmerman * 387197ba5f4SPaul Zimmerman * The values that are not in dwc2_core_params are documented below. 388197ba5f4SPaul Zimmerman * 389197ba5f4SPaul Zimmerman * @op_mode Mode of Operation 390197ba5f4SPaul Zimmerman * 0 - HNP- and SRP-Capable OTG (Host & Device) 391197ba5f4SPaul Zimmerman * 1 - SRP-Capable OTG (Host & Device) 392197ba5f4SPaul Zimmerman * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 393197ba5f4SPaul Zimmerman * 3 - SRP-Capable Device 394197ba5f4SPaul Zimmerman * 4 - Non-OTG Device 395197ba5f4SPaul Zimmerman * 5 - SRP-Capable Host 396197ba5f4SPaul Zimmerman * 6 - Non-OTG Host 397197ba5f4SPaul Zimmerman * @arch Architecture 398197ba5f4SPaul Zimmerman * 0 - Slave only 399197ba5f4SPaul Zimmerman * 1 - External DMA 400197ba5f4SPaul Zimmerman * 2 - Internal DMA 401197ba5f4SPaul Zimmerman * @power_optimized Are power optimizations enabled? 402197ba5f4SPaul Zimmerman * @num_dev_ep Number of device endpoints available 403197ba5f4SPaul Zimmerman * @num_dev_perio_in_ep Number of device periodic IN endpoints 404997f4f81SMickael Maison * available 405197ba5f4SPaul Zimmerman * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue 406197ba5f4SPaul Zimmerman * Depth 407197ba5f4SPaul Zimmerman * 0 to 30 408197ba5f4SPaul Zimmerman * @host_perio_tx_q_depth 409197ba5f4SPaul Zimmerman * Host Mode Periodic Request Queue Depth 410197ba5f4SPaul Zimmerman * 2, 4 or 8 411197ba5f4SPaul Zimmerman * @nperio_tx_q_depth 412197ba5f4SPaul Zimmerman * Non-Periodic Request Queue Depth 413197ba5f4SPaul Zimmerman * 2, 4 or 8 414197ba5f4SPaul Zimmerman * @hs_phy_type High-speed PHY interface type 415197ba5f4SPaul Zimmerman * 0 - High-speed interface not supported 416197ba5f4SPaul Zimmerman * 1 - UTMI+ 417197ba5f4SPaul Zimmerman * 2 - ULPI 418197ba5f4SPaul Zimmerman * 3 - UTMI+ and ULPI 419197ba5f4SPaul Zimmerman * @fs_phy_type Full-speed PHY interface type 420197ba5f4SPaul Zimmerman * 0 - Full speed interface not supported 421197ba5f4SPaul Zimmerman * 1 - Dedicated full speed interface 422197ba5f4SPaul Zimmerman * 2 - FS pins shared with UTMI+ pins 423197ba5f4SPaul Zimmerman * 3 - FS pins shared with ULPI pins 424197ba5f4SPaul Zimmerman * @total_fifo_size: Total internal RAM for FIFOs (bytes) 425197ba5f4SPaul Zimmerman * @utmi_phy_data_width UTMI+ PHY data width 426197ba5f4SPaul Zimmerman * 0 - 8 bits 427197ba5f4SPaul Zimmerman * 1 - 16 bits 428197ba5f4SPaul Zimmerman * 2 - 8 or 16 bits 429197ba5f4SPaul Zimmerman * @snpsid: Value from SNPSID register 430197ba5f4SPaul Zimmerman */ 431197ba5f4SPaul Zimmerman struct dwc2_hw_params { 432197ba5f4SPaul Zimmerman unsigned op_mode:3; 433197ba5f4SPaul Zimmerman unsigned arch:2; 434197ba5f4SPaul Zimmerman unsigned dma_desc_enable:1; 435197ba5f4SPaul Zimmerman unsigned enable_dynamic_fifo:1; 436197ba5f4SPaul Zimmerman unsigned en_multiple_tx_fifo:1; 437197ba5f4SPaul Zimmerman unsigned host_rx_fifo_size:16; 438197ba5f4SPaul Zimmerman unsigned host_nperio_tx_fifo_size:16; 439197ba5f4SPaul Zimmerman unsigned host_perio_tx_fifo_size:16; 440197ba5f4SPaul Zimmerman unsigned nperio_tx_q_depth:3; 441197ba5f4SPaul Zimmerman unsigned host_perio_tx_q_depth:3; 442197ba5f4SPaul Zimmerman unsigned dev_token_q_depth:5; 443197ba5f4SPaul Zimmerman unsigned max_transfer_size:26; 444197ba5f4SPaul Zimmerman unsigned max_packet_count:11; 445197ba5f4SPaul Zimmerman unsigned host_channels:5; 446197ba5f4SPaul Zimmerman unsigned hs_phy_type:2; 447197ba5f4SPaul Zimmerman unsigned fs_phy_type:2; 448197ba5f4SPaul Zimmerman unsigned i2c_enable:1; 449197ba5f4SPaul Zimmerman unsigned num_dev_ep:4; 450197ba5f4SPaul Zimmerman unsigned num_dev_perio_in_ep:4; 451197ba5f4SPaul Zimmerman unsigned total_fifo_size:16; 452197ba5f4SPaul Zimmerman unsigned power_optimized:1; 453197ba5f4SPaul Zimmerman unsigned utmi_phy_data_width:2; 454197ba5f4SPaul Zimmerman u32 snpsid; 455197ba5f4SPaul Zimmerman }; 456197ba5f4SPaul Zimmerman 4573f95001dSMian Yousaf Kaukab /* Size of control and EP0 buffers */ 4583f95001dSMian Yousaf Kaukab #define DWC2_CTRL_BUFF_SIZE 8 4593f95001dSMian Yousaf Kaukab 460197ba5f4SPaul Zimmerman /** 461d17ee77bSGregory Herrero * struct dwc2_gregs_backup - Holds global registers state before entering partial 462d17ee77bSGregory Herrero * power down 463d17ee77bSGregory Herrero * @gotgctl: Backup of GOTGCTL register 464d17ee77bSGregory Herrero * @gintmsk: Backup of GINTMSK register 465d17ee77bSGregory Herrero * @gahbcfg: Backup of GAHBCFG register 466d17ee77bSGregory Herrero * @gusbcfg: Backup of GUSBCFG register 467d17ee77bSGregory Herrero * @grxfsiz: Backup of GRXFSIZ register 468d17ee77bSGregory Herrero * @gnptxfsiz: Backup of GNPTXFSIZ register 469d17ee77bSGregory Herrero * @gi2cctl: Backup of GI2CCTL register 470d17ee77bSGregory Herrero * @hptxfsiz: Backup of HPTXFSIZ register 471d17ee77bSGregory Herrero * @gdfifocfg: Backup of GDFIFOCFG register 472d17ee77bSGregory Herrero * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 473d17ee77bSGregory Herrero * @gpwrdn: Backup of GPWRDN register 474d17ee77bSGregory Herrero */ 475d17ee77bSGregory Herrero struct dwc2_gregs_backup { 476d17ee77bSGregory Herrero u32 gotgctl; 477d17ee77bSGregory Herrero u32 gintmsk; 478d17ee77bSGregory Herrero u32 gahbcfg; 479d17ee77bSGregory Herrero u32 gusbcfg; 480d17ee77bSGregory Herrero u32 grxfsiz; 481d17ee77bSGregory Herrero u32 gnptxfsiz; 482d17ee77bSGregory Herrero u32 gi2cctl; 483d17ee77bSGregory Herrero u32 hptxfsiz; 484d17ee77bSGregory Herrero u32 pcgcctl; 485d17ee77bSGregory Herrero u32 gdfifocfg; 486d17ee77bSGregory Herrero u32 dtxfsiz[MAX_EPS_CHANNELS]; 487d17ee77bSGregory Herrero u32 gpwrdn; 488d17ee77bSGregory Herrero }; 489d17ee77bSGregory Herrero 490d17ee77bSGregory Herrero /** 491d17ee77bSGregory Herrero * struct dwc2_dregs_backup - Holds device registers state before entering partial 492d17ee77bSGregory Herrero * power down 493d17ee77bSGregory Herrero * @dcfg: Backup of DCFG register 494d17ee77bSGregory Herrero * @dctl: Backup of DCTL register 495d17ee77bSGregory Herrero * @daintmsk: Backup of DAINTMSK register 496d17ee77bSGregory Herrero * @diepmsk: Backup of DIEPMSK register 497d17ee77bSGregory Herrero * @doepmsk: Backup of DOEPMSK register 498d17ee77bSGregory Herrero * @diepctl: Backup of DIEPCTL register 499d17ee77bSGregory Herrero * @dieptsiz: Backup of DIEPTSIZ register 500d17ee77bSGregory Herrero * @diepdma: Backup of DIEPDMA register 501d17ee77bSGregory Herrero * @doepctl: Backup of DOEPCTL register 502d17ee77bSGregory Herrero * @doeptsiz: Backup of DOEPTSIZ register 503d17ee77bSGregory Herrero * @doepdma: Backup of DOEPDMA register 504d17ee77bSGregory Herrero */ 505d17ee77bSGregory Herrero struct dwc2_dregs_backup { 506d17ee77bSGregory Herrero u32 dcfg; 507d17ee77bSGregory Herrero u32 dctl; 508d17ee77bSGregory Herrero u32 daintmsk; 509d17ee77bSGregory Herrero u32 diepmsk; 510d17ee77bSGregory Herrero u32 doepmsk; 511d17ee77bSGregory Herrero u32 diepctl[MAX_EPS_CHANNELS]; 512d17ee77bSGregory Herrero u32 dieptsiz[MAX_EPS_CHANNELS]; 513d17ee77bSGregory Herrero u32 diepdma[MAX_EPS_CHANNELS]; 514d17ee77bSGregory Herrero u32 doepctl[MAX_EPS_CHANNELS]; 515d17ee77bSGregory Herrero u32 doeptsiz[MAX_EPS_CHANNELS]; 516d17ee77bSGregory Herrero u32 doepdma[MAX_EPS_CHANNELS]; 517d17ee77bSGregory Herrero }; 518d17ee77bSGregory Herrero 519d17ee77bSGregory Herrero /** 520d17ee77bSGregory Herrero * struct dwc2_hregs_backup - Holds host registers state before entering partial 521d17ee77bSGregory Herrero * power down 522d17ee77bSGregory Herrero * @hcfg: Backup of HCFG register 523d17ee77bSGregory Herrero * @haintmsk: Backup of HAINTMSK register 524d17ee77bSGregory Herrero * @hcintmsk: Backup of HCINTMSK register 525d17ee77bSGregory Herrero * @hptr0: Backup of HPTR0 register 526d17ee77bSGregory Herrero * @hfir: Backup of HFIR register 527d17ee77bSGregory Herrero */ 528d17ee77bSGregory Herrero struct dwc2_hregs_backup { 529d17ee77bSGregory Herrero u32 hcfg; 530d17ee77bSGregory Herrero u32 haintmsk; 531d17ee77bSGregory Herrero u32 hcintmsk[MAX_EPS_CHANNELS]; 532d17ee77bSGregory Herrero u32 hprt0; 533d17ee77bSGregory Herrero u32 hfir; 534d17ee77bSGregory Herrero }; 535d17ee77bSGregory Herrero 536d17ee77bSGregory Herrero /** 537197ba5f4SPaul Zimmerman * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 538197ba5f4SPaul Zimmerman * and periodic schedules 539197ba5f4SPaul Zimmerman * 540941fcce4SDinh Nguyen * These are common for both host and peripheral modes: 541941fcce4SDinh Nguyen * 542197ba5f4SPaul Zimmerman * @dev: The struct device pointer 543197ba5f4SPaul Zimmerman * @regs: Pointer to controller regs 544197ba5f4SPaul Zimmerman * @hw_params: Parameters that were autodetected from the 545197ba5f4SPaul Zimmerman * hardware registers 546941fcce4SDinh Nguyen * @core_params: Parameters that define how the core should be configured 547197ba5f4SPaul Zimmerman * @op_state: The operational State, during transitions (a_host=> 548197ba5f4SPaul Zimmerman * a_peripheral and b_device=>b_host) this may not match 549197ba5f4SPaul Zimmerman * the core, but allows the software to determine 550197ba5f4SPaul Zimmerman * transitions 551c0155b9dSKever Yang * @dr_mode: Requested mode of operation, one of following: 552c0155b9dSKever Yang * - USB_DR_MODE_PERIPHERAL 553c0155b9dSKever Yang * - USB_DR_MODE_HOST 554c0155b9dSKever Yang * - USB_DR_MODE_OTG 555941fcce4SDinh Nguyen * @lock: Spinlock that protects all the driver data structures 556941fcce4SDinh Nguyen * @priv: Stores a pointer to the struct usb_hcd 557197ba5f4SPaul Zimmerman * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 558197ba5f4SPaul Zimmerman * transfer are in process of being queued 559197ba5f4SPaul Zimmerman * @srp_success: Stores status of SRP request in the case of a FS PHY 560197ba5f4SPaul Zimmerman * with an I2C interface 561197ba5f4SPaul Zimmerman * @wq_otg: Workqueue object used for handling of some interrupts 562197ba5f4SPaul Zimmerman * @wf_otg: Work object for handling Connector ID Status Change 563197ba5f4SPaul Zimmerman * interrupt 564197ba5f4SPaul Zimmerman * @wkp_timer: Timer object for handling Wakeup Detected interrupt 565197ba5f4SPaul Zimmerman * @lx_state: Lx state of connected device 566d17ee77bSGregory Herrero * @gregs_backup: Backup of global registers during suspend 567d17ee77bSGregory Herrero * @dregs_backup: Backup of device registers during suspend 568d17ee77bSGregory Herrero * @hregs_backup: Backup of host registers during suspend 569941fcce4SDinh Nguyen * 570941fcce4SDinh Nguyen * These are for host mode: 571941fcce4SDinh Nguyen * 572197ba5f4SPaul Zimmerman * @flags: Flags for handling root port state changes 573197ba5f4SPaul Zimmerman * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 574197ba5f4SPaul Zimmerman * Transfers associated with these QHs are not currently 575197ba5f4SPaul Zimmerman * assigned to a host channel. 576197ba5f4SPaul Zimmerman * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 577197ba5f4SPaul Zimmerman * Transfers associated with these QHs are currently 578197ba5f4SPaul Zimmerman * assigned to a host channel. 579197ba5f4SPaul Zimmerman * @non_periodic_qh_ptr: Pointer to next QH to process in the active 580197ba5f4SPaul Zimmerman * non-periodic schedule 581197ba5f4SPaul Zimmerman * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 582197ba5f4SPaul Zimmerman * list of QHs for periodic transfers that are _not_ 583197ba5f4SPaul Zimmerman * scheduled for the next frame. Each QH in the list has an 584197ba5f4SPaul Zimmerman * interval counter that determines when it needs to be 585197ba5f4SPaul Zimmerman * scheduled for execution. This scheduling mechanism 586197ba5f4SPaul Zimmerman * allows only a simple calculation for periodic bandwidth 587197ba5f4SPaul Zimmerman * used (i.e. must assume that all periodic transfers may 588197ba5f4SPaul Zimmerman * need to execute in the same frame). However, it greatly 589197ba5f4SPaul Zimmerman * simplifies scheduling and should be sufficient for the 590197ba5f4SPaul Zimmerman * vast majority of OTG hosts, which need to connect to a 591197ba5f4SPaul Zimmerman * small number of peripherals at one time. Items move from 592197ba5f4SPaul Zimmerman * this list to periodic_sched_ready when the QH interval 593197ba5f4SPaul Zimmerman * counter is 0 at SOF. 594197ba5f4SPaul Zimmerman * @periodic_sched_ready: List of periodic QHs that are ready for execution in 595197ba5f4SPaul Zimmerman * the next frame, but have not yet been assigned to host 596197ba5f4SPaul Zimmerman * channels. Items move from this list to 597197ba5f4SPaul Zimmerman * periodic_sched_assigned as host channels become 598197ba5f4SPaul Zimmerman * available during the current frame. 599197ba5f4SPaul Zimmerman * @periodic_sched_assigned: List of periodic QHs to be executed in the next 600197ba5f4SPaul Zimmerman * frame that are assigned to host channels. Items move 601197ba5f4SPaul Zimmerman * from this list to periodic_sched_queued as the 602197ba5f4SPaul Zimmerman * transactions for the QH are queued to the DWC_otg 603197ba5f4SPaul Zimmerman * controller. 604197ba5f4SPaul Zimmerman * @periodic_sched_queued: List of periodic QHs that have been queued for 605197ba5f4SPaul Zimmerman * execution. Items move from this list to either 606197ba5f4SPaul Zimmerman * periodic_sched_inactive or periodic_sched_ready when the 607197ba5f4SPaul Zimmerman * channel associated with the transfer is released. If the 608197ba5f4SPaul Zimmerman * interval for the QH is 1, the item moves to 609197ba5f4SPaul Zimmerman * periodic_sched_ready because it must be rescheduled for 610197ba5f4SPaul Zimmerman * the next frame. Otherwise, the item moves to 611197ba5f4SPaul Zimmerman * periodic_sched_inactive. 612197ba5f4SPaul Zimmerman * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 613197ba5f4SPaul Zimmerman * This value is in microseconds per (micro)frame. The 614197ba5f4SPaul Zimmerman * assumption is that all periodic transfers may occur in 615197ba5f4SPaul Zimmerman * the same (micro)frame. 616197ba5f4SPaul Zimmerman * @frame_usecs: Internal variable used by the microframe scheduler 617197ba5f4SPaul Zimmerman * @frame_number: Frame number read from the core at SOF. The value ranges 618197ba5f4SPaul Zimmerman * from 0 to HFNUM_MAX_FRNUM. 619197ba5f4SPaul Zimmerman * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 620197ba5f4SPaul Zimmerman * SOF enable/disable. 621197ba5f4SPaul Zimmerman * @free_hc_list: Free host channels in the controller. This is a list of 622197ba5f4SPaul Zimmerman * struct dwc2_host_chan items. 623197ba5f4SPaul Zimmerman * @periodic_channels: Number of host channels assigned to periodic transfers. 624197ba5f4SPaul Zimmerman * Currently assuming that there is a dedicated host 625197ba5f4SPaul Zimmerman * channel for each periodic transaction and at least one 626197ba5f4SPaul Zimmerman * host channel is available for non-periodic transactions. 627197ba5f4SPaul Zimmerman * @non_periodic_channels: Number of host channels assigned to non-periodic 628197ba5f4SPaul Zimmerman * transfers 629197ba5f4SPaul Zimmerman * @available_host_channels Number of host channels available for the microframe 630197ba5f4SPaul Zimmerman * scheduler to use 631197ba5f4SPaul Zimmerman * @hc_ptr_array: Array of pointers to the host channel descriptors. 632197ba5f4SPaul Zimmerman * Allows accessing a host channel descriptor given the 633197ba5f4SPaul Zimmerman * host channel number. This is useful in interrupt 634197ba5f4SPaul Zimmerman * handlers. 635197ba5f4SPaul Zimmerman * @status_buf: Buffer used for data received during the status phase of 636197ba5f4SPaul Zimmerman * a control transfer. 637197ba5f4SPaul Zimmerman * @status_buf_dma: DMA address for status_buf 638197ba5f4SPaul Zimmerman * @start_work: Delayed work for handling host A-cable connection 639197ba5f4SPaul Zimmerman * @reset_work: Delayed work for handling a port reset 640197ba5f4SPaul Zimmerman * @otg_port: OTG port number 641197ba5f4SPaul Zimmerman * @frame_list: Frame list 642197ba5f4SPaul Zimmerman * @frame_list_dma: Frame list DMA address 643941fcce4SDinh Nguyen * 644941fcce4SDinh Nguyen * These are for peripheral mode: 645941fcce4SDinh Nguyen * 646941fcce4SDinh Nguyen * @driver: USB gadget driver 647941fcce4SDinh Nguyen * @phy: The otg phy transceiver structure for phy control. 648941fcce4SDinh Nguyen * @uphy: The otg phy transceiver structure for old USB phy control. 649941fcce4SDinh Nguyen * @plat: The platform specific configuration data. This can be removed once 650941fcce4SDinh Nguyen * all SoCs support usb transceiver. 651941fcce4SDinh Nguyen * @supplies: Definition of USB power supplies 652941fcce4SDinh Nguyen * @phyif: PHY interface width 653941fcce4SDinh Nguyen * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 654941fcce4SDinh Nguyen * @num_of_eps: Number of available EPs (excluding EP0) 655941fcce4SDinh Nguyen * @debug_root: Root directrory for debugfs. 656941fcce4SDinh Nguyen * @debug_file: Main status file for debugfs. 6579e14d0a5SGregory Herrero * @debug_testmode: Testmode status file for debugfs. 658941fcce4SDinh Nguyen * @debug_fifo: FIFO status file for debugfs. 659941fcce4SDinh Nguyen * @ep0_reply: Request used for ep0 reply. 660941fcce4SDinh Nguyen * @ep0_buff: Buffer for EP0 reply data, if needed. 661941fcce4SDinh Nguyen * @ctrl_buff: Buffer for EP0 control requests. 662941fcce4SDinh Nguyen * @ctrl_req: Request for EP0 control packets. 663fe0b94abSMian Yousaf Kaukab * @ep0_state: EP0 control transfers state 6649e14d0a5SGregory Herrero * @test_mode: USB test mode requested by the host 665941fcce4SDinh Nguyen * @last_rst: Time of last reset 666941fcce4SDinh Nguyen * @eps: The endpoints being supplied to the gadget framework 667edd74be8SGregory Herrero * @g_using_dma: Indicate if dma usage is enabled 6680a176279SGregory Herrero * @g_rx_fifo_sz: Contains rx fifo size value 6690a176279SGregory Herrero * @g_np_g_tx_fifo_sz: Contains Non-Periodic tx fifo size value 6700a176279SGregory Herrero * @g_tx_fifo_sz: Contains tx fifo size value per endpoints 671197ba5f4SPaul Zimmerman */ 672197ba5f4SPaul Zimmerman struct dwc2_hsotg { 673197ba5f4SPaul Zimmerman struct device *dev; 674197ba5f4SPaul Zimmerman void __iomem *regs; 675197ba5f4SPaul Zimmerman /** Params detected from hardware */ 676197ba5f4SPaul Zimmerman struct dwc2_hw_params hw_params; 677197ba5f4SPaul Zimmerman /** Params to actually use */ 678197ba5f4SPaul Zimmerman struct dwc2_core_params *core_params; 679197ba5f4SPaul Zimmerman enum usb_otg_state op_state; 680c0155b9dSKever Yang enum usb_dr_mode dr_mode; 681e39af88fSMarek Szyprowski unsigned int hcd_enabled:1; 682e39af88fSMarek Szyprowski unsigned int gadget_enabled:1; 683197ba5f4SPaul Zimmerman 684941fcce4SDinh Nguyen struct phy *phy; 685941fcce4SDinh Nguyen struct usb_phy *uphy; 686941fcce4SDinh Nguyen struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsotg_supply_names)]; 687941fcce4SDinh Nguyen 688941fcce4SDinh Nguyen spinlock_t lock; 6897ad8096eSMarek Szyprowski struct mutex init_mutex; 690941fcce4SDinh Nguyen void *priv; 691941fcce4SDinh Nguyen int irq; 692941fcce4SDinh Nguyen struct clk *clk; 693941fcce4SDinh Nguyen 694197ba5f4SPaul Zimmerman unsigned int queuing_high_bandwidth:1; 695197ba5f4SPaul Zimmerman unsigned int srp_success:1; 696197ba5f4SPaul Zimmerman 697197ba5f4SPaul Zimmerman struct workqueue_struct *wq_otg; 698197ba5f4SPaul Zimmerman struct work_struct wf_otg; 699197ba5f4SPaul Zimmerman struct timer_list wkp_timer; 700197ba5f4SPaul Zimmerman enum dwc2_lx_state lx_state; 701d17ee77bSGregory Herrero struct dwc2_gregs_backup *gr_backup; 702d17ee77bSGregory Herrero struct dwc2_dregs_backup *dr_backup; 703d17ee77bSGregory Herrero struct dwc2_hregs_backup *hr_backup; 704197ba5f4SPaul Zimmerman 705941fcce4SDinh Nguyen struct dentry *debug_root; 706563cf017SMian Yousaf Kaukab struct debugfs_regset32 *regset; 707941fcce4SDinh Nguyen 708941fcce4SDinh Nguyen /* DWC OTG HW Release versions */ 709941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_71a 0x4f54271a 710941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_90a 0x4f54290a 711941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_92a 0x4f54292a 712941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_94a 0x4f54294a 713941fcce4SDinh Nguyen #define DWC2_CORE_REV_3_00a 0x4f54300a 714941fcce4SDinh Nguyen 715941fcce4SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 716197ba5f4SPaul Zimmerman union dwc2_hcd_internal_flags { 717197ba5f4SPaul Zimmerman u32 d32; 718197ba5f4SPaul Zimmerman struct { 719197ba5f4SPaul Zimmerman unsigned port_connect_status_change:1; 720197ba5f4SPaul Zimmerman unsigned port_connect_status:1; 721197ba5f4SPaul Zimmerman unsigned port_reset_change:1; 722197ba5f4SPaul Zimmerman unsigned port_enable_change:1; 723197ba5f4SPaul Zimmerman unsigned port_suspend_change:1; 724197ba5f4SPaul Zimmerman unsigned port_over_current_change:1; 725197ba5f4SPaul Zimmerman unsigned port_l1_change:1; 726fd4850cfSCharles Manning unsigned reserved:25; 727197ba5f4SPaul Zimmerman } b; 728197ba5f4SPaul Zimmerman } flags; 729197ba5f4SPaul Zimmerman 730197ba5f4SPaul Zimmerman struct list_head non_periodic_sched_inactive; 731197ba5f4SPaul Zimmerman struct list_head non_periodic_sched_active; 732197ba5f4SPaul Zimmerman struct list_head *non_periodic_qh_ptr; 733197ba5f4SPaul Zimmerman struct list_head periodic_sched_inactive; 734197ba5f4SPaul Zimmerman struct list_head periodic_sched_ready; 735197ba5f4SPaul Zimmerman struct list_head periodic_sched_assigned; 736197ba5f4SPaul Zimmerman struct list_head periodic_sched_queued; 737197ba5f4SPaul Zimmerman u16 periodic_usecs; 738197ba5f4SPaul Zimmerman u16 frame_usecs[8]; 739197ba5f4SPaul Zimmerman u16 frame_number; 740197ba5f4SPaul Zimmerman u16 periodic_qh_count; 741197ba5f4SPaul Zimmerman 742197ba5f4SPaul Zimmerman #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 743197ba5f4SPaul Zimmerman #define FRAME_NUM_ARRAY_SIZE 1000 744197ba5f4SPaul Zimmerman u16 last_frame_num; 745197ba5f4SPaul Zimmerman u16 *frame_num_array; 746197ba5f4SPaul Zimmerman u16 *last_frame_num_array; 747197ba5f4SPaul Zimmerman int frame_num_idx; 748197ba5f4SPaul Zimmerman int dumped_frame_num_array; 749197ba5f4SPaul Zimmerman #endif 750197ba5f4SPaul Zimmerman 751197ba5f4SPaul Zimmerman struct list_head free_hc_list; 752197ba5f4SPaul Zimmerman int periodic_channels; 753197ba5f4SPaul Zimmerman int non_periodic_channels; 754197ba5f4SPaul Zimmerman int available_host_channels; 755197ba5f4SPaul Zimmerman struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 756197ba5f4SPaul Zimmerman u8 *status_buf; 757197ba5f4SPaul Zimmerman dma_addr_t status_buf_dma; 758197ba5f4SPaul Zimmerman #define DWC2_HCD_STATUS_BUF_SIZE 64 759197ba5f4SPaul Zimmerman 760197ba5f4SPaul Zimmerman struct delayed_work start_work; 761197ba5f4SPaul Zimmerman struct delayed_work reset_work; 762197ba5f4SPaul Zimmerman u8 otg_port; 763197ba5f4SPaul Zimmerman u32 *frame_list; 764197ba5f4SPaul Zimmerman dma_addr_t frame_list_dma; 765197ba5f4SPaul Zimmerman 766197ba5f4SPaul Zimmerman #ifdef DEBUG 767197ba5f4SPaul Zimmerman u32 frrem_samples; 768197ba5f4SPaul Zimmerman u64 frrem_accum; 769197ba5f4SPaul Zimmerman 770197ba5f4SPaul Zimmerman u32 hfnum_7_samples_a; 771197ba5f4SPaul Zimmerman u64 hfnum_7_frrem_accum_a; 772197ba5f4SPaul Zimmerman u32 hfnum_0_samples_a; 773197ba5f4SPaul Zimmerman u64 hfnum_0_frrem_accum_a; 774197ba5f4SPaul Zimmerman u32 hfnum_other_samples_a; 775197ba5f4SPaul Zimmerman u64 hfnum_other_frrem_accum_a; 776197ba5f4SPaul Zimmerman 777197ba5f4SPaul Zimmerman u32 hfnum_7_samples_b; 778197ba5f4SPaul Zimmerman u64 hfnum_7_frrem_accum_b; 779197ba5f4SPaul Zimmerman u32 hfnum_0_samples_b; 780197ba5f4SPaul Zimmerman u64 hfnum_0_frrem_accum_b; 781197ba5f4SPaul Zimmerman u32 hfnum_other_samples_b; 782197ba5f4SPaul Zimmerman u64 hfnum_other_frrem_accum_b; 783197ba5f4SPaul Zimmerman #endif 784941fcce4SDinh Nguyen #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ 785941fcce4SDinh Nguyen 786941fcce4SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 787941fcce4SDinh Nguyen /* Gadget structures */ 788941fcce4SDinh Nguyen struct usb_gadget_driver *driver; 789941fcce4SDinh Nguyen struct s3c_hsotg_plat *plat; 790941fcce4SDinh Nguyen 791941fcce4SDinh Nguyen u32 phyif; 792941fcce4SDinh Nguyen int fifo_mem; 793941fcce4SDinh Nguyen unsigned int dedicated_fifos:1; 794941fcce4SDinh Nguyen unsigned char num_of_eps; 795941fcce4SDinh Nguyen u32 fifo_map; 796941fcce4SDinh Nguyen 797941fcce4SDinh Nguyen struct usb_request *ep0_reply; 798941fcce4SDinh Nguyen struct usb_request *ctrl_req; 7993f95001dSMian Yousaf Kaukab void *ep0_buff; 8003f95001dSMian Yousaf Kaukab void *ctrl_buff; 801fe0b94abSMian Yousaf Kaukab enum dwc2_ep0_state ep0_state; 8029e14d0a5SGregory Herrero u8 test_mode; 803941fcce4SDinh Nguyen 804941fcce4SDinh Nguyen struct usb_gadget gadget; 805dc6e69e6SMarek Szyprowski unsigned int enabled:1; 8064ace06e8SMarek Szyprowski unsigned int connected:1; 807941fcce4SDinh Nguyen unsigned long last_rst; 808c6f5c050SMian Yousaf Kaukab struct s3c_hsotg_ep *eps_in[MAX_EPS_CHANNELS]; 809c6f5c050SMian Yousaf Kaukab struct s3c_hsotg_ep *eps_out[MAX_EPS_CHANNELS]; 810edd74be8SGregory Herrero u32 g_using_dma; 8110a176279SGregory Herrero u32 g_rx_fifo_sz; 8120a176279SGregory Herrero u32 g_np_g_tx_fifo_sz; 8130a176279SGregory Herrero u32 g_tx_fifo_sz[MAX_EPS_CHANNELS]; 814941fcce4SDinh Nguyen #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 815197ba5f4SPaul Zimmerman }; 816197ba5f4SPaul Zimmerman 817197ba5f4SPaul Zimmerman /* Reasons for halting a host channel */ 818197ba5f4SPaul Zimmerman enum dwc2_halt_status { 819197ba5f4SPaul Zimmerman DWC2_HC_XFER_NO_HALT_STATUS, 820197ba5f4SPaul Zimmerman DWC2_HC_XFER_COMPLETE, 821197ba5f4SPaul Zimmerman DWC2_HC_XFER_URB_COMPLETE, 822197ba5f4SPaul Zimmerman DWC2_HC_XFER_ACK, 823197ba5f4SPaul Zimmerman DWC2_HC_XFER_NAK, 824197ba5f4SPaul Zimmerman DWC2_HC_XFER_NYET, 825197ba5f4SPaul Zimmerman DWC2_HC_XFER_STALL, 826197ba5f4SPaul Zimmerman DWC2_HC_XFER_XACT_ERR, 827197ba5f4SPaul Zimmerman DWC2_HC_XFER_FRAME_OVERRUN, 828197ba5f4SPaul Zimmerman DWC2_HC_XFER_BABBLE_ERR, 829197ba5f4SPaul Zimmerman DWC2_HC_XFER_DATA_TOGGLE_ERR, 830197ba5f4SPaul Zimmerman DWC2_HC_XFER_AHB_ERR, 831197ba5f4SPaul Zimmerman DWC2_HC_XFER_PERIODIC_INCOMPLETE, 832197ba5f4SPaul Zimmerman DWC2_HC_XFER_URB_DEQUEUE, 833197ba5f4SPaul Zimmerman }; 834197ba5f4SPaul Zimmerman 835197ba5f4SPaul Zimmerman /* 836197ba5f4SPaul Zimmerman * The following functions support initialization of the core driver component 837197ba5f4SPaul Zimmerman * and the DWC_otg controller 838197ba5f4SPaul Zimmerman */ 839197ba5f4SPaul Zimmerman extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg); 840d17ee77bSGregory Herrero extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg); 841d17ee77bSGregory Herrero extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore); 842197ba5f4SPaul Zimmerman 843197ba5f4SPaul Zimmerman /* 844197ba5f4SPaul Zimmerman * Host core Functions. 845197ba5f4SPaul Zimmerman * The following functions support managing the DWC_otg controller in host 846197ba5f4SPaul Zimmerman * mode. 847197ba5f4SPaul Zimmerman */ 848197ba5f4SPaul Zimmerman extern void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan); 849197ba5f4SPaul Zimmerman extern void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 850197ba5f4SPaul Zimmerman enum dwc2_halt_status halt_status); 851197ba5f4SPaul Zimmerman extern void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, 852197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan); 853197ba5f4SPaul Zimmerman extern void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 854197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan); 855197ba5f4SPaul Zimmerman extern void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 856197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan); 857197ba5f4SPaul Zimmerman extern int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 858197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan); 859197ba5f4SPaul Zimmerman extern void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, 860197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan); 861197ba5f4SPaul Zimmerman extern void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg); 862197ba5f4SPaul Zimmerman extern void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg); 863197ba5f4SPaul Zimmerman 864197ba5f4SPaul Zimmerman extern u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg); 865197ba5f4SPaul Zimmerman extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 866197ba5f4SPaul Zimmerman 867197ba5f4SPaul Zimmerman /* 868197ba5f4SPaul Zimmerman * Common core Functions. 869197ba5f4SPaul Zimmerman * The following functions support managing the DWC_otg controller in either 870197ba5f4SPaul Zimmerman * device or host mode. 871197ba5f4SPaul Zimmerman */ 872197ba5f4SPaul Zimmerman extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 873197ba5f4SPaul Zimmerman extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 874197ba5f4SPaul Zimmerman extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 875197ba5f4SPaul Zimmerman 876197ba5f4SPaul Zimmerman extern int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq); 877197ba5f4SPaul Zimmerman extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 878197ba5f4SPaul Zimmerman extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 879197ba5f4SPaul Zimmerman 880197ba5f4SPaul Zimmerman /* This function should be called on every hardware interrupt. */ 881197ba5f4SPaul Zimmerman extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 882197ba5f4SPaul Zimmerman 883197ba5f4SPaul Zimmerman /* OTG Core Parameters */ 884197ba5f4SPaul Zimmerman 885197ba5f4SPaul Zimmerman /* 886197ba5f4SPaul Zimmerman * Specifies the OTG capabilities. The driver will automatically 887197ba5f4SPaul Zimmerman * detect the value for this parameter if none is specified. 888197ba5f4SPaul Zimmerman * 0 - HNP and SRP capable (default) 889197ba5f4SPaul Zimmerman * 1 - SRP Only capable 890197ba5f4SPaul Zimmerman * 2 - No HNP/SRP capable 891197ba5f4SPaul Zimmerman */ 892197ba5f4SPaul Zimmerman extern void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val); 893197ba5f4SPaul Zimmerman #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 894197ba5f4SPaul Zimmerman #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 895197ba5f4SPaul Zimmerman #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 896197ba5f4SPaul Zimmerman 897197ba5f4SPaul Zimmerman /* 898197ba5f4SPaul Zimmerman * Specifies whether to use slave or DMA mode for accessing the data 899197ba5f4SPaul Zimmerman * FIFOs. The driver will automatically detect the value for this 900197ba5f4SPaul Zimmerman * parameter if none is specified. 901197ba5f4SPaul Zimmerman * 0 - Slave 902197ba5f4SPaul Zimmerman * 1 - DMA (default, if available) 903197ba5f4SPaul Zimmerman */ 904197ba5f4SPaul Zimmerman extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val); 905197ba5f4SPaul Zimmerman 906197ba5f4SPaul Zimmerman /* 907197ba5f4SPaul Zimmerman * When DMA mode is enabled specifies whether to use 908197ba5f4SPaul Zimmerman * address DMA or DMA Descritor mode for accessing the data 909197ba5f4SPaul Zimmerman * FIFOs in device mode. The driver will automatically detect 910197ba5f4SPaul Zimmerman * the value for this parameter if none is specified. 911197ba5f4SPaul Zimmerman * 0 - address DMA 912197ba5f4SPaul Zimmerman * 1 - DMA Descriptor(default, if available) 913197ba5f4SPaul Zimmerman */ 914197ba5f4SPaul Zimmerman extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val); 915197ba5f4SPaul Zimmerman 916197ba5f4SPaul Zimmerman /* 917197ba5f4SPaul Zimmerman * Specifies the maximum speed of operation in host and device mode. 918197ba5f4SPaul Zimmerman * The actual speed depends on the speed of the attached device and 919197ba5f4SPaul Zimmerman * the value of phy_type. The actual speed depends on the speed of the 920197ba5f4SPaul Zimmerman * attached device. 921197ba5f4SPaul Zimmerman * 0 - High Speed (default) 922197ba5f4SPaul Zimmerman * 1 - Full Speed 923197ba5f4SPaul Zimmerman */ 924197ba5f4SPaul Zimmerman extern void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val); 925197ba5f4SPaul Zimmerman #define DWC2_SPEED_PARAM_HIGH 0 926197ba5f4SPaul Zimmerman #define DWC2_SPEED_PARAM_FULL 1 927197ba5f4SPaul Zimmerman 928197ba5f4SPaul Zimmerman /* 929197ba5f4SPaul Zimmerman * Specifies whether low power mode is supported when attached 930197ba5f4SPaul Zimmerman * to a Full Speed or Low Speed device in host mode. 931197ba5f4SPaul Zimmerman * 932197ba5f4SPaul Zimmerman * 0 - Don't support low power mode (default) 933197ba5f4SPaul Zimmerman * 1 - Support low power mode 934197ba5f4SPaul Zimmerman */ 935197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_support_fs_ls_low_power( 936197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg, int val); 937197ba5f4SPaul Zimmerman 938197ba5f4SPaul Zimmerman /* 939197ba5f4SPaul Zimmerman * Specifies the PHY clock rate in low power mode when connected to a 940197ba5f4SPaul Zimmerman * Low Speed device in host mode. This parameter is applicable only if 941197ba5f4SPaul Zimmerman * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS 942197ba5f4SPaul Zimmerman * then defaults to 6 MHZ otherwise 48 MHZ. 943197ba5f4SPaul Zimmerman * 944197ba5f4SPaul Zimmerman * 0 - 48 MHz 945197ba5f4SPaul Zimmerman * 1 - 6 MHz 946197ba5f4SPaul Zimmerman */ 947197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, 948197ba5f4SPaul Zimmerman int val); 949197ba5f4SPaul Zimmerman #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 950197ba5f4SPaul Zimmerman #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 951197ba5f4SPaul Zimmerman 952197ba5f4SPaul Zimmerman /* 953197ba5f4SPaul Zimmerman * 0 - Use cC FIFO size parameters 954197ba5f4SPaul Zimmerman * 1 - Allow dynamic FIFO sizing (default) 955197ba5f4SPaul Zimmerman */ 956197ba5f4SPaul Zimmerman extern void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, 957197ba5f4SPaul Zimmerman int val); 958197ba5f4SPaul Zimmerman 959197ba5f4SPaul Zimmerman /* 960197ba5f4SPaul Zimmerman * Number of 4-byte words in the Rx FIFO in host mode when dynamic 961197ba5f4SPaul Zimmerman * FIFO sizing is enabled. 962197ba5f4SPaul Zimmerman * 16 to 32768 (default 1024) 963197ba5f4SPaul Zimmerman */ 964197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val); 965197ba5f4SPaul Zimmerman 966197ba5f4SPaul Zimmerman /* 967197ba5f4SPaul Zimmerman * Number of 4-byte words in the non-periodic Tx FIFO in host mode 968197ba5f4SPaul Zimmerman * when Dynamic FIFO sizing is enabled in the core. 969197ba5f4SPaul Zimmerman * 16 to 32768 (default 256) 970197ba5f4SPaul Zimmerman */ 971197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, 972197ba5f4SPaul Zimmerman int val); 973197ba5f4SPaul Zimmerman 974197ba5f4SPaul Zimmerman /* 975197ba5f4SPaul Zimmerman * Number of 4-byte words in the host periodic Tx FIFO when dynamic 976197ba5f4SPaul Zimmerman * FIFO sizing is enabled. 977197ba5f4SPaul Zimmerman * 16 to 32768 (default 256) 978197ba5f4SPaul Zimmerman */ 979197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, 980197ba5f4SPaul Zimmerman int val); 981197ba5f4SPaul Zimmerman 982197ba5f4SPaul Zimmerman /* 983197ba5f4SPaul Zimmerman * The maximum transfer size supported in bytes. 984197ba5f4SPaul Zimmerman * 2047 to 65,535 (default 65,535) 985197ba5f4SPaul Zimmerman */ 986197ba5f4SPaul Zimmerman extern void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val); 987197ba5f4SPaul Zimmerman 988197ba5f4SPaul Zimmerman /* 989197ba5f4SPaul Zimmerman * The maximum number of packets in a transfer. 990197ba5f4SPaul Zimmerman * 15 to 511 (default 511) 991197ba5f4SPaul Zimmerman */ 992197ba5f4SPaul Zimmerman extern void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val); 993197ba5f4SPaul Zimmerman 994197ba5f4SPaul Zimmerman /* 995197ba5f4SPaul Zimmerman * The number of host channel registers to use. 996197ba5f4SPaul Zimmerman * 1 to 16 (default 11) 997197ba5f4SPaul Zimmerman * Note: The FPGA configuration supports a maximum of 11 host channels. 998197ba5f4SPaul Zimmerman */ 999197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val); 1000197ba5f4SPaul Zimmerman 1001197ba5f4SPaul Zimmerman /* 1002197ba5f4SPaul Zimmerman * Specifies the type of PHY interface to use. By default, the driver 1003197ba5f4SPaul Zimmerman * will automatically detect the phy_type. 1004197ba5f4SPaul Zimmerman * 1005197ba5f4SPaul Zimmerman * 0 - Full Speed PHY 1006197ba5f4SPaul Zimmerman * 1 - UTMI+ (default) 1007197ba5f4SPaul Zimmerman * 2 - ULPI 1008197ba5f4SPaul Zimmerman */ 1009197ba5f4SPaul Zimmerman extern void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val); 1010197ba5f4SPaul Zimmerman #define DWC2_PHY_TYPE_PARAM_FS 0 1011197ba5f4SPaul Zimmerman #define DWC2_PHY_TYPE_PARAM_UTMI 1 1012197ba5f4SPaul Zimmerman #define DWC2_PHY_TYPE_PARAM_ULPI 2 1013197ba5f4SPaul Zimmerman 1014197ba5f4SPaul Zimmerman /* 1015197ba5f4SPaul Zimmerman * Specifies the UTMI+ Data Width. This parameter is 1016197ba5f4SPaul Zimmerman * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI 1017197ba5f4SPaul Zimmerman * PHY_TYPE, this parameter indicates the data width between 1018197ba5f4SPaul Zimmerman * the MAC and the ULPI Wrapper.) Also, this parameter is 1019197ba5f4SPaul Zimmerman * applicable only if the OTG_HSPHY_WIDTH cC parameter was set 1020197ba5f4SPaul Zimmerman * to "8 and 16 bits", meaning that the core has been 1021197ba5f4SPaul Zimmerman * configured to work at either data path width. 1022197ba5f4SPaul Zimmerman * 1023197ba5f4SPaul Zimmerman * 8 or 16 bits (default 16) 1024197ba5f4SPaul Zimmerman */ 1025197ba5f4SPaul Zimmerman extern void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val); 1026197ba5f4SPaul Zimmerman 1027197ba5f4SPaul Zimmerman /* 1028197ba5f4SPaul Zimmerman * Specifies whether the ULPI operates at double or single 1029197ba5f4SPaul Zimmerman * data rate. This parameter is only applicable if PHY_TYPE is 1030197ba5f4SPaul Zimmerman * ULPI. 1031197ba5f4SPaul Zimmerman * 1032197ba5f4SPaul Zimmerman * 0 - single data rate ULPI interface with 8 bit wide data 1033197ba5f4SPaul Zimmerman * bus (default) 1034197ba5f4SPaul Zimmerman * 1 - double data rate ULPI interface with 4 bit wide data 1035197ba5f4SPaul Zimmerman * bus 1036197ba5f4SPaul Zimmerman */ 1037197ba5f4SPaul Zimmerman extern void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val); 1038197ba5f4SPaul Zimmerman 1039197ba5f4SPaul Zimmerman /* 1040197ba5f4SPaul Zimmerman * Specifies whether to use the internal or external supply to 1041197ba5f4SPaul Zimmerman * drive the vbus with a ULPI phy. 1042197ba5f4SPaul Zimmerman */ 1043197ba5f4SPaul Zimmerman extern void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val); 1044197ba5f4SPaul Zimmerman #define DWC2_PHY_ULPI_INTERNAL_VBUS 0 1045197ba5f4SPaul Zimmerman #define DWC2_PHY_ULPI_EXTERNAL_VBUS 1 1046197ba5f4SPaul Zimmerman 1047197ba5f4SPaul Zimmerman /* 1048197ba5f4SPaul Zimmerman * Specifies whether to use the I2Cinterface for full speed PHY. This 1049197ba5f4SPaul Zimmerman * parameter is only applicable if PHY_TYPE is FS. 1050197ba5f4SPaul Zimmerman * 0 - No (default) 1051197ba5f4SPaul Zimmerman * 1 - Yes 1052197ba5f4SPaul Zimmerman */ 1053197ba5f4SPaul Zimmerman extern void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val); 1054197ba5f4SPaul Zimmerman 1055197ba5f4SPaul Zimmerman extern void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val); 1056197ba5f4SPaul Zimmerman 1057197ba5f4SPaul Zimmerman extern void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val); 1058197ba5f4SPaul Zimmerman 1059197ba5f4SPaul Zimmerman /* 1060197ba5f4SPaul Zimmerman * Specifies whether dedicated transmit FIFOs are 1061197ba5f4SPaul Zimmerman * enabled for non periodic IN endpoints in device mode 1062197ba5f4SPaul Zimmerman * 0 - No 1063197ba5f4SPaul Zimmerman * 1 - Yes 1064197ba5f4SPaul Zimmerman */ 1065197ba5f4SPaul Zimmerman extern void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, 1066197ba5f4SPaul Zimmerman int val); 1067197ba5f4SPaul Zimmerman 1068197ba5f4SPaul Zimmerman extern void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val); 1069197ba5f4SPaul Zimmerman 1070197ba5f4SPaul Zimmerman extern void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val); 1071197ba5f4SPaul Zimmerman 1072197ba5f4SPaul Zimmerman extern void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val); 1073197ba5f4SPaul Zimmerman 1074ecb176c6SMian Yousaf Kaukab extern void dwc2_set_parameters(struct dwc2_hsotg *hsotg, 1075ecb176c6SMian Yousaf Kaukab const struct dwc2_core_params *params); 1076ecb176c6SMian Yousaf Kaukab 1077ecb176c6SMian Yousaf Kaukab extern void dwc2_set_all_params(struct dwc2_core_params *params, int value); 1078ecb176c6SMian Yousaf Kaukab 1079ecb176c6SMian Yousaf Kaukab extern int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); 1080ecb176c6SMian Yousaf Kaukab 1081ecb176c6SMian Yousaf Kaukab 1082ecb176c6SMian Yousaf Kaukab 1083197ba5f4SPaul Zimmerman /* 1084197ba5f4SPaul Zimmerman * Dump core registers and SPRAM 1085197ba5f4SPaul Zimmerman */ 1086197ba5f4SPaul Zimmerman extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 1087197ba5f4SPaul Zimmerman extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 1088197ba5f4SPaul Zimmerman extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 1089197ba5f4SPaul Zimmerman 1090197ba5f4SPaul Zimmerman /* 1091197ba5f4SPaul Zimmerman * Return OTG version - either 1.3 or 2.0 1092197ba5f4SPaul Zimmerman */ 1093197ba5f4SPaul Zimmerman extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg); 1094197ba5f4SPaul Zimmerman 1095117777b2SDinh Nguyen /* Gadget defines */ 1096117777b2SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1097117777b2SDinh Nguyen extern int s3c_hsotg_remove(struct dwc2_hsotg *hsotg); 1098117777b2SDinh Nguyen extern int s3c_hsotg_suspend(struct dwc2_hsotg *dwc2); 1099117777b2SDinh Nguyen extern int s3c_hsotg_resume(struct dwc2_hsotg *dwc2); 1100117777b2SDinh Nguyen extern int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq); 1101643cc4deSGregory Herrero extern void s3c_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1102643cc4deSGregory Herrero bool reset); 1103510ffaa4SDinh Nguyen extern void s3c_hsotg_core_connect(struct dwc2_hsotg *hsotg); 11044ace06e8SMarek Szyprowski extern void s3c_hsotg_disconnect(struct dwc2_hsotg *dwc2); 1105f91eea44SMian Yousaf Kaukab extern int s3c_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode); 1106f81f46e1SGregory Herrero #define dwc2_is_device_connected(hsotg) (hsotg->connected) 1107117777b2SDinh Nguyen #else 1108117777b2SDinh Nguyen static inline int s3c_hsotg_remove(struct dwc2_hsotg *dwc2) 1109117777b2SDinh Nguyen { return 0; } 1110117777b2SDinh Nguyen static inline int s3c_hsotg_suspend(struct dwc2_hsotg *dwc2) 1111117777b2SDinh Nguyen { return 0; } 1112117777b2SDinh Nguyen static inline int s3c_hsotg_resume(struct dwc2_hsotg *dwc2) 1113117777b2SDinh Nguyen { return 0; } 1114117777b2SDinh Nguyen static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) 1115117777b2SDinh Nguyen { return 0; } 1116643cc4deSGregory Herrero static inline void s3c_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1117643cc4deSGregory Herrero bool reset) {} 1118510ffaa4SDinh Nguyen static inline void s3c_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} 11194ace06e8SMarek Szyprowski static inline void s3c_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} 1120f91eea44SMian Yousaf Kaukab static inline int s3c_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, 1121f91eea44SMian Yousaf Kaukab int testmode) 1122f91eea44SMian Yousaf Kaukab { return 0; } 1123f81f46e1SGregory Herrero #define dwc2_is_device_connected(hsotg) (0) 1124117777b2SDinh Nguyen #endif 1125117777b2SDinh Nguyen 1126117777b2SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1127117777b2SDinh Nguyen extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 1128117777b2SDinh Nguyen extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg); 1129117777b2SDinh Nguyen extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 1130117777b2SDinh Nguyen #else 1131117777b2SDinh Nguyen static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1132117777b2SDinh Nguyen { return 0; } 1133117777b2SDinh Nguyen static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg) {} 1134117777b2SDinh Nguyen static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} 1135117777b2SDinh Nguyen static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} 1136ecb176c6SMian Yousaf Kaukab static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) 1137117777b2SDinh Nguyen { return 0; } 1138117777b2SDinh Nguyen #endif 1139117777b2SDinh Nguyen 1140197ba5f4SPaul Zimmerman #endif /* __DWC2_CORE_H__ */ 1141