15fd54aceSGreg Kroah-Hartman // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2197ba5f4SPaul Zimmerman /* 3197ba5f4SPaul Zimmerman * core.h - DesignWare HS OTG Controller common declarations 4197ba5f4SPaul Zimmerman * 5197ba5f4SPaul Zimmerman * Copyright (C) 2004-2013 Synopsys, Inc. 6197ba5f4SPaul Zimmerman * 7197ba5f4SPaul Zimmerman * Redistribution and use in source and binary forms, with or without 8197ba5f4SPaul Zimmerman * modification, are permitted provided that the following conditions 9197ba5f4SPaul Zimmerman * are met: 10197ba5f4SPaul Zimmerman * 1. Redistributions of source code must retain the above copyright 11197ba5f4SPaul Zimmerman * notice, this list of conditions, and the following disclaimer, 12197ba5f4SPaul Zimmerman * without modification. 13197ba5f4SPaul Zimmerman * 2. Redistributions in binary form must reproduce the above copyright 14197ba5f4SPaul Zimmerman * notice, this list of conditions and the following disclaimer in the 15197ba5f4SPaul Zimmerman * documentation and/or other materials provided with the distribution. 16197ba5f4SPaul Zimmerman * 3. The names of the above-listed copyright holders may not be used 17197ba5f4SPaul Zimmerman * to endorse or promote products derived from this software without 18197ba5f4SPaul Zimmerman * specific prior written permission. 19197ba5f4SPaul Zimmerman * 20197ba5f4SPaul Zimmerman * ALTERNATIVELY, this software may be distributed under the terms of the 21197ba5f4SPaul Zimmerman * GNU General Public License ("GPL") as published by the Free Software 22197ba5f4SPaul Zimmerman * Foundation; either version 2 of the License, or (at your option) any 23197ba5f4SPaul Zimmerman * later version. 24197ba5f4SPaul Zimmerman * 25197ba5f4SPaul Zimmerman * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 26197ba5f4SPaul Zimmerman * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 27197ba5f4SPaul Zimmerman * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28197ba5f4SPaul Zimmerman * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 29197ba5f4SPaul Zimmerman * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 30197ba5f4SPaul Zimmerman * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 31197ba5f4SPaul Zimmerman * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32197ba5f4SPaul Zimmerman * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 33197ba5f4SPaul Zimmerman * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 34197ba5f4SPaul Zimmerman * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 35197ba5f4SPaul Zimmerman * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36197ba5f4SPaul Zimmerman */ 37197ba5f4SPaul Zimmerman 38197ba5f4SPaul Zimmerman #ifndef __DWC2_CORE_H__ 39197ba5f4SPaul Zimmerman #define __DWC2_CORE_H__ 40197ba5f4SPaul Zimmerman 41f7c0b143SDinh Nguyen #include <linux/phy/phy.h> 42f7c0b143SDinh Nguyen #include <linux/regulator/consumer.h> 43f7c0b143SDinh Nguyen #include <linux/usb/gadget.h> 44f7c0b143SDinh Nguyen #include <linux/usb/otg.h> 45197ba5f4SPaul Zimmerman #include <linux/usb/phy.h> 46197ba5f4SPaul Zimmerman #include "hw.h" 47197ba5f4SPaul Zimmerman 4874fc4a75SDouglas Anderson /* 4974fc4a75SDouglas Anderson * Suggested defines for tracers: 5074fc4a75SDouglas Anderson * - no_printk: Disable tracing 5174fc4a75SDouglas Anderson * - pr_info: Print this info to the console 5274fc4a75SDouglas Anderson * - trace_printk: Print this info to trace buffer (good for verbose logging) 5374fc4a75SDouglas Anderson */ 5474fc4a75SDouglas Anderson 5574fc4a75SDouglas Anderson #define DWC2_TRACE_SCHEDULER no_printk 5674fc4a75SDouglas Anderson #define DWC2_TRACE_SCHEDULER_VB no_printk 5774fc4a75SDouglas Anderson 5874fc4a75SDouglas Anderson /* Detailed scheduler tracing, but won't overwhelm console */ 5974fc4a75SDouglas Anderson #define dwc2_sch_dbg(hsotg, fmt, ...) \ 6074fc4a75SDouglas Anderson DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \ 6174fc4a75SDouglas Anderson dev_name(hsotg->dev), ##__VA_ARGS__) 6274fc4a75SDouglas Anderson 6374fc4a75SDouglas Anderson /* Verbose scheduler tracing */ 6474fc4a75SDouglas Anderson #define dwc2_sch_vdbg(hsotg, fmt, ...) \ 6574fc4a75SDouglas Anderson DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \ 6674fc4a75SDouglas Anderson dev_name(hsotg->dev), ##__VA_ARGS__) 6774fc4a75SDouglas Anderson 68197ba5f4SPaul Zimmerman /* Maximum number of Endpoints/HostChannels */ 69197ba5f4SPaul Zimmerman #define MAX_EPS_CHANNELS 16 70197ba5f4SPaul Zimmerman 711f91b4ccSFelipe Balbi /* dwc2-hsotg declarations */ 721f91b4ccSFelipe Balbi static const char * const dwc2_hsotg_supply_names[] = { 73f7c0b143SDinh Nguyen "vusb_d", /* digital USB supply, 1.2V */ 74f7c0b143SDinh Nguyen "vusb_a", /* analog USB supply, 1.1V */ 75f7c0b143SDinh Nguyen }; 76f7c0b143SDinh Nguyen 77b98866c2SJohn Youn #define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names) 78b98866c2SJohn Youn 79f7c0b143SDinh Nguyen /* 80f7c0b143SDinh Nguyen * EP0_MPS_LIMIT 81f7c0b143SDinh Nguyen * 82f7c0b143SDinh Nguyen * Unfortunately there seems to be a limit of the amount of data that can 83f7c0b143SDinh Nguyen * be transferred by IN transactions on EP0. This is either 127 bytes or 3 84f7c0b143SDinh Nguyen * packets (which practically means 1 packet and 63 bytes of data) when the 85f7c0b143SDinh Nguyen * MPS is set to 64. 86f7c0b143SDinh Nguyen * 87f7c0b143SDinh Nguyen * This means if we are wanting to move >127 bytes of data, we need to 88f7c0b143SDinh Nguyen * split the transactions up, but just doing one packet at a time does 89f7c0b143SDinh Nguyen * not work (this may be an implicit DATA0 PID on first packet of the 90f7c0b143SDinh Nguyen * transaction) and doing 2 packets is outside the controller's limits. 91f7c0b143SDinh Nguyen * 92f7c0b143SDinh Nguyen * If we try to lower the MPS size for EP0, then no transfers work properly 93f7c0b143SDinh Nguyen * for EP0, and the system will fail basic enumeration. As no cause for this 94f7c0b143SDinh Nguyen * has currently been found, we cannot support any large IN transfers for 95f7c0b143SDinh Nguyen * EP0. 96f7c0b143SDinh Nguyen */ 97f7c0b143SDinh Nguyen #define EP0_MPS_LIMIT 64 98f7c0b143SDinh Nguyen 99941fcce4SDinh Nguyen struct dwc2_hsotg; 1001f91b4ccSFelipe Balbi struct dwc2_hsotg_req; 101f7c0b143SDinh Nguyen 102f7c0b143SDinh Nguyen /** 1031f91b4ccSFelipe Balbi * struct dwc2_hsotg_ep - driver endpoint definition. 104f7c0b143SDinh Nguyen * @ep: The gadget layer representation of the endpoint. 105f7c0b143SDinh Nguyen * @name: The driver generated name for the endpoint. 106f7c0b143SDinh Nguyen * @queue: Queue of requests for this endpoint. 107f7c0b143SDinh Nguyen * @parent: Reference back to the parent device structure. 108f7c0b143SDinh Nguyen * @req: The current request that the endpoint is processing. This is 109f7c0b143SDinh Nguyen * used to indicate an request has been loaded onto the endpoint 110f7c0b143SDinh Nguyen * and has yet to be completed (maybe due to data move, or simply 111f7c0b143SDinh Nguyen * awaiting an ack from the core all the data has been completed). 112f7c0b143SDinh Nguyen * @debugfs: File entry for debugfs file for this endpoint. 113f7c0b143SDinh Nguyen * @dir_in: Set to true if this endpoint is of the IN direction, which 114f7c0b143SDinh Nguyen * means that it is sending data to the Host. 115f7c0b143SDinh Nguyen * @index: The index for the endpoint registers. 116f7c0b143SDinh Nguyen * @mc: Multi Count - number of transactions per microframe 1176fb914d7SGrigor Tovmasyan * @interval: Interval for periodic endpoints, in frames or microframes. 118f7c0b143SDinh Nguyen * @name: The name array passed to the USB core. 119f7c0b143SDinh Nguyen * @halted: Set if the endpoint has been halted. 120f7c0b143SDinh Nguyen * @periodic: Set if this is a periodic ep, such as Interrupt 121f7c0b143SDinh Nguyen * @isochronous: Set if this is a isochronous ep 1228a20fa45SMian Yousaf Kaukab * @send_zlp: Set if we need to send a zero-length packet. 1235f54c54bSVahram Aharonyan * @desc_list_dma: The DMA address of descriptor chain currently in use. 1245f54c54bSVahram Aharonyan * @desc_list: Pointer to descriptor DMA chain head currently in use. 1255f54c54bSVahram Aharonyan * @desc_count: Count of entries within the DMA descriptor chain of EP. 126ab7d2192SVahram Aharonyan * @next_desc: index of next free descriptor in the ISOC chain under SW control. 127729cac69SMinas Harutyunyan * @compl_desc: index of next descriptor to be completed by xFerComplete 128f7c0b143SDinh Nguyen * @total_data: The total number of data bytes done. 129f7c0b143SDinh Nguyen * @fifo_size: The size of the FIFO (for periodic IN endpoints) 1306fb914d7SGrigor Tovmasyan * @fifo_index: For Dedicated FIFO operation, only FIFO0 can be used for EP0. 131f7c0b143SDinh Nguyen * @fifo_load: The amount of data loaded into the FIFO (periodic IN) 132f7c0b143SDinh Nguyen * @last_load: The offset of data for the last start of request. 133f7c0b143SDinh Nguyen * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN 13492d1635dSVardan Mikayelyan * @target_frame: Targeted frame num to setup next ISOC transfer 13592d1635dSVardan Mikayelyan * @frame_overrun: Indicates SOF number overrun in DSTS 136f7c0b143SDinh Nguyen * 137f7c0b143SDinh Nguyen * This is the driver's state for each registered enpoint, allowing it 138f7c0b143SDinh Nguyen * to keep track of transactions that need doing. Each endpoint has a 139f7c0b143SDinh Nguyen * lock to protect the state, to try and avoid using an overall lock 140f7c0b143SDinh Nguyen * for the host controller as much as possible. 141f7c0b143SDinh Nguyen * 142f7c0b143SDinh Nguyen * For periodic IN endpoints, we have fifo_size and fifo_load to try 143f7c0b143SDinh Nguyen * and keep track of the amount of data in the periodic FIFO for each 144f7c0b143SDinh Nguyen * of these as we don't have a status register that tells us how much 145f7c0b143SDinh Nguyen * is in each of them. (note, this may actually be useless information 146f7c0b143SDinh Nguyen * as in shared-fifo mode periodic in acts like a single-frame packet 147f7c0b143SDinh Nguyen * buffer than a fifo) 148f7c0b143SDinh Nguyen */ 1491f91b4ccSFelipe Balbi struct dwc2_hsotg_ep { 150f7c0b143SDinh Nguyen struct usb_ep ep; 151f7c0b143SDinh Nguyen struct list_head queue; 152941fcce4SDinh Nguyen struct dwc2_hsotg *parent; 1531f91b4ccSFelipe Balbi struct dwc2_hsotg_req *req; 154f7c0b143SDinh Nguyen struct dentry *debugfs; 155f7c0b143SDinh Nguyen 156f7c0b143SDinh Nguyen unsigned long total_data; 157f7c0b143SDinh Nguyen unsigned int size_loaded; 158f7c0b143SDinh Nguyen unsigned int last_load; 159f7c0b143SDinh Nguyen unsigned int fifo_load; 160f7c0b143SDinh Nguyen unsigned short fifo_size; 161b203d0a2SRobert Baldyga unsigned short fifo_index; 162f7c0b143SDinh Nguyen 163f7c0b143SDinh Nguyen unsigned char dir_in; 164f7c0b143SDinh Nguyen unsigned char index; 165f7c0b143SDinh Nguyen unsigned char mc; 16612814a3fSGrigor Tovmasyan u16 interval; 167f7c0b143SDinh Nguyen 168f7c0b143SDinh Nguyen unsigned int halted:1; 169f7c0b143SDinh Nguyen unsigned int periodic:1; 170f7c0b143SDinh Nguyen unsigned int isochronous:1; 1718a20fa45SMian Yousaf Kaukab unsigned int send_zlp:1; 17292d1635dSVardan Mikayelyan unsigned int target_frame; 17392d1635dSVardan Mikayelyan #define TARGET_FRAME_INITIAL 0xFFFFFFFF 17492d1635dSVardan Mikayelyan bool frame_overrun; 175f7c0b143SDinh Nguyen 1765f54c54bSVahram Aharonyan dma_addr_t desc_list_dma; 1775f54c54bSVahram Aharonyan struct dwc2_dma_desc *desc_list; 1785f54c54bSVahram Aharonyan u8 desc_count; 1795f54c54bSVahram Aharonyan 180ab7d2192SVahram Aharonyan unsigned int next_desc; 181729cac69SMinas Harutyunyan unsigned int compl_desc; 182ab7d2192SVahram Aharonyan 183f7c0b143SDinh Nguyen char name[10]; 184f7c0b143SDinh Nguyen }; 185f7c0b143SDinh Nguyen 186f7c0b143SDinh Nguyen /** 1871f91b4ccSFelipe Balbi * struct dwc2_hsotg_req - data transfer request 188f7c0b143SDinh Nguyen * @req: The USB gadget request 189f7c0b143SDinh Nguyen * @queue: The list of requests for the endpoint this is queued for. 1907d24c1b5SMian Yousaf Kaukab * @saved_req_buf: variable to save req.buf when bounce buffers are used. 191f7c0b143SDinh Nguyen */ 1921f91b4ccSFelipe Balbi struct dwc2_hsotg_req { 193f7c0b143SDinh Nguyen struct usb_request req; 194f7c0b143SDinh Nguyen struct list_head queue; 1957d24c1b5SMian Yousaf Kaukab void *saved_req_buf; 196f7c0b143SDinh Nguyen }; 197f7c0b143SDinh Nguyen 198b98866c2SJohn Youn #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 199b98866c2SJohn Youn IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 200f7c0b143SDinh Nguyen #define call_gadget(_hs, _entry) \ 201f7c0b143SDinh Nguyen do { \ 202f7c0b143SDinh Nguyen if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ 203f7c0b143SDinh Nguyen (_hs)->driver && (_hs)->driver->_entry) { \ 204f7c0b143SDinh Nguyen spin_unlock(&_hs->lock); \ 205f7c0b143SDinh Nguyen (_hs)->driver->_entry(&(_hs)->gadget); \ 206f7c0b143SDinh Nguyen spin_lock(&_hs->lock); \ 207f7c0b143SDinh Nguyen } \ 208f7c0b143SDinh Nguyen } while (0) 209941fcce4SDinh Nguyen #else 210941fcce4SDinh Nguyen #define call_gadget(_hs, _entry) do {} while (0) 211941fcce4SDinh Nguyen #endif 212f7c0b143SDinh Nguyen 213197ba5f4SPaul Zimmerman struct dwc2_hsotg; 214197ba5f4SPaul Zimmerman struct dwc2_host_chan; 215197ba5f4SPaul Zimmerman 216197ba5f4SPaul Zimmerman /* Device States */ 217197ba5f4SPaul Zimmerman enum dwc2_lx_state { 218197ba5f4SPaul Zimmerman DWC2_L0, /* On state */ 219197ba5f4SPaul Zimmerman DWC2_L1, /* LPM sleep state */ 220197ba5f4SPaul Zimmerman DWC2_L2, /* USB suspend state */ 221197ba5f4SPaul Zimmerman DWC2_L3, /* Off state */ 222197ba5f4SPaul Zimmerman }; 223197ba5f4SPaul Zimmerman 224fe0b94abSMian Yousaf Kaukab /* Gadget ep0 states */ 225fe0b94abSMian Yousaf Kaukab enum dwc2_ep0_state { 226fe0b94abSMian Yousaf Kaukab DWC2_EP0_SETUP, 227fe0b94abSMian Yousaf Kaukab DWC2_EP0_DATA_IN, 228fe0b94abSMian Yousaf Kaukab DWC2_EP0_DATA_OUT, 229fe0b94abSMian Yousaf Kaukab DWC2_EP0_STATUS_IN, 230fe0b94abSMian Yousaf Kaukab DWC2_EP0_STATUS_OUT, 231fe0b94abSMian Yousaf Kaukab }; 232fe0b94abSMian Yousaf Kaukab 233197ba5f4SPaul Zimmerman /** 234197ba5f4SPaul Zimmerman * struct dwc2_core_params - Parameters for configuring the core 235197ba5f4SPaul Zimmerman * 236197ba5f4SPaul Zimmerman * @otg_cap: Specifies the OTG capabilities. 237197ba5f4SPaul Zimmerman * 0 - HNP and SRP capable 238197ba5f4SPaul Zimmerman * 1 - SRP Only capable 239197ba5f4SPaul Zimmerman * 2 - No HNP/SRP capable (always available) 240197ba5f4SPaul Zimmerman * Defaults to best available option (0, 1, then 2) 241e7839f99SJohn Youn * @host_dma: Specifies whether to use slave or DMA mode for accessing 242197ba5f4SPaul Zimmerman * the data FIFOs. The driver will automatically detect the 243197ba5f4SPaul Zimmerman * value for this parameter if none is specified. 244197ba5f4SPaul Zimmerman * 0 - Slave (always available) 245197ba5f4SPaul Zimmerman * 1 - DMA (default, if available) 246197ba5f4SPaul Zimmerman * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 247197ba5f4SPaul Zimmerman * address DMA mode or descriptor DMA mode for accessing 248197ba5f4SPaul Zimmerman * the data FIFOs. The driver will automatically detect the 249197ba5f4SPaul Zimmerman * value for this if none is specified. 250197ba5f4SPaul Zimmerman * 0 - Address DMA 251197ba5f4SPaul Zimmerman * 1 - Descriptor DMA (default, if available) 252fbb9e22bSMian Yousaf Kaukab * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use 253fbb9e22bSMian Yousaf Kaukab * address DMA mode or descriptor DMA mode for accessing 254fbb9e22bSMian Yousaf Kaukab * the data FIFOs in Full Speed mode only. The driver 255fbb9e22bSMian Yousaf Kaukab * will automatically detect the value for this if none is 256fbb9e22bSMian Yousaf Kaukab * specified. 257fbb9e22bSMian Yousaf Kaukab * 0 - Address DMA 258fbb9e22bSMian Yousaf Kaukab * 1 - Descriptor DMA in FS (default, if available) 259197ba5f4SPaul Zimmerman * @speed: Specifies the maximum speed of operation in host and 260197ba5f4SPaul Zimmerman * device mode. The actual speed depends on the speed of 261197ba5f4SPaul Zimmerman * the attached device and the value of phy_type. 262197ba5f4SPaul Zimmerman * 0 - High Speed 263197ba5f4SPaul Zimmerman * (default when phy_type is UTMI+ or ULPI) 264197ba5f4SPaul Zimmerman * 1 - Full Speed 265197ba5f4SPaul Zimmerman * (default when phy_type is Full Speed) 266197ba5f4SPaul Zimmerman * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 267197ba5f4SPaul Zimmerman * 1 - Allow dynamic FIFO sizing (default, if available) 268197ba5f4SPaul Zimmerman * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 269c1d286cfSJohn Youn * are enabled for non-periodic IN endpoints in device 270c1d286cfSJohn Youn * mode. 271197ba5f4SPaul Zimmerman * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 272197ba5f4SPaul Zimmerman * dynamic FIFO sizing is enabled 273197ba5f4SPaul Zimmerman * 16 to 32768 274197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 275197ba5f4SPaul Zimmerman * the default. 276197ba5f4SPaul Zimmerman * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 277197ba5f4SPaul Zimmerman * in host mode when dynamic FIFO sizing is enabled 278197ba5f4SPaul Zimmerman * 16 to 32768 279197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 280197ba5f4SPaul Zimmerman * the default. 281197ba5f4SPaul Zimmerman * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 282197ba5f4SPaul Zimmerman * host mode when dynamic FIFO sizing is enabled 283197ba5f4SPaul Zimmerman * 16 to 32768 284197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 285197ba5f4SPaul Zimmerman * the default. 286197ba5f4SPaul Zimmerman * @max_transfer_size: The maximum transfer size supported, in bytes 287197ba5f4SPaul Zimmerman * 2047 to 65,535 288197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 289197ba5f4SPaul Zimmerman * the default. 290197ba5f4SPaul Zimmerman * @max_packet_count: The maximum number of packets in a transfer 291197ba5f4SPaul Zimmerman * 15 to 511 292197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 293197ba5f4SPaul Zimmerman * the default. 294197ba5f4SPaul Zimmerman * @host_channels: The number of host channel registers to use 295197ba5f4SPaul Zimmerman * 1 to 16 296197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 297197ba5f4SPaul Zimmerman * the default. 298197ba5f4SPaul Zimmerman * @phy_type: Specifies the type of PHY interface to use. By default, 299197ba5f4SPaul Zimmerman * the driver will automatically detect the phy_type. 300197ba5f4SPaul Zimmerman * 0 - Full Speed Phy 301197ba5f4SPaul Zimmerman * 1 - UTMI+ Phy 302197ba5f4SPaul Zimmerman * 2 - ULPI Phy 303197ba5f4SPaul Zimmerman * Defaults to best available option (2, 1, then 0) 304197ba5f4SPaul Zimmerman * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 305197ba5f4SPaul Zimmerman * is applicable for a phy_type of UTMI+ or ULPI. (For a 306197ba5f4SPaul Zimmerman * ULPI phy_type, this parameter indicates the data width 307197ba5f4SPaul Zimmerman * between the MAC and the ULPI Wrapper.) Also, this 308197ba5f4SPaul Zimmerman * parameter is applicable only if the OTG_HSPHY_WIDTH cC 309197ba5f4SPaul Zimmerman * parameter was set to "8 and 16 bits", meaning that the 310197ba5f4SPaul Zimmerman * core has been configured to work at either data path 311197ba5f4SPaul Zimmerman * width. 312197ba5f4SPaul Zimmerman * 8 or 16 (default 16 if available) 313197ba5f4SPaul Zimmerman * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 314197ba5f4SPaul Zimmerman * data rate. This parameter is only applicable if phy_type 315197ba5f4SPaul Zimmerman * is ULPI. 316197ba5f4SPaul Zimmerman * 0 - single data rate ULPI interface with 8 bit wide 317197ba5f4SPaul Zimmerman * data bus (default) 318197ba5f4SPaul Zimmerman * 1 - double data rate ULPI interface with 4 bit wide 319197ba5f4SPaul Zimmerman * data bus 320197ba5f4SPaul Zimmerman * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 321197ba5f4SPaul Zimmerman * external supply to drive the VBus 322197ba5f4SPaul Zimmerman * 0 - Internal supply (default) 323197ba5f4SPaul Zimmerman * 1 - External supply 324197ba5f4SPaul Zimmerman * @i2c_enable: Specifies whether to use the I2Cinterface for a full 325197ba5f4SPaul Zimmerman * speed PHY. This parameter is only applicable if phy_type 326197ba5f4SPaul Zimmerman * is FS. 327197ba5f4SPaul Zimmerman * 0 - No (default) 328197ba5f4SPaul Zimmerman * 1 - Yes 3296fb914d7SGrigor Tovmasyan * @ipg_isoc_en: Indicates the IPG supports is enabled or disabled. 330b43ebc96SGrigor Tovmasyan * 0 - Disable (default) 331b43ebc96SGrigor Tovmasyan * 1 - Enable 3326fb914d7SGrigor Tovmasyan * @acg_enable: For enabling Active Clock Gating in the controller 3336fb914d7SGrigor Tovmasyan * 0 - No 3346fb914d7SGrigor Tovmasyan * 1 - Yes 335197ba5f4SPaul Zimmerman * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 336197ba5f4SPaul Zimmerman * 0 - No (default) 337197ba5f4SPaul Zimmerman * 1 - Yes 338197ba5f4SPaul Zimmerman * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 339197ba5f4SPaul Zimmerman * when attached to a Full Speed or Low Speed device in 340197ba5f4SPaul Zimmerman * host mode. 341197ba5f4SPaul Zimmerman * 0 - Don't support low power mode (default) 342197ba5f4SPaul Zimmerman * 1 - Support low power mode 343197ba5f4SPaul Zimmerman * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 344197ba5f4SPaul Zimmerman * when connected to a Low Speed device in host 345197ba5f4SPaul Zimmerman * mode. This parameter is applicable only if 346197ba5f4SPaul Zimmerman * host_support_fs_ls_low_power is enabled. 347197ba5f4SPaul Zimmerman * 0 - 48 MHz 348197ba5f4SPaul Zimmerman * (default when phy_type is UTMI+ or ULPI) 349197ba5f4SPaul Zimmerman * 1 - 6 MHz 350197ba5f4SPaul Zimmerman * (default when phy_type is Full Speed) 351b11633c4SDinh Nguyen * @oc_disable: Flag to disable overcurrent condition. 352b11633c4SDinh Nguyen * 0 - Allow overcurrent condition to get detected 353b11633c4SDinh Nguyen * 1 - Disable overcurrent condtion to get detected 354197ba5f4SPaul Zimmerman * @ts_dline: Enable Term Select Dline pulsing 355197ba5f4SPaul Zimmerman * 0 - No (default) 356197ba5f4SPaul Zimmerman * 1 - Yes 357197ba5f4SPaul Zimmerman * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 358197ba5f4SPaul Zimmerman * 0 - No (default for core < 2.92a) 359197ba5f4SPaul Zimmerman * 1 - Yes (default for core >= 2.92a) 360197ba5f4SPaul Zimmerman * @ahbcfg: This field allows the default value of the GAHBCFG 361197ba5f4SPaul Zimmerman * register to be overridden 362197ba5f4SPaul Zimmerman * -1 - GAHBCFG value will be set to 0x06 3631b52d2faSRazmik Karapetyan * (INCR, default) 364197ba5f4SPaul Zimmerman * all others - GAHBCFG value will be overridden with 365197ba5f4SPaul Zimmerman * this value 366197ba5f4SPaul Zimmerman * Not all bits can be controlled like this, the 367197ba5f4SPaul Zimmerman * bits defined by GAHBCFG_CTRL_MASK are controlled 368197ba5f4SPaul Zimmerman * by the driver and are ignored in this 369197ba5f4SPaul Zimmerman * configuration value. 370197ba5f4SPaul Zimmerman * @uframe_sched: True to enable the microframe scheduler 371a6d249d8SGregory Herrero * @external_id_pin_ctl: Specifies whether ID pin is handled externally. 372a6d249d8SGregory Herrero * Disable CONIDSTSCHNG controller interrupt in such 373a6d249d8SGregory Herrero * case. 374a6d249d8SGregory Herrero * 0 - No (default) 375a6d249d8SGregory Herrero * 1 - Yes 37641ba9b9bSVardan Mikayelyan * @power_down: Specifies whether the controller support power_down. 37741ba9b9bSVardan Mikayelyan * If power_down is enabled, the controller will enter 37841ba9b9bSVardan Mikayelyan * power_down in both peripheral and host mode when 379285046aaSGregory Herrero * needed. 380285046aaSGregory Herrero * 0 - No (default) 381631a2310SVardan Mikayelyan * 1 - Partial power down 382631a2310SVardan Mikayelyan * 2 - Hibernation 3836f80b6deSSevak Arakelyan * @lpm: Enable LPM support. 3846f80b6deSSevak Arakelyan * 0 - No 3856f80b6deSSevak Arakelyan * 1 - Yes 3866f80b6deSSevak Arakelyan * @lpm_clock_gating: Enable core PHY clock gating. 3876f80b6deSSevak Arakelyan * 0 - No 3886f80b6deSSevak Arakelyan * 1 - Yes 3896f80b6deSSevak Arakelyan * @besl: Enable LPM Errata support. 3906f80b6deSSevak Arakelyan * 0 - No 3916f80b6deSSevak Arakelyan * 1 - Yes 3926f80b6deSSevak Arakelyan * @hird_threshold_en: HIRD or HIRD Threshold enable. 3936f80b6deSSevak Arakelyan * 0 - No 3946f80b6deSSevak Arakelyan * 1 - Yes 3956f80b6deSSevak Arakelyan * @hird_threshold: Value of BESL or HIRD Threshold. 396e35b1350SBruno Herrera * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO 397e35b1350SBruno Herrera * register. 398e35b1350SBruno Herrera * 0 - Deactivate the transceiver (default) 399e35b1350SBruno Herrera * 1 - Activate the transceiver 4009962b62fSJohn Youn * @g_dma: Enables gadget dma usage (default: autodetect). 401dec4b556SVahram Aharonyan * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect). 40205ee799fSJohn Youn * @g_rx_fifo_size: The periodic rx fifo size for the device, in 40305ee799fSJohn Youn * DWORDS from 16-32768 (default: 2048 if 40405ee799fSJohn Youn * possible, otherwise autodetect). 40505ee799fSJohn Youn * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in 40605ee799fSJohn Youn * DWORDS from 16-32768 (default: 1024 if 40705ee799fSJohn Youn * possible, otherwise autodetect). 40805ee799fSJohn Youn * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo 40905ee799fSJohn Youn * mode. Each value corresponds to one EP 41005ee799fSJohn Youn * starting from EP1 (max 15 values). Sizes are 41105ee799fSJohn Youn * in DWORDS with possible values from from 41205ee799fSJohn Youn * 16-32768 (default: 256, 256, 256, 256, 768, 41305ee799fSJohn Youn * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0). 414ca8b0332SChen Yu * @change_speed_quirk: Change speed configuration to DWC2_SPEED_PARAM_FULL 415ca8b0332SChen Yu * while full&low speed device connect. And change speed 416ca8b0332SChen Yu * back to DWC2_SPEED_PARAM_HIGH while device is gone. 417ca8b0332SChen Yu * 0 - No (default) 418ca8b0332SChen Yu * 1 - Yes 419ca531bc2SGrigor Tovmasyan * @service_interval: Enable service interval based scheduling. 420ca531bc2SGrigor Tovmasyan * 0 - No 421ca531bc2SGrigor Tovmasyan * 1 - Yes 422197ba5f4SPaul Zimmerman * 423197ba5f4SPaul Zimmerman * The following parameters may be specified when starting the module. These 424197ba5f4SPaul Zimmerman * parameters define how the DWC_otg controller should be configured. A 425197ba5f4SPaul Zimmerman * value of -1 (or any other out of range value) for any parameter means 426197ba5f4SPaul Zimmerman * to read the value from hardware (if possible) or use the builtin 427197ba5f4SPaul Zimmerman * default described above. 428197ba5f4SPaul Zimmerman */ 429197ba5f4SPaul Zimmerman struct dwc2_core_params { 430d21bcc3fSJohn Youn u8 otg_cap; 431c1d286cfSJohn Youn #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 432c1d286cfSJohn Youn #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 433c1d286cfSJohn Youn #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 434c1d286cfSJohn Youn 435d21bcc3fSJohn Youn u8 phy_type; 436c1d286cfSJohn Youn #define DWC2_PHY_TYPE_PARAM_FS 0 437c1d286cfSJohn Youn #define DWC2_PHY_TYPE_PARAM_UTMI 1 438c1d286cfSJohn Youn #define DWC2_PHY_TYPE_PARAM_ULPI 2 439c1d286cfSJohn Youn 44057b8e235SJohn Youn u8 speed; 44157b8e235SJohn Youn #define DWC2_SPEED_PARAM_HIGH 0 44257b8e235SJohn Youn #define DWC2_SPEED_PARAM_FULL 1 44357b8e235SJohn Youn #define DWC2_SPEED_PARAM_LOW 2 44457b8e235SJohn Youn 445d21bcc3fSJohn Youn u8 phy_utmi_width; 446d21bcc3fSJohn Youn bool phy_ulpi_ddr; 447d21bcc3fSJohn Youn bool phy_ulpi_ext_vbus; 44857b8e235SJohn Youn bool enable_dynamic_fifo; 44957b8e235SJohn Youn bool en_multiple_tx_fifo; 450d21bcc3fSJohn Youn bool i2c_enable; 45166e77a24SRazmik Karapetyan bool acg_enable; 452d21bcc3fSJohn Youn bool ulpi_fs_ls; 45357b8e235SJohn Youn bool ts_dline; 45457b8e235SJohn Youn bool reload_ctl; 45557b8e235SJohn Youn bool uframe_sched; 45657b8e235SJohn Youn bool external_id_pin_ctl; 457631a2310SVardan Mikayelyan 458631a2310SVardan Mikayelyan int power_down; 459631a2310SVardan Mikayelyan #define DWC2_POWER_DOWN_PARAM_NONE 0 460631a2310SVardan Mikayelyan #define DWC2_POWER_DOWN_PARAM_PARTIAL 1 461631a2310SVardan Mikayelyan #define DWC2_POWER_DOWN_PARAM_HIBERNATION 2 462631a2310SVardan Mikayelyan 4636f80b6deSSevak Arakelyan bool lpm; 4646f80b6deSSevak Arakelyan bool lpm_clock_gating; 4656f80b6deSSevak Arakelyan bool besl; 4666f80b6deSSevak Arakelyan bool hird_threshold_en; 467ca531bc2SGrigor Tovmasyan bool service_interval; 4686f80b6deSSevak Arakelyan u8 hird_threshold; 469e35b1350SBruno Herrera bool activate_stm_fs_transceiver; 470b43ebc96SGrigor Tovmasyan bool ipg_isoc_en; 47157b8e235SJohn Youn u16 max_packet_count; 47257b8e235SJohn Youn u32 max_transfer_size; 47357b8e235SJohn Youn u32 ahbcfg; 47457b8e235SJohn Youn 47557b8e235SJohn Youn /* Host parameters */ 47657b8e235SJohn Youn bool host_dma; 47757b8e235SJohn Youn bool dma_desc_enable; 47857b8e235SJohn Youn bool dma_desc_fs_enable; 479d21bcc3fSJohn Youn bool host_support_fs_ls_low_power; 480d21bcc3fSJohn Youn bool host_ls_low_power_phy_clk; 481b11633c4SDinh Nguyen bool oc_disable; 482c1d286cfSJohn Youn 48357b8e235SJohn Youn u8 host_channels; 48457b8e235SJohn Youn u16 host_rx_fifo_size; 48557b8e235SJohn Youn u16 host_nperio_tx_fifo_size; 48657b8e235SJohn Youn u16 host_perio_tx_fifo_size; 4876b66ce51SJohn Youn 4886b66ce51SJohn Youn /* Gadget parameters */ 48905ee799fSJohn Youn bool g_dma; 490dec4b556SVahram Aharonyan bool g_dma_desc; 49100c704ccSLeo Yan u32 g_rx_fifo_size; 49200c704ccSLeo Yan u32 g_np_tx_fifo_size; 49305ee799fSJohn Youn u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; 494ca8b0332SChen Yu 495ca8b0332SChen Yu bool change_speed_quirk; 496197ba5f4SPaul Zimmerman }; 497197ba5f4SPaul Zimmerman 498197ba5f4SPaul Zimmerman /** 499197ba5f4SPaul Zimmerman * struct dwc2_hw_params - Autodetected parameters. 500197ba5f4SPaul Zimmerman * 501197ba5f4SPaul Zimmerman * These parameters are the various parameters read from hardware 502197ba5f4SPaul Zimmerman * registers during initialization. They typically contain the best 503197ba5f4SPaul Zimmerman * supported or maximum value that can be configured in the 504197ba5f4SPaul Zimmerman * corresponding dwc2_core_params value. 505197ba5f4SPaul Zimmerman * 506197ba5f4SPaul Zimmerman * The values that are not in dwc2_core_params are documented below. 507197ba5f4SPaul Zimmerman * 5086fb914d7SGrigor Tovmasyan * @op_mode: Mode of Operation 509197ba5f4SPaul Zimmerman * 0 - HNP- and SRP-Capable OTG (Host & Device) 510197ba5f4SPaul Zimmerman * 1 - SRP-Capable OTG (Host & Device) 511197ba5f4SPaul Zimmerman * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 512197ba5f4SPaul Zimmerman * 3 - SRP-Capable Device 513197ba5f4SPaul Zimmerman * 4 - Non-OTG Device 514197ba5f4SPaul Zimmerman * 5 - SRP-Capable Host 515197ba5f4SPaul Zimmerman * 6 - Non-OTG Host 5166fb914d7SGrigor Tovmasyan * @arch: Architecture 517197ba5f4SPaul Zimmerman * 0 - Slave only 518197ba5f4SPaul Zimmerman * 1 - External DMA 519197ba5f4SPaul Zimmerman * 2 - Internal DMA 5206fb914d7SGrigor Tovmasyan * @ipg_isoc_en: This feature indicates that the controller supports 521b43ebc96SGrigor Tovmasyan * the worst-case scenario of Rx followed by Rx 522b43ebc96SGrigor Tovmasyan * Interpacket Gap (IPG) (32 bitTimes) as per the utmi 523b43ebc96SGrigor Tovmasyan * specification for any token following ISOC OUT token. 524b43ebc96SGrigor Tovmasyan * 0 - Don't support 525b43ebc96SGrigor Tovmasyan * 1 - Support 5266fb914d7SGrigor Tovmasyan * @power_optimized: Are power optimizations enabled? 5276fb914d7SGrigor Tovmasyan * @num_dev_ep: Number of device endpoints available 5286fb914d7SGrigor Tovmasyan * @num_dev_in_eps: Number of device IN endpoints available 5296fb914d7SGrigor Tovmasyan * @num_dev_perio_in_ep: Number of device periodic IN endpoints 530997f4f81SMickael Maison * available 5316fb914d7SGrigor Tovmasyan * @dev_token_q_depth: Device Mode IN Token Sequence Learning Queue 532197ba5f4SPaul Zimmerman * Depth 533197ba5f4SPaul Zimmerman * 0 to 30 5346fb914d7SGrigor Tovmasyan * @host_perio_tx_q_depth: 535197ba5f4SPaul Zimmerman * Host Mode Periodic Request Queue Depth 536197ba5f4SPaul Zimmerman * 2, 4 or 8 5376fb914d7SGrigor Tovmasyan * @nperio_tx_q_depth: 538197ba5f4SPaul Zimmerman * Non-Periodic Request Queue Depth 539197ba5f4SPaul Zimmerman * 2, 4 or 8 5406fb914d7SGrigor Tovmasyan * @hs_phy_type: High-speed PHY interface type 541197ba5f4SPaul Zimmerman * 0 - High-speed interface not supported 542197ba5f4SPaul Zimmerman * 1 - UTMI+ 543197ba5f4SPaul Zimmerman * 2 - ULPI 544197ba5f4SPaul Zimmerman * 3 - UTMI+ and ULPI 5456fb914d7SGrigor Tovmasyan * @fs_phy_type: Full-speed PHY interface type 546197ba5f4SPaul Zimmerman * 0 - Full speed interface not supported 547197ba5f4SPaul Zimmerman * 1 - Dedicated full speed interface 548197ba5f4SPaul Zimmerman * 2 - FS pins shared with UTMI+ pins 549197ba5f4SPaul Zimmerman * 3 - FS pins shared with ULPI pins 550197ba5f4SPaul Zimmerman * @total_fifo_size: Total internal RAM for FIFOs (bytes) 5516fb914d7SGrigor Tovmasyan * @hibernation: Is hibernation enabled? 5526fb914d7SGrigor Tovmasyan * @utmi_phy_data_width: UTMI+ PHY data width 553197ba5f4SPaul Zimmerman * 0 - 8 bits 554197ba5f4SPaul Zimmerman * 1 - 16 bits 555197ba5f4SPaul Zimmerman * 2 - 8 or 16 bits 556197ba5f4SPaul Zimmerman * @snpsid: Value from SNPSID register 55755e1040eSJohn Youn * @dev_ep_dirs: Direction of device endpoints (GHWCFG1) 5586fb914d7SGrigor Tovmasyan * @g_tx_fifo_size: Power-on values of TxFIFO sizes 5596fb914d7SGrigor Tovmasyan * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 5606fb914d7SGrigor Tovmasyan * address DMA mode or descriptor DMA mode for accessing 5616fb914d7SGrigor Tovmasyan * the data FIFOs. The driver will automatically detect the 5626fb914d7SGrigor Tovmasyan * value for this if none is specified. 5636fb914d7SGrigor Tovmasyan * 0 - Address DMA 5646fb914d7SGrigor Tovmasyan * 1 - Descriptor DMA (default, if available) 5656fb914d7SGrigor Tovmasyan * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 5666fb914d7SGrigor Tovmasyan * 1 - Allow dynamic FIFO sizing (default, if available) 5676fb914d7SGrigor Tovmasyan * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 5686fb914d7SGrigor Tovmasyan * are enabled for non-periodic IN endpoints in device 5696fb914d7SGrigor Tovmasyan * mode. 5706fb914d7SGrigor Tovmasyan * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 5716fb914d7SGrigor Tovmasyan * in host mode when dynamic FIFO sizing is enabled 5726fb914d7SGrigor Tovmasyan * 16 to 32768 5736fb914d7SGrigor Tovmasyan * Actual maximum value is autodetected and also 5746fb914d7SGrigor Tovmasyan * the default. 5756fb914d7SGrigor Tovmasyan * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 5766fb914d7SGrigor Tovmasyan * host mode when dynamic FIFO sizing is enabled 5776fb914d7SGrigor Tovmasyan * 16 to 32768 5786fb914d7SGrigor Tovmasyan * Actual maximum value is autodetected and also 5796fb914d7SGrigor Tovmasyan * the default. 5806fb914d7SGrigor Tovmasyan * @max_transfer_size: The maximum transfer size supported, in bytes 5816fb914d7SGrigor Tovmasyan * 2047 to 65,535 5826fb914d7SGrigor Tovmasyan * Actual maximum value is autodetected and also 5836fb914d7SGrigor Tovmasyan * the default. 5846fb914d7SGrigor Tovmasyan * @max_packet_count: The maximum number of packets in a transfer 5856fb914d7SGrigor Tovmasyan * 15 to 511 5866fb914d7SGrigor Tovmasyan * Actual maximum value is autodetected and also 5876fb914d7SGrigor Tovmasyan * the default. 5886fb914d7SGrigor Tovmasyan * @host_channels: The number of host channel registers to use 5896fb914d7SGrigor Tovmasyan * 1 to 16 5906fb914d7SGrigor Tovmasyan * Actual maximum value is autodetected and also 5916fb914d7SGrigor Tovmasyan * the default. 5926fb914d7SGrigor Tovmasyan * @dev_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 5936fb914d7SGrigor Tovmasyan * in device mode when dynamic FIFO sizing is enabled 5946fb914d7SGrigor Tovmasyan * 16 to 32768 5956fb914d7SGrigor Tovmasyan * Actual maximum value is autodetected and also 5966fb914d7SGrigor Tovmasyan * the default. 5976fb914d7SGrigor Tovmasyan * @i2c_enable: Specifies whether to use the I2Cinterface for a full 5986fb914d7SGrigor Tovmasyan * speed PHY. This parameter is only applicable if phy_type 5996fb914d7SGrigor Tovmasyan * is FS. 6006fb914d7SGrigor Tovmasyan * 0 - No (default) 6016fb914d7SGrigor Tovmasyan * 1 - Yes 6026fb914d7SGrigor Tovmasyan * @acg_enable: For enabling Active Clock Gating in the controller 6036fb914d7SGrigor Tovmasyan * 0 - Disable 6046fb914d7SGrigor Tovmasyan * 1 - Enable 6056fb914d7SGrigor Tovmasyan * @lpm_mode: For enabling Link Power Management in the controller 6066fb914d7SGrigor Tovmasyan * 0 - Disable 6076fb914d7SGrigor Tovmasyan * 1 - Enable 6086fb914d7SGrigor Tovmasyan * @rx_fifo_size: Number of 4-byte words in the Rx FIFO when dynamic 6096fb914d7SGrigor Tovmasyan * FIFO sizing is enabled 16 to 32768 6106fb914d7SGrigor Tovmasyan * Actual maximum value is autodetected and also 6116fb914d7SGrigor Tovmasyan * the default. 612ca531bc2SGrigor Tovmasyan * @service_interval_mode: For enabling service interval based scheduling in the 613ca531bc2SGrigor Tovmasyan * controller. 614ca531bc2SGrigor Tovmasyan * 0 - Disable 615ca531bc2SGrigor Tovmasyan * 1 - Enable 616197ba5f4SPaul Zimmerman */ 617197ba5f4SPaul Zimmerman struct dwc2_hw_params { 618197ba5f4SPaul Zimmerman unsigned op_mode:3; 619197ba5f4SPaul Zimmerman unsigned arch:2; 620197ba5f4SPaul Zimmerman unsigned dma_desc_enable:1; 621197ba5f4SPaul Zimmerman unsigned enable_dynamic_fifo:1; 622197ba5f4SPaul Zimmerman unsigned en_multiple_tx_fifo:1; 623d1531319SJohn Youn unsigned rx_fifo_size:16; 624197ba5f4SPaul Zimmerman unsigned host_nperio_tx_fifo_size:16; 62555e1040eSJohn Youn unsigned dev_nperio_tx_fifo_size:16; 626197ba5f4SPaul Zimmerman unsigned host_perio_tx_fifo_size:16; 627197ba5f4SPaul Zimmerman unsigned nperio_tx_q_depth:3; 628197ba5f4SPaul Zimmerman unsigned host_perio_tx_q_depth:3; 629197ba5f4SPaul Zimmerman unsigned dev_token_q_depth:5; 630197ba5f4SPaul Zimmerman unsigned max_transfer_size:26; 631197ba5f4SPaul Zimmerman unsigned max_packet_count:11; 632197ba5f4SPaul Zimmerman unsigned host_channels:5; 633197ba5f4SPaul Zimmerman unsigned hs_phy_type:2; 634197ba5f4SPaul Zimmerman unsigned fs_phy_type:2; 635197ba5f4SPaul Zimmerman unsigned i2c_enable:1; 63666e77a24SRazmik Karapetyan unsigned acg_enable:1; 637197ba5f4SPaul Zimmerman unsigned num_dev_ep:4; 6389273083aSMinas Harutyunyan unsigned num_dev_in_eps : 4; 639197ba5f4SPaul Zimmerman unsigned num_dev_perio_in_ep:4; 640197ba5f4SPaul Zimmerman unsigned total_fifo_size:16; 641197ba5f4SPaul Zimmerman unsigned power_optimized:1; 642631a2310SVardan Mikayelyan unsigned hibernation:1; 643197ba5f4SPaul Zimmerman unsigned utmi_phy_data_width:2; 6446f80b6deSSevak Arakelyan unsigned lpm_mode:1; 645b43ebc96SGrigor Tovmasyan unsigned ipg_isoc_en:1; 646ca531bc2SGrigor Tovmasyan unsigned service_interval_mode:1; 647197ba5f4SPaul Zimmerman u32 snpsid; 64855e1040eSJohn Youn u32 dev_ep_dirs; 6499273083aSMinas Harutyunyan u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; 650197ba5f4SPaul Zimmerman }; 651197ba5f4SPaul Zimmerman 6523f95001dSMian Yousaf Kaukab /* Size of control and EP0 buffers */ 6533f95001dSMian Yousaf Kaukab #define DWC2_CTRL_BUFF_SIZE 8 6543f95001dSMian Yousaf Kaukab 655197ba5f4SPaul Zimmerman /** 65638beaec6SJohn Youn * struct dwc2_gregs_backup - Holds global registers state before 65738beaec6SJohn Youn * entering partial power down 658d17ee77bSGregory Herrero * @gotgctl: Backup of GOTGCTL register 659d17ee77bSGregory Herrero * @gintmsk: Backup of GINTMSK register 660d17ee77bSGregory Herrero * @gahbcfg: Backup of GAHBCFG register 661d17ee77bSGregory Herrero * @gusbcfg: Backup of GUSBCFG register 662d17ee77bSGregory Herrero * @grxfsiz: Backup of GRXFSIZ register 663d17ee77bSGregory Herrero * @gnptxfsiz: Backup of GNPTXFSIZ register 664d17ee77bSGregory Herrero * @gi2cctl: Backup of GI2CCTL register 66566a36096SVardan Mikayelyan * @glpmcfg: Backup of GLPMCFG register 666d17ee77bSGregory Herrero * @gdfifocfg: Backup of GDFIFOCFG register 6676fb914d7SGrigor Tovmasyan * @pcgcctl: Backup of PCGCCTL register 6686fb914d7SGrigor Tovmasyan * @pcgcctl1: Backup of PCGCCTL1 register 6696fb914d7SGrigor Tovmasyan * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 670d17ee77bSGregory Herrero * @gpwrdn: Backup of GPWRDN register 6716fb914d7SGrigor Tovmasyan * @valid: True if registers values backuped. 672d17ee77bSGregory Herrero */ 673d17ee77bSGregory Herrero struct dwc2_gregs_backup { 674d17ee77bSGregory Herrero u32 gotgctl; 675d17ee77bSGregory Herrero u32 gintmsk; 676d17ee77bSGregory Herrero u32 gahbcfg; 677d17ee77bSGregory Herrero u32 gusbcfg; 678d17ee77bSGregory Herrero u32 grxfsiz; 679d17ee77bSGregory Herrero u32 gnptxfsiz; 680d17ee77bSGregory Herrero u32 gi2cctl; 68166a36096SVardan Mikayelyan u32 glpmcfg; 682d17ee77bSGregory Herrero u32 pcgcctl; 683600a490eSRazmik Karapetyan u32 pcgcctl1; 684d17ee77bSGregory Herrero u32 gdfifocfg; 685d17ee77bSGregory Herrero u32 gpwrdn; 686cc1e204cSMian Yousaf Kaukab bool valid; 687d17ee77bSGregory Herrero }; 688d17ee77bSGregory Herrero 689d17ee77bSGregory Herrero /** 69038beaec6SJohn Youn * struct dwc2_dregs_backup - Holds device registers state before 69138beaec6SJohn Youn * entering partial power down 692d17ee77bSGregory Herrero * @dcfg: Backup of DCFG register 693d17ee77bSGregory Herrero * @dctl: Backup of DCTL register 694d17ee77bSGregory Herrero * @daintmsk: Backup of DAINTMSK register 695d17ee77bSGregory Herrero * @diepmsk: Backup of DIEPMSK register 696d17ee77bSGregory Herrero * @doepmsk: Backup of DOEPMSK register 697d17ee77bSGregory Herrero * @diepctl: Backup of DIEPCTL register 698d17ee77bSGregory Herrero * @dieptsiz: Backup of DIEPTSIZ register 699d17ee77bSGregory Herrero * @diepdma: Backup of DIEPDMA register 700d17ee77bSGregory Herrero * @doepctl: Backup of DOEPCTL register 701d17ee77bSGregory Herrero * @doeptsiz: Backup of DOEPTSIZ register 702d17ee77bSGregory Herrero * @doepdma: Backup of DOEPDMA register 703af7c2bd3SVardan Mikayelyan * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 7046fb914d7SGrigor Tovmasyan * @valid: True if registers values backuped. 705d17ee77bSGregory Herrero */ 706d17ee77bSGregory Herrero struct dwc2_dregs_backup { 707d17ee77bSGregory Herrero u32 dcfg; 708d17ee77bSGregory Herrero u32 dctl; 709d17ee77bSGregory Herrero u32 daintmsk; 710d17ee77bSGregory Herrero u32 diepmsk; 711d17ee77bSGregory Herrero u32 doepmsk; 712d17ee77bSGregory Herrero u32 diepctl[MAX_EPS_CHANNELS]; 713d17ee77bSGregory Herrero u32 dieptsiz[MAX_EPS_CHANNELS]; 714d17ee77bSGregory Herrero u32 diepdma[MAX_EPS_CHANNELS]; 715d17ee77bSGregory Herrero u32 doepctl[MAX_EPS_CHANNELS]; 716d17ee77bSGregory Herrero u32 doeptsiz[MAX_EPS_CHANNELS]; 717d17ee77bSGregory Herrero u32 doepdma[MAX_EPS_CHANNELS]; 718af7c2bd3SVardan Mikayelyan u32 dtxfsiz[MAX_EPS_CHANNELS]; 719cc1e204cSMian Yousaf Kaukab bool valid; 720d17ee77bSGregory Herrero }; 721d17ee77bSGregory Herrero 722d17ee77bSGregory Herrero /** 72338beaec6SJohn Youn * struct dwc2_hregs_backup - Holds host registers state before 72438beaec6SJohn Youn * entering partial power down 725d17ee77bSGregory Herrero * @hcfg: Backup of HCFG register 726d17ee77bSGregory Herrero * @haintmsk: Backup of HAINTMSK register 727d17ee77bSGregory Herrero * @hcintmsk: Backup of HCINTMSK register 7286fb914d7SGrigor Tovmasyan * @hprt0: Backup of HPTR0 register 729d17ee77bSGregory Herrero * @hfir: Backup of HFIR register 73066a36096SVardan Mikayelyan * @hptxfsiz: Backup of HPTXFSIZ register 7316fb914d7SGrigor Tovmasyan * @valid: True if registers values backuped. 732d17ee77bSGregory Herrero */ 733d17ee77bSGregory Herrero struct dwc2_hregs_backup { 734d17ee77bSGregory Herrero u32 hcfg; 735d17ee77bSGregory Herrero u32 haintmsk; 736d17ee77bSGregory Herrero u32 hcintmsk[MAX_EPS_CHANNELS]; 737d17ee77bSGregory Herrero u32 hprt0; 738d17ee77bSGregory Herrero u32 hfir; 73966a36096SVardan Mikayelyan u32 hptxfsiz; 740cc1e204cSMian Yousaf Kaukab bool valid; 741d17ee77bSGregory Herrero }; 742d17ee77bSGregory Herrero 7439f9f09b0SDouglas Anderson /* 7449f9f09b0SDouglas Anderson * Constants related to high speed periodic scheduling 7459f9f09b0SDouglas Anderson * 7469f9f09b0SDouglas Anderson * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a 7479f9f09b0SDouglas Anderson * reservation point of view it's assumed that the schedule goes right back to 7489f9f09b0SDouglas Anderson * the beginning after the end of the schedule. 7499f9f09b0SDouglas Anderson * 7509f9f09b0SDouglas Anderson * What does that mean for scheduling things with a long interval? It means 7519f9f09b0SDouglas Anderson * we'll reserve time for them in every possible microframe that they could 7529f9f09b0SDouglas Anderson * ever be scheduled in. ...but we'll still only actually schedule them as 7539f9f09b0SDouglas Anderson * often as they were requested. 7549f9f09b0SDouglas Anderson * 7559f9f09b0SDouglas Anderson * We keep our schedule in a "bitmap" structure. This simplifies having 7569f9f09b0SDouglas Anderson * to keep track of and merge intervals: we just let the bitmap code do most 7579f9f09b0SDouglas Anderson * of the heavy lifting. In a way scheduling is much like memory allocation. 7589f9f09b0SDouglas Anderson * 7599f9f09b0SDouglas Anderson * We schedule 100us per uframe or 80% of 125us (the maximum amount you're 7609f9f09b0SDouglas Anderson * supposed to schedule for periodic transfers). That's according to spec. 7619f9f09b0SDouglas Anderson * 7629f9f09b0SDouglas Anderson * Note that though we only schedule 80% of each microframe, the bitmap that we 7639f9f09b0SDouglas Anderson * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of 7649f9f09b0SDouglas Anderson * space for each uFrame). 7659f9f09b0SDouglas Anderson * 7669f9f09b0SDouglas Anderson * Requirements: 7679f9f09b0SDouglas Anderson * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1) 7689f9f09b0SDouglas Anderson * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably 7699f9f09b0SDouglas Anderson * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might 7709f9f09b0SDouglas Anderson * be bugs). The 8 comes from the USB spec: number of microframes per frame. 7719f9f09b0SDouglas Anderson */ 7729f9f09b0SDouglas Anderson #define DWC2_US_PER_UFRAME 125 7739f9f09b0SDouglas Anderson #define DWC2_HS_PERIODIC_US_PER_UFRAME 100 7749f9f09b0SDouglas Anderson 7759f9f09b0SDouglas Anderson #define DWC2_HS_SCHEDULE_UFRAMES 8 7769f9f09b0SDouglas Anderson #define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \ 7779f9f09b0SDouglas Anderson DWC2_HS_PERIODIC_US_PER_UFRAME) 7789f9f09b0SDouglas Anderson 7799f9f09b0SDouglas Anderson /* 7809f9f09b0SDouglas Anderson * Constants related to low speed scheduling 7819f9f09b0SDouglas Anderson * 7829f9f09b0SDouglas Anderson * For high speed we schedule every 1us. For low speed that's a bit overkill, 7839f9f09b0SDouglas Anderson * so we make up a unit called a "slice" that's worth 25us. There are 40 7849f9f09b0SDouglas Anderson * slices in a full frame and we can schedule 36 of those (90%) for periodic 7859f9f09b0SDouglas Anderson * transfers. 7869f9f09b0SDouglas Anderson * 7879f9f09b0SDouglas Anderson * Our low speed schedule can be as short as 1 frame or could be longer. When 7889f9f09b0SDouglas Anderson * we only schedule 1 frame it means that we'll need to reserve a time every 7899f9f09b0SDouglas Anderson * frame even for things that only transfer very rarely, so something that runs 7909f9f09b0SDouglas Anderson * every 2048 frames will get time reserved in every frame. Our low speed 7919f9f09b0SDouglas Anderson * schedule can be longer and we'll be able to handle more overlap, but that 7929f9f09b0SDouglas Anderson * will come at increased memory cost and increased time to schedule. 7939f9f09b0SDouglas Anderson * 7949f9f09b0SDouglas Anderson * Note: one other advantage of a short low speed schedule is that if we mess 7959f9f09b0SDouglas Anderson * up and miss scheduling we can jump in and use any of the slots that we 7969f9f09b0SDouglas Anderson * happened to reserve. 7979f9f09b0SDouglas Anderson * 7989f9f09b0SDouglas Anderson * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for 7999f9f09b0SDouglas Anderson * the schedule. There will be one schedule per TT. 8009f9f09b0SDouglas Anderson * 8019f9f09b0SDouglas Anderson * Requirements: 8029f9f09b0SDouglas Anderson * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME. 8039f9f09b0SDouglas Anderson */ 8049f9f09b0SDouglas Anderson #define DWC2_US_PER_SLICE 25 8059f9f09b0SDouglas Anderson #define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE) 8069f9f09b0SDouglas Anderson 8079f9f09b0SDouglas Anderson #define DWC2_ROUND_US_TO_SLICE(us) \ 8089f9f09b0SDouglas Anderson (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \ 8099f9f09b0SDouglas Anderson DWC2_US_PER_SLICE) 8109f9f09b0SDouglas Anderson 8119f9f09b0SDouglas Anderson #define DWC2_LS_PERIODIC_US_PER_FRAME \ 8129f9f09b0SDouglas Anderson 900 8139f9f09b0SDouglas Anderson #define DWC2_LS_PERIODIC_SLICES_PER_FRAME \ 8149f9f09b0SDouglas Anderson (DWC2_LS_PERIODIC_US_PER_FRAME / \ 8159f9f09b0SDouglas Anderson DWC2_US_PER_SLICE) 8169f9f09b0SDouglas Anderson 8179f9f09b0SDouglas Anderson #define DWC2_LS_SCHEDULE_FRAMES 1 8189f9f09b0SDouglas Anderson #define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \ 8199f9f09b0SDouglas Anderson DWC2_LS_PERIODIC_SLICES_PER_FRAME) 8209f9f09b0SDouglas Anderson 821d17ee77bSGregory Herrero /** 822197ba5f4SPaul Zimmerman * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 823197ba5f4SPaul Zimmerman * and periodic schedules 824197ba5f4SPaul Zimmerman * 825941fcce4SDinh Nguyen * These are common for both host and peripheral modes: 826941fcce4SDinh Nguyen * 827197ba5f4SPaul Zimmerman * @dev: The struct device pointer 828197ba5f4SPaul Zimmerman * @regs: Pointer to controller regs 829197ba5f4SPaul Zimmerman * @hw_params: Parameters that were autodetected from the 830197ba5f4SPaul Zimmerman * hardware registers 8316fb914d7SGrigor Tovmasyan * @params: Parameters that define how the core should be configured 832197ba5f4SPaul Zimmerman * @op_state: The operational State, during transitions (a_host=> 833197ba5f4SPaul Zimmerman * a_peripheral and b_device=>b_host) this may not match 834197ba5f4SPaul Zimmerman * the core, but allows the software to determine 835197ba5f4SPaul Zimmerman * transitions 836c0155b9dSKever Yang * @dr_mode: Requested mode of operation, one of following: 837c0155b9dSKever Yang * - USB_DR_MODE_PERIPHERAL 838c0155b9dSKever Yang * - USB_DR_MODE_HOST 839c0155b9dSKever Yang * - USB_DR_MODE_OTG 8406fb914d7SGrigor Tovmasyan * @hcd_enabled: Host mode sub-driver initialization indicator. 8416fb914d7SGrigor Tovmasyan * @gadget_enabled: Peripheral mode sub-driver initialization indicator. 8426fb914d7SGrigor Tovmasyan * @ll_hw_enabled: Status of low-level hardware resources. 84320fe4409SVardan Mikayelyan * @hibernated: True if core is hibernated 844c7c24e7aSArtur Petrosyan * @frame_number: Frame number read from the core. For both device 845c7c24e7aSArtur Petrosyan * and host modes. The value ranges are from 0 846c7c24e7aSArtur Petrosyan * to HFNUM_MAX_FRNUM. 84709a75e85SMarek Szyprowski * @phy: The otg phy transceiver structure for phy control. 84838beaec6SJohn Youn * @uphy: The otg phy transceiver structure for old USB phy 84938beaec6SJohn Youn * control. 85038beaec6SJohn Youn * @plat: The platform specific configuration data. This can be 85138beaec6SJohn Youn * removed once all SoCs support usb transceiver. 85209a75e85SMarek Szyprowski * @supplies: Definition of USB power supplies 853531ef5ebSAmelie Delaunay * @vbus_supply: Regulator supplying vbus. 85409a75e85SMarek Szyprowski * @phyif: PHY interface width 855941fcce4SDinh Nguyen * @lock: Spinlock that protects all the driver data structures 856941fcce4SDinh Nguyen * @priv: Stores a pointer to the struct usb_hcd 857197ba5f4SPaul Zimmerman * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 858197ba5f4SPaul Zimmerman * transfer are in process of being queued 859197ba5f4SPaul Zimmerman * @srp_success: Stores status of SRP request in the case of a FS PHY 860197ba5f4SPaul Zimmerman * with an I2C interface 861197ba5f4SPaul Zimmerman * @wq_otg: Workqueue object used for handling of some interrupts 862197ba5f4SPaul Zimmerman * @wf_otg: Work object for handling Connector ID Status Change 863197ba5f4SPaul Zimmerman * interrupt 864197ba5f4SPaul Zimmerman * @wkp_timer: Timer object for handling Wakeup Detected interrupt 865197ba5f4SPaul Zimmerman * @lx_state: Lx state of connected device 8666fb914d7SGrigor Tovmasyan * @gr_backup: Backup of global registers during suspend 8676fb914d7SGrigor Tovmasyan * @dr_backup: Backup of device registers during suspend 8686fb914d7SGrigor Tovmasyan * @hr_backup: Backup of host registers during suspend 869fe369e18SGevorg Sahakyan * @needs_byte_swap: Specifies whether the opposite endianness. 870941fcce4SDinh Nguyen * 871941fcce4SDinh Nguyen * These are for host mode: 872941fcce4SDinh Nguyen * 873197ba5f4SPaul Zimmerman * @flags: Flags for handling root port state changes 8746fb914d7SGrigor Tovmasyan * @flags.d32: Contain all root port flags 8756fb914d7SGrigor Tovmasyan * @flags.b: Separate root port flags from each other 8766fb914d7SGrigor Tovmasyan * @flags.b.port_connect_status_change: True if root port connect status 8776fb914d7SGrigor Tovmasyan * changed 8786fb914d7SGrigor Tovmasyan * @flags.b.port_connect_status: True if device connected to root port 8796fb914d7SGrigor Tovmasyan * @flags.b.port_reset_change: True if root port reset status changed 8806fb914d7SGrigor Tovmasyan * @flags.b.port_enable_change: True if root port enable status changed 8816fb914d7SGrigor Tovmasyan * @flags.b.port_suspend_change: True if root port suspend status changed 8826fb914d7SGrigor Tovmasyan * @flags.b.port_over_current_change: True if root port over current state 8836fb914d7SGrigor Tovmasyan * changed. 8846fb914d7SGrigor Tovmasyan * @flags.b.port_l1_change: True if root port l1 status changed 8856fb914d7SGrigor Tovmasyan * @flags.b.reserved: Reserved bits of root port register 886197ba5f4SPaul Zimmerman * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 887197ba5f4SPaul Zimmerman * Transfers associated with these QHs are not currently 888197ba5f4SPaul Zimmerman * assigned to a host channel. 889197ba5f4SPaul Zimmerman * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 890197ba5f4SPaul Zimmerman * Transfers associated with these QHs are currently 891197ba5f4SPaul Zimmerman * assigned to a host channel. 892197ba5f4SPaul Zimmerman * @non_periodic_qh_ptr: Pointer to next QH to process in the active 893197ba5f4SPaul Zimmerman * non-periodic schedule 8946fb914d7SGrigor Tovmasyan * @non_periodic_sched_waiting: Waiting QHs in the non-periodic schedule. 8956fb914d7SGrigor Tovmasyan * Transfers associated with these QHs are not currently 8966fb914d7SGrigor Tovmasyan * assigned to a host channel. 897197ba5f4SPaul Zimmerman * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 898197ba5f4SPaul Zimmerman * list of QHs for periodic transfers that are _not_ 899197ba5f4SPaul Zimmerman * scheduled for the next frame. Each QH in the list has an 900197ba5f4SPaul Zimmerman * interval counter that determines when it needs to be 901197ba5f4SPaul Zimmerman * scheduled for execution. This scheduling mechanism 902197ba5f4SPaul Zimmerman * allows only a simple calculation for periodic bandwidth 903197ba5f4SPaul Zimmerman * used (i.e. must assume that all periodic transfers may 904197ba5f4SPaul Zimmerman * need to execute in the same frame). However, it greatly 905197ba5f4SPaul Zimmerman * simplifies scheduling and should be sufficient for the 906197ba5f4SPaul Zimmerman * vast majority of OTG hosts, which need to connect to a 907197ba5f4SPaul Zimmerman * small number of peripherals at one time. Items move from 908197ba5f4SPaul Zimmerman * this list to periodic_sched_ready when the QH interval 909197ba5f4SPaul Zimmerman * counter is 0 at SOF. 910197ba5f4SPaul Zimmerman * @periodic_sched_ready: List of periodic QHs that are ready for execution in 911197ba5f4SPaul Zimmerman * the next frame, but have not yet been assigned to host 912197ba5f4SPaul Zimmerman * channels. Items move from this list to 913197ba5f4SPaul Zimmerman * periodic_sched_assigned as host channels become 914197ba5f4SPaul Zimmerman * available during the current frame. 915197ba5f4SPaul Zimmerman * @periodic_sched_assigned: List of periodic QHs to be executed in the next 916197ba5f4SPaul Zimmerman * frame that are assigned to host channels. Items move 917197ba5f4SPaul Zimmerman * from this list to periodic_sched_queued as the 918197ba5f4SPaul Zimmerman * transactions for the QH are queued to the DWC_otg 919197ba5f4SPaul Zimmerman * controller. 920197ba5f4SPaul Zimmerman * @periodic_sched_queued: List of periodic QHs that have been queued for 921197ba5f4SPaul Zimmerman * execution. Items move from this list to either 922197ba5f4SPaul Zimmerman * periodic_sched_inactive or periodic_sched_ready when the 923197ba5f4SPaul Zimmerman * channel associated with the transfer is released. If the 924197ba5f4SPaul Zimmerman * interval for the QH is 1, the item moves to 925197ba5f4SPaul Zimmerman * periodic_sched_ready because it must be rescheduled for 926197ba5f4SPaul Zimmerman * the next frame. Otherwise, the item moves to 927197ba5f4SPaul Zimmerman * periodic_sched_inactive. 928c9c8ac01SDouglas Anderson * @split_order: List keeping track of channels doing splits, in order. 929197ba5f4SPaul Zimmerman * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 930197ba5f4SPaul Zimmerman * This value is in microseconds per (micro)frame. The 931197ba5f4SPaul Zimmerman * assumption is that all periodic transfers may occur in 932197ba5f4SPaul Zimmerman * the same (micro)frame. 9339f9f09b0SDouglas Anderson * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the 9349f9f09b0SDouglas Anderson * host is in high speed mode; low speed schedules are 9359f9f09b0SDouglas Anderson * stored elsewhere since we need one per TT. 936197ba5f4SPaul Zimmerman * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 937197ba5f4SPaul Zimmerman * SOF enable/disable. 938197ba5f4SPaul Zimmerman * @free_hc_list: Free host channels in the controller. This is a list of 939197ba5f4SPaul Zimmerman * struct dwc2_host_chan items. 940197ba5f4SPaul Zimmerman * @periodic_channels: Number of host channels assigned to periodic transfers. 941197ba5f4SPaul Zimmerman * Currently assuming that there is a dedicated host 942197ba5f4SPaul Zimmerman * channel for each periodic transaction and at least one 943197ba5f4SPaul Zimmerman * host channel is available for non-periodic transactions. 944197ba5f4SPaul Zimmerman * @non_periodic_channels: Number of host channels assigned to non-periodic 945197ba5f4SPaul Zimmerman * transfers 9466fb914d7SGrigor Tovmasyan * @available_host_channels: Number of host channels available for the 9476fb914d7SGrigor Tovmasyan * microframe scheduler to use 948197ba5f4SPaul Zimmerman * @hc_ptr_array: Array of pointers to the host channel descriptors. 949197ba5f4SPaul Zimmerman * Allows accessing a host channel descriptor given the 950197ba5f4SPaul Zimmerman * host channel number. This is useful in interrupt 951197ba5f4SPaul Zimmerman * handlers. 952197ba5f4SPaul Zimmerman * @status_buf: Buffer used for data received during the status phase of 953197ba5f4SPaul Zimmerman * a control transfer. 954197ba5f4SPaul Zimmerman * @status_buf_dma: DMA address for status_buf 955197ba5f4SPaul Zimmerman * @start_work: Delayed work for handling host A-cable connection 956197ba5f4SPaul Zimmerman * @reset_work: Delayed work for handling a port reset 957197ba5f4SPaul Zimmerman * @otg_port: OTG port number 958197ba5f4SPaul Zimmerman * @frame_list: Frame list 959197ba5f4SPaul Zimmerman * @frame_list_dma: Frame list DMA address 96095105a99SGregory Herrero * @frame_list_sz: Frame list size 9613b5fcc9aSGregory Herrero * @desc_gen_cache: Kmem cache for generic descriptors 9623b5fcc9aSGregory Herrero * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors 963af424a41SWilliam Wu * @unaligned_cache: Kmem cache for DMA mode to handle non-aligned buf 964941fcce4SDinh Nguyen * 965941fcce4SDinh Nguyen * These are for peripheral mode: 966941fcce4SDinh Nguyen * 967941fcce4SDinh Nguyen * @driver: USB gadget driver 968941fcce4SDinh Nguyen * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 969941fcce4SDinh Nguyen * @num_of_eps: Number of available EPs (excluding EP0) 970941fcce4SDinh Nguyen * @debug_root: Root directrory for debugfs. 971941fcce4SDinh Nguyen * @ep0_reply: Request used for ep0 reply. 972941fcce4SDinh Nguyen * @ep0_buff: Buffer for EP0 reply data, if needed. 973941fcce4SDinh Nguyen * @ctrl_buff: Buffer for EP0 control requests. 974941fcce4SDinh Nguyen * @ctrl_req: Request for EP0 control packets. 975fe0b94abSMian Yousaf Kaukab * @ep0_state: EP0 control transfers state 9769e14d0a5SGregory Herrero * @test_mode: USB test mode requested by the host 977fa389a6dSVardan Mikayelyan * @remote_wakeup_allowed: True if device is allowed to wake-up host by 978fa389a6dSVardan Mikayelyan * remote-wakeup signalling 9790f6b80c0SVahram Aharonyan * @setup_desc_dma: EP0 setup stage desc chain DMA address 9800f6b80c0SVahram Aharonyan * @setup_desc: EP0 setup stage desc chain pointer 9810f6b80c0SVahram Aharonyan * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address 9820f6b80c0SVahram Aharonyan * @ctrl_in_desc: EP0 IN data phase desc chain pointer 9830f6b80c0SVahram Aharonyan * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address 9840f6b80c0SVahram Aharonyan * @ctrl_out_desc: EP0 OUT data phase desc chain pointer 9856fb914d7SGrigor Tovmasyan * @irq: Interrupt request line number 9866fb914d7SGrigor Tovmasyan * @clk: Pointer to otg clock 9876fb914d7SGrigor Tovmasyan * @reset: Pointer to dwc2 reset controller 9886fb914d7SGrigor Tovmasyan * @reset_ecc: Pointer to dwc2 optional reset controller in Stratix10. 9896fb914d7SGrigor Tovmasyan * @regset: A pointer to a struct debugfs_regset32, which contains 9906fb914d7SGrigor Tovmasyan * a pointer to an array of register definitions, the 9916fb914d7SGrigor Tovmasyan * array size and the base address where the register bank 9926fb914d7SGrigor Tovmasyan * is to be found. 9936fb914d7SGrigor Tovmasyan * @bus_suspended: True if bus is suspended 9946fb914d7SGrigor Tovmasyan * @last_frame_num: Number of last frame. Range from 0 to 32768 9956fb914d7SGrigor Tovmasyan * @frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is 9966fb914d7SGrigor Tovmasyan * defined, for missed SOFs tracking. Array holds that 9976fb914d7SGrigor Tovmasyan * frame numbers, which not equal to last_frame_num +1 9986fb914d7SGrigor Tovmasyan * @last_frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is 9996fb914d7SGrigor Tovmasyan * defined, for missed SOFs tracking. 10006fb914d7SGrigor Tovmasyan * If current_frame_number != last_frame_num+1 10016fb914d7SGrigor Tovmasyan * then last_frame_num added to this array 10026fb914d7SGrigor Tovmasyan * @frame_num_idx: Actual size of frame_num_array and last_frame_num_array 10036fb914d7SGrigor Tovmasyan * @dumped_frame_num_array: 1 - if missed SOFs frame numbers dumbed 10046fb914d7SGrigor Tovmasyan * 0 - if missed SOFs frame numbers not dumbed 10056fb914d7SGrigor Tovmasyan * @fifo_mem: Total internal RAM for FIFOs (bytes) 10066fb914d7SGrigor Tovmasyan * @fifo_map: Each bit intend for concrete fifo. If that bit is set, 10076fb914d7SGrigor Tovmasyan * then that fifo is used 10086fb914d7SGrigor Tovmasyan * @gadget: Represents a usb slave device 10096fb914d7SGrigor Tovmasyan * @connected: Used in slave mode. True if device connected with host 10106fb914d7SGrigor Tovmasyan * @eps_in: The IN endpoints being supplied to the gadget framework 10116fb914d7SGrigor Tovmasyan * @eps_out: The OUT endpoints being supplied to the gadget framework 10126fb914d7SGrigor Tovmasyan * @new_connection: Used in host mode. True if there are new connected 10136fb914d7SGrigor Tovmasyan * device 10146fb914d7SGrigor Tovmasyan * @enabled: Indicates the enabling state of controller 10156fb914d7SGrigor Tovmasyan * 1016197ba5f4SPaul Zimmerman */ 1017197ba5f4SPaul Zimmerman struct dwc2_hsotg { 1018197ba5f4SPaul Zimmerman struct device *dev; 1019197ba5f4SPaul Zimmerman void __iomem *regs; 1020197ba5f4SPaul Zimmerman /** Params detected from hardware */ 1021197ba5f4SPaul Zimmerman struct dwc2_hw_params hw_params; 1022197ba5f4SPaul Zimmerman /** Params to actually use */ 1023bea8e86cSJohn Youn struct dwc2_core_params params; 1024197ba5f4SPaul Zimmerman enum usb_otg_state op_state; 1025c0155b9dSKever Yang enum usb_dr_mode dr_mode; 1026e39af88fSMarek Szyprowski unsigned int hcd_enabled:1; 1027e39af88fSMarek Szyprowski unsigned int gadget_enabled:1; 102809a75e85SMarek Szyprowski unsigned int ll_hw_enabled:1; 102920fe4409SVardan Mikayelyan unsigned int hibernated:1; 1030c7c24e7aSArtur Petrosyan u16 frame_number; 1031197ba5f4SPaul Zimmerman 1032941fcce4SDinh Nguyen struct phy *phy; 1033941fcce4SDinh Nguyen struct usb_phy *uphy; 103409a75e85SMarek Szyprowski struct dwc2_hsotg_plat *plat; 1035b98866c2SJohn Youn struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES]; 1036531ef5ebSAmelie Delaunay struct regulator *vbus_supply; 103709a75e85SMarek Szyprowski u32 phyif; 1038941fcce4SDinh Nguyen 1039941fcce4SDinh Nguyen spinlock_t lock; 1040941fcce4SDinh Nguyen void *priv; 1041941fcce4SDinh Nguyen int irq; 1042941fcce4SDinh Nguyen struct clk *clk; 104383f8da56SDinh Nguyen struct reset_control *reset; 1044f2830ad4SDinh Nguyen struct reset_control *reset_ecc; 1045941fcce4SDinh Nguyen 1046197ba5f4SPaul Zimmerman unsigned int queuing_high_bandwidth:1; 1047197ba5f4SPaul Zimmerman unsigned int srp_success:1; 1048197ba5f4SPaul Zimmerman 1049197ba5f4SPaul Zimmerman struct workqueue_struct *wq_otg; 1050197ba5f4SPaul Zimmerman struct work_struct wf_otg; 1051197ba5f4SPaul Zimmerman struct timer_list wkp_timer; 1052197ba5f4SPaul Zimmerman enum dwc2_lx_state lx_state; 1053cc1e204cSMian Yousaf Kaukab struct dwc2_gregs_backup gr_backup; 1054cc1e204cSMian Yousaf Kaukab struct dwc2_dregs_backup dr_backup; 1055cc1e204cSMian Yousaf Kaukab struct dwc2_hregs_backup hr_backup; 1056197ba5f4SPaul Zimmerman 1057941fcce4SDinh Nguyen struct dentry *debug_root; 1058563cf017SMian Yousaf Kaukab struct debugfs_regset32 *regset; 1059fe369e18SGevorg Sahakyan bool needs_byte_swap; 1060941fcce4SDinh Nguyen 1061941fcce4SDinh Nguyen /* DWC OTG HW Release versions */ 1062941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_71a 0x4f54271a 10635295322aSArtur Petrosyan #define DWC2_CORE_REV_2_72a 0x4f54272a 10646f80b6deSSevak Arakelyan #define DWC2_CORE_REV_2_80a 0x4f54280a 1065941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_90a 0x4f54290a 1066e1f411d1SSevak Arakelyan #define DWC2_CORE_REV_2_91a 0x4f54291a 1067941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_92a 0x4f54292a 1068941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_94a 0x4f54294a 1069941fcce4SDinh Nguyen #define DWC2_CORE_REV_3_00a 0x4f54300a 1070fef6bc37SJohn Youn #define DWC2_CORE_REV_3_10a 0x4f54310a 10715295322aSArtur Petrosyan #define DWC2_CORE_REV_4_00a 0x4f54400a 10721e6b98ebSVardan Mikayelyan #define DWC2_FS_IOT_REV_1_00a 0x5531100a 10731e6b98ebSVardan Mikayelyan #define DWC2_HS_IOT_REV_1_00a 0x5532100a 1074941fcce4SDinh Nguyen 1075d14ccabaSGevorg Sahakyan /* DWC OTG HW Core ID */ 1076d14ccabaSGevorg Sahakyan #define DWC2_OTG_ID 0x4f540000 1077d14ccabaSGevorg Sahakyan #define DWC2_FS_IOT_ID 0x55310000 1078d14ccabaSGevorg Sahakyan #define DWC2_HS_IOT_ID 0x55320000 1079d14ccabaSGevorg Sahakyan 1080941fcce4SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1081197ba5f4SPaul Zimmerman union dwc2_hcd_internal_flags { 1082197ba5f4SPaul Zimmerman u32 d32; 1083197ba5f4SPaul Zimmerman struct { 1084197ba5f4SPaul Zimmerman unsigned port_connect_status_change:1; 1085197ba5f4SPaul Zimmerman unsigned port_connect_status:1; 1086197ba5f4SPaul Zimmerman unsigned port_reset_change:1; 1087197ba5f4SPaul Zimmerman unsigned port_enable_change:1; 1088197ba5f4SPaul Zimmerman unsigned port_suspend_change:1; 1089197ba5f4SPaul Zimmerman unsigned port_over_current_change:1; 1090197ba5f4SPaul Zimmerman unsigned port_l1_change:1; 1091fd4850cfSCharles Manning unsigned reserved:25; 1092197ba5f4SPaul Zimmerman } b; 1093197ba5f4SPaul Zimmerman } flags; 1094197ba5f4SPaul Zimmerman 1095197ba5f4SPaul Zimmerman struct list_head non_periodic_sched_inactive; 109638d2b5fbSDouglas Anderson struct list_head non_periodic_sched_waiting; 1097197ba5f4SPaul Zimmerman struct list_head non_periodic_sched_active; 1098197ba5f4SPaul Zimmerman struct list_head *non_periodic_qh_ptr; 1099197ba5f4SPaul Zimmerman struct list_head periodic_sched_inactive; 1100197ba5f4SPaul Zimmerman struct list_head periodic_sched_ready; 1101197ba5f4SPaul Zimmerman struct list_head periodic_sched_assigned; 1102197ba5f4SPaul Zimmerman struct list_head periodic_sched_queued; 1103c9c8ac01SDouglas Anderson struct list_head split_order; 1104197ba5f4SPaul Zimmerman u16 periodic_usecs; 11059f9f09b0SDouglas Anderson unsigned long hs_periodic_bitmap[ 11069f9f09b0SDouglas Anderson DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)]; 1107197ba5f4SPaul Zimmerman u16 periodic_qh_count; 1108734643dfSGregory Herrero bool bus_suspended; 1109fbb9e22bSMian Yousaf Kaukab bool new_connection; 1110197ba5f4SPaul Zimmerman 1111483bb254SDouglas Anderson u16 last_frame_num; 1112483bb254SDouglas Anderson 1113197ba5f4SPaul Zimmerman #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 1114197ba5f4SPaul Zimmerman #define FRAME_NUM_ARRAY_SIZE 1000 1115197ba5f4SPaul Zimmerman u16 *frame_num_array; 1116197ba5f4SPaul Zimmerman u16 *last_frame_num_array; 1117197ba5f4SPaul Zimmerman int frame_num_idx; 1118197ba5f4SPaul Zimmerman int dumped_frame_num_array; 1119197ba5f4SPaul Zimmerman #endif 1120197ba5f4SPaul Zimmerman 1121197ba5f4SPaul Zimmerman struct list_head free_hc_list; 1122197ba5f4SPaul Zimmerman int periodic_channels; 1123197ba5f4SPaul Zimmerman int non_periodic_channels; 1124197ba5f4SPaul Zimmerman int available_host_channels; 1125197ba5f4SPaul Zimmerman struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 1126197ba5f4SPaul Zimmerman u8 *status_buf; 1127197ba5f4SPaul Zimmerman dma_addr_t status_buf_dma; 1128197ba5f4SPaul Zimmerman #define DWC2_HCD_STATUS_BUF_SIZE 64 1129197ba5f4SPaul Zimmerman 1130197ba5f4SPaul Zimmerman struct delayed_work start_work; 1131197ba5f4SPaul Zimmerman struct delayed_work reset_work; 1132197ba5f4SPaul Zimmerman u8 otg_port; 1133197ba5f4SPaul Zimmerman u32 *frame_list; 1134197ba5f4SPaul Zimmerman dma_addr_t frame_list_dma; 113595105a99SGregory Herrero u32 frame_list_sz; 11363b5fcc9aSGregory Herrero struct kmem_cache *desc_gen_cache; 11373b5fcc9aSGregory Herrero struct kmem_cache *desc_hsisoc_cache; 1138af424a41SWilliam Wu struct kmem_cache *unaligned_cache; 1139af424a41SWilliam Wu #define DWC2_KMEM_UNALIGNED_BUF_SIZE 1024 1140197ba5f4SPaul Zimmerman 1141941fcce4SDinh Nguyen #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ 1142941fcce4SDinh Nguyen 1143b98866c2SJohn Youn #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1144b98866c2SJohn Youn IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1145941fcce4SDinh Nguyen /* Gadget structures */ 1146941fcce4SDinh Nguyen struct usb_gadget_driver *driver; 1147941fcce4SDinh Nguyen int fifo_mem; 1148941fcce4SDinh Nguyen unsigned int dedicated_fifos:1; 1149941fcce4SDinh Nguyen unsigned char num_of_eps; 1150941fcce4SDinh Nguyen u32 fifo_map; 1151941fcce4SDinh Nguyen 1152941fcce4SDinh Nguyen struct usb_request *ep0_reply; 1153941fcce4SDinh Nguyen struct usb_request *ctrl_req; 11543f95001dSMian Yousaf Kaukab void *ep0_buff; 11553f95001dSMian Yousaf Kaukab void *ctrl_buff; 1156fe0b94abSMian Yousaf Kaukab enum dwc2_ep0_state ep0_state; 11579e14d0a5SGregory Herrero u8 test_mode; 1158941fcce4SDinh Nguyen 11590f6b80c0SVahram Aharonyan dma_addr_t setup_desc_dma[2]; 11600f6b80c0SVahram Aharonyan struct dwc2_dma_desc *setup_desc[2]; 11610f6b80c0SVahram Aharonyan dma_addr_t ctrl_in_desc_dma; 11620f6b80c0SVahram Aharonyan struct dwc2_dma_desc *ctrl_in_desc; 11630f6b80c0SVahram Aharonyan dma_addr_t ctrl_out_desc_dma; 11640f6b80c0SVahram Aharonyan struct dwc2_dma_desc *ctrl_out_desc; 11650f6b80c0SVahram Aharonyan 1166941fcce4SDinh Nguyen struct usb_gadget gadget; 1167dc6e69e6SMarek Szyprowski unsigned int enabled:1; 11684ace06e8SMarek Szyprowski unsigned int connected:1; 1169fa389a6dSVardan Mikayelyan unsigned int remote_wakeup_allowed:1; 11701f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS]; 11711f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS]; 1172941fcce4SDinh Nguyen #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 1173197ba5f4SPaul Zimmerman }; 1174197ba5f4SPaul Zimmerman 11750f548098SGevorg Sahakyan /* Normal architectures just use readl/write */ 1176f25c42b8SGevorg Sahakyan static inline u32 dwc2_readl(struct dwc2_hsotg *hsotg, u32 offset) 11770f548098SGevorg Sahakyan { 1178fe369e18SGevorg Sahakyan u32 val; 1179fe369e18SGevorg Sahakyan 1180fe369e18SGevorg Sahakyan val = readl(hsotg->regs + offset); 1181fe369e18SGevorg Sahakyan if (hsotg->needs_byte_swap) 1182fe369e18SGevorg Sahakyan return swab32(val); 1183fe369e18SGevorg Sahakyan else 1184fe369e18SGevorg Sahakyan return val; 11850f548098SGevorg Sahakyan } 11860f548098SGevorg Sahakyan 1187f25c42b8SGevorg Sahakyan static inline void dwc2_writel(struct dwc2_hsotg *hsotg, u32 value, u32 offset) 11880f548098SGevorg Sahakyan { 1189fe369e18SGevorg Sahakyan if (hsotg->needs_byte_swap) 1190fe369e18SGevorg Sahakyan writel(swab32(value), hsotg->regs + offset); 1191fe369e18SGevorg Sahakyan else 1192f25c42b8SGevorg Sahakyan writel(value, hsotg->regs + offset); 11930f548098SGevorg Sahakyan 11940f548098SGevorg Sahakyan #ifdef DWC2_LOG_WRITES 1195f25c42b8SGevorg Sahakyan pr_info("info:: wrote %08x to %p\n", value, hsotg->regs + offset); 11960f548098SGevorg Sahakyan #endif 11970f548098SGevorg Sahakyan } 1198342ccce1SGevorg Sahakyan 1199342ccce1SGevorg Sahakyan static inline void dwc2_readl_rep(struct dwc2_hsotg *hsotg, u32 offset, 1200342ccce1SGevorg Sahakyan void *buffer, unsigned int count) 1201342ccce1SGevorg Sahakyan { 1202342ccce1SGevorg Sahakyan if (count) { 1203342ccce1SGevorg Sahakyan u32 *buf = buffer; 1204342ccce1SGevorg Sahakyan 1205342ccce1SGevorg Sahakyan do { 1206342ccce1SGevorg Sahakyan u32 x = dwc2_readl(hsotg, offset); 1207342ccce1SGevorg Sahakyan *buf++ = x; 1208342ccce1SGevorg Sahakyan } while (--count); 1209342ccce1SGevorg Sahakyan } 1210342ccce1SGevorg Sahakyan } 1211342ccce1SGevorg Sahakyan 1212342ccce1SGevorg Sahakyan static inline void dwc2_writel_rep(struct dwc2_hsotg *hsotg, u32 offset, 1213342ccce1SGevorg Sahakyan const void *buffer, unsigned int count) 1214342ccce1SGevorg Sahakyan { 1215342ccce1SGevorg Sahakyan if (count) { 1216342ccce1SGevorg Sahakyan const u32 *buf = buffer; 1217342ccce1SGevorg Sahakyan 1218342ccce1SGevorg Sahakyan do { 1219342ccce1SGevorg Sahakyan dwc2_writel(hsotg, *buf++, offset); 1220342ccce1SGevorg Sahakyan } while (--count); 1221342ccce1SGevorg Sahakyan } 1222342ccce1SGevorg Sahakyan } 12230f548098SGevorg Sahakyan 1224197ba5f4SPaul Zimmerman /* Reasons for halting a host channel */ 1225197ba5f4SPaul Zimmerman enum dwc2_halt_status { 1226197ba5f4SPaul Zimmerman DWC2_HC_XFER_NO_HALT_STATUS, 1227197ba5f4SPaul Zimmerman DWC2_HC_XFER_COMPLETE, 1228197ba5f4SPaul Zimmerman DWC2_HC_XFER_URB_COMPLETE, 1229197ba5f4SPaul Zimmerman DWC2_HC_XFER_ACK, 1230197ba5f4SPaul Zimmerman DWC2_HC_XFER_NAK, 1231197ba5f4SPaul Zimmerman DWC2_HC_XFER_NYET, 1232197ba5f4SPaul Zimmerman DWC2_HC_XFER_STALL, 1233197ba5f4SPaul Zimmerman DWC2_HC_XFER_XACT_ERR, 1234197ba5f4SPaul Zimmerman DWC2_HC_XFER_FRAME_OVERRUN, 1235197ba5f4SPaul Zimmerman DWC2_HC_XFER_BABBLE_ERR, 1236197ba5f4SPaul Zimmerman DWC2_HC_XFER_DATA_TOGGLE_ERR, 1237197ba5f4SPaul Zimmerman DWC2_HC_XFER_AHB_ERR, 1238197ba5f4SPaul Zimmerman DWC2_HC_XFER_PERIODIC_INCOMPLETE, 1239197ba5f4SPaul Zimmerman DWC2_HC_XFER_URB_DEQUEUE, 1240197ba5f4SPaul Zimmerman }; 1241197ba5f4SPaul Zimmerman 12421e6b98ebSVardan Mikayelyan /* Core version information */ 12431e6b98ebSVardan Mikayelyan static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg) 12441e6b98ebSVardan Mikayelyan { 12451e6b98ebSVardan Mikayelyan return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000; 12461e6b98ebSVardan Mikayelyan } 12471e6b98ebSVardan Mikayelyan 12481e6b98ebSVardan Mikayelyan static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg) 12491e6b98ebSVardan Mikayelyan { 12501e6b98ebSVardan Mikayelyan return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000; 12511e6b98ebSVardan Mikayelyan } 12521e6b98ebSVardan Mikayelyan 12531e6b98ebSVardan Mikayelyan static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg) 12541e6b98ebSVardan Mikayelyan { 12551e6b98ebSVardan Mikayelyan return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000; 12561e6b98ebSVardan Mikayelyan } 12571e6b98ebSVardan Mikayelyan 1258197ba5f4SPaul Zimmerman /* 1259197ba5f4SPaul Zimmerman * The following functions support initialization of the core driver component 1260197ba5f4SPaul Zimmerman * and the DWC_otg controller 1261197ba5f4SPaul Zimmerman */ 12626e6360b6SJohn Stultz int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait); 126341ba9b9bSVardan Mikayelyan int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg); 126441ba9b9bSVardan Mikayelyan int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, bool restore); 1265624815ceSVardan Mikayelyan int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host); 1266624815ceSVardan Mikayelyan int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup, 1267624815ceSVardan Mikayelyan int reset, int is_host); 1268197ba5f4SPaul Zimmerman 126913b1f8e2SVardan Mikayelyan void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host); 127009c96980SJohn Youn void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg); 127109c96980SJohn Youn 12729da51974SJohn Youn bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 1273197ba5f4SPaul Zimmerman 1274197ba5f4SPaul Zimmerman /* 1275197ba5f4SPaul Zimmerman * Common core Functions. 1276197ba5f4SPaul Zimmerman * The following functions support managing the DWC_otg controller in either 1277197ba5f4SPaul Zimmerman * device or host mode. 1278197ba5f4SPaul Zimmerman */ 12799da51974SJohn Youn void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 12809da51974SJohn Youn void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 12819da51974SJohn Youn void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 1282197ba5f4SPaul Zimmerman 12839da51974SJohn Youn void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 12849da51974SJohn Youn void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 1285197ba5f4SPaul Zimmerman 128694d2666cSVardan Mikayelyan void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup, 128794d2666cSVardan Mikayelyan int is_host); 1288c5c403dcSVardan Mikayelyan int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg); 1289c5c403dcSVardan Mikayelyan int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg); 129094d2666cSVardan Mikayelyan 129166e77a24SRazmik Karapetyan void dwc2_enable_acg(struct dwc2_hsotg *hsotg); 129266e77a24SRazmik Karapetyan 1293197ba5f4SPaul Zimmerman /* This function should be called on every hardware interrupt. */ 12949da51974SJohn Youn irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 1295197ba5f4SPaul Zimmerman 1296323230efSJohn Youn /* The device ID match table */ 1297323230efSJohn Youn extern const struct of_device_id dwc2_of_match_table[]; 1298323230efSJohn Youn 12999da51974SJohn Youn int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg); 13009da51974SJohn Youn int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg); 1301ecb176c6SMian Yousaf Kaukab 130279d6b8c5SSevak Arakelyan /* Common polling functions */ 130379d6b8c5SSevak Arakelyan int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit, 130479d6b8c5SSevak Arakelyan u32 timeout); 130579d6b8c5SSevak Arakelyan int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit, 130679d6b8c5SSevak Arakelyan u32 timeout); 1307334bbd4eSJohn Youn /* Parameters */ 1308c1d286cfSJohn Youn int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); 1309334bbd4eSJohn Youn int dwc2_init_params(struct dwc2_hsotg *hsotg); 1310334bbd4eSJohn Youn 1311197ba5f4SPaul Zimmerman /* 13126bea9620SJohn Youn * The following functions check the controller's OTG operation mode 13136bea9620SJohn Youn * capability (GHWCFG2.OTG_MODE). 13146bea9620SJohn Youn * 13156bea9620SJohn Youn * These functions can be used before the internal hsotg->hw_params 13166bea9620SJohn Youn * are read in and cached so they always read directly from the 13176bea9620SJohn Youn * GHWCFG2 register. 13186bea9620SJohn Youn */ 13199da51974SJohn Youn unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg); 13206bea9620SJohn Youn bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg); 13216bea9620SJohn Youn bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg); 13226bea9620SJohn Youn bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg); 13236bea9620SJohn Youn 13246bea9620SJohn Youn /* 13251696d5abSJohn Youn * Returns the mode of operation, host or device 13261696d5abSJohn Youn */ 13271696d5abSJohn Youn static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) 13281696d5abSJohn Youn { 1329f25c42b8SGevorg Sahakyan return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) != 0; 13301696d5abSJohn Youn } 13319da51974SJohn Youn 13321696d5abSJohn Youn static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) 13331696d5abSJohn Youn { 1334f25c42b8SGevorg Sahakyan return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) == 0; 13351696d5abSJohn Youn } 13361696d5abSJohn Youn 13371696d5abSJohn Youn /* 1338197ba5f4SPaul Zimmerman * Dump core registers and SPRAM 1339197ba5f4SPaul Zimmerman */ 13409da51974SJohn Youn void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 13419da51974SJohn Youn void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 13429da51974SJohn Youn void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 1343197ba5f4SPaul Zimmerman 1344117777b2SDinh Nguyen /* Gadget defines */ 1345b98866c2SJohn Youn #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1346b98866c2SJohn Youn IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 13479da51974SJohn Youn int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg); 13489da51974SJohn Youn int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2); 13499da51974SJohn Youn int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2); 1350f3768997SVardan Mikayelyan int dwc2_gadget_init(struct dwc2_hsotg *hsotg); 13519da51974SJohn Youn void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1352643cc4deSGregory Herrero bool reset); 13539da51974SJohn Youn void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg); 13549da51974SJohn Youn void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2); 13559da51974SJohn Youn int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode); 1356f81f46e1SGregory Herrero #define dwc2_is_device_connected(hsotg) (hsotg->connected) 135758e52ff6SJohn Youn int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg); 13589a5d2816SVardan Mikayelyan int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup); 1359c5c403dcSVardan Mikayelyan int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg); 1360c5c403dcSVardan Mikayelyan int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, 1361c5c403dcSVardan Mikayelyan int rem_wakeup, int reset); 1362c138ecfaSSevak Arakelyan int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg); 1363c138ecfaSSevak Arakelyan int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg); 1364c138ecfaSSevak Arakelyan int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg); 136521b03405SSevak Arakelyan void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg); 1366117777b2SDinh Nguyen #else 13671f91b4ccSFelipe Balbi static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2) 1368117777b2SDinh Nguyen { return 0; } 13691f91b4ccSFelipe Balbi static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2) 1370117777b2SDinh Nguyen { return 0; } 13711f91b4ccSFelipe Balbi static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2) 1372117777b2SDinh Nguyen { return 0; } 1373f3768997SVardan Mikayelyan static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg) 1374117777b2SDinh Nguyen { return 0; } 13751f91b4ccSFelipe Balbi static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1376643cc4deSGregory Herrero bool reset) {} 13771f91b4ccSFelipe Balbi static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} 13781f91b4ccSFelipe Balbi static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} 13791f91b4ccSFelipe Balbi static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, 1380f91eea44SMian Yousaf Kaukab int testmode) 1381f91eea44SMian Yousaf Kaukab { return 0; } 1382f81f46e1SGregory Herrero #define dwc2_is_device_connected(hsotg) (0) 138358e52ff6SJohn Youn static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) 138458e52ff6SJohn Youn { return 0; } 13859a5d2816SVardan Mikayelyan static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, 13869a5d2816SVardan Mikayelyan int remote_wakeup) 138758e52ff6SJohn Youn { return 0; } 1388c5c403dcSVardan Mikayelyan static inline int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg) 1389c5c403dcSVardan Mikayelyan { return 0; } 1390c5c403dcSVardan Mikayelyan static inline int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, 1391c5c403dcSVardan Mikayelyan int rem_wakeup, int reset) 1392c5c403dcSVardan Mikayelyan { return 0; } 1393c138ecfaSSevak Arakelyan static inline int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg) 1394c138ecfaSSevak Arakelyan { return 0; } 1395c138ecfaSSevak Arakelyan static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) 1396c138ecfaSSevak Arakelyan { return 0; } 1397c138ecfaSSevak Arakelyan static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg) 1398c138ecfaSSevak Arakelyan { return 0; } 139921b03405SSevak Arakelyan static inline void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) {} 1400117777b2SDinh Nguyen #endif 1401117777b2SDinh Nguyen 1402117777b2SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 14039da51974SJohn Youn int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 14049da51974SJohn Youn int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us); 14059da51974SJohn Youn void dwc2_hcd_connect(struct dwc2_hsotg *hsotg); 14069da51974SJohn Youn void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force); 14079da51974SJohn Youn void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 140865c9c4c6SVardan Mikayelyan int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup); 140958e52ff6SJohn Youn int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg); 141058e52ff6SJohn Youn int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg); 1411c5c403dcSVardan Mikayelyan int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg); 1412c5c403dcSVardan Mikayelyan int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, 1413c5c403dcSVardan Mikayelyan int rem_wakeup, int reset); 1414117777b2SDinh Nguyen #else 1415117777b2SDinh Nguyen static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1416117777b2SDinh Nguyen { return 0; } 1417fae4e826SDouglas Anderson static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, 1418fae4e826SDouglas Anderson int us) 1419fae4e826SDouglas Anderson { return 0; } 14206a659531SDouglas Anderson static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {} 14216a659531SDouglas Anderson static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {} 1422117777b2SDinh Nguyen static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} 1423117777b2SDinh Nguyen static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} 142465c9c4c6SVardan Mikayelyan static inline int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) 142565c9c4c6SVardan Mikayelyan { return 0; } 14264fe160d5SHeiner Kallweit static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg) 1427117777b2SDinh Nguyen { return 0; } 142858e52ff6SJohn Youn static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 142958e52ff6SJohn Youn { return 0; } 143058e52ff6SJohn Youn static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 143158e52ff6SJohn Youn { return 0; } 1432c5c403dcSVardan Mikayelyan static inline int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg) 1433c5c403dcSVardan Mikayelyan { return 0; } 1434c5c403dcSVardan Mikayelyan static inline int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, 1435c5c403dcSVardan Mikayelyan int rem_wakeup, int reset) 1436c5c403dcSVardan Mikayelyan { return 0; } 143758e52ff6SJohn Youn 1438117777b2SDinh Nguyen #endif 1439117777b2SDinh Nguyen 1440197ba5f4SPaul Zimmerman #endif /* __DWC2_CORE_H__ */ 1441