1197ba5f4SPaul Zimmerman /* 2197ba5f4SPaul Zimmerman * core.h - DesignWare HS OTG Controller common declarations 3197ba5f4SPaul Zimmerman * 4197ba5f4SPaul Zimmerman * Copyright (C) 2004-2013 Synopsys, Inc. 5197ba5f4SPaul Zimmerman * 6197ba5f4SPaul Zimmerman * Redistribution and use in source and binary forms, with or without 7197ba5f4SPaul Zimmerman * modification, are permitted provided that the following conditions 8197ba5f4SPaul Zimmerman * are met: 9197ba5f4SPaul Zimmerman * 1. Redistributions of source code must retain the above copyright 10197ba5f4SPaul Zimmerman * notice, this list of conditions, and the following disclaimer, 11197ba5f4SPaul Zimmerman * without modification. 12197ba5f4SPaul Zimmerman * 2. Redistributions in binary form must reproduce the above copyright 13197ba5f4SPaul Zimmerman * notice, this list of conditions and the following disclaimer in the 14197ba5f4SPaul Zimmerman * documentation and/or other materials provided with the distribution. 15197ba5f4SPaul Zimmerman * 3. The names of the above-listed copyright holders may not be used 16197ba5f4SPaul Zimmerman * to endorse or promote products derived from this software without 17197ba5f4SPaul Zimmerman * specific prior written permission. 18197ba5f4SPaul Zimmerman * 19197ba5f4SPaul Zimmerman * ALTERNATIVELY, this software may be distributed under the terms of the 20197ba5f4SPaul Zimmerman * GNU General Public License ("GPL") as published by the Free Software 21197ba5f4SPaul Zimmerman * Foundation; either version 2 of the License, or (at your option) any 22197ba5f4SPaul Zimmerman * later version. 23197ba5f4SPaul Zimmerman * 24197ba5f4SPaul Zimmerman * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25197ba5f4SPaul Zimmerman * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26197ba5f4SPaul Zimmerman * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27197ba5f4SPaul Zimmerman * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28197ba5f4SPaul Zimmerman * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29197ba5f4SPaul Zimmerman * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30197ba5f4SPaul Zimmerman * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31197ba5f4SPaul Zimmerman * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32197ba5f4SPaul Zimmerman * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33197ba5f4SPaul Zimmerman * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34197ba5f4SPaul Zimmerman * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35197ba5f4SPaul Zimmerman */ 36197ba5f4SPaul Zimmerman 37197ba5f4SPaul Zimmerman #ifndef __DWC2_CORE_H__ 38197ba5f4SPaul Zimmerman #define __DWC2_CORE_H__ 39197ba5f4SPaul Zimmerman 40f7c0b143SDinh Nguyen #include <linux/phy/phy.h> 41f7c0b143SDinh Nguyen #include <linux/regulator/consumer.h> 42f7c0b143SDinh Nguyen #include <linux/usb/gadget.h> 43f7c0b143SDinh Nguyen #include <linux/usb/otg.h> 44197ba5f4SPaul Zimmerman #include <linux/usb/phy.h> 45197ba5f4SPaul Zimmerman #include "hw.h" 46197ba5f4SPaul Zimmerman 4774fc4a75SDouglas Anderson /* 4874fc4a75SDouglas Anderson * Suggested defines for tracers: 4974fc4a75SDouglas Anderson * - no_printk: Disable tracing 5074fc4a75SDouglas Anderson * - pr_info: Print this info to the console 5174fc4a75SDouglas Anderson * - trace_printk: Print this info to trace buffer (good for verbose logging) 5274fc4a75SDouglas Anderson */ 5374fc4a75SDouglas Anderson 5474fc4a75SDouglas Anderson #define DWC2_TRACE_SCHEDULER no_printk 5574fc4a75SDouglas Anderson #define DWC2_TRACE_SCHEDULER_VB no_printk 5674fc4a75SDouglas Anderson 5774fc4a75SDouglas Anderson /* Detailed scheduler tracing, but won't overwhelm console */ 5874fc4a75SDouglas Anderson #define dwc2_sch_dbg(hsotg, fmt, ...) \ 5974fc4a75SDouglas Anderson DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \ 6074fc4a75SDouglas Anderson dev_name(hsotg->dev), ##__VA_ARGS__) 6174fc4a75SDouglas Anderson 6274fc4a75SDouglas Anderson /* Verbose scheduler tracing */ 6374fc4a75SDouglas Anderson #define dwc2_sch_vdbg(hsotg, fmt, ...) \ 6474fc4a75SDouglas Anderson DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \ 6574fc4a75SDouglas Anderson dev_name(hsotg->dev), ##__VA_ARGS__) 6674fc4a75SDouglas Anderson 6723e34392SArnd Bergmann #ifdef CONFIG_MIPS 6823e34392SArnd Bergmann /* 6923e34392SArnd Bergmann * There are some MIPS machines that can run in either big-endian 7023e34392SArnd Bergmann * or little-endian mode and that use the dwc2 register without 7123e34392SArnd Bergmann * a byteswap in both ways. 7223e34392SArnd Bergmann * Unlike other architectures, MIPS apparently does not require a 7323e34392SArnd Bergmann * barrier before the __raw_writel() to synchronize with DMA but does 7423e34392SArnd Bergmann * require the barrier after the __raw_writel() to serialize a set of 7523e34392SArnd Bergmann * writes. This set of operations was added specifically for MIPS and 7623e34392SArnd Bergmann * should only be used there. 7723e34392SArnd Bergmann */ 7895c8bc36SAntti Seppälä static inline u32 dwc2_readl(const void __iomem *addr) 79197ba5f4SPaul Zimmerman { 8095c8bc36SAntti Seppälä u32 value = __raw_readl(addr); 8195c8bc36SAntti Seppälä 8295c8bc36SAntti Seppälä /* In order to preserve endianness __raw_* operation is used. Therefore 8395c8bc36SAntti Seppälä * a barrier is needed to ensure IO access is not re-ordered across 8495c8bc36SAntti Seppälä * reads or writes 8595c8bc36SAntti Seppälä */ 8695c8bc36SAntti Seppälä mb(); 8795c8bc36SAntti Seppälä return value; 88197ba5f4SPaul Zimmerman } 89197ba5f4SPaul Zimmerman 9095c8bc36SAntti Seppälä static inline void dwc2_writel(u32 value, void __iomem *addr) 9195c8bc36SAntti Seppälä { 9295c8bc36SAntti Seppälä __raw_writel(value, addr); 9395c8bc36SAntti Seppälä 9495c8bc36SAntti Seppälä /* 9595c8bc36SAntti Seppälä * In order to preserve endianness __raw_* operation is used. Therefore 9695c8bc36SAntti Seppälä * a barrier is needed to ensure IO access is not re-ordered across 9795c8bc36SAntti Seppälä * reads or writes 9895c8bc36SAntti Seppälä */ 9995c8bc36SAntti Seppälä mb(); 10095c8bc36SAntti Seppälä #ifdef DWC2_LOG_WRITES 10195c8bc36SAntti Seppälä pr_info("INFO:: wrote %08x to %p\n", value, addr); 102197ba5f4SPaul Zimmerman #endif 10395c8bc36SAntti Seppälä } 10423e34392SArnd Bergmann #else 10523e34392SArnd Bergmann /* Normal architectures just use readl/write */ 10623e34392SArnd Bergmann static inline u32 dwc2_readl(const void __iomem *addr) 10723e34392SArnd Bergmann { 10823e34392SArnd Bergmann return readl(addr); 10923e34392SArnd Bergmann } 11023e34392SArnd Bergmann 11123e34392SArnd Bergmann static inline void dwc2_writel(u32 value, void __iomem *addr) 11223e34392SArnd Bergmann { 11323e34392SArnd Bergmann writel(value, addr); 11423e34392SArnd Bergmann 11523e34392SArnd Bergmann #ifdef DWC2_LOG_WRITES 11623e34392SArnd Bergmann pr_info("info:: wrote %08x to %p\n", value, addr); 11723e34392SArnd Bergmann #endif 11823e34392SArnd Bergmann } 11923e34392SArnd Bergmann #endif 120197ba5f4SPaul Zimmerman 121197ba5f4SPaul Zimmerman /* Maximum number of Endpoints/HostChannels */ 122197ba5f4SPaul Zimmerman #define MAX_EPS_CHANNELS 16 123197ba5f4SPaul Zimmerman 1241f91b4ccSFelipe Balbi /* dwc2-hsotg declarations */ 1251f91b4ccSFelipe Balbi static const char * const dwc2_hsotg_supply_names[] = { 126f7c0b143SDinh Nguyen "vusb_d", /* digital USB supply, 1.2V */ 127f7c0b143SDinh Nguyen "vusb_a", /* analog USB supply, 1.1V */ 128f7c0b143SDinh Nguyen }; 129f7c0b143SDinh Nguyen 130f7c0b143SDinh Nguyen /* 131f7c0b143SDinh Nguyen * EP0_MPS_LIMIT 132f7c0b143SDinh Nguyen * 133f7c0b143SDinh Nguyen * Unfortunately there seems to be a limit of the amount of data that can 134f7c0b143SDinh Nguyen * be transferred by IN transactions on EP0. This is either 127 bytes or 3 135f7c0b143SDinh Nguyen * packets (which practically means 1 packet and 63 bytes of data) when the 136f7c0b143SDinh Nguyen * MPS is set to 64. 137f7c0b143SDinh Nguyen * 138f7c0b143SDinh Nguyen * This means if we are wanting to move >127 bytes of data, we need to 139f7c0b143SDinh Nguyen * split the transactions up, but just doing one packet at a time does 140f7c0b143SDinh Nguyen * not work (this may be an implicit DATA0 PID on first packet of the 141f7c0b143SDinh Nguyen * transaction) and doing 2 packets is outside the controller's limits. 142f7c0b143SDinh Nguyen * 143f7c0b143SDinh Nguyen * If we try to lower the MPS size for EP0, then no transfers work properly 144f7c0b143SDinh Nguyen * for EP0, and the system will fail basic enumeration. As no cause for this 145f7c0b143SDinh Nguyen * has currently been found, we cannot support any large IN transfers for 146f7c0b143SDinh Nguyen * EP0. 147f7c0b143SDinh Nguyen */ 148f7c0b143SDinh Nguyen #define EP0_MPS_LIMIT 64 149f7c0b143SDinh Nguyen 150941fcce4SDinh Nguyen struct dwc2_hsotg; 1511f91b4ccSFelipe Balbi struct dwc2_hsotg_req; 152f7c0b143SDinh Nguyen 153f7c0b143SDinh Nguyen /** 1541f91b4ccSFelipe Balbi * struct dwc2_hsotg_ep - driver endpoint definition. 155f7c0b143SDinh Nguyen * @ep: The gadget layer representation of the endpoint. 156f7c0b143SDinh Nguyen * @name: The driver generated name for the endpoint. 157f7c0b143SDinh Nguyen * @queue: Queue of requests for this endpoint. 158f7c0b143SDinh Nguyen * @parent: Reference back to the parent device structure. 159f7c0b143SDinh Nguyen * @req: The current request that the endpoint is processing. This is 160f7c0b143SDinh Nguyen * used to indicate an request has been loaded onto the endpoint 161f7c0b143SDinh Nguyen * and has yet to be completed (maybe due to data move, or simply 162f7c0b143SDinh Nguyen * awaiting an ack from the core all the data has been completed). 163f7c0b143SDinh Nguyen * @debugfs: File entry for debugfs file for this endpoint. 164f7c0b143SDinh Nguyen * @lock: State lock to protect contents of endpoint. 165f7c0b143SDinh Nguyen * @dir_in: Set to true if this endpoint is of the IN direction, which 166f7c0b143SDinh Nguyen * means that it is sending data to the Host. 167f7c0b143SDinh Nguyen * @index: The index for the endpoint registers. 168f7c0b143SDinh Nguyen * @mc: Multi Count - number of transactions per microframe 169142bd33fSVardan Mikayelyan * @interval - Interval for periodic endpoints, in frames or microframes. 170f7c0b143SDinh Nguyen * @name: The name array passed to the USB core. 171f7c0b143SDinh Nguyen * @halted: Set if the endpoint has been halted. 172f7c0b143SDinh Nguyen * @periodic: Set if this is a periodic ep, such as Interrupt 173f7c0b143SDinh Nguyen * @isochronous: Set if this is a isochronous ep 1748a20fa45SMian Yousaf Kaukab * @send_zlp: Set if we need to send a zero-length packet. 175f7c0b143SDinh Nguyen * @total_data: The total number of data bytes done. 176f7c0b143SDinh Nguyen * @fifo_size: The size of the FIFO (for periodic IN endpoints) 177f7c0b143SDinh Nguyen * @fifo_load: The amount of data loaded into the FIFO (periodic IN) 178f7c0b143SDinh Nguyen * @last_load: The offset of data for the last start of request. 179f7c0b143SDinh Nguyen * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN 18092d1635dSVardan Mikayelyan * @target_frame: Targeted frame num to setup next ISOC transfer 18192d1635dSVardan Mikayelyan * @frame_overrun: Indicates SOF number overrun in DSTS 182f7c0b143SDinh Nguyen * 183f7c0b143SDinh Nguyen * This is the driver's state for each registered enpoint, allowing it 184f7c0b143SDinh Nguyen * to keep track of transactions that need doing. Each endpoint has a 185f7c0b143SDinh Nguyen * lock to protect the state, to try and avoid using an overall lock 186f7c0b143SDinh Nguyen * for the host controller as much as possible. 187f7c0b143SDinh Nguyen * 188f7c0b143SDinh Nguyen * For periodic IN endpoints, we have fifo_size and fifo_load to try 189f7c0b143SDinh Nguyen * and keep track of the amount of data in the periodic FIFO for each 190f7c0b143SDinh Nguyen * of these as we don't have a status register that tells us how much 191f7c0b143SDinh Nguyen * is in each of them. (note, this may actually be useless information 192f7c0b143SDinh Nguyen * as in shared-fifo mode periodic in acts like a single-frame packet 193f7c0b143SDinh Nguyen * buffer than a fifo) 194f7c0b143SDinh Nguyen */ 1951f91b4ccSFelipe Balbi struct dwc2_hsotg_ep { 196f7c0b143SDinh Nguyen struct usb_ep ep; 197f7c0b143SDinh Nguyen struct list_head queue; 198941fcce4SDinh Nguyen struct dwc2_hsotg *parent; 1991f91b4ccSFelipe Balbi struct dwc2_hsotg_req *req; 200f7c0b143SDinh Nguyen struct dentry *debugfs; 201f7c0b143SDinh Nguyen 202f7c0b143SDinh Nguyen unsigned long total_data; 203f7c0b143SDinh Nguyen unsigned int size_loaded; 204f7c0b143SDinh Nguyen unsigned int last_load; 205f7c0b143SDinh Nguyen unsigned int fifo_load; 206f7c0b143SDinh Nguyen unsigned short fifo_size; 207b203d0a2SRobert Baldyga unsigned short fifo_index; 208f7c0b143SDinh Nguyen 209f7c0b143SDinh Nguyen unsigned char dir_in; 210f7c0b143SDinh Nguyen unsigned char index; 211f7c0b143SDinh Nguyen unsigned char mc; 212f7c0b143SDinh Nguyen unsigned char interval; 213f7c0b143SDinh Nguyen 214f7c0b143SDinh Nguyen unsigned int halted:1; 215f7c0b143SDinh Nguyen unsigned int periodic:1; 216f7c0b143SDinh Nguyen unsigned int isochronous:1; 2178a20fa45SMian Yousaf Kaukab unsigned int send_zlp:1; 21892d1635dSVardan Mikayelyan unsigned int target_frame; 21992d1635dSVardan Mikayelyan #define TARGET_FRAME_INITIAL 0xFFFFFFFF 22092d1635dSVardan Mikayelyan bool frame_overrun; 221f7c0b143SDinh Nguyen 222f7c0b143SDinh Nguyen char name[10]; 223f7c0b143SDinh Nguyen }; 224f7c0b143SDinh Nguyen 225f7c0b143SDinh Nguyen /** 2261f91b4ccSFelipe Balbi * struct dwc2_hsotg_req - data transfer request 227f7c0b143SDinh Nguyen * @req: The USB gadget request 228f7c0b143SDinh Nguyen * @queue: The list of requests for the endpoint this is queued for. 2297d24c1b5SMian Yousaf Kaukab * @saved_req_buf: variable to save req.buf when bounce buffers are used. 230f7c0b143SDinh Nguyen */ 2311f91b4ccSFelipe Balbi struct dwc2_hsotg_req { 232f7c0b143SDinh Nguyen struct usb_request req; 233f7c0b143SDinh Nguyen struct list_head queue; 2347d24c1b5SMian Yousaf Kaukab void *saved_req_buf; 235f7c0b143SDinh Nguyen }; 236f7c0b143SDinh Nguyen 237941fcce4SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 238f7c0b143SDinh Nguyen #define call_gadget(_hs, _entry) \ 239f7c0b143SDinh Nguyen do { \ 240f7c0b143SDinh Nguyen if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ 241f7c0b143SDinh Nguyen (_hs)->driver && (_hs)->driver->_entry) { \ 242f7c0b143SDinh Nguyen spin_unlock(&_hs->lock); \ 243f7c0b143SDinh Nguyen (_hs)->driver->_entry(&(_hs)->gadget); \ 244f7c0b143SDinh Nguyen spin_lock(&_hs->lock); \ 245f7c0b143SDinh Nguyen } \ 246f7c0b143SDinh Nguyen } while (0) 247941fcce4SDinh Nguyen #else 248941fcce4SDinh Nguyen #define call_gadget(_hs, _entry) do {} while (0) 249941fcce4SDinh Nguyen #endif 250f7c0b143SDinh Nguyen 251197ba5f4SPaul Zimmerman struct dwc2_hsotg; 252197ba5f4SPaul Zimmerman struct dwc2_host_chan; 253197ba5f4SPaul Zimmerman 254197ba5f4SPaul Zimmerman /* Device States */ 255197ba5f4SPaul Zimmerman enum dwc2_lx_state { 256197ba5f4SPaul Zimmerman DWC2_L0, /* On state */ 257197ba5f4SPaul Zimmerman DWC2_L1, /* LPM sleep state */ 258197ba5f4SPaul Zimmerman DWC2_L2, /* USB suspend state */ 259197ba5f4SPaul Zimmerman DWC2_L3, /* Off state */ 260197ba5f4SPaul Zimmerman }; 261197ba5f4SPaul Zimmerman 2623fa95385SJohn Youn /* 2633fa95385SJohn Youn * Gadget periodic tx fifo sizes as used by legacy driver 2643fa95385SJohn Youn * EP0 is not included 2653fa95385SJohn Youn */ 2663fa95385SJohn Youn #define DWC2_G_P_LEGACY_TX_FIFO_SIZE {256, 256, 256, 256, 768, 768, 768, \ 2673fa95385SJohn Youn 768, 0, 0, 0, 0, 0, 0, 0} 2683fa95385SJohn Youn 269fe0b94abSMian Yousaf Kaukab /* Gadget ep0 states */ 270fe0b94abSMian Yousaf Kaukab enum dwc2_ep0_state { 271fe0b94abSMian Yousaf Kaukab DWC2_EP0_SETUP, 272fe0b94abSMian Yousaf Kaukab DWC2_EP0_DATA_IN, 273fe0b94abSMian Yousaf Kaukab DWC2_EP0_DATA_OUT, 274fe0b94abSMian Yousaf Kaukab DWC2_EP0_STATUS_IN, 275fe0b94abSMian Yousaf Kaukab DWC2_EP0_STATUS_OUT, 276fe0b94abSMian Yousaf Kaukab }; 277fe0b94abSMian Yousaf Kaukab 278197ba5f4SPaul Zimmerman /** 279197ba5f4SPaul Zimmerman * struct dwc2_core_params - Parameters for configuring the core 280197ba5f4SPaul Zimmerman * 281197ba5f4SPaul Zimmerman * @otg_cap: Specifies the OTG capabilities. 282197ba5f4SPaul Zimmerman * 0 - HNP and SRP capable 283197ba5f4SPaul Zimmerman * 1 - SRP Only capable 284197ba5f4SPaul Zimmerman * 2 - No HNP/SRP capable (always available) 285197ba5f4SPaul Zimmerman * Defaults to best available option (0, 1, then 2) 286197ba5f4SPaul Zimmerman * @otg_ver: OTG version supported 287197ba5f4SPaul Zimmerman * 0 - 1.3 (default) 288197ba5f4SPaul Zimmerman * 1 - 2.0 289197ba5f4SPaul Zimmerman * @dma_enable: Specifies whether to use slave or DMA mode for accessing 290197ba5f4SPaul Zimmerman * the data FIFOs. The driver will automatically detect the 291197ba5f4SPaul Zimmerman * value for this parameter if none is specified. 292197ba5f4SPaul Zimmerman * 0 - Slave (always available) 293197ba5f4SPaul Zimmerman * 1 - DMA (default, if available) 294197ba5f4SPaul Zimmerman * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 295197ba5f4SPaul Zimmerman * address DMA mode or descriptor DMA mode for accessing 296197ba5f4SPaul Zimmerman * the data FIFOs. The driver will automatically detect the 297197ba5f4SPaul Zimmerman * value for this if none is specified. 298197ba5f4SPaul Zimmerman * 0 - Address DMA 299197ba5f4SPaul Zimmerman * 1 - Descriptor DMA (default, if available) 300fbb9e22bSMian Yousaf Kaukab * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use 301fbb9e22bSMian Yousaf Kaukab * address DMA mode or descriptor DMA mode for accessing 302fbb9e22bSMian Yousaf Kaukab * the data FIFOs in Full Speed mode only. The driver 303fbb9e22bSMian Yousaf Kaukab * will automatically detect the value for this if none is 304fbb9e22bSMian Yousaf Kaukab * specified. 305fbb9e22bSMian Yousaf Kaukab * 0 - Address DMA 306fbb9e22bSMian Yousaf Kaukab * 1 - Descriptor DMA in FS (default, if available) 307197ba5f4SPaul Zimmerman * @speed: Specifies the maximum speed of operation in host and 308197ba5f4SPaul Zimmerman * device mode. The actual speed depends on the speed of 309197ba5f4SPaul Zimmerman * the attached device and the value of phy_type. 310197ba5f4SPaul Zimmerman * 0 - High Speed 311197ba5f4SPaul Zimmerman * (default when phy_type is UTMI+ or ULPI) 312197ba5f4SPaul Zimmerman * 1 - Full Speed 313197ba5f4SPaul Zimmerman * (default when phy_type is Full Speed) 314197ba5f4SPaul Zimmerman * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 315197ba5f4SPaul Zimmerman * 1 - Allow dynamic FIFO sizing (default, if available) 316197ba5f4SPaul Zimmerman * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 317c1d286cfSJohn Youn * are enabled for non-periodic IN endpoints in device 318c1d286cfSJohn Youn * mode. 319197ba5f4SPaul Zimmerman * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 320197ba5f4SPaul Zimmerman * dynamic FIFO sizing is enabled 321197ba5f4SPaul Zimmerman * 16 to 32768 322197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 323197ba5f4SPaul Zimmerman * the default. 324197ba5f4SPaul Zimmerman * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 325197ba5f4SPaul Zimmerman * in host mode when dynamic FIFO sizing is enabled 326197ba5f4SPaul Zimmerman * 16 to 32768 327197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 328197ba5f4SPaul Zimmerman * the default. 329197ba5f4SPaul Zimmerman * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 330197ba5f4SPaul Zimmerman * host mode when dynamic FIFO sizing is enabled 331197ba5f4SPaul Zimmerman * 16 to 32768 332197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 333197ba5f4SPaul Zimmerman * the default. 334197ba5f4SPaul Zimmerman * @max_transfer_size: The maximum transfer size supported, in bytes 335197ba5f4SPaul Zimmerman * 2047 to 65,535 336197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 337197ba5f4SPaul Zimmerman * the default. 338197ba5f4SPaul Zimmerman * @max_packet_count: The maximum number of packets in a transfer 339197ba5f4SPaul Zimmerman * 15 to 511 340197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 341197ba5f4SPaul Zimmerman * the default. 342197ba5f4SPaul Zimmerman * @host_channels: The number of host channel registers to use 343197ba5f4SPaul Zimmerman * 1 to 16 344197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 345197ba5f4SPaul Zimmerman * the default. 346197ba5f4SPaul Zimmerman * @phy_type: Specifies the type of PHY interface to use. By default, 347197ba5f4SPaul Zimmerman * the driver will automatically detect the phy_type. 348197ba5f4SPaul Zimmerman * 0 - Full Speed Phy 349197ba5f4SPaul Zimmerman * 1 - UTMI+ Phy 350197ba5f4SPaul Zimmerman * 2 - ULPI Phy 351197ba5f4SPaul Zimmerman * Defaults to best available option (2, 1, then 0) 352197ba5f4SPaul Zimmerman * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 353197ba5f4SPaul Zimmerman * is applicable for a phy_type of UTMI+ or ULPI. (For a 354197ba5f4SPaul Zimmerman * ULPI phy_type, this parameter indicates the data width 355197ba5f4SPaul Zimmerman * between the MAC and the ULPI Wrapper.) Also, this 356197ba5f4SPaul Zimmerman * parameter is applicable only if the OTG_HSPHY_WIDTH cC 357197ba5f4SPaul Zimmerman * parameter was set to "8 and 16 bits", meaning that the 358197ba5f4SPaul Zimmerman * core has been configured to work at either data path 359197ba5f4SPaul Zimmerman * width. 360197ba5f4SPaul Zimmerman * 8 or 16 (default 16 if available) 361197ba5f4SPaul Zimmerman * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 362197ba5f4SPaul Zimmerman * data rate. This parameter is only applicable if phy_type 363197ba5f4SPaul Zimmerman * is ULPI. 364197ba5f4SPaul Zimmerman * 0 - single data rate ULPI interface with 8 bit wide 365197ba5f4SPaul Zimmerman * data bus (default) 366197ba5f4SPaul Zimmerman * 1 - double data rate ULPI interface with 4 bit wide 367197ba5f4SPaul Zimmerman * data bus 368197ba5f4SPaul Zimmerman * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 369197ba5f4SPaul Zimmerman * external supply to drive the VBus 370197ba5f4SPaul Zimmerman * 0 - Internal supply (default) 371197ba5f4SPaul Zimmerman * 1 - External supply 372197ba5f4SPaul Zimmerman * @i2c_enable: Specifies whether to use the I2Cinterface for a full 373197ba5f4SPaul Zimmerman * speed PHY. This parameter is only applicable if phy_type 374197ba5f4SPaul Zimmerman * is FS. 375197ba5f4SPaul Zimmerman * 0 - No (default) 376197ba5f4SPaul Zimmerman * 1 - Yes 377197ba5f4SPaul Zimmerman * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 378197ba5f4SPaul Zimmerman * 0 - No (default) 379197ba5f4SPaul Zimmerman * 1 - Yes 380197ba5f4SPaul Zimmerman * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 381197ba5f4SPaul Zimmerman * when attached to a Full Speed or Low Speed device in 382197ba5f4SPaul Zimmerman * host mode. 383197ba5f4SPaul Zimmerman * 0 - Don't support low power mode (default) 384197ba5f4SPaul Zimmerman * 1 - Support low power mode 385197ba5f4SPaul Zimmerman * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 386197ba5f4SPaul Zimmerman * when connected to a Low Speed device in host 387197ba5f4SPaul Zimmerman * mode. This parameter is applicable only if 388197ba5f4SPaul Zimmerman * host_support_fs_ls_low_power is enabled. 389197ba5f4SPaul Zimmerman * 0 - 48 MHz 390197ba5f4SPaul Zimmerman * (default when phy_type is UTMI+ or ULPI) 391197ba5f4SPaul Zimmerman * 1 - 6 MHz 392197ba5f4SPaul Zimmerman * (default when phy_type is Full Speed) 393197ba5f4SPaul Zimmerman * @ts_dline: Enable Term Select Dline pulsing 394197ba5f4SPaul Zimmerman * 0 - No (default) 395197ba5f4SPaul Zimmerman * 1 - Yes 396197ba5f4SPaul Zimmerman * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 397197ba5f4SPaul Zimmerman * 0 - No (default for core < 2.92a) 398197ba5f4SPaul Zimmerman * 1 - Yes (default for core >= 2.92a) 399197ba5f4SPaul Zimmerman * @ahbcfg: This field allows the default value of the GAHBCFG 400197ba5f4SPaul Zimmerman * register to be overridden 401197ba5f4SPaul Zimmerman * -1 - GAHBCFG value will be set to 0x06 402197ba5f4SPaul Zimmerman * (INCR4, default) 403197ba5f4SPaul Zimmerman * all others - GAHBCFG value will be overridden with 404197ba5f4SPaul Zimmerman * this value 405197ba5f4SPaul Zimmerman * Not all bits can be controlled like this, the 406197ba5f4SPaul Zimmerman * bits defined by GAHBCFG_CTRL_MASK are controlled 407197ba5f4SPaul Zimmerman * by the driver and are ignored in this 408197ba5f4SPaul Zimmerman * configuration value. 409197ba5f4SPaul Zimmerman * @uframe_sched: True to enable the microframe scheduler 410a6d249d8SGregory Herrero * @external_id_pin_ctl: Specifies whether ID pin is handled externally. 411a6d249d8SGregory Herrero * Disable CONIDSTSCHNG controller interrupt in such 412a6d249d8SGregory Herrero * case. 413a6d249d8SGregory Herrero * 0 - No (default) 414a6d249d8SGregory Herrero * 1 - Yes 415285046aaSGregory Herrero * @hibernation: Specifies whether the controller support hibernation. 416285046aaSGregory Herrero * If hibernation is enabled, the controller will enter 417285046aaSGregory Herrero * hibernation in both peripheral and host mode when 418285046aaSGregory Herrero * needed. 419285046aaSGregory Herrero * 0 - No (default) 420285046aaSGregory Herrero * 1 - Yes 421197ba5f4SPaul Zimmerman * 422197ba5f4SPaul Zimmerman * The following parameters may be specified when starting the module. These 423197ba5f4SPaul Zimmerman * parameters define how the DWC_otg controller should be configured. A 424197ba5f4SPaul Zimmerman * value of -1 (or any other out of range value) for any parameter means 425197ba5f4SPaul Zimmerman * to read the value from hardware (if possible) or use the builtin 426197ba5f4SPaul Zimmerman * default described above. 427197ba5f4SPaul Zimmerman */ 428197ba5f4SPaul Zimmerman struct dwc2_core_params { 429197ba5f4SPaul Zimmerman /* 430197ba5f4SPaul Zimmerman * Don't add any non-int members here, this will break 431197ba5f4SPaul Zimmerman * dwc2_set_all_params! 432197ba5f4SPaul Zimmerman */ 433197ba5f4SPaul Zimmerman int otg_cap; 434c1d286cfSJohn Youn #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 435c1d286cfSJohn Youn #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 436c1d286cfSJohn Youn #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 437c1d286cfSJohn Youn 438197ba5f4SPaul Zimmerman int otg_ver; 439197ba5f4SPaul Zimmerman int dma_enable; 440197ba5f4SPaul Zimmerman int dma_desc_enable; 441fbb9e22bSMian Yousaf Kaukab int dma_desc_fs_enable; 442197ba5f4SPaul Zimmerman int speed; 443c1d286cfSJohn Youn #define DWC2_SPEED_PARAM_HIGH 0 444c1d286cfSJohn Youn #define DWC2_SPEED_PARAM_FULL 1 445c1d286cfSJohn Youn 446197ba5f4SPaul Zimmerman int enable_dynamic_fifo; 447197ba5f4SPaul Zimmerman int en_multiple_tx_fifo; 448197ba5f4SPaul Zimmerman int host_rx_fifo_size; 449197ba5f4SPaul Zimmerman int host_nperio_tx_fifo_size; 450197ba5f4SPaul Zimmerman int host_perio_tx_fifo_size; 451197ba5f4SPaul Zimmerman int max_transfer_size; 452197ba5f4SPaul Zimmerman int max_packet_count; 453197ba5f4SPaul Zimmerman int host_channels; 454197ba5f4SPaul Zimmerman int phy_type; 455c1d286cfSJohn Youn #define DWC2_PHY_TYPE_PARAM_FS 0 456c1d286cfSJohn Youn #define DWC2_PHY_TYPE_PARAM_UTMI 1 457c1d286cfSJohn Youn #define DWC2_PHY_TYPE_PARAM_ULPI 2 458c1d286cfSJohn Youn 459197ba5f4SPaul Zimmerman int phy_utmi_width; 460197ba5f4SPaul Zimmerman int phy_ulpi_ddr; 461197ba5f4SPaul Zimmerman int phy_ulpi_ext_vbus; 462c1d286cfSJohn Youn #define DWC2_PHY_ULPI_INTERNAL_VBUS 0 463c1d286cfSJohn Youn #define DWC2_PHY_ULPI_EXTERNAL_VBUS 1 464c1d286cfSJohn Youn 465197ba5f4SPaul Zimmerman int i2c_enable; 466197ba5f4SPaul Zimmerman int ulpi_fs_ls; 467197ba5f4SPaul Zimmerman int host_support_fs_ls_low_power; 468197ba5f4SPaul Zimmerman int host_ls_low_power_phy_clk; 469c1d286cfSJohn Youn #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 470c1d286cfSJohn Youn #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 471c1d286cfSJohn Youn 472197ba5f4SPaul Zimmerman int ts_dline; 473197ba5f4SPaul Zimmerman int reload_ctl; 474197ba5f4SPaul Zimmerman int ahbcfg; 475197ba5f4SPaul Zimmerman int uframe_sched; 476a6d249d8SGregory Herrero int external_id_pin_ctl; 477285046aaSGregory Herrero int hibernation; 478197ba5f4SPaul Zimmerman }; 479197ba5f4SPaul Zimmerman 480197ba5f4SPaul Zimmerman /** 481197ba5f4SPaul Zimmerman * struct dwc2_hw_params - Autodetected parameters. 482197ba5f4SPaul Zimmerman * 483197ba5f4SPaul Zimmerman * These parameters are the various parameters read from hardware 484197ba5f4SPaul Zimmerman * registers during initialization. They typically contain the best 485197ba5f4SPaul Zimmerman * supported or maximum value that can be configured in the 486197ba5f4SPaul Zimmerman * corresponding dwc2_core_params value. 487197ba5f4SPaul Zimmerman * 488197ba5f4SPaul Zimmerman * The values that are not in dwc2_core_params are documented below. 489197ba5f4SPaul Zimmerman * 490197ba5f4SPaul Zimmerman * @op_mode Mode of Operation 491197ba5f4SPaul Zimmerman * 0 - HNP- and SRP-Capable OTG (Host & Device) 492197ba5f4SPaul Zimmerman * 1 - SRP-Capable OTG (Host & Device) 493197ba5f4SPaul Zimmerman * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 494197ba5f4SPaul Zimmerman * 3 - SRP-Capable Device 495197ba5f4SPaul Zimmerman * 4 - Non-OTG Device 496197ba5f4SPaul Zimmerman * 5 - SRP-Capable Host 497197ba5f4SPaul Zimmerman * 6 - Non-OTG Host 498197ba5f4SPaul Zimmerman * @arch Architecture 499197ba5f4SPaul Zimmerman * 0 - Slave only 500197ba5f4SPaul Zimmerman * 1 - External DMA 501197ba5f4SPaul Zimmerman * 2 - Internal DMA 502197ba5f4SPaul Zimmerman * @power_optimized Are power optimizations enabled? 503197ba5f4SPaul Zimmerman * @num_dev_ep Number of device endpoints available 504197ba5f4SPaul Zimmerman * @num_dev_perio_in_ep Number of device periodic IN endpoints 505997f4f81SMickael Maison * available 506197ba5f4SPaul Zimmerman * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue 507197ba5f4SPaul Zimmerman * Depth 508197ba5f4SPaul Zimmerman * 0 to 30 509197ba5f4SPaul Zimmerman * @host_perio_tx_q_depth 510197ba5f4SPaul Zimmerman * Host Mode Periodic Request Queue Depth 511197ba5f4SPaul Zimmerman * 2, 4 or 8 512197ba5f4SPaul Zimmerman * @nperio_tx_q_depth 513197ba5f4SPaul Zimmerman * Non-Periodic Request Queue Depth 514197ba5f4SPaul Zimmerman * 2, 4 or 8 515197ba5f4SPaul Zimmerman * @hs_phy_type High-speed PHY interface type 516197ba5f4SPaul Zimmerman * 0 - High-speed interface not supported 517197ba5f4SPaul Zimmerman * 1 - UTMI+ 518197ba5f4SPaul Zimmerman * 2 - ULPI 519197ba5f4SPaul Zimmerman * 3 - UTMI+ and ULPI 520197ba5f4SPaul Zimmerman * @fs_phy_type Full-speed PHY interface type 521197ba5f4SPaul Zimmerman * 0 - Full speed interface not supported 522197ba5f4SPaul Zimmerman * 1 - Dedicated full speed interface 523197ba5f4SPaul Zimmerman * 2 - FS pins shared with UTMI+ pins 524197ba5f4SPaul Zimmerman * 3 - FS pins shared with ULPI pins 525197ba5f4SPaul Zimmerman * @total_fifo_size: Total internal RAM for FIFOs (bytes) 526197ba5f4SPaul Zimmerman * @utmi_phy_data_width UTMI+ PHY data width 527197ba5f4SPaul Zimmerman * 0 - 8 bits 528197ba5f4SPaul Zimmerman * 1 - 16 bits 529197ba5f4SPaul Zimmerman * 2 - 8 or 16 bits 530197ba5f4SPaul Zimmerman * @snpsid: Value from SNPSID register 53155e1040eSJohn Youn * @dev_ep_dirs: Direction of device endpoints (GHWCFG1) 532197ba5f4SPaul Zimmerman */ 533197ba5f4SPaul Zimmerman struct dwc2_hw_params { 534197ba5f4SPaul Zimmerman unsigned op_mode:3; 535197ba5f4SPaul Zimmerman unsigned arch:2; 536197ba5f4SPaul Zimmerman unsigned dma_desc_enable:1; 537197ba5f4SPaul Zimmerman unsigned enable_dynamic_fifo:1; 538197ba5f4SPaul Zimmerman unsigned en_multiple_tx_fifo:1; 539197ba5f4SPaul Zimmerman unsigned host_rx_fifo_size:16; 540197ba5f4SPaul Zimmerman unsigned host_nperio_tx_fifo_size:16; 54155e1040eSJohn Youn unsigned dev_nperio_tx_fifo_size:16; 542197ba5f4SPaul Zimmerman unsigned host_perio_tx_fifo_size:16; 543197ba5f4SPaul Zimmerman unsigned nperio_tx_q_depth:3; 544197ba5f4SPaul Zimmerman unsigned host_perio_tx_q_depth:3; 545197ba5f4SPaul Zimmerman unsigned dev_token_q_depth:5; 546197ba5f4SPaul Zimmerman unsigned max_transfer_size:26; 547197ba5f4SPaul Zimmerman unsigned max_packet_count:11; 548197ba5f4SPaul Zimmerman unsigned host_channels:5; 549197ba5f4SPaul Zimmerman unsigned hs_phy_type:2; 550197ba5f4SPaul Zimmerman unsigned fs_phy_type:2; 551197ba5f4SPaul Zimmerman unsigned i2c_enable:1; 552197ba5f4SPaul Zimmerman unsigned num_dev_ep:4; 553197ba5f4SPaul Zimmerman unsigned num_dev_perio_in_ep:4; 554197ba5f4SPaul Zimmerman unsigned total_fifo_size:16; 555197ba5f4SPaul Zimmerman unsigned power_optimized:1; 556197ba5f4SPaul Zimmerman unsigned utmi_phy_data_width:2; 557197ba5f4SPaul Zimmerman u32 snpsid; 55855e1040eSJohn Youn u32 dev_ep_dirs; 559197ba5f4SPaul Zimmerman }; 560197ba5f4SPaul Zimmerman 5613f95001dSMian Yousaf Kaukab /* Size of control and EP0 buffers */ 5623f95001dSMian Yousaf Kaukab #define DWC2_CTRL_BUFF_SIZE 8 5633f95001dSMian Yousaf Kaukab 564197ba5f4SPaul Zimmerman /** 565d17ee77bSGregory Herrero * struct dwc2_gregs_backup - Holds global registers state before entering partial 566d17ee77bSGregory Herrero * power down 567d17ee77bSGregory Herrero * @gotgctl: Backup of GOTGCTL register 568d17ee77bSGregory Herrero * @gintmsk: Backup of GINTMSK register 569d17ee77bSGregory Herrero * @gahbcfg: Backup of GAHBCFG register 570d17ee77bSGregory Herrero * @gusbcfg: Backup of GUSBCFG register 571d17ee77bSGregory Herrero * @grxfsiz: Backup of GRXFSIZ register 572d17ee77bSGregory Herrero * @gnptxfsiz: Backup of GNPTXFSIZ register 573d17ee77bSGregory Herrero * @gi2cctl: Backup of GI2CCTL register 574d17ee77bSGregory Herrero * @hptxfsiz: Backup of HPTXFSIZ register 575d17ee77bSGregory Herrero * @gdfifocfg: Backup of GDFIFOCFG register 576d17ee77bSGregory Herrero * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 577d17ee77bSGregory Herrero * @gpwrdn: Backup of GPWRDN register 578d17ee77bSGregory Herrero */ 579d17ee77bSGregory Herrero struct dwc2_gregs_backup { 580d17ee77bSGregory Herrero u32 gotgctl; 581d17ee77bSGregory Herrero u32 gintmsk; 582d17ee77bSGregory Herrero u32 gahbcfg; 583d17ee77bSGregory Herrero u32 gusbcfg; 584d17ee77bSGregory Herrero u32 grxfsiz; 585d17ee77bSGregory Herrero u32 gnptxfsiz; 586d17ee77bSGregory Herrero u32 gi2cctl; 587d17ee77bSGregory Herrero u32 hptxfsiz; 588d17ee77bSGregory Herrero u32 pcgcctl; 589d17ee77bSGregory Herrero u32 gdfifocfg; 590d17ee77bSGregory Herrero u32 dtxfsiz[MAX_EPS_CHANNELS]; 591d17ee77bSGregory Herrero u32 gpwrdn; 592cc1e204cSMian Yousaf Kaukab bool valid; 593d17ee77bSGregory Herrero }; 594d17ee77bSGregory Herrero 595d17ee77bSGregory Herrero /** 596d17ee77bSGregory Herrero * struct dwc2_dregs_backup - Holds device registers state before entering partial 597d17ee77bSGregory Herrero * power down 598d17ee77bSGregory Herrero * @dcfg: Backup of DCFG register 599d17ee77bSGregory Herrero * @dctl: Backup of DCTL register 600d17ee77bSGregory Herrero * @daintmsk: Backup of DAINTMSK register 601d17ee77bSGregory Herrero * @diepmsk: Backup of DIEPMSK register 602d17ee77bSGregory Herrero * @doepmsk: Backup of DOEPMSK register 603d17ee77bSGregory Herrero * @diepctl: Backup of DIEPCTL register 604d17ee77bSGregory Herrero * @dieptsiz: Backup of DIEPTSIZ register 605d17ee77bSGregory Herrero * @diepdma: Backup of DIEPDMA register 606d17ee77bSGregory Herrero * @doepctl: Backup of DOEPCTL register 607d17ee77bSGregory Herrero * @doeptsiz: Backup of DOEPTSIZ register 608d17ee77bSGregory Herrero * @doepdma: Backup of DOEPDMA register 609d17ee77bSGregory Herrero */ 610d17ee77bSGregory Herrero struct dwc2_dregs_backup { 611d17ee77bSGregory Herrero u32 dcfg; 612d17ee77bSGregory Herrero u32 dctl; 613d17ee77bSGregory Herrero u32 daintmsk; 614d17ee77bSGregory Herrero u32 diepmsk; 615d17ee77bSGregory Herrero u32 doepmsk; 616d17ee77bSGregory Herrero u32 diepctl[MAX_EPS_CHANNELS]; 617d17ee77bSGregory Herrero u32 dieptsiz[MAX_EPS_CHANNELS]; 618d17ee77bSGregory Herrero u32 diepdma[MAX_EPS_CHANNELS]; 619d17ee77bSGregory Herrero u32 doepctl[MAX_EPS_CHANNELS]; 620d17ee77bSGregory Herrero u32 doeptsiz[MAX_EPS_CHANNELS]; 621d17ee77bSGregory Herrero u32 doepdma[MAX_EPS_CHANNELS]; 622cc1e204cSMian Yousaf Kaukab bool valid; 623d17ee77bSGregory Herrero }; 624d17ee77bSGregory Herrero 625d17ee77bSGregory Herrero /** 626d17ee77bSGregory Herrero * struct dwc2_hregs_backup - Holds host registers state before entering partial 627d17ee77bSGregory Herrero * power down 628d17ee77bSGregory Herrero * @hcfg: Backup of HCFG register 629d17ee77bSGregory Herrero * @haintmsk: Backup of HAINTMSK register 630d17ee77bSGregory Herrero * @hcintmsk: Backup of HCINTMSK register 631d17ee77bSGregory Herrero * @hptr0: Backup of HPTR0 register 632d17ee77bSGregory Herrero * @hfir: Backup of HFIR register 633d17ee77bSGregory Herrero */ 634d17ee77bSGregory Herrero struct dwc2_hregs_backup { 635d17ee77bSGregory Herrero u32 hcfg; 636d17ee77bSGregory Herrero u32 haintmsk; 637d17ee77bSGregory Herrero u32 hcintmsk[MAX_EPS_CHANNELS]; 638d17ee77bSGregory Herrero u32 hprt0; 639d17ee77bSGregory Herrero u32 hfir; 640cc1e204cSMian Yousaf Kaukab bool valid; 641d17ee77bSGregory Herrero }; 642d17ee77bSGregory Herrero 6439f9f09b0SDouglas Anderson /* 6449f9f09b0SDouglas Anderson * Constants related to high speed periodic scheduling 6459f9f09b0SDouglas Anderson * 6469f9f09b0SDouglas Anderson * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a 6479f9f09b0SDouglas Anderson * reservation point of view it's assumed that the schedule goes right back to 6489f9f09b0SDouglas Anderson * the beginning after the end of the schedule. 6499f9f09b0SDouglas Anderson * 6509f9f09b0SDouglas Anderson * What does that mean for scheduling things with a long interval? It means 6519f9f09b0SDouglas Anderson * we'll reserve time for them in every possible microframe that they could 6529f9f09b0SDouglas Anderson * ever be scheduled in. ...but we'll still only actually schedule them as 6539f9f09b0SDouglas Anderson * often as they were requested. 6549f9f09b0SDouglas Anderson * 6559f9f09b0SDouglas Anderson * We keep our schedule in a "bitmap" structure. This simplifies having 6569f9f09b0SDouglas Anderson * to keep track of and merge intervals: we just let the bitmap code do most 6579f9f09b0SDouglas Anderson * of the heavy lifting. In a way scheduling is much like memory allocation. 6589f9f09b0SDouglas Anderson * 6599f9f09b0SDouglas Anderson * We schedule 100us per uframe or 80% of 125us (the maximum amount you're 6609f9f09b0SDouglas Anderson * supposed to schedule for periodic transfers). That's according to spec. 6619f9f09b0SDouglas Anderson * 6629f9f09b0SDouglas Anderson * Note that though we only schedule 80% of each microframe, the bitmap that we 6639f9f09b0SDouglas Anderson * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of 6649f9f09b0SDouglas Anderson * space for each uFrame). 6659f9f09b0SDouglas Anderson * 6669f9f09b0SDouglas Anderson * Requirements: 6679f9f09b0SDouglas Anderson * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1) 6689f9f09b0SDouglas Anderson * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably 6699f9f09b0SDouglas Anderson * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might 6709f9f09b0SDouglas Anderson * be bugs). The 8 comes from the USB spec: number of microframes per frame. 6719f9f09b0SDouglas Anderson */ 6729f9f09b0SDouglas Anderson #define DWC2_US_PER_UFRAME 125 6739f9f09b0SDouglas Anderson #define DWC2_HS_PERIODIC_US_PER_UFRAME 100 6749f9f09b0SDouglas Anderson 6759f9f09b0SDouglas Anderson #define DWC2_HS_SCHEDULE_UFRAMES 8 6769f9f09b0SDouglas Anderson #define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \ 6779f9f09b0SDouglas Anderson DWC2_HS_PERIODIC_US_PER_UFRAME) 6789f9f09b0SDouglas Anderson 6799f9f09b0SDouglas Anderson /* 6809f9f09b0SDouglas Anderson * Constants related to low speed scheduling 6819f9f09b0SDouglas Anderson * 6829f9f09b0SDouglas Anderson * For high speed we schedule every 1us. For low speed that's a bit overkill, 6839f9f09b0SDouglas Anderson * so we make up a unit called a "slice" that's worth 25us. There are 40 6849f9f09b0SDouglas Anderson * slices in a full frame and we can schedule 36 of those (90%) for periodic 6859f9f09b0SDouglas Anderson * transfers. 6869f9f09b0SDouglas Anderson * 6879f9f09b0SDouglas Anderson * Our low speed schedule can be as short as 1 frame or could be longer. When 6889f9f09b0SDouglas Anderson * we only schedule 1 frame it means that we'll need to reserve a time every 6899f9f09b0SDouglas Anderson * frame even for things that only transfer very rarely, so something that runs 6909f9f09b0SDouglas Anderson * every 2048 frames will get time reserved in every frame. Our low speed 6919f9f09b0SDouglas Anderson * schedule can be longer and we'll be able to handle more overlap, but that 6929f9f09b0SDouglas Anderson * will come at increased memory cost and increased time to schedule. 6939f9f09b0SDouglas Anderson * 6949f9f09b0SDouglas Anderson * Note: one other advantage of a short low speed schedule is that if we mess 6959f9f09b0SDouglas Anderson * up and miss scheduling we can jump in and use any of the slots that we 6969f9f09b0SDouglas Anderson * happened to reserve. 6979f9f09b0SDouglas Anderson * 6989f9f09b0SDouglas Anderson * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for 6999f9f09b0SDouglas Anderson * the schedule. There will be one schedule per TT. 7009f9f09b0SDouglas Anderson * 7019f9f09b0SDouglas Anderson * Requirements: 7029f9f09b0SDouglas Anderson * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME. 7039f9f09b0SDouglas Anderson */ 7049f9f09b0SDouglas Anderson #define DWC2_US_PER_SLICE 25 7059f9f09b0SDouglas Anderson #define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE) 7069f9f09b0SDouglas Anderson 7079f9f09b0SDouglas Anderson #define DWC2_ROUND_US_TO_SLICE(us) \ 7089f9f09b0SDouglas Anderson (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \ 7099f9f09b0SDouglas Anderson DWC2_US_PER_SLICE) 7109f9f09b0SDouglas Anderson 7119f9f09b0SDouglas Anderson #define DWC2_LS_PERIODIC_US_PER_FRAME \ 7129f9f09b0SDouglas Anderson 900 7139f9f09b0SDouglas Anderson #define DWC2_LS_PERIODIC_SLICES_PER_FRAME \ 7149f9f09b0SDouglas Anderson (DWC2_LS_PERIODIC_US_PER_FRAME / \ 7159f9f09b0SDouglas Anderson DWC2_US_PER_SLICE) 7169f9f09b0SDouglas Anderson 7179f9f09b0SDouglas Anderson #define DWC2_LS_SCHEDULE_FRAMES 1 7189f9f09b0SDouglas Anderson #define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \ 7199f9f09b0SDouglas Anderson DWC2_LS_PERIODIC_SLICES_PER_FRAME) 7209f9f09b0SDouglas Anderson 721d17ee77bSGregory Herrero /** 722197ba5f4SPaul Zimmerman * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 723197ba5f4SPaul Zimmerman * and periodic schedules 724197ba5f4SPaul Zimmerman * 725941fcce4SDinh Nguyen * These are common for both host and peripheral modes: 726941fcce4SDinh Nguyen * 727197ba5f4SPaul Zimmerman * @dev: The struct device pointer 728197ba5f4SPaul Zimmerman * @regs: Pointer to controller regs 729197ba5f4SPaul Zimmerman * @hw_params: Parameters that were autodetected from the 730197ba5f4SPaul Zimmerman * hardware registers 731941fcce4SDinh Nguyen * @core_params: Parameters that define how the core should be configured 732197ba5f4SPaul Zimmerman * @op_state: The operational State, during transitions (a_host=> 733197ba5f4SPaul Zimmerman * a_peripheral and b_device=>b_host) this may not match 734197ba5f4SPaul Zimmerman * the core, but allows the software to determine 735197ba5f4SPaul Zimmerman * transitions 736c0155b9dSKever Yang * @dr_mode: Requested mode of operation, one of following: 737c0155b9dSKever Yang * - USB_DR_MODE_PERIPHERAL 738c0155b9dSKever Yang * - USB_DR_MODE_HOST 739c0155b9dSKever Yang * - USB_DR_MODE_OTG 74009a75e85SMarek Szyprowski * @hcd_enabled Host mode sub-driver initialization indicator. 74109a75e85SMarek Szyprowski * @gadget_enabled Peripheral mode sub-driver initialization indicator. 74209a75e85SMarek Szyprowski * @ll_hw_enabled Status of low-level hardware resources. 74309a75e85SMarek Szyprowski * @phy: The otg phy transceiver structure for phy control. 74409a75e85SMarek Szyprowski * @uphy: The otg phy transceiver structure for old USB phy control. 74509a75e85SMarek Szyprowski * @plat: The platform specific configuration data. This can be removed once 74609a75e85SMarek Szyprowski * all SoCs support usb transceiver. 74709a75e85SMarek Szyprowski * @supplies: Definition of USB power supplies 74809a75e85SMarek Szyprowski * @phyif: PHY interface width 749941fcce4SDinh Nguyen * @lock: Spinlock that protects all the driver data structures 750941fcce4SDinh Nguyen * @priv: Stores a pointer to the struct usb_hcd 751197ba5f4SPaul Zimmerman * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 752197ba5f4SPaul Zimmerman * transfer are in process of being queued 753197ba5f4SPaul Zimmerman * @srp_success: Stores status of SRP request in the case of a FS PHY 754197ba5f4SPaul Zimmerman * with an I2C interface 755197ba5f4SPaul Zimmerman * @wq_otg: Workqueue object used for handling of some interrupts 756197ba5f4SPaul Zimmerman * @wf_otg: Work object for handling Connector ID Status Change 757197ba5f4SPaul Zimmerman * interrupt 758197ba5f4SPaul Zimmerman * @wkp_timer: Timer object for handling Wakeup Detected interrupt 759197ba5f4SPaul Zimmerman * @lx_state: Lx state of connected device 760d17ee77bSGregory Herrero * @gregs_backup: Backup of global registers during suspend 761d17ee77bSGregory Herrero * @dregs_backup: Backup of device registers during suspend 762d17ee77bSGregory Herrero * @hregs_backup: Backup of host registers during suspend 763941fcce4SDinh Nguyen * 764941fcce4SDinh Nguyen * These are for host mode: 765941fcce4SDinh Nguyen * 766197ba5f4SPaul Zimmerman * @flags: Flags for handling root port state changes 767197ba5f4SPaul Zimmerman * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 768197ba5f4SPaul Zimmerman * Transfers associated with these QHs are not currently 769197ba5f4SPaul Zimmerman * assigned to a host channel. 770197ba5f4SPaul Zimmerman * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 771197ba5f4SPaul Zimmerman * Transfers associated with these QHs are currently 772197ba5f4SPaul Zimmerman * assigned to a host channel. 773197ba5f4SPaul Zimmerman * @non_periodic_qh_ptr: Pointer to next QH to process in the active 774197ba5f4SPaul Zimmerman * non-periodic schedule 775197ba5f4SPaul Zimmerman * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 776197ba5f4SPaul Zimmerman * list of QHs for periodic transfers that are _not_ 777197ba5f4SPaul Zimmerman * scheduled for the next frame. Each QH in the list has an 778197ba5f4SPaul Zimmerman * interval counter that determines when it needs to be 779197ba5f4SPaul Zimmerman * scheduled for execution. This scheduling mechanism 780197ba5f4SPaul Zimmerman * allows only a simple calculation for periodic bandwidth 781197ba5f4SPaul Zimmerman * used (i.e. must assume that all periodic transfers may 782197ba5f4SPaul Zimmerman * need to execute in the same frame). However, it greatly 783197ba5f4SPaul Zimmerman * simplifies scheduling and should be sufficient for the 784197ba5f4SPaul Zimmerman * vast majority of OTG hosts, which need to connect to a 785197ba5f4SPaul Zimmerman * small number of peripherals at one time. Items move from 786197ba5f4SPaul Zimmerman * this list to periodic_sched_ready when the QH interval 787197ba5f4SPaul Zimmerman * counter is 0 at SOF. 788197ba5f4SPaul Zimmerman * @periodic_sched_ready: List of periodic QHs that are ready for execution in 789197ba5f4SPaul Zimmerman * the next frame, but have not yet been assigned to host 790197ba5f4SPaul Zimmerman * channels. Items move from this list to 791197ba5f4SPaul Zimmerman * periodic_sched_assigned as host channels become 792197ba5f4SPaul Zimmerman * available during the current frame. 793197ba5f4SPaul Zimmerman * @periodic_sched_assigned: List of periodic QHs to be executed in the next 794197ba5f4SPaul Zimmerman * frame that are assigned to host channels. Items move 795197ba5f4SPaul Zimmerman * from this list to periodic_sched_queued as the 796197ba5f4SPaul Zimmerman * transactions for the QH are queued to the DWC_otg 797197ba5f4SPaul Zimmerman * controller. 798197ba5f4SPaul Zimmerman * @periodic_sched_queued: List of periodic QHs that have been queued for 799197ba5f4SPaul Zimmerman * execution. Items move from this list to either 800197ba5f4SPaul Zimmerman * periodic_sched_inactive or periodic_sched_ready when the 801197ba5f4SPaul Zimmerman * channel associated with the transfer is released. If the 802197ba5f4SPaul Zimmerman * interval for the QH is 1, the item moves to 803197ba5f4SPaul Zimmerman * periodic_sched_ready because it must be rescheduled for 804197ba5f4SPaul Zimmerman * the next frame. Otherwise, the item moves to 805197ba5f4SPaul Zimmerman * periodic_sched_inactive. 806c9c8ac01SDouglas Anderson * @split_order: List keeping track of channels doing splits, in order. 807197ba5f4SPaul Zimmerman * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 808197ba5f4SPaul Zimmerman * This value is in microseconds per (micro)frame. The 809197ba5f4SPaul Zimmerman * assumption is that all periodic transfers may occur in 810197ba5f4SPaul Zimmerman * the same (micro)frame. 8119f9f09b0SDouglas Anderson * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the 8129f9f09b0SDouglas Anderson * host is in high speed mode; low speed schedules are 8139f9f09b0SDouglas Anderson * stored elsewhere since we need one per TT. 814197ba5f4SPaul Zimmerman * @frame_number: Frame number read from the core at SOF. The value ranges 815197ba5f4SPaul Zimmerman * from 0 to HFNUM_MAX_FRNUM. 816197ba5f4SPaul Zimmerman * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 817197ba5f4SPaul Zimmerman * SOF enable/disable. 818197ba5f4SPaul Zimmerman * @free_hc_list: Free host channels in the controller. This is a list of 819197ba5f4SPaul Zimmerman * struct dwc2_host_chan items. 820197ba5f4SPaul Zimmerman * @periodic_channels: Number of host channels assigned to periodic transfers. 821197ba5f4SPaul Zimmerman * Currently assuming that there is a dedicated host 822197ba5f4SPaul Zimmerman * channel for each periodic transaction and at least one 823197ba5f4SPaul Zimmerman * host channel is available for non-periodic transactions. 824197ba5f4SPaul Zimmerman * @non_periodic_channels: Number of host channels assigned to non-periodic 825197ba5f4SPaul Zimmerman * transfers 826197ba5f4SPaul Zimmerman * @available_host_channels Number of host channels available for the microframe 827197ba5f4SPaul Zimmerman * scheduler to use 828197ba5f4SPaul Zimmerman * @hc_ptr_array: Array of pointers to the host channel descriptors. 829197ba5f4SPaul Zimmerman * Allows accessing a host channel descriptor given the 830197ba5f4SPaul Zimmerman * host channel number. This is useful in interrupt 831197ba5f4SPaul Zimmerman * handlers. 832197ba5f4SPaul Zimmerman * @status_buf: Buffer used for data received during the status phase of 833197ba5f4SPaul Zimmerman * a control transfer. 834197ba5f4SPaul Zimmerman * @status_buf_dma: DMA address for status_buf 835197ba5f4SPaul Zimmerman * @start_work: Delayed work for handling host A-cable connection 836197ba5f4SPaul Zimmerman * @reset_work: Delayed work for handling a port reset 837197ba5f4SPaul Zimmerman * @otg_port: OTG port number 838197ba5f4SPaul Zimmerman * @frame_list: Frame list 839197ba5f4SPaul Zimmerman * @frame_list_dma: Frame list DMA address 84095105a99SGregory Herrero * @frame_list_sz: Frame list size 8413b5fcc9aSGregory Herrero * @desc_gen_cache: Kmem cache for generic descriptors 8423b5fcc9aSGregory Herrero * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors 843941fcce4SDinh Nguyen * 844941fcce4SDinh Nguyen * These are for peripheral mode: 845941fcce4SDinh Nguyen * 846941fcce4SDinh Nguyen * @driver: USB gadget driver 847941fcce4SDinh Nguyen * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 848941fcce4SDinh Nguyen * @num_of_eps: Number of available EPs (excluding EP0) 849941fcce4SDinh Nguyen * @debug_root: Root directrory for debugfs. 850941fcce4SDinh Nguyen * @debug_file: Main status file for debugfs. 8519e14d0a5SGregory Herrero * @debug_testmode: Testmode status file for debugfs. 852941fcce4SDinh Nguyen * @debug_fifo: FIFO status file for debugfs. 853941fcce4SDinh Nguyen * @ep0_reply: Request used for ep0 reply. 854941fcce4SDinh Nguyen * @ep0_buff: Buffer for EP0 reply data, if needed. 855941fcce4SDinh Nguyen * @ctrl_buff: Buffer for EP0 control requests. 856941fcce4SDinh Nguyen * @ctrl_req: Request for EP0 control packets. 857fe0b94abSMian Yousaf Kaukab * @ep0_state: EP0 control transfers state 8589e14d0a5SGregory Herrero * @test_mode: USB test mode requested by the host 859941fcce4SDinh Nguyen * @eps: The endpoints being supplied to the gadget framework 860edd74be8SGregory Herrero * @g_using_dma: Indicate if dma usage is enabled 8610a176279SGregory Herrero * @g_rx_fifo_sz: Contains rx fifo size value 8620a176279SGregory Herrero * @g_np_g_tx_fifo_sz: Contains Non-Periodic tx fifo size value 8630a176279SGregory Herrero * @g_tx_fifo_sz: Contains tx fifo size value per endpoints 864197ba5f4SPaul Zimmerman */ 865197ba5f4SPaul Zimmerman struct dwc2_hsotg { 866197ba5f4SPaul Zimmerman struct device *dev; 867197ba5f4SPaul Zimmerman void __iomem *regs; 868197ba5f4SPaul Zimmerman /** Params detected from hardware */ 869197ba5f4SPaul Zimmerman struct dwc2_hw_params hw_params; 870197ba5f4SPaul Zimmerman /** Params to actually use */ 871bea8e86cSJohn Youn struct dwc2_core_params params; 872197ba5f4SPaul Zimmerman enum usb_otg_state op_state; 873c0155b9dSKever Yang enum usb_dr_mode dr_mode; 874e39af88fSMarek Szyprowski unsigned int hcd_enabled:1; 875e39af88fSMarek Szyprowski unsigned int gadget_enabled:1; 87609a75e85SMarek Szyprowski unsigned int ll_hw_enabled:1; 877197ba5f4SPaul Zimmerman 878941fcce4SDinh Nguyen struct phy *phy; 879941fcce4SDinh Nguyen struct usb_phy *uphy; 88009a75e85SMarek Szyprowski struct dwc2_hsotg_plat *plat; 8811f91b4ccSFelipe Balbi struct regulator_bulk_data supplies[ARRAY_SIZE(dwc2_hsotg_supply_names)]; 88209a75e85SMarek Szyprowski u32 phyif; 883941fcce4SDinh Nguyen 884941fcce4SDinh Nguyen spinlock_t lock; 885941fcce4SDinh Nguyen void *priv; 886941fcce4SDinh Nguyen int irq; 887941fcce4SDinh Nguyen struct clk *clk; 88883f8da56SDinh Nguyen struct reset_control *reset; 889941fcce4SDinh Nguyen 890197ba5f4SPaul Zimmerman unsigned int queuing_high_bandwidth:1; 891197ba5f4SPaul Zimmerman unsigned int srp_success:1; 892197ba5f4SPaul Zimmerman 893197ba5f4SPaul Zimmerman struct workqueue_struct *wq_otg; 894197ba5f4SPaul Zimmerman struct work_struct wf_otg; 895197ba5f4SPaul Zimmerman struct timer_list wkp_timer; 896197ba5f4SPaul Zimmerman enum dwc2_lx_state lx_state; 897cc1e204cSMian Yousaf Kaukab struct dwc2_gregs_backup gr_backup; 898cc1e204cSMian Yousaf Kaukab struct dwc2_dregs_backup dr_backup; 899cc1e204cSMian Yousaf Kaukab struct dwc2_hregs_backup hr_backup; 900197ba5f4SPaul Zimmerman 901941fcce4SDinh Nguyen struct dentry *debug_root; 902563cf017SMian Yousaf Kaukab struct debugfs_regset32 *regset; 903941fcce4SDinh Nguyen 904941fcce4SDinh Nguyen /* DWC OTG HW Release versions */ 905941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_71a 0x4f54271a 906941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_90a 0x4f54290a 907941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_92a 0x4f54292a 908941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_94a 0x4f54294a 909941fcce4SDinh Nguyen #define DWC2_CORE_REV_3_00a 0x4f54300a 910fef6bc37SJohn Youn #define DWC2_CORE_REV_3_10a 0x4f54310a 911941fcce4SDinh Nguyen 912941fcce4SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 913197ba5f4SPaul Zimmerman union dwc2_hcd_internal_flags { 914197ba5f4SPaul Zimmerman u32 d32; 915197ba5f4SPaul Zimmerman struct { 916197ba5f4SPaul Zimmerman unsigned port_connect_status_change:1; 917197ba5f4SPaul Zimmerman unsigned port_connect_status:1; 918197ba5f4SPaul Zimmerman unsigned port_reset_change:1; 919197ba5f4SPaul Zimmerman unsigned port_enable_change:1; 920197ba5f4SPaul Zimmerman unsigned port_suspend_change:1; 921197ba5f4SPaul Zimmerman unsigned port_over_current_change:1; 922197ba5f4SPaul Zimmerman unsigned port_l1_change:1; 923fd4850cfSCharles Manning unsigned reserved:25; 924197ba5f4SPaul Zimmerman } b; 925197ba5f4SPaul Zimmerman } flags; 926197ba5f4SPaul Zimmerman 927197ba5f4SPaul Zimmerman struct list_head non_periodic_sched_inactive; 928197ba5f4SPaul Zimmerman struct list_head non_periodic_sched_active; 929197ba5f4SPaul Zimmerman struct list_head *non_periodic_qh_ptr; 930197ba5f4SPaul Zimmerman struct list_head periodic_sched_inactive; 931197ba5f4SPaul Zimmerman struct list_head periodic_sched_ready; 932197ba5f4SPaul Zimmerman struct list_head periodic_sched_assigned; 933197ba5f4SPaul Zimmerman struct list_head periodic_sched_queued; 934c9c8ac01SDouglas Anderson struct list_head split_order; 935197ba5f4SPaul Zimmerman u16 periodic_usecs; 9369f9f09b0SDouglas Anderson unsigned long hs_periodic_bitmap[ 9379f9f09b0SDouglas Anderson DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)]; 938197ba5f4SPaul Zimmerman u16 frame_number; 939197ba5f4SPaul Zimmerman u16 periodic_qh_count; 940734643dfSGregory Herrero bool bus_suspended; 941fbb9e22bSMian Yousaf Kaukab bool new_connection; 942197ba5f4SPaul Zimmerman 943483bb254SDouglas Anderson u16 last_frame_num; 944483bb254SDouglas Anderson 945197ba5f4SPaul Zimmerman #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 946197ba5f4SPaul Zimmerman #define FRAME_NUM_ARRAY_SIZE 1000 947197ba5f4SPaul Zimmerman u16 *frame_num_array; 948197ba5f4SPaul Zimmerman u16 *last_frame_num_array; 949197ba5f4SPaul Zimmerman int frame_num_idx; 950197ba5f4SPaul Zimmerman int dumped_frame_num_array; 951197ba5f4SPaul Zimmerman #endif 952197ba5f4SPaul Zimmerman 953197ba5f4SPaul Zimmerman struct list_head free_hc_list; 954197ba5f4SPaul Zimmerman int periodic_channels; 955197ba5f4SPaul Zimmerman int non_periodic_channels; 956197ba5f4SPaul Zimmerman int available_host_channels; 957197ba5f4SPaul Zimmerman struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 958197ba5f4SPaul Zimmerman u8 *status_buf; 959197ba5f4SPaul Zimmerman dma_addr_t status_buf_dma; 960197ba5f4SPaul Zimmerman #define DWC2_HCD_STATUS_BUF_SIZE 64 961197ba5f4SPaul Zimmerman 962197ba5f4SPaul Zimmerman struct delayed_work start_work; 963197ba5f4SPaul Zimmerman struct delayed_work reset_work; 964197ba5f4SPaul Zimmerman u8 otg_port; 965197ba5f4SPaul Zimmerman u32 *frame_list; 966197ba5f4SPaul Zimmerman dma_addr_t frame_list_dma; 96795105a99SGregory Herrero u32 frame_list_sz; 9683b5fcc9aSGregory Herrero struct kmem_cache *desc_gen_cache; 9693b5fcc9aSGregory Herrero struct kmem_cache *desc_hsisoc_cache; 970197ba5f4SPaul Zimmerman 971197ba5f4SPaul Zimmerman #ifdef DEBUG 972197ba5f4SPaul Zimmerman u32 frrem_samples; 973197ba5f4SPaul Zimmerman u64 frrem_accum; 974197ba5f4SPaul Zimmerman 975197ba5f4SPaul Zimmerman u32 hfnum_7_samples_a; 976197ba5f4SPaul Zimmerman u64 hfnum_7_frrem_accum_a; 977197ba5f4SPaul Zimmerman u32 hfnum_0_samples_a; 978197ba5f4SPaul Zimmerman u64 hfnum_0_frrem_accum_a; 979197ba5f4SPaul Zimmerman u32 hfnum_other_samples_a; 980197ba5f4SPaul Zimmerman u64 hfnum_other_frrem_accum_a; 981197ba5f4SPaul Zimmerman 982197ba5f4SPaul Zimmerman u32 hfnum_7_samples_b; 983197ba5f4SPaul Zimmerman u64 hfnum_7_frrem_accum_b; 984197ba5f4SPaul Zimmerman u32 hfnum_0_samples_b; 985197ba5f4SPaul Zimmerman u64 hfnum_0_frrem_accum_b; 986197ba5f4SPaul Zimmerman u32 hfnum_other_samples_b; 987197ba5f4SPaul Zimmerman u64 hfnum_other_frrem_accum_b; 988197ba5f4SPaul Zimmerman #endif 989941fcce4SDinh Nguyen #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ 990941fcce4SDinh Nguyen 991941fcce4SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 992941fcce4SDinh Nguyen /* Gadget structures */ 993941fcce4SDinh Nguyen struct usb_gadget_driver *driver; 994941fcce4SDinh Nguyen int fifo_mem; 995941fcce4SDinh Nguyen unsigned int dedicated_fifos:1; 996941fcce4SDinh Nguyen unsigned char num_of_eps; 997941fcce4SDinh Nguyen u32 fifo_map; 998941fcce4SDinh Nguyen 999941fcce4SDinh Nguyen struct usb_request *ep0_reply; 1000941fcce4SDinh Nguyen struct usb_request *ctrl_req; 10013f95001dSMian Yousaf Kaukab void *ep0_buff; 10023f95001dSMian Yousaf Kaukab void *ctrl_buff; 1003fe0b94abSMian Yousaf Kaukab enum dwc2_ep0_state ep0_state; 10049e14d0a5SGregory Herrero u8 test_mode; 1005941fcce4SDinh Nguyen 1006941fcce4SDinh Nguyen struct usb_gadget gadget; 1007dc6e69e6SMarek Szyprowski unsigned int enabled:1; 10084ace06e8SMarek Szyprowski unsigned int connected:1; 10091f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS]; 10101f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS]; 1011edd74be8SGregory Herrero u32 g_using_dma; 10120a176279SGregory Herrero u32 g_rx_fifo_sz; 10130a176279SGregory Herrero u32 g_np_g_tx_fifo_sz; 10140a176279SGregory Herrero u32 g_tx_fifo_sz[MAX_EPS_CHANNELS]; 1015941fcce4SDinh Nguyen #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 1016197ba5f4SPaul Zimmerman }; 1017197ba5f4SPaul Zimmerman 1018197ba5f4SPaul Zimmerman /* Reasons for halting a host channel */ 1019197ba5f4SPaul Zimmerman enum dwc2_halt_status { 1020197ba5f4SPaul Zimmerman DWC2_HC_XFER_NO_HALT_STATUS, 1021197ba5f4SPaul Zimmerman DWC2_HC_XFER_COMPLETE, 1022197ba5f4SPaul Zimmerman DWC2_HC_XFER_URB_COMPLETE, 1023197ba5f4SPaul Zimmerman DWC2_HC_XFER_ACK, 1024197ba5f4SPaul Zimmerman DWC2_HC_XFER_NAK, 1025197ba5f4SPaul Zimmerman DWC2_HC_XFER_NYET, 1026197ba5f4SPaul Zimmerman DWC2_HC_XFER_STALL, 1027197ba5f4SPaul Zimmerman DWC2_HC_XFER_XACT_ERR, 1028197ba5f4SPaul Zimmerman DWC2_HC_XFER_FRAME_OVERRUN, 1029197ba5f4SPaul Zimmerman DWC2_HC_XFER_BABBLE_ERR, 1030197ba5f4SPaul Zimmerman DWC2_HC_XFER_DATA_TOGGLE_ERR, 1031197ba5f4SPaul Zimmerman DWC2_HC_XFER_AHB_ERR, 1032197ba5f4SPaul Zimmerman DWC2_HC_XFER_PERIODIC_INCOMPLETE, 1033197ba5f4SPaul Zimmerman DWC2_HC_XFER_URB_DEQUEUE, 1034197ba5f4SPaul Zimmerman }; 1035197ba5f4SPaul Zimmerman 1036197ba5f4SPaul Zimmerman /* 1037197ba5f4SPaul Zimmerman * The following functions support initialization of the core driver component 1038197ba5f4SPaul Zimmerman * and the DWC_otg controller 1039197ba5f4SPaul Zimmerman */ 1040b5d308abSJohn Youn extern int dwc2_core_reset(struct dwc2_hsotg *hsotg); 10416d58f346SJohn Youn extern int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg); 1042d17ee77bSGregory Herrero extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg); 1043d17ee77bSGregory Herrero extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore); 1044197ba5f4SPaul Zimmerman 1045323230efSJohn Youn bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host); 1046323230efSJohn Youn void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg); 104709c96980SJohn Youn void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg); 104809c96980SJohn Youn 1049197ba5f4SPaul Zimmerman extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 1050197ba5f4SPaul Zimmerman 1051197ba5f4SPaul Zimmerman /* 1052197ba5f4SPaul Zimmerman * Common core Functions. 1053197ba5f4SPaul Zimmerman * The following functions support managing the DWC_otg controller in either 1054197ba5f4SPaul Zimmerman * device or host mode. 1055197ba5f4SPaul Zimmerman */ 1056197ba5f4SPaul Zimmerman extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 1057197ba5f4SPaul Zimmerman extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 1058197ba5f4SPaul Zimmerman extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 1059197ba5f4SPaul Zimmerman 1060197ba5f4SPaul Zimmerman extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 1061197ba5f4SPaul Zimmerman extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 1062197ba5f4SPaul Zimmerman 1063197ba5f4SPaul Zimmerman /* This function should be called on every hardware interrupt. */ 1064197ba5f4SPaul Zimmerman extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 1065197ba5f4SPaul Zimmerman 1066323230efSJohn Youn /* The device ID match table */ 1067323230efSJohn Youn extern const struct of_device_id dwc2_of_match_table[]; 1068323230efSJohn Youn 106909a75e85SMarek Szyprowski extern int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg); 107009a75e85SMarek Szyprowski extern int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg); 1071ecb176c6SMian Yousaf Kaukab 1072334bbd4eSJohn Youn /* Parameters */ 1073c1d286cfSJohn Youn int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); 1074334bbd4eSJohn Youn int dwc2_init_params(struct dwc2_hsotg *hsotg); 1075334bbd4eSJohn Youn 1076197ba5f4SPaul Zimmerman /* 10776bea9620SJohn Youn * The following functions check the controller's OTG operation mode 10786bea9620SJohn Youn * capability (GHWCFG2.OTG_MODE). 10796bea9620SJohn Youn * 10806bea9620SJohn Youn * These functions can be used before the internal hsotg->hw_params 10816bea9620SJohn Youn * are read in and cached so they always read directly from the 10826bea9620SJohn Youn * GHWCFG2 register. 10836bea9620SJohn Youn */ 10846bea9620SJohn Youn unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg); 10856bea9620SJohn Youn bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg); 10866bea9620SJohn Youn bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg); 10876bea9620SJohn Youn bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg); 10886bea9620SJohn Youn 10896bea9620SJohn Youn /* 10901696d5abSJohn Youn * Returns the mode of operation, host or device 10911696d5abSJohn Youn */ 10921696d5abSJohn Youn static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) 10931696d5abSJohn Youn { 10941696d5abSJohn Youn return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0; 10951696d5abSJohn Youn } 10961696d5abSJohn Youn static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) 10971696d5abSJohn Youn { 10981696d5abSJohn Youn return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0; 10991696d5abSJohn Youn } 11001696d5abSJohn Youn 11011696d5abSJohn Youn /* 1102197ba5f4SPaul Zimmerman * Dump core registers and SPRAM 1103197ba5f4SPaul Zimmerman */ 1104197ba5f4SPaul Zimmerman extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 1105197ba5f4SPaul Zimmerman extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 1106197ba5f4SPaul Zimmerman extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 1107197ba5f4SPaul Zimmerman 1108197ba5f4SPaul Zimmerman /* 1109197ba5f4SPaul Zimmerman * Return OTG version - either 1.3 or 2.0 1110197ba5f4SPaul Zimmerman */ 1111197ba5f4SPaul Zimmerman extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg); 1112197ba5f4SPaul Zimmerman 1113117777b2SDinh Nguyen /* Gadget defines */ 1114117777b2SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 11151f91b4ccSFelipe Balbi extern int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg); 11161f91b4ccSFelipe Balbi extern int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2); 11171f91b4ccSFelipe Balbi extern int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2); 1118117777b2SDinh Nguyen extern int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq); 11191f91b4ccSFelipe Balbi extern void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1120643cc4deSGregory Herrero bool reset); 11211f91b4ccSFelipe Balbi extern void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg); 11221f91b4ccSFelipe Balbi extern void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2); 11231f91b4ccSFelipe Balbi extern int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode); 1124f81f46e1SGregory Herrero #define dwc2_is_device_connected(hsotg) (hsotg->connected) 112558e52ff6SJohn Youn int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg); 112658e52ff6SJohn Youn int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg); 1127117777b2SDinh Nguyen #else 11281f91b4ccSFelipe Balbi static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2) 1129117777b2SDinh Nguyen { return 0; } 11301f91b4ccSFelipe Balbi static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2) 1131117777b2SDinh Nguyen { return 0; } 11321f91b4ccSFelipe Balbi static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2) 1133117777b2SDinh Nguyen { return 0; } 1134117777b2SDinh Nguyen static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) 1135117777b2SDinh Nguyen { return 0; } 11361f91b4ccSFelipe Balbi static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1137643cc4deSGregory Herrero bool reset) {} 11381f91b4ccSFelipe Balbi static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} 11391f91b4ccSFelipe Balbi static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} 11401f91b4ccSFelipe Balbi static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, 1141f91eea44SMian Yousaf Kaukab int testmode) 1142f91eea44SMian Yousaf Kaukab { return 0; } 1143f81f46e1SGregory Herrero #define dwc2_is_device_connected(hsotg) (0) 114458e52ff6SJohn Youn static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) 114558e52ff6SJohn Youn { return 0; } 114658e52ff6SJohn Youn static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg) 114758e52ff6SJohn Youn { return 0; } 1148117777b2SDinh Nguyen #endif 1149117777b2SDinh Nguyen 1150117777b2SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1151117777b2SDinh Nguyen extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 1152fae4e826SDouglas Anderson extern int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us); 11536a659531SDouglas Anderson extern void dwc2_hcd_connect(struct dwc2_hsotg *hsotg); 11546a659531SDouglas Anderson extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force); 1155117777b2SDinh Nguyen extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 115658e52ff6SJohn Youn int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg); 115758e52ff6SJohn Youn int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg); 1158117777b2SDinh Nguyen #else 1159117777b2SDinh Nguyen static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1160117777b2SDinh Nguyen { return 0; } 1161fae4e826SDouglas Anderson static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, 1162fae4e826SDouglas Anderson int us) 1163fae4e826SDouglas Anderson { return 0; } 11646a659531SDouglas Anderson static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {} 11656a659531SDouglas Anderson static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {} 1166117777b2SDinh Nguyen static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} 1167117777b2SDinh Nguyen static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} 1168ecb176c6SMian Yousaf Kaukab static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) 1169117777b2SDinh Nguyen { return 0; } 117058e52ff6SJohn Youn static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 117158e52ff6SJohn Youn { return 0; } 117258e52ff6SJohn Youn static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 117358e52ff6SJohn Youn { return 0; } 117458e52ff6SJohn Youn 1175117777b2SDinh Nguyen #endif 1176117777b2SDinh Nguyen 1177197ba5f4SPaul Zimmerman #endif /* __DWC2_CORE_H__ */ 1178