1197ba5f4SPaul Zimmerman /* 2197ba5f4SPaul Zimmerman * core.h - DesignWare HS OTG Controller common declarations 3197ba5f4SPaul Zimmerman * 4197ba5f4SPaul Zimmerman * Copyright (C) 2004-2013 Synopsys, Inc. 5197ba5f4SPaul Zimmerman * 6197ba5f4SPaul Zimmerman * Redistribution and use in source and binary forms, with or without 7197ba5f4SPaul Zimmerman * modification, are permitted provided that the following conditions 8197ba5f4SPaul Zimmerman * are met: 9197ba5f4SPaul Zimmerman * 1. Redistributions of source code must retain the above copyright 10197ba5f4SPaul Zimmerman * notice, this list of conditions, and the following disclaimer, 11197ba5f4SPaul Zimmerman * without modification. 12197ba5f4SPaul Zimmerman * 2. Redistributions in binary form must reproduce the above copyright 13197ba5f4SPaul Zimmerman * notice, this list of conditions and the following disclaimer in the 14197ba5f4SPaul Zimmerman * documentation and/or other materials provided with the distribution. 15197ba5f4SPaul Zimmerman * 3. The names of the above-listed copyright holders may not be used 16197ba5f4SPaul Zimmerman * to endorse or promote products derived from this software without 17197ba5f4SPaul Zimmerman * specific prior written permission. 18197ba5f4SPaul Zimmerman * 19197ba5f4SPaul Zimmerman * ALTERNATIVELY, this software may be distributed under the terms of the 20197ba5f4SPaul Zimmerman * GNU General Public License ("GPL") as published by the Free Software 21197ba5f4SPaul Zimmerman * Foundation; either version 2 of the License, or (at your option) any 22197ba5f4SPaul Zimmerman * later version. 23197ba5f4SPaul Zimmerman * 24197ba5f4SPaul Zimmerman * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25197ba5f4SPaul Zimmerman * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26197ba5f4SPaul Zimmerman * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27197ba5f4SPaul Zimmerman * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28197ba5f4SPaul Zimmerman * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29197ba5f4SPaul Zimmerman * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30197ba5f4SPaul Zimmerman * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31197ba5f4SPaul Zimmerman * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32197ba5f4SPaul Zimmerman * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33197ba5f4SPaul Zimmerman * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34197ba5f4SPaul Zimmerman * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35197ba5f4SPaul Zimmerman */ 36197ba5f4SPaul Zimmerman 37197ba5f4SPaul Zimmerman #ifndef __DWC2_CORE_H__ 38197ba5f4SPaul Zimmerman #define __DWC2_CORE_H__ 39197ba5f4SPaul Zimmerman 40f7c0b143SDinh Nguyen #include <linux/phy/phy.h> 41f7c0b143SDinh Nguyen #include <linux/regulator/consumer.h> 42f7c0b143SDinh Nguyen #include <linux/usb/gadget.h> 43f7c0b143SDinh Nguyen #include <linux/usb/otg.h> 44197ba5f4SPaul Zimmerman #include <linux/usb/phy.h> 45197ba5f4SPaul Zimmerman #include "hw.h" 46197ba5f4SPaul Zimmerman 4774fc4a75SDouglas Anderson /* 4874fc4a75SDouglas Anderson * Suggested defines for tracers: 4974fc4a75SDouglas Anderson * - no_printk: Disable tracing 5074fc4a75SDouglas Anderson * - pr_info: Print this info to the console 5174fc4a75SDouglas Anderson * - trace_printk: Print this info to trace buffer (good for verbose logging) 5274fc4a75SDouglas Anderson */ 5374fc4a75SDouglas Anderson 5474fc4a75SDouglas Anderson #define DWC2_TRACE_SCHEDULER no_printk 5574fc4a75SDouglas Anderson #define DWC2_TRACE_SCHEDULER_VB no_printk 5674fc4a75SDouglas Anderson 5774fc4a75SDouglas Anderson /* Detailed scheduler tracing, but won't overwhelm console */ 5874fc4a75SDouglas Anderson #define dwc2_sch_dbg(hsotg, fmt, ...) \ 5974fc4a75SDouglas Anderson DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \ 6074fc4a75SDouglas Anderson dev_name(hsotg->dev), ##__VA_ARGS__) 6174fc4a75SDouglas Anderson 6274fc4a75SDouglas Anderson /* Verbose scheduler tracing */ 6374fc4a75SDouglas Anderson #define dwc2_sch_vdbg(hsotg, fmt, ...) \ 6474fc4a75SDouglas Anderson DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \ 6574fc4a75SDouglas Anderson dev_name(hsotg->dev), ##__VA_ARGS__) 6674fc4a75SDouglas Anderson 6723e34392SArnd Bergmann #ifdef CONFIG_MIPS 6823e34392SArnd Bergmann /* 6923e34392SArnd Bergmann * There are some MIPS machines that can run in either big-endian 7023e34392SArnd Bergmann * or little-endian mode and that use the dwc2 register without 7123e34392SArnd Bergmann * a byteswap in both ways. 7223e34392SArnd Bergmann * Unlike other architectures, MIPS apparently does not require a 7323e34392SArnd Bergmann * barrier before the __raw_writel() to synchronize with DMA but does 7423e34392SArnd Bergmann * require the barrier after the __raw_writel() to serialize a set of 7523e34392SArnd Bergmann * writes. This set of operations was added specifically for MIPS and 7623e34392SArnd Bergmann * should only be used there. 7723e34392SArnd Bergmann */ 7895c8bc36SAntti Seppälä static inline u32 dwc2_readl(const void __iomem *addr) 79197ba5f4SPaul Zimmerman { 8095c8bc36SAntti Seppälä u32 value = __raw_readl(addr); 8195c8bc36SAntti Seppälä 8295c8bc36SAntti Seppälä /* In order to preserve endianness __raw_* operation is used. Therefore 8395c8bc36SAntti Seppälä * a barrier is needed to ensure IO access is not re-ordered across 8495c8bc36SAntti Seppälä * reads or writes 8595c8bc36SAntti Seppälä */ 8695c8bc36SAntti Seppälä mb(); 8795c8bc36SAntti Seppälä return value; 88197ba5f4SPaul Zimmerman } 89197ba5f4SPaul Zimmerman 9095c8bc36SAntti Seppälä static inline void dwc2_writel(u32 value, void __iomem *addr) 9195c8bc36SAntti Seppälä { 9295c8bc36SAntti Seppälä __raw_writel(value, addr); 9395c8bc36SAntti Seppälä 9495c8bc36SAntti Seppälä /* 9595c8bc36SAntti Seppälä * In order to preserve endianness __raw_* operation is used. Therefore 9695c8bc36SAntti Seppälä * a barrier is needed to ensure IO access is not re-ordered across 9795c8bc36SAntti Seppälä * reads or writes 9895c8bc36SAntti Seppälä */ 9995c8bc36SAntti Seppälä mb(); 10095c8bc36SAntti Seppälä #ifdef DWC2_LOG_WRITES 10195c8bc36SAntti Seppälä pr_info("INFO:: wrote %08x to %p\n", value, addr); 102197ba5f4SPaul Zimmerman #endif 10395c8bc36SAntti Seppälä } 10423e34392SArnd Bergmann #else 10523e34392SArnd Bergmann /* Normal architectures just use readl/write */ 10623e34392SArnd Bergmann static inline u32 dwc2_readl(const void __iomem *addr) 10723e34392SArnd Bergmann { 10823e34392SArnd Bergmann return readl(addr); 10923e34392SArnd Bergmann } 11023e34392SArnd Bergmann 11123e34392SArnd Bergmann static inline void dwc2_writel(u32 value, void __iomem *addr) 11223e34392SArnd Bergmann { 11323e34392SArnd Bergmann writel(value, addr); 11423e34392SArnd Bergmann 11523e34392SArnd Bergmann #ifdef DWC2_LOG_WRITES 11623e34392SArnd Bergmann pr_info("info:: wrote %08x to %p\n", value, addr); 11723e34392SArnd Bergmann #endif 11823e34392SArnd Bergmann } 11923e34392SArnd Bergmann #endif 120197ba5f4SPaul Zimmerman 121197ba5f4SPaul Zimmerman /* Maximum number of Endpoints/HostChannels */ 122197ba5f4SPaul Zimmerman #define MAX_EPS_CHANNELS 16 123197ba5f4SPaul Zimmerman 1241f91b4ccSFelipe Balbi /* dwc2-hsotg declarations */ 1251f91b4ccSFelipe Balbi static const char * const dwc2_hsotg_supply_names[] = { 126f7c0b143SDinh Nguyen "vusb_d", /* digital USB supply, 1.2V */ 127f7c0b143SDinh Nguyen "vusb_a", /* analog USB supply, 1.1V */ 128f7c0b143SDinh Nguyen }; 129f7c0b143SDinh Nguyen 130f7c0b143SDinh Nguyen /* 131f7c0b143SDinh Nguyen * EP0_MPS_LIMIT 132f7c0b143SDinh Nguyen * 133f7c0b143SDinh Nguyen * Unfortunately there seems to be a limit of the amount of data that can 134f7c0b143SDinh Nguyen * be transferred by IN transactions on EP0. This is either 127 bytes or 3 135f7c0b143SDinh Nguyen * packets (which practically means 1 packet and 63 bytes of data) when the 136f7c0b143SDinh Nguyen * MPS is set to 64. 137f7c0b143SDinh Nguyen * 138f7c0b143SDinh Nguyen * This means if we are wanting to move >127 bytes of data, we need to 139f7c0b143SDinh Nguyen * split the transactions up, but just doing one packet at a time does 140f7c0b143SDinh Nguyen * not work (this may be an implicit DATA0 PID on first packet of the 141f7c0b143SDinh Nguyen * transaction) and doing 2 packets is outside the controller's limits. 142f7c0b143SDinh Nguyen * 143f7c0b143SDinh Nguyen * If we try to lower the MPS size for EP0, then no transfers work properly 144f7c0b143SDinh Nguyen * for EP0, and the system will fail basic enumeration. As no cause for this 145f7c0b143SDinh Nguyen * has currently been found, we cannot support any large IN transfers for 146f7c0b143SDinh Nguyen * EP0. 147f7c0b143SDinh Nguyen */ 148f7c0b143SDinh Nguyen #define EP0_MPS_LIMIT 64 149f7c0b143SDinh Nguyen 150941fcce4SDinh Nguyen struct dwc2_hsotg; 1511f91b4ccSFelipe Balbi struct dwc2_hsotg_req; 152f7c0b143SDinh Nguyen 153f7c0b143SDinh Nguyen /** 1541f91b4ccSFelipe Balbi * struct dwc2_hsotg_ep - driver endpoint definition. 155f7c0b143SDinh Nguyen * @ep: The gadget layer representation of the endpoint. 156f7c0b143SDinh Nguyen * @name: The driver generated name for the endpoint. 157f7c0b143SDinh Nguyen * @queue: Queue of requests for this endpoint. 158f7c0b143SDinh Nguyen * @parent: Reference back to the parent device structure. 159f7c0b143SDinh Nguyen * @req: The current request that the endpoint is processing. This is 160f7c0b143SDinh Nguyen * used to indicate an request has been loaded onto the endpoint 161f7c0b143SDinh Nguyen * and has yet to be completed (maybe due to data move, or simply 162f7c0b143SDinh Nguyen * awaiting an ack from the core all the data has been completed). 163f7c0b143SDinh Nguyen * @debugfs: File entry for debugfs file for this endpoint. 164f7c0b143SDinh Nguyen * @lock: State lock to protect contents of endpoint. 165f7c0b143SDinh Nguyen * @dir_in: Set to true if this endpoint is of the IN direction, which 166f7c0b143SDinh Nguyen * means that it is sending data to the Host. 167f7c0b143SDinh Nguyen * @index: The index for the endpoint registers. 168f7c0b143SDinh Nguyen * @mc: Multi Count - number of transactions per microframe 169142bd33fSVardan Mikayelyan * @interval - Interval for periodic endpoints, in frames or microframes. 170f7c0b143SDinh Nguyen * @name: The name array passed to the USB core. 171f7c0b143SDinh Nguyen * @halted: Set if the endpoint has been halted. 172f7c0b143SDinh Nguyen * @periodic: Set if this is a periodic ep, such as Interrupt 173f7c0b143SDinh Nguyen * @isochronous: Set if this is a isochronous ep 1748a20fa45SMian Yousaf Kaukab * @send_zlp: Set if we need to send a zero-length packet. 175f7c0b143SDinh Nguyen * @total_data: The total number of data bytes done. 176f7c0b143SDinh Nguyen * @fifo_size: The size of the FIFO (for periodic IN endpoints) 177f7c0b143SDinh Nguyen * @fifo_load: The amount of data loaded into the FIFO (periodic IN) 178f7c0b143SDinh Nguyen * @last_load: The offset of data for the last start of request. 179f7c0b143SDinh Nguyen * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN 18092d1635dSVardan Mikayelyan * @target_frame: Targeted frame num to setup next ISOC transfer 18192d1635dSVardan Mikayelyan * @frame_overrun: Indicates SOF number overrun in DSTS 182f7c0b143SDinh Nguyen * 183f7c0b143SDinh Nguyen * This is the driver's state for each registered enpoint, allowing it 184f7c0b143SDinh Nguyen * to keep track of transactions that need doing. Each endpoint has a 185f7c0b143SDinh Nguyen * lock to protect the state, to try and avoid using an overall lock 186f7c0b143SDinh Nguyen * for the host controller as much as possible. 187f7c0b143SDinh Nguyen * 188f7c0b143SDinh Nguyen * For periodic IN endpoints, we have fifo_size and fifo_load to try 189f7c0b143SDinh Nguyen * and keep track of the amount of data in the periodic FIFO for each 190f7c0b143SDinh Nguyen * of these as we don't have a status register that tells us how much 191f7c0b143SDinh Nguyen * is in each of them. (note, this may actually be useless information 192f7c0b143SDinh Nguyen * as in shared-fifo mode periodic in acts like a single-frame packet 193f7c0b143SDinh Nguyen * buffer than a fifo) 194f7c0b143SDinh Nguyen */ 1951f91b4ccSFelipe Balbi struct dwc2_hsotg_ep { 196f7c0b143SDinh Nguyen struct usb_ep ep; 197f7c0b143SDinh Nguyen struct list_head queue; 198941fcce4SDinh Nguyen struct dwc2_hsotg *parent; 1991f91b4ccSFelipe Balbi struct dwc2_hsotg_req *req; 200f7c0b143SDinh Nguyen struct dentry *debugfs; 201f7c0b143SDinh Nguyen 202f7c0b143SDinh Nguyen unsigned long total_data; 203f7c0b143SDinh Nguyen unsigned int size_loaded; 204f7c0b143SDinh Nguyen unsigned int last_load; 205f7c0b143SDinh Nguyen unsigned int fifo_load; 206f7c0b143SDinh Nguyen unsigned short fifo_size; 207b203d0a2SRobert Baldyga unsigned short fifo_index; 208f7c0b143SDinh Nguyen 209f7c0b143SDinh Nguyen unsigned char dir_in; 210f7c0b143SDinh Nguyen unsigned char index; 211f7c0b143SDinh Nguyen unsigned char mc; 212f7c0b143SDinh Nguyen unsigned char interval; 213f7c0b143SDinh Nguyen 214f7c0b143SDinh Nguyen unsigned int halted:1; 215f7c0b143SDinh Nguyen unsigned int periodic:1; 216f7c0b143SDinh Nguyen unsigned int isochronous:1; 2178a20fa45SMian Yousaf Kaukab unsigned int send_zlp:1; 21892d1635dSVardan Mikayelyan unsigned int target_frame; 21992d1635dSVardan Mikayelyan #define TARGET_FRAME_INITIAL 0xFFFFFFFF 22092d1635dSVardan Mikayelyan bool frame_overrun; 221f7c0b143SDinh Nguyen 222f7c0b143SDinh Nguyen char name[10]; 223f7c0b143SDinh Nguyen }; 224f7c0b143SDinh Nguyen 225f7c0b143SDinh Nguyen /** 2261f91b4ccSFelipe Balbi * struct dwc2_hsotg_req - data transfer request 227f7c0b143SDinh Nguyen * @req: The USB gadget request 228f7c0b143SDinh Nguyen * @queue: The list of requests for the endpoint this is queued for. 2297d24c1b5SMian Yousaf Kaukab * @saved_req_buf: variable to save req.buf when bounce buffers are used. 230f7c0b143SDinh Nguyen */ 2311f91b4ccSFelipe Balbi struct dwc2_hsotg_req { 232f7c0b143SDinh Nguyen struct usb_request req; 233f7c0b143SDinh Nguyen struct list_head queue; 2347d24c1b5SMian Yousaf Kaukab void *saved_req_buf; 235f7c0b143SDinh Nguyen }; 236f7c0b143SDinh Nguyen 237941fcce4SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 238f7c0b143SDinh Nguyen #define call_gadget(_hs, _entry) \ 239f7c0b143SDinh Nguyen do { \ 240f7c0b143SDinh Nguyen if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ 241f7c0b143SDinh Nguyen (_hs)->driver && (_hs)->driver->_entry) { \ 242f7c0b143SDinh Nguyen spin_unlock(&_hs->lock); \ 243f7c0b143SDinh Nguyen (_hs)->driver->_entry(&(_hs)->gadget); \ 244f7c0b143SDinh Nguyen spin_lock(&_hs->lock); \ 245f7c0b143SDinh Nguyen } \ 246f7c0b143SDinh Nguyen } while (0) 247941fcce4SDinh Nguyen #else 248941fcce4SDinh Nguyen #define call_gadget(_hs, _entry) do {} while (0) 249941fcce4SDinh Nguyen #endif 250f7c0b143SDinh Nguyen 251197ba5f4SPaul Zimmerman struct dwc2_hsotg; 252197ba5f4SPaul Zimmerman struct dwc2_host_chan; 253197ba5f4SPaul Zimmerman 254197ba5f4SPaul Zimmerman /* Device States */ 255197ba5f4SPaul Zimmerman enum dwc2_lx_state { 256197ba5f4SPaul Zimmerman DWC2_L0, /* On state */ 257197ba5f4SPaul Zimmerman DWC2_L1, /* LPM sleep state */ 258197ba5f4SPaul Zimmerman DWC2_L2, /* USB suspend state */ 259197ba5f4SPaul Zimmerman DWC2_L3, /* Off state */ 260197ba5f4SPaul Zimmerman }; 261197ba5f4SPaul Zimmerman 2623fa95385SJohn Youn /* 2633fa95385SJohn Youn * Gadget periodic tx fifo sizes as used by legacy driver 2643fa95385SJohn Youn * EP0 is not included 2653fa95385SJohn Youn */ 2663fa95385SJohn Youn #define DWC2_G_P_LEGACY_TX_FIFO_SIZE {256, 256, 256, 256, 768, 768, 768, \ 2673fa95385SJohn Youn 768, 0, 0, 0, 0, 0, 0, 0} 2683fa95385SJohn Youn 269fe0b94abSMian Yousaf Kaukab /* Gadget ep0 states */ 270fe0b94abSMian Yousaf Kaukab enum dwc2_ep0_state { 271fe0b94abSMian Yousaf Kaukab DWC2_EP0_SETUP, 272fe0b94abSMian Yousaf Kaukab DWC2_EP0_DATA_IN, 273fe0b94abSMian Yousaf Kaukab DWC2_EP0_DATA_OUT, 274fe0b94abSMian Yousaf Kaukab DWC2_EP0_STATUS_IN, 275fe0b94abSMian Yousaf Kaukab DWC2_EP0_STATUS_OUT, 276fe0b94abSMian Yousaf Kaukab }; 277fe0b94abSMian Yousaf Kaukab 278197ba5f4SPaul Zimmerman /** 279197ba5f4SPaul Zimmerman * struct dwc2_core_params - Parameters for configuring the core 280197ba5f4SPaul Zimmerman * 281197ba5f4SPaul Zimmerman * @otg_cap: Specifies the OTG capabilities. 282197ba5f4SPaul Zimmerman * 0 - HNP and SRP capable 283197ba5f4SPaul Zimmerman * 1 - SRP Only capable 284197ba5f4SPaul Zimmerman * 2 - No HNP/SRP capable (always available) 285197ba5f4SPaul Zimmerman * Defaults to best available option (0, 1, then 2) 286197ba5f4SPaul Zimmerman * @otg_ver: OTG version supported 287197ba5f4SPaul Zimmerman * 0 - 1.3 (default) 288197ba5f4SPaul Zimmerman * 1 - 2.0 289197ba5f4SPaul Zimmerman * @dma_enable: Specifies whether to use slave or DMA mode for accessing 290197ba5f4SPaul Zimmerman * the data FIFOs. The driver will automatically detect the 291197ba5f4SPaul Zimmerman * value for this parameter if none is specified. 292197ba5f4SPaul Zimmerman * 0 - Slave (always available) 293197ba5f4SPaul Zimmerman * 1 - DMA (default, if available) 294197ba5f4SPaul Zimmerman * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 295197ba5f4SPaul Zimmerman * address DMA mode or descriptor DMA mode for accessing 296197ba5f4SPaul Zimmerman * the data FIFOs. The driver will automatically detect the 297197ba5f4SPaul Zimmerman * value for this if none is specified. 298197ba5f4SPaul Zimmerman * 0 - Address DMA 299197ba5f4SPaul Zimmerman * 1 - Descriptor DMA (default, if available) 300fbb9e22bSMian Yousaf Kaukab * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use 301fbb9e22bSMian Yousaf Kaukab * address DMA mode or descriptor DMA mode for accessing 302fbb9e22bSMian Yousaf Kaukab * the data FIFOs in Full Speed mode only. The driver 303fbb9e22bSMian Yousaf Kaukab * will automatically detect the value for this if none is 304fbb9e22bSMian Yousaf Kaukab * specified. 305fbb9e22bSMian Yousaf Kaukab * 0 - Address DMA 306fbb9e22bSMian Yousaf Kaukab * 1 - Descriptor DMA in FS (default, if available) 307197ba5f4SPaul Zimmerman * @speed: Specifies the maximum speed of operation in host and 308197ba5f4SPaul Zimmerman * device mode. The actual speed depends on the speed of 309197ba5f4SPaul Zimmerman * the attached device and the value of phy_type. 310197ba5f4SPaul Zimmerman * 0 - High Speed 311197ba5f4SPaul Zimmerman * (default when phy_type is UTMI+ or ULPI) 312197ba5f4SPaul Zimmerman * 1 - Full Speed 313197ba5f4SPaul Zimmerman * (default when phy_type is Full Speed) 314197ba5f4SPaul Zimmerman * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 315197ba5f4SPaul Zimmerman * 1 - Allow dynamic FIFO sizing (default, if available) 316197ba5f4SPaul Zimmerman * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 317197ba5f4SPaul Zimmerman * are enabled 318197ba5f4SPaul Zimmerman * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 319197ba5f4SPaul Zimmerman * dynamic FIFO sizing is enabled 320197ba5f4SPaul Zimmerman * 16 to 32768 321197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 322197ba5f4SPaul Zimmerman * the default. 323197ba5f4SPaul Zimmerman * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 324197ba5f4SPaul Zimmerman * in host mode when dynamic FIFO sizing is enabled 325197ba5f4SPaul Zimmerman * 16 to 32768 326197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 327197ba5f4SPaul Zimmerman * the default. 328197ba5f4SPaul Zimmerman * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 329197ba5f4SPaul Zimmerman * host mode when dynamic FIFO sizing is enabled 330197ba5f4SPaul Zimmerman * 16 to 32768 331197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 332197ba5f4SPaul Zimmerman * the default. 333197ba5f4SPaul Zimmerman * @max_transfer_size: The maximum transfer size supported, in bytes 334197ba5f4SPaul Zimmerman * 2047 to 65,535 335197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 336197ba5f4SPaul Zimmerman * the default. 337197ba5f4SPaul Zimmerman * @max_packet_count: The maximum number of packets in a transfer 338197ba5f4SPaul Zimmerman * 15 to 511 339197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 340197ba5f4SPaul Zimmerman * the default. 341197ba5f4SPaul Zimmerman * @host_channels: The number of host channel registers to use 342197ba5f4SPaul Zimmerman * 1 to 16 343197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 344197ba5f4SPaul Zimmerman * the default. 345197ba5f4SPaul Zimmerman * @phy_type: Specifies the type of PHY interface to use. By default, 346197ba5f4SPaul Zimmerman * the driver will automatically detect the phy_type. 347197ba5f4SPaul Zimmerman * 0 - Full Speed Phy 348197ba5f4SPaul Zimmerman * 1 - UTMI+ Phy 349197ba5f4SPaul Zimmerman * 2 - ULPI Phy 350197ba5f4SPaul Zimmerman * Defaults to best available option (2, 1, then 0) 351197ba5f4SPaul Zimmerman * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 352197ba5f4SPaul Zimmerman * is applicable for a phy_type of UTMI+ or ULPI. (For a 353197ba5f4SPaul Zimmerman * ULPI phy_type, this parameter indicates the data width 354197ba5f4SPaul Zimmerman * between the MAC and the ULPI Wrapper.) Also, this 355197ba5f4SPaul Zimmerman * parameter is applicable only if the OTG_HSPHY_WIDTH cC 356197ba5f4SPaul Zimmerman * parameter was set to "8 and 16 bits", meaning that the 357197ba5f4SPaul Zimmerman * core has been configured to work at either data path 358197ba5f4SPaul Zimmerman * width. 359197ba5f4SPaul Zimmerman * 8 or 16 (default 16 if available) 360197ba5f4SPaul Zimmerman * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 361197ba5f4SPaul Zimmerman * data rate. This parameter is only applicable if phy_type 362197ba5f4SPaul Zimmerman * is ULPI. 363197ba5f4SPaul Zimmerman * 0 - single data rate ULPI interface with 8 bit wide 364197ba5f4SPaul Zimmerman * data bus (default) 365197ba5f4SPaul Zimmerman * 1 - double data rate ULPI interface with 4 bit wide 366197ba5f4SPaul Zimmerman * data bus 367197ba5f4SPaul Zimmerman * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 368197ba5f4SPaul Zimmerman * external supply to drive the VBus 369197ba5f4SPaul Zimmerman * 0 - Internal supply (default) 370197ba5f4SPaul Zimmerman * 1 - External supply 371197ba5f4SPaul Zimmerman * @i2c_enable: Specifies whether to use the I2Cinterface for a full 372197ba5f4SPaul Zimmerman * speed PHY. This parameter is only applicable if phy_type 373197ba5f4SPaul Zimmerman * is FS. 374197ba5f4SPaul Zimmerman * 0 - No (default) 375197ba5f4SPaul Zimmerman * 1 - Yes 376197ba5f4SPaul Zimmerman * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 377197ba5f4SPaul Zimmerman * 0 - No (default) 378197ba5f4SPaul Zimmerman * 1 - Yes 379197ba5f4SPaul Zimmerman * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 380197ba5f4SPaul Zimmerman * when attached to a Full Speed or Low Speed device in 381197ba5f4SPaul Zimmerman * host mode. 382197ba5f4SPaul Zimmerman * 0 - Don't support low power mode (default) 383197ba5f4SPaul Zimmerman * 1 - Support low power mode 384197ba5f4SPaul Zimmerman * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 385197ba5f4SPaul Zimmerman * when connected to a Low Speed device in host 386197ba5f4SPaul Zimmerman * mode. This parameter is applicable only if 387197ba5f4SPaul Zimmerman * host_support_fs_ls_low_power is enabled. 388197ba5f4SPaul Zimmerman * 0 - 48 MHz 389197ba5f4SPaul Zimmerman * (default when phy_type is UTMI+ or ULPI) 390197ba5f4SPaul Zimmerman * 1 - 6 MHz 391197ba5f4SPaul Zimmerman * (default when phy_type is Full Speed) 392197ba5f4SPaul Zimmerman * @ts_dline: Enable Term Select Dline pulsing 393197ba5f4SPaul Zimmerman * 0 - No (default) 394197ba5f4SPaul Zimmerman * 1 - Yes 395197ba5f4SPaul Zimmerman * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 396197ba5f4SPaul Zimmerman * 0 - No (default for core < 2.92a) 397197ba5f4SPaul Zimmerman * 1 - Yes (default for core >= 2.92a) 398197ba5f4SPaul Zimmerman * @ahbcfg: This field allows the default value of the GAHBCFG 399197ba5f4SPaul Zimmerman * register to be overridden 400197ba5f4SPaul Zimmerman * -1 - GAHBCFG value will be set to 0x06 401197ba5f4SPaul Zimmerman * (INCR4, default) 402197ba5f4SPaul Zimmerman * all others - GAHBCFG value will be overridden with 403197ba5f4SPaul Zimmerman * this value 404197ba5f4SPaul Zimmerman * Not all bits can be controlled like this, the 405197ba5f4SPaul Zimmerman * bits defined by GAHBCFG_CTRL_MASK are controlled 406197ba5f4SPaul Zimmerman * by the driver and are ignored in this 407197ba5f4SPaul Zimmerman * configuration value. 408197ba5f4SPaul Zimmerman * @uframe_sched: True to enable the microframe scheduler 409a6d249d8SGregory Herrero * @external_id_pin_ctl: Specifies whether ID pin is handled externally. 410a6d249d8SGregory Herrero * Disable CONIDSTSCHNG controller interrupt in such 411a6d249d8SGregory Herrero * case. 412a6d249d8SGregory Herrero * 0 - No (default) 413a6d249d8SGregory Herrero * 1 - Yes 414285046aaSGregory Herrero * @hibernation: Specifies whether the controller support hibernation. 415285046aaSGregory Herrero * If hibernation is enabled, the controller will enter 416285046aaSGregory Herrero * hibernation in both peripheral and host mode when 417285046aaSGregory Herrero * needed. 418285046aaSGregory Herrero * 0 - No (default) 419285046aaSGregory Herrero * 1 - Yes 420197ba5f4SPaul Zimmerman * 421197ba5f4SPaul Zimmerman * The following parameters may be specified when starting the module. These 422197ba5f4SPaul Zimmerman * parameters define how the DWC_otg controller should be configured. A 423197ba5f4SPaul Zimmerman * value of -1 (or any other out of range value) for any parameter means 424197ba5f4SPaul Zimmerman * to read the value from hardware (if possible) or use the builtin 425197ba5f4SPaul Zimmerman * default described above. 426197ba5f4SPaul Zimmerman */ 427197ba5f4SPaul Zimmerman struct dwc2_core_params { 428197ba5f4SPaul Zimmerman /* 429197ba5f4SPaul Zimmerman * Don't add any non-int members here, this will break 430197ba5f4SPaul Zimmerman * dwc2_set_all_params! 431197ba5f4SPaul Zimmerman */ 432197ba5f4SPaul Zimmerman int otg_cap; 433197ba5f4SPaul Zimmerman int otg_ver; 434197ba5f4SPaul Zimmerman int dma_enable; 435197ba5f4SPaul Zimmerman int dma_desc_enable; 436fbb9e22bSMian Yousaf Kaukab int dma_desc_fs_enable; 437197ba5f4SPaul Zimmerman int speed; 438197ba5f4SPaul Zimmerman int enable_dynamic_fifo; 439197ba5f4SPaul Zimmerman int en_multiple_tx_fifo; 440197ba5f4SPaul Zimmerman int host_rx_fifo_size; 441197ba5f4SPaul Zimmerman int host_nperio_tx_fifo_size; 442197ba5f4SPaul Zimmerman int host_perio_tx_fifo_size; 443197ba5f4SPaul Zimmerman int max_transfer_size; 444197ba5f4SPaul Zimmerman int max_packet_count; 445197ba5f4SPaul Zimmerman int host_channels; 446197ba5f4SPaul Zimmerman int phy_type; 447197ba5f4SPaul Zimmerman int phy_utmi_width; 448197ba5f4SPaul Zimmerman int phy_ulpi_ddr; 449197ba5f4SPaul Zimmerman int phy_ulpi_ext_vbus; 450197ba5f4SPaul Zimmerman int i2c_enable; 451197ba5f4SPaul Zimmerman int ulpi_fs_ls; 452197ba5f4SPaul Zimmerman int host_support_fs_ls_low_power; 453197ba5f4SPaul Zimmerman int host_ls_low_power_phy_clk; 454197ba5f4SPaul Zimmerman int ts_dline; 455197ba5f4SPaul Zimmerman int reload_ctl; 456197ba5f4SPaul Zimmerman int ahbcfg; 457197ba5f4SPaul Zimmerman int uframe_sched; 458a6d249d8SGregory Herrero int external_id_pin_ctl; 459285046aaSGregory Herrero int hibernation; 460197ba5f4SPaul Zimmerman }; 461197ba5f4SPaul Zimmerman 462197ba5f4SPaul Zimmerman /** 463197ba5f4SPaul Zimmerman * struct dwc2_hw_params - Autodetected parameters. 464197ba5f4SPaul Zimmerman * 465197ba5f4SPaul Zimmerman * These parameters are the various parameters read from hardware 466197ba5f4SPaul Zimmerman * registers during initialization. They typically contain the best 467197ba5f4SPaul Zimmerman * supported or maximum value that can be configured in the 468197ba5f4SPaul Zimmerman * corresponding dwc2_core_params value. 469197ba5f4SPaul Zimmerman * 470197ba5f4SPaul Zimmerman * The values that are not in dwc2_core_params are documented below. 471197ba5f4SPaul Zimmerman * 472197ba5f4SPaul Zimmerman * @op_mode Mode of Operation 473197ba5f4SPaul Zimmerman * 0 - HNP- and SRP-Capable OTG (Host & Device) 474197ba5f4SPaul Zimmerman * 1 - SRP-Capable OTG (Host & Device) 475197ba5f4SPaul Zimmerman * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 476197ba5f4SPaul Zimmerman * 3 - SRP-Capable Device 477197ba5f4SPaul Zimmerman * 4 - Non-OTG Device 478197ba5f4SPaul Zimmerman * 5 - SRP-Capable Host 479197ba5f4SPaul Zimmerman * 6 - Non-OTG Host 480197ba5f4SPaul Zimmerman * @arch Architecture 481197ba5f4SPaul Zimmerman * 0 - Slave only 482197ba5f4SPaul Zimmerman * 1 - External DMA 483197ba5f4SPaul Zimmerman * 2 - Internal DMA 484197ba5f4SPaul Zimmerman * @power_optimized Are power optimizations enabled? 485197ba5f4SPaul Zimmerman * @num_dev_ep Number of device endpoints available 486197ba5f4SPaul Zimmerman * @num_dev_perio_in_ep Number of device periodic IN endpoints 487997f4f81SMickael Maison * available 488197ba5f4SPaul Zimmerman * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue 489197ba5f4SPaul Zimmerman * Depth 490197ba5f4SPaul Zimmerman * 0 to 30 491197ba5f4SPaul Zimmerman * @host_perio_tx_q_depth 492197ba5f4SPaul Zimmerman * Host Mode Periodic Request Queue Depth 493197ba5f4SPaul Zimmerman * 2, 4 or 8 494197ba5f4SPaul Zimmerman * @nperio_tx_q_depth 495197ba5f4SPaul Zimmerman * Non-Periodic Request Queue Depth 496197ba5f4SPaul Zimmerman * 2, 4 or 8 497197ba5f4SPaul Zimmerman * @hs_phy_type High-speed PHY interface type 498197ba5f4SPaul Zimmerman * 0 - High-speed interface not supported 499197ba5f4SPaul Zimmerman * 1 - UTMI+ 500197ba5f4SPaul Zimmerman * 2 - ULPI 501197ba5f4SPaul Zimmerman * 3 - UTMI+ and ULPI 502197ba5f4SPaul Zimmerman * @fs_phy_type Full-speed PHY interface type 503197ba5f4SPaul Zimmerman * 0 - Full speed interface not supported 504197ba5f4SPaul Zimmerman * 1 - Dedicated full speed interface 505197ba5f4SPaul Zimmerman * 2 - FS pins shared with UTMI+ pins 506197ba5f4SPaul Zimmerman * 3 - FS pins shared with ULPI pins 507197ba5f4SPaul Zimmerman * @total_fifo_size: Total internal RAM for FIFOs (bytes) 508197ba5f4SPaul Zimmerman * @utmi_phy_data_width UTMI+ PHY data width 509197ba5f4SPaul Zimmerman * 0 - 8 bits 510197ba5f4SPaul Zimmerman * 1 - 16 bits 511197ba5f4SPaul Zimmerman * 2 - 8 or 16 bits 512197ba5f4SPaul Zimmerman * @snpsid: Value from SNPSID register 51355e1040eSJohn Youn * @dev_ep_dirs: Direction of device endpoints (GHWCFG1) 514197ba5f4SPaul Zimmerman */ 515197ba5f4SPaul Zimmerman struct dwc2_hw_params { 516197ba5f4SPaul Zimmerman unsigned op_mode:3; 517197ba5f4SPaul Zimmerman unsigned arch:2; 518197ba5f4SPaul Zimmerman unsigned dma_desc_enable:1; 519197ba5f4SPaul Zimmerman unsigned enable_dynamic_fifo:1; 520197ba5f4SPaul Zimmerman unsigned en_multiple_tx_fifo:1; 521197ba5f4SPaul Zimmerman unsigned host_rx_fifo_size:16; 522197ba5f4SPaul Zimmerman unsigned host_nperio_tx_fifo_size:16; 52355e1040eSJohn Youn unsigned dev_nperio_tx_fifo_size:16; 524197ba5f4SPaul Zimmerman unsigned host_perio_tx_fifo_size:16; 525197ba5f4SPaul Zimmerman unsigned nperio_tx_q_depth:3; 526197ba5f4SPaul Zimmerman unsigned host_perio_tx_q_depth:3; 527197ba5f4SPaul Zimmerman unsigned dev_token_q_depth:5; 528197ba5f4SPaul Zimmerman unsigned max_transfer_size:26; 529197ba5f4SPaul Zimmerman unsigned max_packet_count:11; 530197ba5f4SPaul Zimmerman unsigned host_channels:5; 531197ba5f4SPaul Zimmerman unsigned hs_phy_type:2; 532197ba5f4SPaul Zimmerman unsigned fs_phy_type:2; 533197ba5f4SPaul Zimmerman unsigned i2c_enable:1; 534197ba5f4SPaul Zimmerman unsigned num_dev_ep:4; 535197ba5f4SPaul Zimmerman unsigned num_dev_perio_in_ep:4; 536197ba5f4SPaul Zimmerman unsigned total_fifo_size:16; 537197ba5f4SPaul Zimmerman unsigned power_optimized:1; 538197ba5f4SPaul Zimmerman unsigned utmi_phy_data_width:2; 539197ba5f4SPaul Zimmerman u32 snpsid; 54055e1040eSJohn Youn u32 dev_ep_dirs; 541197ba5f4SPaul Zimmerman }; 542197ba5f4SPaul Zimmerman 5433f95001dSMian Yousaf Kaukab /* Size of control and EP0 buffers */ 5443f95001dSMian Yousaf Kaukab #define DWC2_CTRL_BUFF_SIZE 8 5453f95001dSMian Yousaf Kaukab 546197ba5f4SPaul Zimmerman /** 547d17ee77bSGregory Herrero * struct dwc2_gregs_backup - Holds global registers state before entering partial 548d17ee77bSGregory Herrero * power down 549d17ee77bSGregory Herrero * @gotgctl: Backup of GOTGCTL register 550d17ee77bSGregory Herrero * @gintmsk: Backup of GINTMSK register 551d17ee77bSGregory Herrero * @gahbcfg: Backup of GAHBCFG register 552d17ee77bSGregory Herrero * @gusbcfg: Backup of GUSBCFG register 553d17ee77bSGregory Herrero * @grxfsiz: Backup of GRXFSIZ register 554d17ee77bSGregory Herrero * @gnptxfsiz: Backup of GNPTXFSIZ register 555d17ee77bSGregory Herrero * @gi2cctl: Backup of GI2CCTL register 556d17ee77bSGregory Herrero * @hptxfsiz: Backup of HPTXFSIZ register 557d17ee77bSGregory Herrero * @gdfifocfg: Backup of GDFIFOCFG register 558d17ee77bSGregory Herrero * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 559d17ee77bSGregory Herrero * @gpwrdn: Backup of GPWRDN register 560d17ee77bSGregory Herrero */ 561d17ee77bSGregory Herrero struct dwc2_gregs_backup { 562d17ee77bSGregory Herrero u32 gotgctl; 563d17ee77bSGregory Herrero u32 gintmsk; 564d17ee77bSGregory Herrero u32 gahbcfg; 565d17ee77bSGregory Herrero u32 gusbcfg; 566d17ee77bSGregory Herrero u32 grxfsiz; 567d17ee77bSGregory Herrero u32 gnptxfsiz; 568d17ee77bSGregory Herrero u32 gi2cctl; 569d17ee77bSGregory Herrero u32 hptxfsiz; 570d17ee77bSGregory Herrero u32 pcgcctl; 571d17ee77bSGregory Herrero u32 gdfifocfg; 572d17ee77bSGregory Herrero u32 dtxfsiz[MAX_EPS_CHANNELS]; 573d17ee77bSGregory Herrero u32 gpwrdn; 574cc1e204cSMian Yousaf Kaukab bool valid; 575d17ee77bSGregory Herrero }; 576d17ee77bSGregory Herrero 577d17ee77bSGregory Herrero /** 578d17ee77bSGregory Herrero * struct dwc2_dregs_backup - Holds device registers state before entering partial 579d17ee77bSGregory Herrero * power down 580d17ee77bSGregory Herrero * @dcfg: Backup of DCFG register 581d17ee77bSGregory Herrero * @dctl: Backup of DCTL register 582d17ee77bSGregory Herrero * @daintmsk: Backup of DAINTMSK register 583d17ee77bSGregory Herrero * @diepmsk: Backup of DIEPMSK register 584d17ee77bSGregory Herrero * @doepmsk: Backup of DOEPMSK register 585d17ee77bSGregory Herrero * @diepctl: Backup of DIEPCTL register 586d17ee77bSGregory Herrero * @dieptsiz: Backup of DIEPTSIZ register 587d17ee77bSGregory Herrero * @diepdma: Backup of DIEPDMA register 588d17ee77bSGregory Herrero * @doepctl: Backup of DOEPCTL register 589d17ee77bSGregory Herrero * @doeptsiz: Backup of DOEPTSIZ register 590d17ee77bSGregory Herrero * @doepdma: Backup of DOEPDMA register 591d17ee77bSGregory Herrero */ 592d17ee77bSGregory Herrero struct dwc2_dregs_backup { 593d17ee77bSGregory Herrero u32 dcfg; 594d17ee77bSGregory Herrero u32 dctl; 595d17ee77bSGregory Herrero u32 daintmsk; 596d17ee77bSGregory Herrero u32 diepmsk; 597d17ee77bSGregory Herrero u32 doepmsk; 598d17ee77bSGregory Herrero u32 diepctl[MAX_EPS_CHANNELS]; 599d17ee77bSGregory Herrero u32 dieptsiz[MAX_EPS_CHANNELS]; 600d17ee77bSGregory Herrero u32 diepdma[MAX_EPS_CHANNELS]; 601d17ee77bSGregory Herrero u32 doepctl[MAX_EPS_CHANNELS]; 602d17ee77bSGregory Herrero u32 doeptsiz[MAX_EPS_CHANNELS]; 603d17ee77bSGregory Herrero u32 doepdma[MAX_EPS_CHANNELS]; 604cc1e204cSMian Yousaf Kaukab bool valid; 605d17ee77bSGregory Herrero }; 606d17ee77bSGregory Herrero 607d17ee77bSGregory Herrero /** 608d17ee77bSGregory Herrero * struct dwc2_hregs_backup - Holds host registers state before entering partial 609d17ee77bSGregory Herrero * power down 610d17ee77bSGregory Herrero * @hcfg: Backup of HCFG register 611d17ee77bSGregory Herrero * @haintmsk: Backup of HAINTMSK register 612d17ee77bSGregory Herrero * @hcintmsk: Backup of HCINTMSK register 613d17ee77bSGregory Herrero * @hptr0: Backup of HPTR0 register 614d17ee77bSGregory Herrero * @hfir: Backup of HFIR register 615d17ee77bSGregory Herrero */ 616d17ee77bSGregory Herrero struct dwc2_hregs_backup { 617d17ee77bSGregory Herrero u32 hcfg; 618d17ee77bSGregory Herrero u32 haintmsk; 619d17ee77bSGregory Herrero u32 hcintmsk[MAX_EPS_CHANNELS]; 620d17ee77bSGregory Herrero u32 hprt0; 621d17ee77bSGregory Herrero u32 hfir; 622cc1e204cSMian Yousaf Kaukab bool valid; 623d17ee77bSGregory Herrero }; 624d17ee77bSGregory Herrero 6259f9f09b0SDouglas Anderson /* 6269f9f09b0SDouglas Anderson * Constants related to high speed periodic scheduling 6279f9f09b0SDouglas Anderson * 6289f9f09b0SDouglas Anderson * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a 6299f9f09b0SDouglas Anderson * reservation point of view it's assumed that the schedule goes right back to 6309f9f09b0SDouglas Anderson * the beginning after the end of the schedule. 6319f9f09b0SDouglas Anderson * 6329f9f09b0SDouglas Anderson * What does that mean for scheduling things with a long interval? It means 6339f9f09b0SDouglas Anderson * we'll reserve time for them in every possible microframe that they could 6349f9f09b0SDouglas Anderson * ever be scheduled in. ...but we'll still only actually schedule them as 6359f9f09b0SDouglas Anderson * often as they were requested. 6369f9f09b0SDouglas Anderson * 6379f9f09b0SDouglas Anderson * We keep our schedule in a "bitmap" structure. This simplifies having 6389f9f09b0SDouglas Anderson * to keep track of and merge intervals: we just let the bitmap code do most 6399f9f09b0SDouglas Anderson * of the heavy lifting. In a way scheduling is much like memory allocation. 6409f9f09b0SDouglas Anderson * 6419f9f09b0SDouglas Anderson * We schedule 100us per uframe or 80% of 125us (the maximum amount you're 6429f9f09b0SDouglas Anderson * supposed to schedule for periodic transfers). That's according to spec. 6439f9f09b0SDouglas Anderson * 6449f9f09b0SDouglas Anderson * Note that though we only schedule 80% of each microframe, the bitmap that we 6459f9f09b0SDouglas Anderson * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of 6469f9f09b0SDouglas Anderson * space for each uFrame). 6479f9f09b0SDouglas Anderson * 6489f9f09b0SDouglas Anderson * Requirements: 6499f9f09b0SDouglas Anderson * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1) 6509f9f09b0SDouglas Anderson * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably 6519f9f09b0SDouglas Anderson * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might 6529f9f09b0SDouglas Anderson * be bugs). The 8 comes from the USB spec: number of microframes per frame. 6539f9f09b0SDouglas Anderson */ 6549f9f09b0SDouglas Anderson #define DWC2_US_PER_UFRAME 125 6559f9f09b0SDouglas Anderson #define DWC2_HS_PERIODIC_US_PER_UFRAME 100 6569f9f09b0SDouglas Anderson 6579f9f09b0SDouglas Anderson #define DWC2_HS_SCHEDULE_UFRAMES 8 6589f9f09b0SDouglas Anderson #define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \ 6599f9f09b0SDouglas Anderson DWC2_HS_PERIODIC_US_PER_UFRAME) 6609f9f09b0SDouglas Anderson 6619f9f09b0SDouglas Anderson /* 6629f9f09b0SDouglas Anderson * Constants related to low speed scheduling 6639f9f09b0SDouglas Anderson * 6649f9f09b0SDouglas Anderson * For high speed we schedule every 1us. For low speed that's a bit overkill, 6659f9f09b0SDouglas Anderson * so we make up a unit called a "slice" that's worth 25us. There are 40 6669f9f09b0SDouglas Anderson * slices in a full frame and we can schedule 36 of those (90%) for periodic 6679f9f09b0SDouglas Anderson * transfers. 6689f9f09b0SDouglas Anderson * 6699f9f09b0SDouglas Anderson * Our low speed schedule can be as short as 1 frame or could be longer. When 6709f9f09b0SDouglas Anderson * we only schedule 1 frame it means that we'll need to reserve a time every 6719f9f09b0SDouglas Anderson * frame even for things that only transfer very rarely, so something that runs 6729f9f09b0SDouglas Anderson * every 2048 frames will get time reserved in every frame. Our low speed 6739f9f09b0SDouglas Anderson * schedule can be longer and we'll be able to handle more overlap, but that 6749f9f09b0SDouglas Anderson * will come at increased memory cost and increased time to schedule. 6759f9f09b0SDouglas Anderson * 6769f9f09b0SDouglas Anderson * Note: one other advantage of a short low speed schedule is that if we mess 6779f9f09b0SDouglas Anderson * up and miss scheduling we can jump in and use any of the slots that we 6789f9f09b0SDouglas Anderson * happened to reserve. 6799f9f09b0SDouglas Anderson * 6809f9f09b0SDouglas Anderson * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for 6819f9f09b0SDouglas Anderson * the schedule. There will be one schedule per TT. 6829f9f09b0SDouglas Anderson * 6839f9f09b0SDouglas Anderson * Requirements: 6849f9f09b0SDouglas Anderson * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME. 6859f9f09b0SDouglas Anderson */ 6869f9f09b0SDouglas Anderson #define DWC2_US_PER_SLICE 25 6879f9f09b0SDouglas Anderson #define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE) 6889f9f09b0SDouglas Anderson 6899f9f09b0SDouglas Anderson #define DWC2_ROUND_US_TO_SLICE(us) \ 6909f9f09b0SDouglas Anderson (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \ 6919f9f09b0SDouglas Anderson DWC2_US_PER_SLICE) 6929f9f09b0SDouglas Anderson 6939f9f09b0SDouglas Anderson #define DWC2_LS_PERIODIC_US_PER_FRAME \ 6949f9f09b0SDouglas Anderson 900 6959f9f09b0SDouglas Anderson #define DWC2_LS_PERIODIC_SLICES_PER_FRAME \ 6969f9f09b0SDouglas Anderson (DWC2_LS_PERIODIC_US_PER_FRAME / \ 6979f9f09b0SDouglas Anderson DWC2_US_PER_SLICE) 6989f9f09b0SDouglas Anderson 6999f9f09b0SDouglas Anderson #define DWC2_LS_SCHEDULE_FRAMES 1 7009f9f09b0SDouglas Anderson #define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \ 7019f9f09b0SDouglas Anderson DWC2_LS_PERIODIC_SLICES_PER_FRAME) 7029f9f09b0SDouglas Anderson 703d17ee77bSGregory Herrero /** 704197ba5f4SPaul Zimmerman * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 705197ba5f4SPaul Zimmerman * and periodic schedules 706197ba5f4SPaul Zimmerman * 707941fcce4SDinh Nguyen * These are common for both host and peripheral modes: 708941fcce4SDinh Nguyen * 709197ba5f4SPaul Zimmerman * @dev: The struct device pointer 710197ba5f4SPaul Zimmerman * @regs: Pointer to controller regs 711197ba5f4SPaul Zimmerman * @hw_params: Parameters that were autodetected from the 712197ba5f4SPaul Zimmerman * hardware registers 713941fcce4SDinh Nguyen * @core_params: Parameters that define how the core should be configured 714197ba5f4SPaul Zimmerman * @op_state: The operational State, during transitions (a_host=> 715197ba5f4SPaul Zimmerman * a_peripheral and b_device=>b_host) this may not match 716197ba5f4SPaul Zimmerman * the core, but allows the software to determine 717197ba5f4SPaul Zimmerman * transitions 718c0155b9dSKever Yang * @dr_mode: Requested mode of operation, one of following: 719c0155b9dSKever Yang * - USB_DR_MODE_PERIPHERAL 720c0155b9dSKever Yang * - USB_DR_MODE_HOST 721c0155b9dSKever Yang * - USB_DR_MODE_OTG 72209a75e85SMarek Szyprowski * @hcd_enabled Host mode sub-driver initialization indicator. 72309a75e85SMarek Szyprowski * @gadget_enabled Peripheral mode sub-driver initialization indicator. 72409a75e85SMarek Szyprowski * @ll_hw_enabled Status of low-level hardware resources. 72509a75e85SMarek Szyprowski * @phy: The otg phy transceiver structure for phy control. 72609a75e85SMarek Szyprowski * @uphy: The otg phy transceiver structure for old USB phy control. 72709a75e85SMarek Szyprowski * @plat: The platform specific configuration data. This can be removed once 72809a75e85SMarek Szyprowski * all SoCs support usb transceiver. 72909a75e85SMarek Szyprowski * @supplies: Definition of USB power supplies 73009a75e85SMarek Szyprowski * @phyif: PHY interface width 731941fcce4SDinh Nguyen * @lock: Spinlock that protects all the driver data structures 732941fcce4SDinh Nguyen * @priv: Stores a pointer to the struct usb_hcd 733197ba5f4SPaul Zimmerman * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 734197ba5f4SPaul Zimmerman * transfer are in process of being queued 735197ba5f4SPaul Zimmerman * @srp_success: Stores status of SRP request in the case of a FS PHY 736197ba5f4SPaul Zimmerman * with an I2C interface 737197ba5f4SPaul Zimmerman * @wq_otg: Workqueue object used for handling of some interrupts 738197ba5f4SPaul Zimmerman * @wf_otg: Work object for handling Connector ID Status Change 739197ba5f4SPaul Zimmerman * interrupt 740197ba5f4SPaul Zimmerman * @wkp_timer: Timer object for handling Wakeup Detected interrupt 741197ba5f4SPaul Zimmerman * @lx_state: Lx state of connected device 742d17ee77bSGregory Herrero * @gregs_backup: Backup of global registers during suspend 743d17ee77bSGregory Herrero * @dregs_backup: Backup of device registers during suspend 744d17ee77bSGregory Herrero * @hregs_backup: Backup of host registers during suspend 745941fcce4SDinh Nguyen * 746941fcce4SDinh Nguyen * These are for host mode: 747941fcce4SDinh Nguyen * 748197ba5f4SPaul Zimmerman * @flags: Flags for handling root port state changes 749197ba5f4SPaul Zimmerman * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 750197ba5f4SPaul Zimmerman * Transfers associated with these QHs are not currently 751197ba5f4SPaul Zimmerman * assigned to a host channel. 752197ba5f4SPaul Zimmerman * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 753197ba5f4SPaul Zimmerman * Transfers associated with these QHs are currently 754197ba5f4SPaul Zimmerman * assigned to a host channel. 755197ba5f4SPaul Zimmerman * @non_periodic_qh_ptr: Pointer to next QH to process in the active 756197ba5f4SPaul Zimmerman * non-periodic schedule 757197ba5f4SPaul Zimmerman * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 758197ba5f4SPaul Zimmerman * list of QHs for periodic transfers that are _not_ 759197ba5f4SPaul Zimmerman * scheduled for the next frame. Each QH in the list has an 760197ba5f4SPaul Zimmerman * interval counter that determines when it needs to be 761197ba5f4SPaul Zimmerman * scheduled for execution. This scheduling mechanism 762197ba5f4SPaul Zimmerman * allows only a simple calculation for periodic bandwidth 763197ba5f4SPaul Zimmerman * used (i.e. must assume that all periodic transfers may 764197ba5f4SPaul Zimmerman * need to execute in the same frame). However, it greatly 765197ba5f4SPaul Zimmerman * simplifies scheduling and should be sufficient for the 766197ba5f4SPaul Zimmerman * vast majority of OTG hosts, which need to connect to a 767197ba5f4SPaul Zimmerman * small number of peripherals at one time. Items move from 768197ba5f4SPaul Zimmerman * this list to periodic_sched_ready when the QH interval 769197ba5f4SPaul Zimmerman * counter is 0 at SOF. 770197ba5f4SPaul Zimmerman * @periodic_sched_ready: List of periodic QHs that are ready for execution in 771197ba5f4SPaul Zimmerman * the next frame, but have not yet been assigned to host 772197ba5f4SPaul Zimmerman * channels. Items move from this list to 773197ba5f4SPaul Zimmerman * periodic_sched_assigned as host channels become 774197ba5f4SPaul Zimmerman * available during the current frame. 775197ba5f4SPaul Zimmerman * @periodic_sched_assigned: List of periodic QHs to be executed in the next 776197ba5f4SPaul Zimmerman * frame that are assigned to host channels. Items move 777197ba5f4SPaul Zimmerman * from this list to periodic_sched_queued as the 778197ba5f4SPaul Zimmerman * transactions for the QH are queued to the DWC_otg 779197ba5f4SPaul Zimmerman * controller. 780197ba5f4SPaul Zimmerman * @periodic_sched_queued: List of periodic QHs that have been queued for 781197ba5f4SPaul Zimmerman * execution. Items move from this list to either 782197ba5f4SPaul Zimmerman * periodic_sched_inactive or periodic_sched_ready when the 783197ba5f4SPaul Zimmerman * channel associated with the transfer is released. If the 784197ba5f4SPaul Zimmerman * interval for the QH is 1, the item moves to 785197ba5f4SPaul Zimmerman * periodic_sched_ready because it must be rescheduled for 786197ba5f4SPaul Zimmerman * the next frame. Otherwise, the item moves to 787197ba5f4SPaul Zimmerman * periodic_sched_inactive. 788c9c8ac01SDouglas Anderson * @split_order: List keeping track of channels doing splits, in order. 789197ba5f4SPaul Zimmerman * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 790197ba5f4SPaul Zimmerman * This value is in microseconds per (micro)frame. The 791197ba5f4SPaul Zimmerman * assumption is that all periodic transfers may occur in 792197ba5f4SPaul Zimmerman * the same (micro)frame. 7939f9f09b0SDouglas Anderson * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the 7949f9f09b0SDouglas Anderson * host is in high speed mode; low speed schedules are 7959f9f09b0SDouglas Anderson * stored elsewhere since we need one per TT. 796197ba5f4SPaul Zimmerman * @frame_number: Frame number read from the core at SOF. The value ranges 797197ba5f4SPaul Zimmerman * from 0 to HFNUM_MAX_FRNUM. 798197ba5f4SPaul Zimmerman * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 799197ba5f4SPaul Zimmerman * SOF enable/disable. 800197ba5f4SPaul Zimmerman * @free_hc_list: Free host channels in the controller. This is a list of 801197ba5f4SPaul Zimmerman * struct dwc2_host_chan items. 802197ba5f4SPaul Zimmerman * @periodic_channels: Number of host channels assigned to periodic transfers. 803197ba5f4SPaul Zimmerman * Currently assuming that there is a dedicated host 804197ba5f4SPaul Zimmerman * channel for each periodic transaction and at least one 805197ba5f4SPaul Zimmerman * host channel is available for non-periodic transactions. 806197ba5f4SPaul Zimmerman * @non_periodic_channels: Number of host channels assigned to non-periodic 807197ba5f4SPaul Zimmerman * transfers 808197ba5f4SPaul Zimmerman * @available_host_channels Number of host channels available for the microframe 809197ba5f4SPaul Zimmerman * scheduler to use 810197ba5f4SPaul Zimmerman * @hc_ptr_array: Array of pointers to the host channel descriptors. 811197ba5f4SPaul Zimmerman * Allows accessing a host channel descriptor given the 812197ba5f4SPaul Zimmerman * host channel number. This is useful in interrupt 813197ba5f4SPaul Zimmerman * handlers. 814197ba5f4SPaul Zimmerman * @status_buf: Buffer used for data received during the status phase of 815197ba5f4SPaul Zimmerman * a control transfer. 816197ba5f4SPaul Zimmerman * @status_buf_dma: DMA address for status_buf 817197ba5f4SPaul Zimmerman * @start_work: Delayed work for handling host A-cable connection 818197ba5f4SPaul Zimmerman * @reset_work: Delayed work for handling a port reset 819197ba5f4SPaul Zimmerman * @otg_port: OTG port number 820197ba5f4SPaul Zimmerman * @frame_list: Frame list 821197ba5f4SPaul Zimmerman * @frame_list_dma: Frame list DMA address 82295105a99SGregory Herrero * @frame_list_sz: Frame list size 8233b5fcc9aSGregory Herrero * @desc_gen_cache: Kmem cache for generic descriptors 8243b5fcc9aSGregory Herrero * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors 825941fcce4SDinh Nguyen * 826941fcce4SDinh Nguyen * These are for peripheral mode: 827941fcce4SDinh Nguyen * 828941fcce4SDinh Nguyen * @driver: USB gadget driver 829941fcce4SDinh Nguyen * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 830941fcce4SDinh Nguyen * @num_of_eps: Number of available EPs (excluding EP0) 831941fcce4SDinh Nguyen * @debug_root: Root directrory for debugfs. 832941fcce4SDinh Nguyen * @debug_file: Main status file for debugfs. 8339e14d0a5SGregory Herrero * @debug_testmode: Testmode status file for debugfs. 834941fcce4SDinh Nguyen * @debug_fifo: FIFO status file for debugfs. 835941fcce4SDinh Nguyen * @ep0_reply: Request used for ep0 reply. 836941fcce4SDinh Nguyen * @ep0_buff: Buffer for EP0 reply data, if needed. 837941fcce4SDinh Nguyen * @ctrl_buff: Buffer for EP0 control requests. 838941fcce4SDinh Nguyen * @ctrl_req: Request for EP0 control packets. 839fe0b94abSMian Yousaf Kaukab * @ep0_state: EP0 control transfers state 8409e14d0a5SGregory Herrero * @test_mode: USB test mode requested by the host 841941fcce4SDinh Nguyen * @eps: The endpoints being supplied to the gadget framework 842edd74be8SGregory Herrero * @g_using_dma: Indicate if dma usage is enabled 8430a176279SGregory Herrero * @g_rx_fifo_sz: Contains rx fifo size value 8440a176279SGregory Herrero * @g_np_g_tx_fifo_sz: Contains Non-Periodic tx fifo size value 8450a176279SGregory Herrero * @g_tx_fifo_sz: Contains tx fifo size value per endpoints 846197ba5f4SPaul Zimmerman */ 847197ba5f4SPaul Zimmerman struct dwc2_hsotg { 848197ba5f4SPaul Zimmerman struct device *dev; 849197ba5f4SPaul Zimmerman void __iomem *regs; 850197ba5f4SPaul Zimmerman /** Params detected from hardware */ 851197ba5f4SPaul Zimmerman struct dwc2_hw_params hw_params; 852197ba5f4SPaul Zimmerman /** Params to actually use */ 853bea8e86cSJohn Youn struct dwc2_core_params params; 854197ba5f4SPaul Zimmerman enum usb_otg_state op_state; 855c0155b9dSKever Yang enum usb_dr_mode dr_mode; 856e39af88fSMarek Szyprowski unsigned int hcd_enabled:1; 857e39af88fSMarek Szyprowski unsigned int gadget_enabled:1; 85809a75e85SMarek Szyprowski unsigned int ll_hw_enabled:1; 859197ba5f4SPaul Zimmerman 860941fcce4SDinh Nguyen struct phy *phy; 861941fcce4SDinh Nguyen struct usb_phy *uphy; 86209a75e85SMarek Szyprowski struct dwc2_hsotg_plat *plat; 8631f91b4ccSFelipe Balbi struct regulator_bulk_data supplies[ARRAY_SIZE(dwc2_hsotg_supply_names)]; 86409a75e85SMarek Szyprowski u32 phyif; 865941fcce4SDinh Nguyen 866941fcce4SDinh Nguyen spinlock_t lock; 867941fcce4SDinh Nguyen void *priv; 868941fcce4SDinh Nguyen int irq; 869941fcce4SDinh Nguyen struct clk *clk; 87083f8da56SDinh Nguyen struct reset_control *reset; 871941fcce4SDinh Nguyen 872197ba5f4SPaul Zimmerman unsigned int queuing_high_bandwidth:1; 873197ba5f4SPaul Zimmerman unsigned int srp_success:1; 874197ba5f4SPaul Zimmerman 875197ba5f4SPaul Zimmerman struct workqueue_struct *wq_otg; 876197ba5f4SPaul Zimmerman struct work_struct wf_otg; 877197ba5f4SPaul Zimmerman struct timer_list wkp_timer; 878197ba5f4SPaul Zimmerman enum dwc2_lx_state lx_state; 879cc1e204cSMian Yousaf Kaukab struct dwc2_gregs_backup gr_backup; 880cc1e204cSMian Yousaf Kaukab struct dwc2_dregs_backup dr_backup; 881cc1e204cSMian Yousaf Kaukab struct dwc2_hregs_backup hr_backup; 882197ba5f4SPaul Zimmerman 883941fcce4SDinh Nguyen struct dentry *debug_root; 884563cf017SMian Yousaf Kaukab struct debugfs_regset32 *regset; 885941fcce4SDinh Nguyen 886941fcce4SDinh Nguyen /* DWC OTG HW Release versions */ 887941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_71a 0x4f54271a 888941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_90a 0x4f54290a 889941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_92a 0x4f54292a 890941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_94a 0x4f54294a 891941fcce4SDinh Nguyen #define DWC2_CORE_REV_3_00a 0x4f54300a 892fef6bc37SJohn Youn #define DWC2_CORE_REV_3_10a 0x4f54310a 893941fcce4SDinh Nguyen 894941fcce4SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 895197ba5f4SPaul Zimmerman union dwc2_hcd_internal_flags { 896197ba5f4SPaul Zimmerman u32 d32; 897197ba5f4SPaul Zimmerman struct { 898197ba5f4SPaul Zimmerman unsigned port_connect_status_change:1; 899197ba5f4SPaul Zimmerman unsigned port_connect_status:1; 900197ba5f4SPaul Zimmerman unsigned port_reset_change:1; 901197ba5f4SPaul Zimmerman unsigned port_enable_change:1; 902197ba5f4SPaul Zimmerman unsigned port_suspend_change:1; 903197ba5f4SPaul Zimmerman unsigned port_over_current_change:1; 904197ba5f4SPaul Zimmerman unsigned port_l1_change:1; 905fd4850cfSCharles Manning unsigned reserved:25; 906197ba5f4SPaul Zimmerman } b; 907197ba5f4SPaul Zimmerman } flags; 908197ba5f4SPaul Zimmerman 909197ba5f4SPaul Zimmerman struct list_head non_periodic_sched_inactive; 910197ba5f4SPaul Zimmerman struct list_head non_periodic_sched_active; 911197ba5f4SPaul Zimmerman struct list_head *non_periodic_qh_ptr; 912197ba5f4SPaul Zimmerman struct list_head periodic_sched_inactive; 913197ba5f4SPaul Zimmerman struct list_head periodic_sched_ready; 914197ba5f4SPaul Zimmerman struct list_head periodic_sched_assigned; 915197ba5f4SPaul Zimmerman struct list_head periodic_sched_queued; 916c9c8ac01SDouglas Anderson struct list_head split_order; 917197ba5f4SPaul Zimmerman u16 periodic_usecs; 9189f9f09b0SDouglas Anderson unsigned long hs_periodic_bitmap[ 9199f9f09b0SDouglas Anderson DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)]; 920197ba5f4SPaul Zimmerman u16 frame_number; 921197ba5f4SPaul Zimmerman u16 periodic_qh_count; 922734643dfSGregory Herrero bool bus_suspended; 923fbb9e22bSMian Yousaf Kaukab bool new_connection; 924197ba5f4SPaul Zimmerman 925483bb254SDouglas Anderson u16 last_frame_num; 926483bb254SDouglas Anderson 927197ba5f4SPaul Zimmerman #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 928197ba5f4SPaul Zimmerman #define FRAME_NUM_ARRAY_SIZE 1000 929197ba5f4SPaul Zimmerman u16 *frame_num_array; 930197ba5f4SPaul Zimmerman u16 *last_frame_num_array; 931197ba5f4SPaul Zimmerman int frame_num_idx; 932197ba5f4SPaul Zimmerman int dumped_frame_num_array; 933197ba5f4SPaul Zimmerman #endif 934197ba5f4SPaul Zimmerman 935197ba5f4SPaul Zimmerman struct list_head free_hc_list; 936197ba5f4SPaul Zimmerman int periodic_channels; 937197ba5f4SPaul Zimmerman int non_periodic_channels; 938197ba5f4SPaul Zimmerman int available_host_channels; 939197ba5f4SPaul Zimmerman struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 940197ba5f4SPaul Zimmerman u8 *status_buf; 941197ba5f4SPaul Zimmerman dma_addr_t status_buf_dma; 942197ba5f4SPaul Zimmerman #define DWC2_HCD_STATUS_BUF_SIZE 64 943197ba5f4SPaul Zimmerman 944197ba5f4SPaul Zimmerman struct delayed_work start_work; 945197ba5f4SPaul Zimmerman struct delayed_work reset_work; 946197ba5f4SPaul Zimmerman u8 otg_port; 947197ba5f4SPaul Zimmerman u32 *frame_list; 948197ba5f4SPaul Zimmerman dma_addr_t frame_list_dma; 94995105a99SGregory Herrero u32 frame_list_sz; 9503b5fcc9aSGregory Herrero struct kmem_cache *desc_gen_cache; 9513b5fcc9aSGregory Herrero struct kmem_cache *desc_hsisoc_cache; 952197ba5f4SPaul Zimmerman 953197ba5f4SPaul Zimmerman #ifdef DEBUG 954197ba5f4SPaul Zimmerman u32 frrem_samples; 955197ba5f4SPaul Zimmerman u64 frrem_accum; 956197ba5f4SPaul Zimmerman 957197ba5f4SPaul Zimmerman u32 hfnum_7_samples_a; 958197ba5f4SPaul Zimmerman u64 hfnum_7_frrem_accum_a; 959197ba5f4SPaul Zimmerman u32 hfnum_0_samples_a; 960197ba5f4SPaul Zimmerman u64 hfnum_0_frrem_accum_a; 961197ba5f4SPaul Zimmerman u32 hfnum_other_samples_a; 962197ba5f4SPaul Zimmerman u64 hfnum_other_frrem_accum_a; 963197ba5f4SPaul Zimmerman 964197ba5f4SPaul Zimmerman u32 hfnum_7_samples_b; 965197ba5f4SPaul Zimmerman u64 hfnum_7_frrem_accum_b; 966197ba5f4SPaul Zimmerman u32 hfnum_0_samples_b; 967197ba5f4SPaul Zimmerman u64 hfnum_0_frrem_accum_b; 968197ba5f4SPaul Zimmerman u32 hfnum_other_samples_b; 969197ba5f4SPaul Zimmerman u64 hfnum_other_frrem_accum_b; 970197ba5f4SPaul Zimmerman #endif 971941fcce4SDinh Nguyen #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ 972941fcce4SDinh Nguyen 973941fcce4SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 974941fcce4SDinh Nguyen /* Gadget structures */ 975941fcce4SDinh Nguyen struct usb_gadget_driver *driver; 976941fcce4SDinh Nguyen int fifo_mem; 977941fcce4SDinh Nguyen unsigned int dedicated_fifos:1; 978941fcce4SDinh Nguyen unsigned char num_of_eps; 979941fcce4SDinh Nguyen u32 fifo_map; 980941fcce4SDinh Nguyen 981941fcce4SDinh Nguyen struct usb_request *ep0_reply; 982941fcce4SDinh Nguyen struct usb_request *ctrl_req; 9833f95001dSMian Yousaf Kaukab void *ep0_buff; 9843f95001dSMian Yousaf Kaukab void *ctrl_buff; 985fe0b94abSMian Yousaf Kaukab enum dwc2_ep0_state ep0_state; 9869e14d0a5SGregory Herrero u8 test_mode; 987941fcce4SDinh Nguyen 988941fcce4SDinh Nguyen struct usb_gadget gadget; 989dc6e69e6SMarek Szyprowski unsigned int enabled:1; 9904ace06e8SMarek Szyprowski unsigned int connected:1; 9911f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS]; 9921f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS]; 993edd74be8SGregory Herrero u32 g_using_dma; 9940a176279SGregory Herrero u32 g_rx_fifo_sz; 9950a176279SGregory Herrero u32 g_np_g_tx_fifo_sz; 9960a176279SGregory Herrero u32 g_tx_fifo_sz[MAX_EPS_CHANNELS]; 997941fcce4SDinh Nguyen #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 998197ba5f4SPaul Zimmerman }; 999197ba5f4SPaul Zimmerman 1000197ba5f4SPaul Zimmerman /* Reasons for halting a host channel */ 1001197ba5f4SPaul Zimmerman enum dwc2_halt_status { 1002197ba5f4SPaul Zimmerman DWC2_HC_XFER_NO_HALT_STATUS, 1003197ba5f4SPaul Zimmerman DWC2_HC_XFER_COMPLETE, 1004197ba5f4SPaul Zimmerman DWC2_HC_XFER_URB_COMPLETE, 1005197ba5f4SPaul Zimmerman DWC2_HC_XFER_ACK, 1006197ba5f4SPaul Zimmerman DWC2_HC_XFER_NAK, 1007197ba5f4SPaul Zimmerman DWC2_HC_XFER_NYET, 1008197ba5f4SPaul Zimmerman DWC2_HC_XFER_STALL, 1009197ba5f4SPaul Zimmerman DWC2_HC_XFER_XACT_ERR, 1010197ba5f4SPaul Zimmerman DWC2_HC_XFER_FRAME_OVERRUN, 1011197ba5f4SPaul Zimmerman DWC2_HC_XFER_BABBLE_ERR, 1012197ba5f4SPaul Zimmerman DWC2_HC_XFER_DATA_TOGGLE_ERR, 1013197ba5f4SPaul Zimmerman DWC2_HC_XFER_AHB_ERR, 1014197ba5f4SPaul Zimmerman DWC2_HC_XFER_PERIODIC_INCOMPLETE, 1015197ba5f4SPaul Zimmerman DWC2_HC_XFER_URB_DEQUEUE, 1016197ba5f4SPaul Zimmerman }; 1017197ba5f4SPaul Zimmerman 1018197ba5f4SPaul Zimmerman /* 1019197ba5f4SPaul Zimmerman * The following functions support initialization of the core driver component 1020197ba5f4SPaul Zimmerman * and the DWC_otg controller 1021197ba5f4SPaul Zimmerman */ 1022b5d308abSJohn Youn extern int dwc2_core_reset(struct dwc2_hsotg *hsotg); 10236d58f346SJohn Youn extern int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg); 1024d17ee77bSGregory Herrero extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg); 1025d17ee77bSGregory Herrero extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore); 1026197ba5f4SPaul Zimmerman 1027323230efSJohn Youn bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host); 1028323230efSJohn Youn void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg); 102909c96980SJohn Youn void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg); 103009c96980SJohn Youn 1031197ba5f4SPaul Zimmerman extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 1032197ba5f4SPaul Zimmerman 1033197ba5f4SPaul Zimmerman /* 1034197ba5f4SPaul Zimmerman * Common core Functions. 1035197ba5f4SPaul Zimmerman * The following functions support managing the DWC_otg controller in either 1036197ba5f4SPaul Zimmerman * device or host mode. 1037197ba5f4SPaul Zimmerman */ 1038197ba5f4SPaul Zimmerman extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 1039197ba5f4SPaul Zimmerman extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 1040197ba5f4SPaul Zimmerman extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 1041197ba5f4SPaul Zimmerman 1042197ba5f4SPaul Zimmerman extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 1043197ba5f4SPaul Zimmerman extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 1044197ba5f4SPaul Zimmerman 1045197ba5f4SPaul Zimmerman /* This function should be called on every hardware interrupt. */ 1046197ba5f4SPaul Zimmerman extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 1047197ba5f4SPaul Zimmerman 1048323230efSJohn Youn /* The device ID match table */ 1049323230efSJohn Youn extern const struct of_device_id dwc2_of_match_table[]; 1050323230efSJohn Youn 1051197ba5f4SPaul Zimmerman /* OTG Core Parameters */ 1052197ba5f4SPaul Zimmerman 1053197ba5f4SPaul Zimmerman /* 1054197ba5f4SPaul Zimmerman * Specifies the OTG capabilities. The driver will automatically 1055197ba5f4SPaul Zimmerman * detect the value for this parameter if none is specified. 1056197ba5f4SPaul Zimmerman * 0 - HNP and SRP capable (default) 1057197ba5f4SPaul Zimmerman * 1 - SRP Only capable 1058197ba5f4SPaul Zimmerman * 2 - No HNP/SRP capable 1059197ba5f4SPaul Zimmerman */ 1060197ba5f4SPaul Zimmerman extern void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val); 1061197ba5f4SPaul Zimmerman #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 1062197ba5f4SPaul Zimmerman #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 1063197ba5f4SPaul Zimmerman #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 1064197ba5f4SPaul Zimmerman 1065197ba5f4SPaul Zimmerman /* 1066197ba5f4SPaul Zimmerman * Specifies whether to use slave or DMA mode for accessing the data 1067197ba5f4SPaul Zimmerman * FIFOs. The driver will automatically detect the value for this 1068197ba5f4SPaul Zimmerman * parameter if none is specified. 1069197ba5f4SPaul Zimmerman * 0 - Slave 1070197ba5f4SPaul Zimmerman * 1 - DMA (default, if available) 1071197ba5f4SPaul Zimmerman */ 1072197ba5f4SPaul Zimmerman extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val); 1073197ba5f4SPaul Zimmerman 1074197ba5f4SPaul Zimmerman /* 1075197ba5f4SPaul Zimmerman * When DMA mode is enabled specifies whether to use 1076197ba5f4SPaul Zimmerman * address DMA or DMA Descritor mode for accessing the data 1077197ba5f4SPaul Zimmerman * FIFOs in device mode. The driver will automatically detect 1078197ba5f4SPaul Zimmerman * the value for this parameter if none is specified. 1079197ba5f4SPaul Zimmerman * 0 - address DMA 1080197ba5f4SPaul Zimmerman * 1 - DMA Descriptor(default, if available) 1081197ba5f4SPaul Zimmerman */ 1082197ba5f4SPaul Zimmerman extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val); 1083197ba5f4SPaul Zimmerman 1084197ba5f4SPaul Zimmerman /* 1085fbb9e22bSMian Yousaf Kaukab * When DMA mode is enabled specifies whether to use 1086fbb9e22bSMian Yousaf Kaukab * address DMA or DMA Descritor mode with full speed devices 1087fbb9e22bSMian Yousaf Kaukab * for accessing the data FIFOs in host mode. 1088fbb9e22bSMian Yousaf Kaukab * 0 - address DMA 1089fbb9e22bSMian Yousaf Kaukab * 1 - FS DMA Descriptor(default, if available) 1090fbb9e22bSMian Yousaf Kaukab */ 1091fbb9e22bSMian Yousaf Kaukab extern void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg, 1092fbb9e22bSMian Yousaf Kaukab int val); 1093fbb9e22bSMian Yousaf Kaukab 1094fbb9e22bSMian Yousaf Kaukab /* 1095197ba5f4SPaul Zimmerman * Specifies the maximum speed of operation in host and device mode. 1096197ba5f4SPaul Zimmerman * The actual speed depends on the speed of the attached device and 1097197ba5f4SPaul Zimmerman * the value of phy_type. The actual speed depends on the speed of the 1098197ba5f4SPaul Zimmerman * attached device. 1099197ba5f4SPaul Zimmerman * 0 - High Speed (default) 1100197ba5f4SPaul Zimmerman * 1 - Full Speed 1101197ba5f4SPaul Zimmerman */ 1102197ba5f4SPaul Zimmerman extern void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val); 1103197ba5f4SPaul Zimmerman #define DWC2_SPEED_PARAM_HIGH 0 1104197ba5f4SPaul Zimmerman #define DWC2_SPEED_PARAM_FULL 1 1105197ba5f4SPaul Zimmerman 1106197ba5f4SPaul Zimmerman /* 1107197ba5f4SPaul Zimmerman * Specifies whether low power mode is supported when attached 1108197ba5f4SPaul Zimmerman * to a Full Speed or Low Speed device in host mode. 1109197ba5f4SPaul Zimmerman * 1110197ba5f4SPaul Zimmerman * 0 - Don't support low power mode (default) 1111197ba5f4SPaul Zimmerman * 1 - Support low power mode 1112197ba5f4SPaul Zimmerman */ 1113197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_support_fs_ls_low_power( 1114197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg, int val); 1115197ba5f4SPaul Zimmerman 1116197ba5f4SPaul Zimmerman /* 1117197ba5f4SPaul Zimmerman * Specifies the PHY clock rate in low power mode when connected to a 1118197ba5f4SPaul Zimmerman * Low Speed device in host mode. This parameter is applicable only if 1119197ba5f4SPaul Zimmerman * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS 1120197ba5f4SPaul Zimmerman * then defaults to 6 MHZ otherwise 48 MHZ. 1121197ba5f4SPaul Zimmerman * 1122197ba5f4SPaul Zimmerman * 0 - 48 MHz 1123197ba5f4SPaul Zimmerman * 1 - 6 MHz 1124197ba5f4SPaul Zimmerman */ 1125197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, 1126197ba5f4SPaul Zimmerman int val); 1127197ba5f4SPaul Zimmerman #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 1128197ba5f4SPaul Zimmerman #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 1129197ba5f4SPaul Zimmerman 1130197ba5f4SPaul Zimmerman /* 1131197ba5f4SPaul Zimmerman * 0 - Use cC FIFO size parameters 1132197ba5f4SPaul Zimmerman * 1 - Allow dynamic FIFO sizing (default) 1133197ba5f4SPaul Zimmerman */ 1134197ba5f4SPaul Zimmerman extern void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, 1135197ba5f4SPaul Zimmerman int val); 1136197ba5f4SPaul Zimmerman 1137197ba5f4SPaul Zimmerman /* 1138197ba5f4SPaul Zimmerman * Number of 4-byte words in the Rx FIFO in host mode when dynamic 1139197ba5f4SPaul Zimmerman * FIFO sizing is enabled. 1140197ba5f4SPaul Zimmerman * 16 to 32768 (default 1024) 1141197ba5f4SPaul Zimmerman */ 1142197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val); 1143197ba5f4SPaul Zimmerman 1144197ba5f4SPaul Zimmerman /* 1145197ba5f4SPaul Zimmerman * Number of 4-byte words in the non-periodic Tx FIFO in host mode 1146197ba5f4SPaul Zimmerman * when Dynamic FIFO sizing is enabled in the core. 1147197ba5f4SPaul Zimmerman * 16 to 32768 (default 256) 1148197ba5f4SPaul Zimmerman */ 1149197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, 1150197ba5f4SPaul Zimmerman int val); 1151197ba5f4SPaul Zimmerman 1152197ba5f4SPaul Zimmerman /* 1153197ba5f4SPaul Zimmerman * Number of 4-byte words in the host periodic Tx FIFO when dynamic 1154197ba5f4SPaul Zimmerman * FIFO sizing is enabled. 1155197ba5f4SPaul Zimmerman * 16 to 32768 (default 256) 1156197ba5f4SPaul Zimmerman */ 1157197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, 1158197ba5f4SPaul Zimmerman int val); 1159197ba5f4SPaul Zimmerman 1160197ba5f4SPaul Zimmerman /* 1161197ba5f4SPaul Zimmerman * The maximum transfer size supported in bytes. 1162197ba5f4SPaul Zimmerman * 2047 to 65,535 (default 65,535) 1163197ba5f4SPaul Zimmerman */ 1164197ba5f4SPaul Zimmerman extern void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val); 1165197ba5f4SPaul Zimmerman 1166197ba5f4SPaul Zimmerman /* 1167197ba5f4SPaul Zimmerman * The maximum number of packets in a transfer. 1168197ba5f4SPaul Zimmerman * 15 to 511 (default 511) 1169197ba5f4SPaul Zimmerman */ 1170197ba5f4SPaul Zimmerman extern void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val); 1171197ba5f4SPaul Zimmerman 1172197ba5f4SPaul Zimmerman /* 1173197ba5f4SPaul Zimmerman * The number of host channel registers to use. 1174197ba5f4SPaul Zimmerman * 1 to 16 (default 11) 1175197ba5f4SPaul Zimmerman * Note: The FPGA configuration supports a maximum of 11 host channels. 1176197ba5f4SPaul Zimmerman */ 1177197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val); 1178197ba5f4SPaul Zimmerman 1179197ba5f4SPaul Zimmerman /* 1180197ba5f4SPaul Zimmerman * Specifies the type of PHY interface to use. By default, the driver 1181197ba5f4SPaul Zimmerman * will automatically detect the phy_type. 1182197ba5f4SPaul Zimmerman * 1183197ba5f4SPaul Zimmerman * 0 - Full Speed PHY 1184197ba5f4SPaul Zimmerman * 1 - UTMI+ (default) 1185197ba5f4SPaul Zimmerman * 2 - ULPI 1186197ba5f4SPaul Zimmerman */ 1187197ba5f4SPaul Zimmerman extern void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val); 1188197ba5f4SPaul Zimmerman #define DWC2_PHY_TYPE_PARAM_FS 0 1189197ba5f4SPaul Zimmerman #define DWC2_PHY_TYPE_PARAM_UTMI 1 1190197ba5f4SPaul Zimmerman #define DWC2_PHY_TYPE_PARAM_ULPI 2 1191197ba5f4SPaul Zimmerman 1192197ba5f4SPaul Zimmerman /* 1193197ba5f4SPaul Zimmerman * Specifies the UTMI+ Data Width. This parameter is 1194197ba5f4SPaul Zimmerman * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI 1195197ba5f4SPaul Zimmerman * PHY_TYPE, this parameter indicates the data width between 1196197ba5f4SPaul Zimmerman * the MAC and the ULPI Wrapper.) Also, this parameter is 1197197ba5f4SPaul Zimmerman * applicable only if the OTG_HSPHY_WIDTH cC parameter was set 1198197ba5f4SPaul Zimmerman * to "8 and 16 bits", meaning that the core has been 1199197ba5f4SPaul Zimmerman * configured to work at either data path width. 1200197ba5f4SPaul Zimmerman * 1201197ba5f4SPaul Zimmerman * 8 or 16 bits (default 16) 1202197ba5f4SPaul Zimmerman */ 1203197ba5f4SPaul Zimmerman extern void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val); 1204197ba5f4SPaul Zimmerman 1205197ba5f4SPaul Zimmerman /* 1206197ba5f4SPaul Zimmerman * Specifies whether the ULPI operates at double or single 1207197ba5f4SPaul Zimmerman * data rate. This parameter is only applicable if PHY_TYPE is 1208197ba5f4SPaul Zimmerman * ULPI. 1209197ba5f4SPaul Zimmerman * 1210197ba5f4SPaul Zimmerman * 0 - single data rate ULPI interface with 8 bit wide data 1211197ba5f4SPaul Zimmerman * bus (default) 1212197ba5f4SPaul Zimmerman * 1 - double data rate ULPI interface with 4 bit wide data 1213197ba5f4SPaul Zimmerman * bus 1214197ba5f4SPaul Zimmerman */ 1215197ba5f4SPaul Zimmerman extern void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val); 1216197ba5f4SPaul Zimmerman 1217197ba5f4SPaul Zimmerman /* 1218197ba5f4SPaul Zimmerman * Specifies whether to use the internal or external supply to 1219197ba5f4SPaul Zimmerman * drive the vbus with a ULPI phy. 1220197ba5f4SPaul Zimmerman */ 1221197ba5f4SPaul Zimmerman extern void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val); 1222197ba5f4SPaul Zimmerman #define DWC2_PHY_ULPI_INTERNAL_VBUS 0 1223197ba5f4SPaul Zimmerman #define DWC2_PHY_ULPI_EXTERNAL_VBUS 1 1224197ba5f4SPaul Zimmerman 1225197ba5f4SPaul Zimmerman /* 1226197ba5f4SPaul Zimmerman * Specifies whether to use the I2Cinterface for full speed PHY. This 1227197ba5f4SPaul Zimmerman * parameter is only applicable if PHY_TYPE is FS. 1228197ba5f4SPaul Zimmerman * 0 - No (default) 1229197ba5f4SPaul Zimmerman * 1 - Yes 1230197ba5f4SPaul Zimmerman */ 1231197ba5f4SPaul Zimmerman extern void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val); 1232197ba5f4SPaul Zimmerman 1233197ba5f4SPaul Zimmerman extern void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val); 1234197ba5f4SPaul Zimmerman 1235197ba5f4SPaul Zimmerman extern void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val); 1236197ba5f4SPaul Zimmerman 1237197ba5f4SPaul Zimmerman /* 1238197ba5f4SPaul Zimmerman * Specifies whether dedicated transmit FIFOs are 1239197ba5f4SPaul Zimmerman * enabled for non periodic IN endpoints in device mode 1240197ba5f4SPaul Zimmerman * 0 - No 1241197ba5f4SPaul Zimmerman * 1 - Yes 1242197ba5f4SPaul Zimmerman */ 1243197ba5f4SPaul Zimmerman extern void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, 1244197ba5f4SPaul Zimmerman int val); 1245197ba5f4SPaul Zimmerman 1246197ba5f4SPaul Zimmerman extern void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val); 1247197ba5f4SPaul Zimmerman 1248197ba5f4SPaul Zimmerman extern void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val); 1249197ba5f4SPaul Zimmerman 1250197ba5f4SPaul Zimmerman extern void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val); 1251197ba5f4SPaul Zimmerman 1252ecb176c6SMian Yousaf Kaukab extern void dwc2_set_parameters(struct dwc2_hsotg *hsotg, 1253ecb176c6SMian Yousaf Kaukab const struct dwc2_core_params *params); 1254ecb176c6SMian Yousaf Kaukab 1255ecb176c6SMian Yousaf Kaukab extern void dwc2_set_all_params(struct dwc2_core_params *params, int value); 1256ecb176c6SMian Yousaf Kaukab 1257ecb176c6SMian Yousaf Kaukab extern int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); 1258ecb176c6SMian Yousaf Kaukab 125909a75e85SMarek Szyprowski extern int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg); 126009a75e85SMarek Szyprowski extern int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg); 1261ecb176c6SMian Yousaf Kaukab 1262197ba5f4SPaul Zimmerman /* 12636bea9620SJohn Youn * The following functions check the controller's OTG operation mode 12646bea9620SJohn Youn * capability (GHWCFG2.OTG_MODE). 12656bea9620SJohn Youn * 12666bea9620SJohn Youn * These functions can be used before the internal hsotg->hw_params 12676bea9620SJohn Youn * are read in and cached so they always read directly from the 12686bea9620SJohn Youn * GHWCFG2 register. 12696bea9620SJohn Youn */ 12706bea9620SJohn Youn unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg); 12716bea9620SJohn Youn bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg); 12726bea9620SJohn Youn bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg); 12736bea9620SJohn Youn bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg); 12746bea9620SJohn Youn 12756bea9620SJohn Youn /* 12761696d5abSJohn Youn * Returns the mode of operation, host or device 12771696d5abSJohn Youn */ 12781696d5abSJohn Youn static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) 12791696d5abSJohn Youn { 12801696d5abSJohn Youn return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0; 12811696d5abSJohn Youn } 12821696d5abSJohn Youn static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) 12831696d5abSJohn Youn { 12841696d5abSJohn Youn return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0; 12851696d5abSJohn Youn } 12861696d5abSJohn Youn 12871696d5abSJohn Youn /* 1288197ba5f4SPaul Zimmerman * Dump core registers and SPRAM 1289197ba5f4SPaul Zimmerman */ 1290197ba5f4SPaul Zimmerman extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 1291197ba5f4SPaul Zimmerman extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 1292197ba5f4SPaul Zimmerman extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 1293197ba5f4SPaul Zimmerman 1294197ba5f4SPaul Zimmerman /* 1295197ba5f4SPaul Zimmerman * Return OTG version - either 1.3 or 2.0 1296197ba5f4SPaul Zimmerman */ 1297197ba5f4SPaul Zimmerman extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg); 1298197ba5f4SPaul Zimmerman 1299117777b2SDinh Nguyen /* Gadget defines */ 1300117777b2SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 13011f91b4ccSFelipe Balbi extern int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg); 13021f91b4ccSFelipe Balbi extern int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2); 13031f91b4ccSFelipe Balbi extern int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2); 1304117777b2SDinh Nguyen extern int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq); 13051f91b4ccSFelipe Balbi extern void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1306643cc4deSGregory Herrero bool reset); 13071f91b4ccSFelipe Balbi extern void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg); 13081f91b4ccSFelipe Balbi extern void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2); 13091f91b4ccSFelipe Balbi extern int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode); 1310f81f46e1SGregory Herrero #define dwc2_is_device_connected(hsotg) (hsotg->connected) 131158e52ff6SJohn Youn int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg); 131258e52ff6SJohn Youn int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg); 1313117777b2SDinh Nguyen #else 13141f91b4ccSFelipe Balbi static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2) 1315117777b2SDinh Nguyen { return 0; } 13161f91b4ccSFelipe Balbi static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2) 1317117777b2SDinh Nguyen { return 0; } 13181f91b4ccSFelipe Balbi static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2) 1319117777b2SDinh Nguyen { return 0; } 1320117777b2SDinh Nguyen static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) 1321117777b2SDinh Nguyen { return 0; } 13221f91b4ccSFelipe Balbi static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1323643cc4deSGregory Herrero bool reset) {} 13241f91b4ccSFelipe Balbi static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} 13251f91b4ccSFelipe Balbi static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} 13261f91b4ccSFelipe Balbi static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, 1327f91eea44SMian Yousaf Kaukab int testmode) 1328f91eea44SMian Yousaf Kaukab { return 0; } 1329f81f46e1SGregory Herrero #define dwc2_is_device_connected(hsotg) (0) 133058e52ff6SJohn Youn static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) 133158e52ff6SJohn Youn { return 0; } 133258e52ff6SJohn Youn static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg) 133358e52ff6SJohn Youn { return 0; } 1334117777b2SDinh Nguyen #endif 1335117777b2SDinh Nguyen 1336117777b2SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1337117777b2SDinh Nguyen extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 1338fae4e826SDouglas Anderson extern int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us); 13396a659531SDouglas Anderson extern void dwc2_hcd_connect(struct dwc2_hsotg *hsotg); 13406a659531SDouglas Anderson extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force); 1341117777b2SDinh Nguyen extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 134258e52ff6SJohn Youn int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg); 134358e52ff6SJohn Youn int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg); 1344117777b2SDinh Nguyen #else 1345117777b2SDinh Nguyen static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1346117777b2SDinh Nguyen { return 0; } 1347fae4e826SDouglas Anderson static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, 1348fae4e826SDouglas Anderson int us) 1349fae4e826SDouglas Anderson { return 0; } 13506a659531SDouglas Anderson static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {} 13516a659531SDouglas Anderson static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {} 1352117777b2SDinh Nguyen static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} 1353117777b2SDinh Nguyen static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} 1354ecb176c6SMian Yousaf Kaukab static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) 1355117777b2SDinh Nguyen { return 0; } 135658e52ff6SJohn Youn static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 135758e52ff6SJohn Youn { return 0; } 135858e52ff6SJohn Youn static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 135958e52ff6SJohn Youn { return 0; } 136058e52ff6SJohn Youn 1361117777b2SDinh Nguyen #endif 1362117777b2SDinh Nguyen 1363197ba5f4SPaul Zimmerman #endif /* __DWC2_CORE_H__ */ 1364