1bdefa3baSNishad Kamdar /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2197ba5f4SPaul Zimmerman /* 3197ba5f4SPaul Zimmerman * core.h - DesignWare HS OTG Controller common declarations 4197ba5f4SPaul Zimmerman * 5197ba5f4SPaul Zimmerman * Copyright (C) 2004-2013 Synopsys, Inc. 6197ba5f4SPaul Zimmerman */ 7197ba5f4SPaul Zimmerman 8197ba5f4SPaul Zimmerman #ifndef __DWC2_CORE_H__ 9197ba5f4SPaul Zimmerman #define __DWC2_CORE_H__ 10197ba5f4SPaul Zimmerman 112e5db2c0SJeremy Linton #include <linux/acpi.h> 12f7c0b143SDinh Nguyen #include <linux/phy/phy.h> 13f7c0b143SDinh Nguyen #include <linux/regulator/consumer.h> 14f7c0b143SDinh Nguyen #include <linux/usb/gadget.h> 15f7c0b143SDinh Nguyen #include <linux/usb/otg.h> 16197ba5f4SPaul Zimmerman #include <linux/usb/phy.h> 17197ba5f4SPaul Zimmerman #include "hw.h" 18197ba5f4SPaul Zimmerman 1974fc4a75SDouglas Anderson /* 2074fc4a75SDouglas Anderson * Suggested defines for tracers: 2174fc4a75SDouglas Anderson * - no_printk: Disable tracing 2274fc4a75SDouglas Anderson * - pr_info: Print this info to the console 2374fc4a75SDouglas Anderson * - trace_printk: Print this info to trace buffer (good for verbose logging) 2474fc4a75SDouglas Anderson */ 2574fc4a75SDouglas Anderson 2674fc4a75SDouglas Anderson #define DWC2_TRACE_SCHEDULER no_printk 2774fc4a75SDouglas Anderson #define DWC2_TRACE_SCHEDULER_VB no_printk 2874fc4a75SDouglas Anderson 2974fc4a75SDouglas Anderson /* Detailed scheduler tracing, but won't overwhelm console */ 3074fc4a75SDouglas Anderson #define dwc2_sch_dbg(hsotg, fmt, ...) \ 3174fc4a75SDouglas Anderson DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \ 3274fc4a75SDouglas Anderson dev_name(hsotg->dev), ##__VA_ARGS__) 3374fc4a75SDouglas Anderson 3474fc4a75SDouglas Anderson /* Verbose scheduler tracing */ 3574fc4a75SDouglas Anderson #define dwc2_sch_vdbg(hsotg, fmt, ...) \ 3674fc4a75SDouglas Anderson DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \ 3774fc4a75SDouglas Anderson dev_name(hsotg->dev), ##__VA_ARGS__) 3874fc4a75SDouglas Anderson 39197ba5f4SPaul Zimmerman /* Maximum number of Endpoints/HostChannels */ 40197ba5f4SPaul Zimmerman #define MAX_EPS_CHANNELS 16 41197ba5f4SPaul Zimmerman 421f91b4ccSFelipe Balbi /* dwc2-hsotg declarations */ 431f91b4ccSFelipe Balbi static const char * const dwc2_hsotg_supply_names[] = { 44f7c0b143SDinh Nguyen "vusb_d", /* digital USB supply, 1.2V */ 45f7c0b143SDinh Nguyen "vusb_a", /* analog USB supply, 1.1V */ 46f7c0b143SDinh Nguyen }; 47f7c0b143SDinh Nguyen 48b98866c2SJohn Youn #define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names) 49b98866c2SJohn Youn 50f7c0b143SDinh Nguyen /* 51f7c0b143SDinh Nguyen * EP0_MPS_LIMIT 52f7c0b143SDinh Nguyen * 53f7c0b143SDinh Nguyen * Unfortunately there seems to be a limit of the amount of data that can 54f7c0b143SDinh Nguyen * be transferred by IN transactions on EP0. This is either 127 bytes or 3 55f7c0b143SDinh Nguyen * packets (which practically means 1 packet and 63 bytes of data) when the 56f7c0b143SDinh Nguyen * MPS is set to 64. 57f7c0b143SDinh Nguyen * 58f7c0b143SDinh Nguyen * This means if we are wanting to move >127 bytes of data, we need to 59f7c0b143SDinh Nguyen * split the transactions up, but just doing one packet at a time does 60f7c0b143SDinh Nguyen * not work (this may be an implicit DATA0 PID on first packet of the 61f7c0b143SDinh Nguyen * transaction) and doing 2 packets is outside the controller's limits. 62f7c0b143SDinh Nguyen * 63f7c0b143SDinh Nguyen * If we try to lower the MPS size for EP0, then no transfers work properly 64f7c0b143SDinh Nguyen * for EP0, and the system will fail basic enumeration. As no cause for this 65f7c0b143SDinh Nguyen * has currently been found, we cannot support any large IN transfers for 66f7c0b143SDinh Nguyen * EP0. 67f7c0b143SDinh Nguyen */ 68f7c0b143SDinh Nguyen #define EP0_MPS_LIMIT 64 69f7c0b143SDinh Nguyen 70941fcce4SDinh Nguyen struct dwc2_hsotg; 711f91b4ccSFelipe Balbi struct dwc2_hsotg_req; 72f7c0b143SDinh Nguyen 73f7c0b143SDinh Nguyen /** 741f91b4ccSFelipe Balbi * struct dwc2_hsotg_ep - driver endpoint definition. 75f7c0b143SDinh Nguyen * @ep: The gadget layer representation of the endpoint. 76f7c0b143SDinh Nguyen * @name: The driver generated name for the endpoint. 77f7c0b143SDinh Nguyen * @queue: Queue of requests for this endpoint. 78f7c0b143SDinh Nguyen * @parent: Reference back to the parent device structure. 79f7c0b143SDinh Nguyen * @req: The current request that the endpoint is processing. This is 80f7c0b143SDinh Nguyen * used to indicate an request has been loaded onto the endpoint 81f7c0b143SDinh Nguyen * and has yet to be completed (maybe due to data move, or simply 82f7c0b143SDinh Nguyen * awaiting an ack from the core all the data has been completed). 83f7c0b143SDinh Nguyen * @debugfs: File entry for debugfs file for this endpoint. 84f7c0b143SDinh Nguyen * @dir_in: Set to true if this endpoint is of the IN direction, which 85f7c0b143SDinh Nguyen * means that it is sending data to the Host. 8675a41ce4SPhil Elwell * @map_dir: Set to the value of dir_in when the DMA buffer is mapped. 87f7c0b143SDinh Nguyen * @index: The index for the endpoint registers. 88f7c0b143SDinh Nguyen * @mc: Multi Count - number of transactions per microframe 896fb914d7SGrigor Tovmasyan * @interval: Interval for periodic endpoints, in frames or microframes. 90f7c0b143SDinh Nguyen * @name: The name array passed to the USB core. 91f7c0b143SDinh Nguyen * @halted: Set if the endpoint has been halted. 92f7c0b143SDinh Nguyen * @periodic: Set if this is a periodic ep, such as Interrupt 93f7c0b143SDinh Nguyen * @isochronous: Set if this is a isochronous ep 948a20fa45SMian Yousaf Kaukab * @send_zlp: Set if we need to send a zero-length packet. 95b833ce15SMinas Harutyunyan * @wedged: Set if ep is wedged. 965f54c54bSVahram Aharonyan * @desc_list_dma: The DMA address of descriptor chain currently in use. 975f54c54bSVahram Aharonyan * @desc_list: Pointer to descriptor DMA chain head currently in use. 985f54c54bSVahram Aharonyan * @desc_count: Count of entries within the DMA descriptor chain of EP. 99ab7d2192SVahram Aharonyan * @next_desc: index of next free descriptor in the ISOC chain under SW control. 100729cac69SMinas Harutyunyan * @compl_desc: index of next descriptor to be completed by xFerComplete 101f7c0b143SDinh Nguyen * @total_data: The total number of data bytes done. 102f7c0b143SDinh Nguyen * @fifo_size: The size of the FIFO (for periodic IN endpoints) 1036fb914d7SGrigor Tovmasyan * @fifo_index: For Dedicated FIFO operation, only FIFO0 can be used for EP0. 104f7c0b143SDinh Nguyen * @fifo_load: The amount of data loaded into the FIFO (periodic IN) 105f7c0b143SDinh Nguyen * @last_load: The offset of data for the last start of request. 106f7c0b143SDinh Nguyen * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN 10792d1635dSVardan Mikayelyan * @target_frame: Targeted frame num to setup next ISOC transfer 10892d1635dSVardan Mikayelyan * @frame_overrun: Indicates SOF number overrun in DSTS 109f7c0b143SDinh Nguyen * 110c1aa81daSGeert Uytterhoeven * This is the driver's state for each registered endpoint, allowing it 111f7c0b143SDinh Nguyen * to keep track of transactions that need doing. Each endpoint has a 112f7c0b143SDinh Nguyen * lock to protect the state, to try and avoid using an overall lock 113f7c0b143SDinh Nguyen * for the host controller as much as possible. 114f7c0b143SDinh Nguyen * 115f7c0b143SDinh Nguyen * For periodic IN endpoints, we have fifo_size and fifo_load to try 116f7c0b143SDinh Nguyen * and keep track of the amount of data in the periodic FIFO for each 117f7c0b143SDinh Nguyen * of these as we don't have a status register that tells us how much 118f7c0b143SDinh Nguyen * is in each of them. (note, this may actually be useless information 119f7c0b143SDinh Nguyen * as in shared-fifo mode periodic in acts like a single-frame packet 120f7c0b143SDinh Nguyen * buffer than a fifo) 121f7c0b143SDinh Nguyen */ 1221f91b4ccSFelipe Balbi struct dwc2_hsotg_ep { 123f7c0b143SDinh Nguyen struct usb_ep ep; 124f7c0b143SDinh Nguyen struct list_head queue; 125941fcce4SDinh Nguyen struct dwc2_hsotg *parent; 1261f91b4ccSFelipe Balbi struct dwc2_hsotg_req *req; 127f7c0b143SDinh Nguyen struct dentry *debugfs; 128f7c0b143SDinh Nguyen 129f7c0b143SDinh Nguyen unsigned long total_data; 130f7c0b143SDinh Nguyen unsigned int size_loaded; 131f7c0b143SDinh Nguyen unsigned int last_load; 132f7c0b143SDinh Nguyen unsigned int fifo_load; 133f7c0b143SDinh Nguyen unsigned short fifo_size; 134b203d0a2SRobert Baldyga unsigned short fifo_index; 135f7c0b143SDinh Nguyen 136f7c0b143SDinh Nguyen unsigned char dir_in; 13775a41ce4SPhil Elwell unsigned char map_dir; 138f7c0b143SDinh Nguyen unsigned char index; 139f7c0b143SDinh Nguyen unsigned char mc; 14012814a3fSGrigor Tovmasyan u16 interval; 141f7c0b143SDinh Nguyen 142f7c0b143SDinh Nguyen unsigned int halted:1; 143f7c0b143SDinh Nguyen unsigned int periodic:1; 144f7c0b143SDinh Nguyen unsigned int isochronous:1; 1458a20fa45SMian Yousaf Kaukab unsigned int send_zlp:1; 146b833ce15SMinas Harutyunyan unsigned int wedged:1; 14792d1635dSVardan Mikayelyan unsigned int target_frame; 14892d1635dSVardan Mikayelyan #define TARGET_FRAME_INITIAL 0xFFFFFFFF 14992d1635dSVardan Mikayelyan bool frame_overrun; 150f7c0b143SDinh Nguyen 1515f54c54bSVahram Aharonyan dma_addr_t desc_list_dma; 1525f54c54bSVahram Aharonyan struct dwc2_dma_desc *desc_list; 1535f54c54bSVahram Aharonyan u8 desc_count; 1545f54c54bSVahram Aharonyan 155ab7d2192SVahram Aharonyan unsigned int next_desc; 156729cac69SMinas Harutyunyan unsigned int compl_desc; 157ab7d2192SVahram Aharonyan 158f7c0b143SDinh Nguyen char name[10]; 159f7c0b143SDinh Nguyen }; 160f7c0b143SDinh Nguyen 161f7c0b143SDinh Nguyen /** 1621f91b4ccSFelipe Balbi * struct dwc2_hsotg_req - data transfer request 163f7c0b143SDinh Nguyen * @req: The USB gadget request 164f7c0b143SDinh Nguyen * @queue: The list of requests for the endpoint this is queued for. 1657d24c1b5SMian Yousaf Kaukab * @saved_req_buf: variable to save req.buf when bounce buffers are used. 166f7c0b143SDinh Nguyen */ 1671f91b4ccSFelipe Balbi struct dwc2_hsotg_req { 168f7c0b143SDinh Nguyen struct usb_request req; 169f7c0b143SDinh Nguyen struct list_head queue; 1707d24c1b5SMian Yousaf Kaukab void *saved_req_buf; 171f7c0b143SDinh Nguyen }; 172f7c0b143SDinh Nguyen 173b98866c2SJohn Youn #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 174b98866c2SJohn Youn IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 175f7c0b143SDinh Nguyen #define call_gadget(_hs, _entry) \ 176f7c0b143SDinh Nguyen do { \ 177f7c0b143SDinh Nguyen if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ 178f7c0b143SDinh Nguyen (_hs)->driver && (_hs)->driver->_entry) { \ 179f7c0b143SDinh Nguyen spin_unlock(&_hs->lock); \ 180f7c0b143SDinh Nguyen (_hs)->driver->_entry(&(_hs)->gadget); \ 181f7c0b143SDinh Nguyen spin_lock(&_hs->lock); \ 182f7c0b143SDinh Nguyen } \ 183f7c0b143SDinh Nguyen } while (0) 184941fcce4SDinh Nguyen #else 185941fcce4SDinh Nguyen #define call_gadget(_hs, _entry) do {} while (0) 186941fcce4SDinh Nguyen #endif 187f7c0b143SDinh Nguyen 188197ba5f4SPaul Zimmerman struct dwc2_hsotg; 189197ba5f4SPaul Zimmerman struct dwc2_host_chan; 190197ba5f4SPaul Zimmerman 191197ba5f4SPaul Zimmerman /* Device States */ 192197ba5f4SPaul Zimmerman enum dwc2_lx_state { 193197ba5f4SPaul Zimmerman DWC2_L0, /* On state */ 194197ba5f4SPaul Zimmerman DWC2_L1, /* LPM sleep state */ 195197ba5f4SPaul Zimmerman DWC2_L2, /* USB suspend state */ 196197ba5f4SPaul Zimmerman DWC2_L3, /* Off state */ 197197ba5f4SPaul Zimmerman }; 198197ba5f4SPaul Zimmerman 199fe0b94abSMian Yousaf Kaukab /* Gadget ep0 states */ 200fe0b94abSMian Yousaf Kaukab enum dwc2_ep0_state { 201fe0b94abSMian Yousaf Kaukab DWC2_EP0_SETUP, 202fe0b94abSMian Yousaf Kaukab DWC2_EP0_DATA_IN, 203fe0b94abSMian Yousaf Kaukab DWC2_EP0_DATA_OUT, 204fe0b94abSMian Yousaf Kaukab DWC2_EP0_STATUS_IN, 205fe0b94abSMian Yousaf Kaukab DWC2_EP0_STATUS_OUT, 206fe0b94abSMian Yousaf Kaukab }; 207fe0b94abSMian Yousaf Kaukab 208197ba5f4SPaul Zimmerman /** 209197ba5f4SPaul Zimmerman * struct dwc2_core_params - Parameters for configuring the core 210197ba5f4SPaul Zimmerman * 211f5c8a6cbSFabrice Gasnier * @otg_caps: Specifies the OTG capabilities. OTG caps from the platform parameters, 212f5c8a6cbSFabrice Gasnier * used to setup the: 213f5c8a6cbSFabrice Gasnier * - HNP and SRP capable 214f5c8a6cbSFabrice Gasnier * - SRP Only capable 215f5c8a6cbSFabrice Gasnier * - No HNP/SRP capable (always available) 216f5c8a6cbSFabrice Gasnier * Defaults to best available option 217f5c8a6cbSFabrice Gasnier * - OTG revision number the device is compliant with, in binary-coded 218f5c8a6cbSFabrice Gasnier * decimal (i.e. 2.0 is 0200H). (see struct usb_otg_caps) 219e7839f99SJohn Youn * @host_dma: Specifies whether to use slave or DMA mode for accessing 220197ba5f4SPaul Zimmerman * the data FIFOs. The driver will automatically detect the 221197ba5f4SPaul Zimmerman * value for this parameter if none is specified. 222197ba5f4SPaul Zimmerman * 0 - Slave (always available) 223197ba5f4SPaul Zimmerman * 1 - DMA (default, if available) 224197ba5f4SPaul Zimmerman * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 225197ba5f4SPaul Zimmerman * address DMA mode or descriptor DMA mode for accessing 226197ba5f4SPaul Zimmerman * the data FIFOs. The driver will automatically detect the 227197ba5f4SPaul Zimmerman * value for this if none is specified. 228197ba5f4SPaul Zimmerman * 0 - Address DMA 229197ba5f4SPaul Zimmerman * 1 - Descriptor DMA (default, if available) 230fbb9e22bSMian Yousaf Kaukab * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use 231fbb9e22bSMian Yousaf Kaukab * address DMA mode or descriptor DMA mode for accessing 232fbb9e22bSMian Yousaf Kaukab * the data FIFOs in Full Speed mode only. The driver 233fbb9e22bSMian Yousaf Kaukab * will automatically detect the value for this if none is 234fbb9e22bSMian Yousaf Kaukab * specified. 235fbb9e22bSMian Yousaf Kaukab * 0 - Address DMA 236fbb9e22bSMian Yousaf Kaukab * 1 - Descriptor DMA in FS (default, if available) 237197ba5f4SPaul Zimmerman * @speed: Specifies the maximum speed of operation in host and 238197ba5f4SPaul Zimmerman * device mode. The actual speed depends on the speed of 239197ba5f4SPaul Zimmerman * the attached device and the value of phy_type. 240197ba5f4SPaul Zimmerman * 0 - High Speed 241197ba5f4SPaul Zimmerman * (default when phy_type is UTMI+ or ULPI) 242197ba5f4SPaul Zimmerman * 1 - Full Speed 243197ba5f4SPaul Zimmerman * (default when phy_type is Full Speed) 244197ba5f4SPaul Zimmerman * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 245197ba5f4SPaul Zimmerman * 1 - Allow dynamic FIFO sizing (default, if available) 246197ba5f4SPaul Zimmerman * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 247c1d286cfSJohn Youn * are enabled for non-periodic IN endpoints in device 248c1d286cfSJohn Youn * mode. 249197ba5f4SPaul Zimmerman * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 250197ba5f4SPaul Zimmerman * dynamic FIFO sizing is enabled 251197ba5f4SPaul Zimmerman * 16 to 32768 252197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 253197ba5f4SPaul Zimmerman * the default. 254197ba5f4SPaul Zimmerman * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 255197ba5f4SPaul Zimmerman * in host mode when dynamic FIFO sizing is enabled 256197ba5f4SPaul Zimmerman * 16 to 32768 257197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 258197ba5f4SPaul Zimmerman * the default. 259197ba5f4SPaul Zimmerman * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 260197ba5f4SPaul Zimmerman * host mode when dynamic FIFO sizing is enabled 261197ba5f4SPaul Zimmerman * 16 to 32768 262197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 263197ba5f4SPaul Zimmerman * the default. 264197ba5f4SPaul Zimmerman * @max_transfer_size: The maximum transfer size supported, in bytes 265197ba5f4SPaul Zimmerman * 2047 to 65,535 266197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 267197ba5f4SPaul Zimmerman * the default. 268197ba5f4SPaul Zimmerman * @max_packet_count: The maximum number of packets in a transfer 269197ba5f4SPaul Zimmerman * 15 to 511 270197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 271197ba5f4SPaul Zimmerman * the default. 272197ba5f4SPaul Zimmerman * @host_channels: The number of host channel registers to use 273197ba5f4SPaul Zimmerman * 1 to 16 274197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 275197ba5f4SPaul Zimmerman * the default. 276197ba5f4SPaul Zimmerman * @phy_type: Specifies the type of PHY interface to use. By default, 277197ba5f4SPaul Zimmerman * the driver will automatically detect the phy_type. 278197ba5f4SPaul Zimmerman * 0 - Full Speed Phy 279197ba5f4SPaul Zimmerman * 1 - UTMI+ Phy 280197ba5f4SPaul Zimmerman * 2 - ULPI Phy 281197ba5f4SPaul Zimmerman * Defaults to best available option (2, 1, then 0) 282197ba5f4SPaul Zimmerman * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 283197ba5f4SPaul Zimmerman * is applicable for a phy_type of UTMI+ or ULPI. (For a 284197ba5f4SPaul Zimmerman * ULPI phy_type, this parameter indicates the data width 285197ba5f4SPaul Zimmerman * between the MAC and the ULPI Wrapper.) Also, this 286197ba5f4SPaul Zimmerman * parameter is applicable only if the OTG_HSPHY_WIDTH cC 287197ba5f4SPaul Zimmerman * parameter was set to "8 and 16 bits", meaning that the 288197ba5f4SPaul Zimmerman * core has been configured to work at either data path 289197ba5f4SPaul Zimmerman * width. 290197ba5f4SPaul Zimmerman * 8 or 16 (default 16 if available) 291197ba5f4SPaul Zimmerman * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 292197ba5f4SPaul Zimmerman * data rate. This parameter is only applicable if phy_type 293197ba5f4SPaul Zimmerman * is ULPI. 294197ba5f4SPaul Zimmerman * 0 - single data rate ULPI interface with 8 bit wide 295197ba5f4SPaul Zimmerman * data bus (default) 296197ba5f4SPaul Zimmerman * 1 - double data rate ULPI interface with 4 bit wide 297197ba5f4SPaul Zimmerman * data bus 298197ba5f4SPaul Zimmerman * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 299197ba5f4SPaul Zimmerman * external supply to drive the VBus 300197ba5f4SPaul Zimmerman * 0 - Internal supply (default) 301197ba5f4SPaul Zimmerman * 1 - External supply 302197ba5f4SPaul Zimmerman * @i2c_enable: Specifies whether to use the I2Cinterface for a full 303197ba5f4SPaul Zimmerman * speed PHY. This parameter is only applicable if phy_type 304197ba5f4SPaul Zimmerman * is FS. 305197ba5f4SPaul Zimmerman * 0 - No (default) 306197ba5f4SPaul Zimmerman * 1 - Yes 3076fb914d7SGrigor Tovmasyan * @ipg_isoc_en: Indicates the IPG supports is enabled or disabled. 308b43ebc96SGrigor Tovmasyan * 0 - Disable (default) 309b43ebc96SGrigor Tovmasyan * 1 - Enable 3106fb914d7SGrigor Tovmasyan * @acg_enable: For enabling Active Clock Gating in the controller 3116fb914d7SGrigor Tovmasyan * 0 - No 3126fb914d7SGrigor Tovmasyan * 1 - Yes 313197ba5f4SPaul Zimmerman * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 314197ba5f4SPaul Zimmerman * 0 - No (default) 315197ba5f4SPaul Zimmerman * 1 - Yes 316197ba5f4SPaul Zimmerman * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 317197ba5f4SPaul Zimmerman * when attached to a Full Speed or Low Speed device in 318197ba5f4SPaul Zimmerman * host mode. 319197ba5f4SPaul Zimmerman * 0 - Don't support low power mode (default) 320197ba5f4SPaul Zimmerman * 1 - Support low power mode 321197ba5f4SPaul Zimmerman * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 322197ba5f4SPaul Zimmerman * when connected to a Low Speed device in host 323197ba5f4SPaul Zimmerman * mode. This parameter is applicable only if 324197ba5f4SPaul Zimmerman * host_support_fs_ls_low_power is enabled. 325197ba5f4SPaul Zimmerman * 0 - 48 MHz 326197ba5f4SPaul Zimmerman * (default when phy_type is UTMI+ or ULPI) 327197ba5f4SPaul Zimmerman * 1 - 6 MHz 328197ba5f4SPaul Zimmerman * (default when phy_type is Full Speed) 329b11633c4SDinh Nguyen * @oc_disable: Flag to disable overcurrent condition. 330b11633c4SDinh Nguyen * 0 - Allow overcurrent condition to get detected 331b11633c4SDinh Nguyen * 1 - Disable overcurrent condtion to get detected 332197ba5f4SPaul Zimmerman * @ts_dline: Enable Term Select Dline pulsing 333197ba5f4SPaul Zimmerman * 0 - No (default) 334197ba5f4SPaul Zimmerman * 1 - Yes 335197ba5f4SPaul Zimmerman * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 336197ba5f4SPaul Zimmerman * 0 - No (default for core < 2.92a) 337197ba5f4SPaul Zimmerman * 1 - Yes (default for core >= 2.92a) 338197ba5f4SPaul Zimmerman * @ahbcfg: This field allows the default value of the GAHBCFG 339197ba5f4SPaul Zimmerman * register to be overridden 340197ba5f4SPaul Zimmerman * -1 - GAHBCFG value will be set to 0x06 3411b52d2faSRazmik Karapetyan * (INCR, default) 342197ba5f4SPaul Zimmerman * all others - GAHBCFG value will be overridden with 343197ba5f4SPaul Zimmerman * this value 344197ba5f4SPaul Zimmerman * Not all bits can be controlled like this, the 345197ba5f4SPaul Zimmerman * bits defined by GAHBCFG_CTRL_MASK are controlled 346197ba5f4SPaul Zimmerman * by the driver and are ignored in this 347197ba5f4SPaul Zimmerman * configuration value. 348197ba5f4SPaul Zimmerman * @uframe_sched: True to enable the microframe scheduler 349a6d249d8SGregory Herrero * @external_id_pin_ctl: Specifies whether ID pin is handled externally. 350a6d249d8SGregory Herrero * Disable CONIDSTSCHNG controller interrupt in such 351a6d249d8SGregory Herrero * case. 352a6d249d8SGregory Herrero * 0 - No (default) 353a6d249d8SGregory Herrero * 1 - Yes 35441ba9b9bSVardan Mikayelyan * @power_down: Specifies whether the controller support power_down. 35541ba9b9bSVardan Mikayelyan * If power_down is enabled, the controller will enter 35641ba9b9bSVardan Mikayelyan * power_down in both peripheral and host mode when 357285046aaSGregory Herrero * needed. 358285046aaSGregory Herrero * 0 - No (default) 359631a2310SVardan Mikayelyan * 1 - Partial power down 360631a2310SVardan Mikayelyan * 2 - Hibernation 361c4a0f7a6SMarek Szyprowski * @no_clock_gating: Specifies whether to avoid clock gating feature. 362c4a0f7a6SMarek Szyprowski * 0 - No (use clock gating) 363c4a0f7a6SMarek Szyprowski * 1 - Yes (avoid it) 3646f80b6deSSevak Arakelyan * @lpm: Enable LPM support. 3656f80b6deSSevak Arakelyan * 0 - No 3666f80b6deSSevak Arakelyan * 1 - Yes 3676f80b6deSSevak Arakelyan * @lpm_clock_gating: Enable core PHY clock gating. 3686f80b6deSSevak Arakelyan * 0 - No 3696f80b6deSSevak Arakelyan * 1 - Yes 3706f80b6deSSevak Arakelyan * @besl: Enable LPM Errata support. 3716f80b6deSSevak Arakelyan * 0 - No 3726f80b6deSSevak Arakelyan * 1 - Yes 3736f80b6deSSevak Arakelyan * @hird_threshold_en: HIRD or HIRD Threshold enable. 3746f80b6deSSevak Arakelyan * 0 - No 3756f80b6deSSevak Arakelyan * 1 - Yes 3766f80b6deSSevak Arakelyan * @hird_threshold: Value of BESL or HIRD Threshold. 377f3a61e4eSGrigor Tovmasyan * @ref_clk_per: Indicates in terms of pico seconds the period 378f3a61e4eSGrigor Tovmasyan * of ref_clk. 379f3a61e4eSGrigor Tovmasyan * 62500 - 16MHz 380f3a61e4eSGrigor Tovmasyan * 58823 - 17MHz 381f3a61e4eSGrigor Tovmasyan * 52083 - 19.2MHz 382f3a61e4eSGrigor Tovmasyan * 50000 - 20MHz 383f3a61e4eSGrigor Tovmasyan * 41666 - 24MHz 384f3a61e4eSGrigor Tovmasyan * 33333 - 30MHz (default) 385f3a61e4eSGrigor Tovmasyan * 25000 - 40MHz 386f3a61e4eSGrigor Tovmasyan * @sof_cnt_wkup_alert: Indicates in term of number of SOF's after which 387f3a61e4eSGrigor Tovmasyan * the controller should generate an interrupt if the 388f3a61e4eSGrigor Tovmasyan * device had been in L1 state until that period. 389f3a61e4eSGrigor Tovmasyan * This is used by SW to initiate Remote WakeUp in the 390f3a61e4eSGrigor Tovmasyan * controller so as to sync to the uF number from the host. 391e35b1350SBruno Herrera * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO 392e35b1350SBruno Herrera * register. 393e35b1350SBruno Herrera * 0 - Deactivate the transceiver (default) 394e35b1350SBruno Herrera * 1 - Activate the transceiver 395a415083aSAmelie Delaunay * @activate_stm_id_vb_detection: Activate external ID pin and Vbus level 396a415083aSAmelie Delaunay * detection using GGPIO register. 397a415083aSAmelie Delaunay * 0 - Deactivate the external level detection (default) 398a415083aSAmelie Delaunay * 1 - Activate the external level detection 399d712b725S周琰杰 (Zhou Yanjie) * @activate_ingenic_overcurrent_detection: Activate Ingenic overcurrent 400d712b725S周琰杰 (Zhou Yanjie) * detection. 401d712b725S周琰杰 (Zhou Yanjie) * 0 - Deactivate the overcurrent detection 402d712b725S周琰杰 (Zhou Yanjie) * 1 - Activate the overcurrent detection (default) 4039962b62fSJohn Youn * @g_dma: Enables gadget dma usage (default: autodetect). 404dec4b556SVahram Aharonyan * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect). 40505ee799fSJohn Youn * @g_rx_fifo_size: The periodic rx fifo size for the device, in 40605ee799fSJohn Youn * DWORDS from 16-32768 (default: 2048 if 40705ee799fSJohn Youn * possible, otherwise autodetect). 40805ee799fSJohn Youn * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in 40905ee799fSJohn Youn * DWORDS from 16-32768 (default: 1024 if 41005ee799fSJohn Youn * possible, otherwise autodetect). 41105ee799fSJohn Youn * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo 41205ee799fSJohn Youn * mode. Each value corresponds to one EP 41305ee799fSJohn Youn * starting from EP1 (max 15 values). Sizes are 414f8590006STian Tao * in DWORDS with possible values from 41505ee799fSJohn Youn * 16-32768 (default: 256, 256, 256, 256, 768, 41605ee799fSJohn Youn * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0). 417ca8b0332SChen Yu * @change_speed_quirk: Change speed configuration to DWC2_SPEED_PARAM_FULL 418ca8b0332SChen Yu * while full&low speed device connect. And change speed 419ca8b0332SChen Yu * back to DWC2_SPEED_PARAM_HIGH while device is gone. 420ca8b0332SChen Yu * 0 - No (default) 421ca8b0332SChen Yu * 1 - Yes 422ca531bc2SGrigor Tovmasyan * @service_interval: Enable service interval based scheduling. 423ca531bc2SGrigor Tovmasyan * 0 - No 424ca531bc2SGrigor Tovmasyan * 1 - Yes 425197ba5f4SPaul Zimmerman * 426197ba5f4SPaul Zimmerman * The following parameters may be specified when starting the module. These 427197ba5f4SPaul Zimmerman * parameters define how the DWC_otg controller should be configured. A 428197ba5f4SPaul Zimmerman * value of -1 (or any other out of range value) for any parameter means 429197ba5f4SPaul Zimmerman * to read the value from hardware (if possible) or use the builtin 430197ba5f4SPaul Zimmerman * default described above. 431197ba5f4SPaul Zimmerman */ 432197ba5f4SPaul Zimmerman struct dwc2_core_params { 433f5c8a6cbSFabrice Gasnier struct usb_otg_caps otg_caps; 434d21bcc3fSJohn Youn u8 phy_type; 435c1d286cfSJohn Youn #define DWC2_PHY_TYPE_PARAM_FS 0 436c1d286cfSJohn Youn #define DWC2_PHY_TYPE_PARAM_UTMI 1 437c1d286cfSJohn Youn #define DWC2_PHY_TYPE_PARAM_ULPI 2 438c1d286cfSJohn Youn 43957b8e235SJohn Youn u8 speed; 44057b8e235SJohn Youn #define DWC2_SPEED_PARAM_HIGH 0 44157b8e235SJohn Youn #define DWC2_SPEED_PARAM_FULL 1 44257b8e235SJohn Youn #define DWC2_SPEED_PARAM_LOW 2 44357b8e235SJohn Youn 444d21bcc3fSJohn Youn u8 phy_utmi_width; 445d21bcc3fSJohn Youn bool phy_ulpi_ddr; 446d21bcc3fSJohn Youn bool phy_ulpi_ext_vbus; 44757b8e235SJohn Youn bool enable_dynamic_fifo; 44857b8e235SJohn Youn bool en_multiple_tx_fifo; 449d21bcc3fSJohn Youn bool i2c_enable; 45066e77a24SRazmik Karapetyan bool acg_enable; 451d21bcc3fSJohn Youn bool ulpi_fs_ls; 45257b8e235SJohn Youn bool ts_dline; 45357b8e235SJohn Youn bool reload_ctl; 45457b8e235SJohn Youn bool uframe_sched; 45557b8e235SJohn Youn bool external_id_pin_ctl; 456631a2310SVardan Mikayelyan 457631a2310SVardan Mikayelyan int power_down; 458631a2310SVardan Mikayelyan #define DWC2_POWER_DOWN_PARAM_NONE 0 459631a2310SVardan Mikayelyan #define DWC2_POWER_DOWN_PARAM_PARTIAL 1 460631a2310SVardan Mikayelyan #define DWC2_POWER_DOWN_PARAM_HIBERNATION 2 461c4a0f7a6SMarek Szyprowski bool no_clock_gating; 462631a2310SVardan Mikayelyan 4636f80b6deSSevak Arakelyan bool lpm; 4646f80b6deSSevak Arakelyan bool lpm_clock_gating; 4656f80b6deSSevak Arakelyan bool besl; 4666f80b6deSSevak Arakelyan bool hird_threshold_en; 467ca531bc2SGrigor Tovmasyan bool service_interval; 4686f80b6deSSevak Arakelyan u8 hird_threshold; 469e35b1350SBruno Herrera bool activate_stm_fs_transceiver; 470a415083aSAmelie Delaunay bool activate_stm_id_vb_detection; 471d712b725S周琰杰 (Zhou Yanjie) bool activate_ingenic_overcurrent_detection; 472b43ebc96SGrigor Tovmasyan bool ipg_isoc_en; 47357b8e235SJohn Youn u16 max_packet_count; 47457b8e235SJohn Youn u32 max_transfer_size; 47557b8e235SJohn Youn u32 ahbcfg; 47657b8e235SJohn Youn 477f3a61e4eSGrigor Tovmasyan /* GREFCLK parameters */ 478f3a61e4eSGrigor Tovmasyan u32 ref_clk_per; 479f3a61e4eSGrigor Tovmasyan u16 sof_cnt_wkup_alert; 480f3a61e4eSGrigor Tovmasyan 48157b8e235SJohn Youn /* Host parameters */ 48257b8e235SJohn Youn bool host_dma; 48357b8e235SJohn Youn bool dma_desc_enable; 48457b8e235SJohn Youn bool dma_desc_fs_enable; 485d21bcc3fSJohn Youn bool host_support_fs_ls_low_power; 486d21bcc3fSJohn Youn bool host_ls_low_power_phy_clk; 487b11633c4SDinh Nguyen bool oc_disable; 488c1d286cfSJohn Youn 48957b8e235SJohn Youn u8 host_channels; 49057b8e235SJohn Youn u16 host_rx_fifo_size; 49157b8e235SJohn Youn u16 host_nperio_tx_fifo_size; 49257b8e235SJohn Youn u16 host_perio_tx_fifo_size; 4936b66ce51SJohn Youn 4946b66ce51SJohn Youn /* Gadget parameters */ 49505ee799fSJohn Youn bool g_dma; 496dec4b556SVahram Aharonyan bool g_dma_desc; 49700c704ccSLeo Yan u32 g_rx_fifo_size; 49800c704ccSLeo Yan u32 g_np_tx_fifo_size; 49905ee799fSJohn Youn u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; 500ca8b0332SChen Yu 501ca8b0332SChen Yu bool change_speed_quirk; 502197ba5f4SPaul Zimmerman }; 503197ba5f4SPaul Zimmerman 504197ba5f4SPaul Zimmerman /** 505197ba5f4SPaul Zimmerman * struct dwc2_hw_params - Autodetected parameters. 506197ba5f4SPaul Zimmerman * 507197ba5f4SPaul Zimmerman * These parameters are the various parameters read from hardware 508197ba5f4SPaul Zimmerman * registers during initialization. They typically contain the best 509197ba5f4SPaul Zimmerman * supported or maximum value that can be configured in the 510197ba5f4SPaul Zimmerman * corresponding dwc2_core_params value. 511197ba5f4SPaul Zimmerman * 512197ba5f4SPaul Zimmerman * The values that are not in dwc2_core_params are documented below. 513197ba5f4SPaul Zimmerman * 5146fb914d7SGrigor Tovmasyan * @op_mode: Mode of Operation 515197ba5f4SPaul Zimmerman * 0 - HNP- and SRP-Capable OTG (Host & Device) 516197ba5f4SPaul Zimmerman * 1 - SRP-Capable OTG (Host & Device) 517197ba5f4SPaul Zimmerman * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 518197ba5f4SPaul Zimmerman * 3 - SRP-Capable Device 519197ba5f4SPaul Zimmerman * 4 - Non-OTG Device 520197ba5f4SPaul Zimmerman * 5 - SRP-Capable Host 521197ba5f4SPaul Zimmerman * 6 - Non-OTG Host 5226fb914d7SGrigor Tovmasyan * @arch: Architecture 523197ba5f4SPaul Zimmerman * 0 - Slave only 524197ba5f4SPaul Zimmerman * 1 - External DMA 525197ba5f4SPaul Zimmerman * 2 - Internal DMA 5266fb914d7SGrigor Tovmasyan * @ipg_isoc_en: This feature indicates that the controller supports 527b43ebc96SGrigor Tovmasyan * the worst-case scenario of Rx followed by Rx 528b43ebc96SGrigor Tovmasyan * Interpacket Gap (IPG) (32 bitTimes) as per the utmi 529b43ebc96SGrigor Tovmasyan * specification for any token following ISOC OUT token. 530b43ebc96SGrigor Tovmasyan * 0 - Don't support 531b43ebc96SGrigor Tovmasyan * 1 - Support 5326fb914d7SGrigor Tovmasyan * @power_optimized: Are power optimizations enabled? 5336fb914d7SGrigor Tovmasyan * @num_dev_ep: Number of device endpoints available 5346fb914d7SGrigor Tovmasyan * @num_dev_in_eps: Number of device IN endpoints available 5356fb914d7SGrigor Tovmasyan * @num_dev_perio_in_ep: Number of device periodic IN endpoints 536997f4f81SMickael Maison * available 5376fb914d7SGrigor Tovmasyan * @dev_token_q_depth: Device Mode IN Token Sequence Learning Queue 538197ba5f4SPaul Zimmerman * Depth 539197ba5f4SPaul Zimmerman * 0 to 30 5406fb914d7SGrigor Tovmasyan * @host_perio_tx_q_depth: 541197ba5f4SPaul Zimmerman * Host Mode Periodic Request Queue Depth 542197ba5f4SPaul Zimmerman * 2, 4 or 8 5436fb914d7SGrigor Tovmasyan * @nperio_tx_q_depth: 544197ba5f4SPaul Zimmerman * Non-Periodic Request Queue Depth 545197ba5f4SPaul Zimmerman * 2, 4 or 8 5466fb914d7SGrigor Tovmasyan * @hs_phy_type: High-speed PHY interface type 547197ba5f4SPaul Zimmerman * 0 - High-speed interface not supported 548197ba5f4SPaul Zimmerman * 1 - UTMI+ 549197ba5f4SPaul Zimmerman * 2 - ULPI 550197ba5f4SPaul Zimmerman * 3 - UTMI+ and ULPI 5516fb914d7SGrigor Tovmasyan * @fs_phy_type: Full-speed PHY interface type 552197ba5f4SPaul Zimmerman * 0 - Full speed interface not supported 553197ba5f4SPaul Zimmerman * 1 - Dedicated full speed interface 554197ba5f4SPaul Zimmerman * 2 - FS pins shared with UTMI+ pins 555197ba5f4SPaul Zimmerman * 3 - FS pins shared with ULPI pins 556197ba5f4SPaul Zimmerman * @total_fifo_size: Total internal RAM for FIFOs (bytes) 5576fb914d7SGrigor Tovmasyan * @hibernation: Is hibernation enabled? 5586fb914d7SGrigor Tovmasyan * @utmi_phy_data_width: UTMI+ PHY data width 559197ba5f4SPaul Zimmerman * 0 - 8 bits 560197ba5f4SPaul Zimmerman * 1 - 16 bits 561197ba5f4SPaul Zimmerman * 2 - 8 or 16 bits 562197ba5f4SPaul Zimmerman * @snpsid: Value from SNPSID register 56355e1040eSJohn Youn * @dev_ep_dirs: Direction of device endpoints (GHWCFG1) 5646fb914d7SGrigor Tovmasyan * @g_tx_fifo_size: Power-on values of TxFIFO sizes 5656fb914d7SGrigor Tovmasyan * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 5666fb914d7SGrigor Tovmasyan * address DMA mode or descriptor DMA mode for accessing 5676fb914d7SGrigor Tovmasyan * the data FIFOs. The driver will automatically detect the 5686fb914d7SGrigor Tovmasyan * value for this if none is specified. 5696fb914d7SGrigor Tovmasyan * 0 - Address DMA 5706fb914d7SGrigor Tovmasyan * 1 - Descriptor DMA (default, if available) 5716fb914d7SGrigor Tovmasyan * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 5726fb914d7SGrigor Tovmasyan * 1 - Allow dynamic FIFO sizing (default, if available) 5736fb914d7SGrigor Tovmasyan * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 5746fb914d7SGrigor Tovmasyan * are enabled for non-periodic IN endpoints in device 5756fb914d7SGrigor Tovmasyan * mode. 5766fb914d7SGrigor Tovmasyan * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 5776fb914d7SGrigor Tovmasyan * in host mode when dynamic FIFO sizing is enabled 5786fb914d7SGrigor Tovmasyan * 16 to 32768 5796fb914d7SGrigor Tovmasyan * Actual maximum value is autodetected and also 5806fb914d7SGrigor Tovmasyan * the default. 5816fb914d7SGrigor Tovmasyan * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 5826fb914d7SGrigor Tovmasyan * host mode when dynamic FIFO sizing is enabled 5836fb914d7SGrigor Tovmasyan * 16 to 32768 5846fb914d7SGrigor Tovmasyan * Actual maximum value is autodetected and also 5856fb914d7SGrigor Tovmasyan * the default. 5866fb914d7SGrigor Tovmasyan * @max_transfer_size: The maximum transfer size supported, in bytes 5876fb914d7SGrigor Tovmasyan * 2047 to 65,535 5886fb914d7SGrigor Tovmasyan * Actual maximum value is autodetected and also 5896fb914d7SGrigor Tovmasyan * the default. 5906fb914d7SGrigor Tovmasyan * @max_packet_count: The maximum number of packets in a transfer 5916fb914d7SGrigor Tovmasyan * 15 to 511 5926fb914d7SGrigor Tovmasyan * Actual maximum value is autodetected and also 5936fb914d7SGrigor Tovmasyan * the default. 5946fb914d7SGrigor Tovmasyan * @host_channels: The number of host channel registers to use 5956fb914d7SGrigor Tovmasyan * 1 to 16 5966fb914d7SGrigor Tovmasyan * Actual maximum value is autodetected and also 5976fb914d7SGrigor Tovmasyan * the default. 5986fb914d7SGrigor Tovmasyan * @dev_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 5996fb914d7SGrigor Tovmasyan * in device mode when dynamic FIFO sizing is enabled 6006fb914d7SGrigor Tovmasyan * 16 to 32768 6016fb914d7SGrigor Tovmasyan * Actual maximum value is autodetected and also 6026fb914d7SGrigor Tovmasyan * the default. 6036fb914d7SGrigor Tovmasyan * @i2c_enable: Specifies whether to use the I2Cinterface for a full 6046fb914d7SGrigor Tovmasyan * speed PHY. This parameter is only applicable if phy_type 6056fb914d7SGrigor Tovmasyan * is FS. 6066fb914d7SGrigor Tovmasyan * 0 - No (default) 6076fb914d7SGrigor Tovmasyan * 1 - Yes 6086fb914d7SGrigor Tovmasyan * @acg_enable: For enabling Active Clock Gating in the controller 6096fb914d7SGrigor Tovmasyan * 0 - Disable 6106fb914d7SGrigor Tovmasyan * 1 - Enable 6116fb914d7SGrigor Tovmasyan * @lpm_mode: For enabling Link Power Management in the controller 6126fb914d7SGrigor Tovmasyan * 0 - Disable 6136fb914d7SGrigor Tovmasyan * 1 - Enable 6146fb914d7SGrigor Tovmasyan * @rx_fifo_size: Number of 4-byte words in the Rx FIFO when dynamic 6156fb914d7SGrigor Tovmasyan * FIFO sizing is enabled 16 to 32768 6166fb914d7SGrigor Tovmasyan * Actual maximum value is autodetected and also 6176fb914d7SGrigor Tovmasyan * the default. 618ca531bc2SGrigor Tovmasyan * @service_interval_mode: For enabling service interval based scheduling in the 619ca531bc2SGrigor Tovmasyan * controller. 620ca531bc2SGrigor Tovmasyan * 0 - Disable 621ca531bc2SGrigor Tovmasyan * 1 - Enable 622197ba5f4SPaul Zimmerman */ 623197ba5f4SPaul Zimmerman struct dwc2_hw_params { 624197ba5f4SPaul Zimmerman unsigned op_mode:3; 625197ba5f4SPaul Zimmerman unsigned arch:2; 626197ba5f4SPaul Zimmerman unsigned dma_desc_enable:1; 627197ba5f4SPaul Zimmerman unsigned enable_dynamic_fifo:1; 628197ba5f4SPaul Zimmerman unsigned en_multiple_tx_fifo:1; 629d1531319SJohn Youn unsigned rx_fifo_size:16; 630197ba5f4SPaul Zimmerman unsigned host_nperio_tx_fifo_size:16; 63155e1040eSJohn Youn unsigned dev_nperio_tx_fifo_size:16; 632197ba5f4SPaul Zimmerman unsigned host_perio_tx_fifo_size:16; 633197ba5f4SPaul Zimmerman unsigned nperio_tx_q_depth:3; 634197ba5f4SPaul Zimmerman unsigned host_perio_tx_q_depth:3; 635197ba5f4SPaul Zimmerman unsigned dev_token_q_depth:5; 636197ba5f4SPaul Zimmerman unsigned max_transfer_size:26; 637197ba5f4SPaul Zimmerman unsigned max_packet_count:11; 638197ba5f4SPaul Zimmerman unsigned host_channels:5; 639197ba5f4SPaul Zimmerman unsigned hs_phy_type:2; 640197ba5f4SPaul Zimmerman unsigned fs_phy_type:2; 641197ba5f4SPaul Zimmerman unsigned i2c_enable:1; 64266e77a24SRazmik Karapetyan unsigned acg_enable:1; 643197ba5f4SPaul Zimmerman unsigned num_dev_ep:4; 6449273083aSMinas Harutyunyan unsigned num_dev_in_eps : 4; 645197ba5f4SPaul Zimmerman unsigned num_dev_perio_in_ep:4; 646197ba5f4SPaul Zimmerman unsigned total_fifo_size:16; 647197ba5f4SPaul Zimmerman unsigned power_optimized:1; 648631a2310SVardan Mikayelyan unsigned hibernation:1; 649197ba5f4SPaul Zimmerman unsigned utmi_phy_data_width:2; 6506f80b6deSSevak Arakelyan unsigned lpm_mode:1; 651b43ebc96SGrigor Tovmasyan unsigned ipg_isoc_en:1; 652ca531bc2SGrigor Tovmasyan unsigned service_interval_mode:1; 653197ba5f4SPaul Zimmerman u32 snpsid; 65455e1040eSJohn Youn u32 dev_ep_dirs; 6559273083aSMinas Harutyunyan u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; 656197ba5f4SPaul Zimmerman }; 657197ba5f4SPaul Zimmerman 6583f95001dSMian Yousaf Kaukab /* Size of control and EP0 buffers */ 6593f95001dSMian Yousaf Kaukab #define DWC2_CTRL_BUFF_SIZE 8 6603f95001dSMian Yousaf Kaukab 661197ba5f4SPaul Zimmerman /** 66238beaec6SJohn Youn * struct dwc2_gregs_backup - Holds global registers state before 66338beaec6SJohn Youn * entering partial power down 664d17ee77bSGregory Herrero * @gotgctl: Backup of GOTGCTL register 665d17ee77bSGregory Herrero * @gintmsk: Backup of GINTMSK register 666d17ee77bSGregory Herrero * @gahbcfg: Backup of GAHBCFG register 667d17ee77bSGregory Herrero * @gusbcfg: Backup of GUSBCFG register 668d17ee77bSGregory Herrero * @grxfsiz: Backup of GRXFSIZ register 669d17ee77bSGregory Herrero * @gnptxfsiz: Backup of GNPTXFSIZ register 670d17ee77bSGregory Herrero * @gi2cctl: Backup of GI2CCTL register 67166a36096SVardan Mikayelyan * @glpmcfg: Backup of GLPMCFG register 672d17ee77bSGregory Herrero * @gdfifocfg: Backup of GDFIFOCFG register 6736fb914d7SGrigor Tovmasyan * @pcgcctl: Backup of PCGCCTL register 6746fb914d7SGrigor Tovmasyan * @pcgcctl1: Backup of PCGCCTL1 register 6756fb914d7SGrigor Tovmasyan * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 676d17ee77bSGregory Herrero * @gpwrdn: Backup of GPWRDN register 6776fb914d7SGrigor Tovmasyan * @valid: True if registers values backuped. 678d17ee77bSGregory Herrero */ 679d17ee77bSGregory Herrero struct dwc2_gregs_backup { 680d17ee77bSGregory Herrero u32 gotgctl; 681d17ee77bSGregory Herrero u32 gintmsk; 682d17ee77bSGregory Herrero u32 gahbcfg; 683d17ee77bSGregory Herrero u32 gusbcfg; 684d17ee77bSGregory Herrero u32 grxfsiz; 685d17ee77bSGregory Herrero u32 gnptxfsiz; 686d17ee77bSGregory Herrero u32 gi2cctl; 68766a36096SVardan Mikayelyan u32 glpmcfg; 688d17ee77bSGregory Herrero u32 pcgcctl; 689600a490eSRazmik Karapetyan u32 pcgcctl1; 690d17ee77bSGregory Herrero u32 gdfifocfg; 691d17ee77bSGregory Herrero u32 gpwrdn; 692cc1e204cSMian Yousaf Kaukab bool valid; 693d17ee77bSGregory Herrero }; 694d17ee77bSGregory Herrero 695d17ee77bSGregory Herrero /** 69638beaec6SJohn Youn * struct dwc2_dregs_backup - Holds device registers state before 69738beaec6SJohn Youn * entering partial power down 698d17ee77bSGregory Herrero * @dcfg: Backup of DCFG register 699d17ee77bSGregory Herrero * @dctl: Backup of DCTL register 700d17ee77bSGregory Herrero * @daintmsk: Backup of DAINTMSK register 701d17ee77bSGregory Herrero * @diepmsk: Backup of DIEPMSK register 702d17ee77bSGregory Herrero * @doepmsk: Backup of DOEPMSK register 703d17ee77bSGregory Herrero * @diepctl: Backup of DIEPCTL register 704d17ee77bSGregory Herrero * @dieptsiz: Backup of DIEPTSIZ register 705d17ee77bSGregory Herrero * @diepdma: Backup of DIEPDMA register 706d17ee77bSGregory Herrero * @doepctl: Backup of DOEPCTL register 707d17ee77bSGregory Herrero * @doeptsiz: Backup of DOEPTSIZ register 708d17ee77bSGregory Herrero * @doepdma: Backup of DOEPDMA register 709af7c2bd3SVardan Mikayelyan * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 7106fb914d7SGrigor Tovmasyan * @valid: True if registers values backuped. 711d17ee77bSGregory Herrero */ 712d17ee77bSGregory Herrero struct dwc2_dregs_backup { 713d17ee77bSGregory Herrero u32 dcfg; 714d17ee77bSGregory Herrero u32 dctl; 715d17ee77bSGregory Herrero u32 daintmsk; 716d17ee77bSGregory Herrero u32 diepmsk; 717d17ee77bSGregory Herrero u32 doepmsk; 718d17ee77bSGregory Herrero u32 diepctl[MAX_EPS_CHANNELS]; 719d17ee77bSGregory Herrero u32 dieptsiz[MAX_EPS_CHANNELS]; 720d17ee77bSGregory Herrero u32 diepdma[MAX_EPS_CHANNELS]; 721d17ee77bSGregory Herrero u32 doepctl[MAX_EPS_CHANNELS]; 722d17ee77bSGregory Herrero u32 doeptsiz[MAX_EPS_CHANNELS]; 723d17ee77bSGregory Herrero u32 doepdma[MAX_EPS_CHANNELS]; 724af7c2bd3SVardan Mikayelyan u32 dtxfsiz[MAX_EPS_CHANNELS]; 725cc1e204cSMian Yousaf Kaukab bool valid; 726d17ee77bSGregory Herrero }; 727d17ee77bSGregory Herrero 728d17ee77bSGregory Herrero /** 72938beaec6SJohn Youn * struct dwc2_hregs_backup - Holds host registers state before 73038beaec6SJohn Youn * entering partial power down 731d17ee77bSGregory Herrero * @hcfg: Backup of HCFG register 732d17ee77bSGregory Herrero * @haintmsk: Backup of HAINTMSK register 733d17ee77bSGregory Herrero * @hcintmsk: Backup of HCINTMSK register 7346fb914d7SGrigor Tovmasyan * @hprt0: Backup of HPTR0 register 735d17ee77bSGregory Herrero * @hfir: Backup of HFIR register 73666a36096SVardan Mikayelyan * @hptxfsiz: Backup of HPTXFSIZ register 7376fb914d7SGrigor Tovmasyan * @valid: True if registers values backuped. 738d17ee77bSGregory Herrero */ 739d17ee77bSGregory Herrero struct dwc2_hregs_backup { 740d17ee77bSGregory Herrero u32 hcfg; 741d17ee77bSGregory Herrero u32 haintmsk; 742d17ee77bSGregory Herrero u32 hcintmsk[MAX_EPS_CHANNELS]; 743d17ee77bSGregory Herrero u32 hprt0; 744d17ee77bSGregory Herrero u32 hfir; 74566a36096SVardan Mikayelyan u32 hptxfsiz; 746cc1e204cSMian Yousaf Kaukab bool valid; 747d17ee77bSGregory Herrero }; 748d17ee77bSGregory Herrero 7499f9f09b0SDouglas Anderson /* 7509f9f09b0SDouglas Anderson * Constants related to high speed periodic scheduling 7519f9f09b0SDouglas Anderson * 7529f9f09b0SDouglas Anderson * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a 7539f9f09b0SDouglas Anderson * reservation point of view it's assumed that the schedule goes right back to 7549f9f09b0SDouglas Anderson * the beginning after the end of the schedule. 7559f9f09b0SDouglas Anderson * 7569f9f09b0SDouglas Anderson * What does that mean for scheduling things with a long interval? It means 7579f9f09b0SDouglas Anderson * we'll reserve time for them in every possible microframe that they could 7589f9f09b0SDouglas Anderson * ever be scheduled in. ...but we'll still only actually schedule them as 7599f9f09b0SDouglas Anderson * often as they were requested. 7609f9f09b0SDouglas Anderson * 7619f9f09b0SDouglas Anderson * We keep our schedule in a "bitmap" structure. This simplifies having 7629f9f09b0SDouglas Anderson * to keep track of and merge intervals: we just let the bitmap code do most 7639f9f09b0SDouglas Anderson * of the heavy lifting. In a way scheduling is much like memory allocation. 7649f9f09b0SDouglas Anderson * 7659f9f09b0SDouglas Anderson * We schedule 100us per uframe or 80% of 125us (the maximum amount you're 7669f9f09b0SDouglas Anderson * supposed to schedule for periodic transfers). That's according to spec. 7679f9f09b0SDouglas Anderson * 7689f9f09b0SDouglas Anderson * Note that though we only schedule 80% of each microframe, the bitmap that we 7699f9f09b0SDouglas Anderson * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of 7709f9f09b0SDouglas Anderson * space for each uFrame). 7719f9f09b0SDouglas Anderson * 7729f9f09b0SDouglas Anderson * Requirements: 7739f9f09b0SDouglas Anderson * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1) 7749f9f09b0SDouglas Anderson * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably 7759f9f09b0SDouglas Anderson * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might 7769f9f09b0SDouglas Anderson * be bugs). The 8 comes from the USB spec: number of microframes per frame. 7779f9f09b0SDouglas Anderson */ 7789f9f09b0SDouglas Anderson #define DWC2_US_PER_UFRAME 125 7799f9f09b0SDouglas Anderson #define DWC2_HS_PERIODIC_US_PER_UFRAME 100 7809f9f09b0SDouglas Anderson 7819f9f09b0SDouglas Anderson #define DWC2_HS_SCHEDULE_UFRAMES 8 7829f9f09b0SDouglas Anderson #define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \ 7839f9f09b0SDouglas Anderson DWC2_HS_PERIODIC_US_PER_UFRAME) 7849f9f09b0SDouglas Anderson 7859f9f09b0SDouglas Anderson /* 7869f9f09b0SDouglas Anderson * Constants related to low speed scheduling 7879f9f09b0SDouglas Anderson * 7889f9f09b0SDouglas Anderson * For high speed we schedule every 1us. For low speed that's a bit overkill, 7899f9f09b0SDouglas Anderson * so we make up a unit called a "slice" that's worth 25us. There are 40 7909f9f09b0SDouglas Anderson * slices in a full frame and we can schedule 36 of those (90%) for periodic 7919f9f09b0SDouglas Anderson * transfers. 7929f9f09b0SDouglas Anderson * 7939f9f09b0SDouglas Anderson * Our low speed schedule can be as short as 1 frame or could be longer. When 7949f9f09b0SDouglas Anderson * we only schedule 1 frame it means that we'll need to reserve a time every 7959f9f09b0SDouglas Anderson * frame even for things that only transfer very rarely, so something that runs 7969f9f09b0SDouglas Anderson * every 2048 frames will get time reserved in every frame. Our low speed 7979f9f09b0SDouglas Anderson * schedule can be longer and we'll be able to handle more overlap, but that 7989f9f09b0SDouglas Anderson * will come at increased memory cost and increased time to schedule. 7999f9f09b0SDouglas Anderson * 8009f9f09b0SDouglas Anderson * Note: one other advantage of a short low speed schedule is that if we mess 8019f9f09b0SDouglas Anderson * up and miss scheduling we can jump in and use any of the slots that we 8029f9f09b0SDouglas Anderson * happened to reserve. 8039f9f09b0SDouglas Anderson * 8049f9f09b0SDouglas Anderson * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for 8059f9f09b0SDouglas Anderson * the schedule. There will be one schedule per TT. 8069f9f09b0SDouglas Anderson * 8079f9f09b0SDouglas Anderson * Requirements: 8089f9f09b0SDouglas Anderson * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME. 8099f9f09b0SDouglas Anderson */ 8109f9f09b0SDouglas Anderson #define DWC2_US_PER_SLICE 25 8119f9f09b0SDouglas Anderson #define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE) 8129f9f09b0SDouglas Anderson 8139f9f09b0SDouglas Anderson #define DWC2_ROUND_US_TO_SLICE(us) \ 8149f9f09b0SDouglas Anderson (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \ 8159f9f09b0SDouglas Anderson DWC2_US_PER_SLICE) 8169f9f09b0SDouglas Anderson 8179f9f09b0SDouglas Anderson #define DWC2_LS_PERIODIC_US_PER_FRAME \ 8189f9f09b0SDouglas Anderson 900 8199f9f09b0SDouglas Anderson #define DWC2_LS_PERIODIC_SLICES_PER_FRAME \ 8209f9f09b0SDouglas Anderson (DWC2_LS_PERIODIC_US_PER_FRAME / \ 8219f9f09b0SDouglas Anderson DWC2_US_PER_SLICE) 8229f9f09b0SDouglas Anderson 8239f9f09b0SDouglas Anderson #define DWC2_LS_SCHEDULE_FRAMES 1 8249f9f09b0SDouglas Anderson #define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \ 8259f9f09b0SDouglas Anderson DWC2_LS_PERIODIC_SLICES_PER_FRAME) 8269f9f09b0SDouglas Anderson 827d17ee77bSGregory Herrero /** 828197ba5f4SPaul Zimmerman * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 829197ba5f4SPaul Zimmerman * and periodic schedules 830197ba5f4SPaul Zimmerman * 831941fcce4SDinh Nguyen * These are common for both host and peripheral modes: 832941fcce4SDinh Nguyen * 833197ba5f4SPaul Zimmerman * @dev: The struct device pointer 834197ba5f4SPaul Zimmerman * @regs: Pointer to controller regs 835197ba5f4SPaul Zimmerman * @hw_params: Parameters that were autodetected from the 836197ba5f4SPaul Zimmerman * hardware registers 8376fb914d7SGrigor Tovmasyan * @params: Parameters that define how the core should be configured 838197ba5f4SPaul Zimmerman * @op_state: The operational State, during transitions (a_host=> 839197ba5f4SPaul Zimmerman * a_peripheral and b_device=>b_host) this may not match 840197ba5f4SPaul Zimmerman * the core, but allows the software to determine 841197ba5f4SPaul Zimmerman * transitions 842c0155b9dSKever Yang * @dr_mode: Requested mode of operation, one of following: 843c0155b9dSKever Yang * - USB_DR_MODE_PERIPHERAL 844c0155b9dSKever Yang * - USB_DR_MODE_HOST 845c0155b9dSKever Yang * - USB_DR_MODE_OTG 84617f93402SAmelie Delaunay * @role_sw: usb_role_switch handle 847e14acb87SFabrice Gasnier * @role_sw_default_mode: default operation mode of controller while usb role 848e14acb87SFabrice Gasnier * is USB_ROLE_NONE 8496fb914d7SGrigor Tovmasyan * @hcd_enabled: Host mode sub-driver initialization indicator. 8506fb914d7SGrigor Tovmasyan * @gadget_enabled: Peripheral mode sub-driver initialization indicator. 8516fb914d7SGrigor Tovmasyan * @ll_hw_enabled: Status of low-level hardware resources. 85220fe4409SVardan Mikayelyan * @hibernated: True if core is hibernated 853be2b960eSArtur Petrosyan * @in_ppd: True if core is partial power down mode. 854012466fcSArtur Petrosyan * @bus_suspended: True if bus is suspended 855c40cf770SDouglas Anderson * @reset_phy_on_wake: Quirk saying that we should assert PHY reset on a 856c40cf770SDouglas Anderson * remote wakeup. 857c846b03fSDouglas Anderson * @phy_off_for_suspend: Status of whether we turned the PHY off at suspend. 858c846b03fSDouglas Anderson * @need_phy_for_wake: Quirk saying that we should keep the PHY on at 859c846b03fSDouglas Anderson * suspend if we need USB to wake us up. 860c7c24e7aSArtur Petrosyan * @frame_number: Frame number read from the core. For both device 861c7c24e7aSArtur Petrosyan * and host modes. The value ranges are from 0 862c7c24e7aSArtur Petrosyan * to HFNUM_MAX_FRNUM. 86309a75e85SMarek Szyprowski * @phy: The otg phy transceiver structure for phy control. 86438beaec6SJohn Youn * @uphy: The otg phy transceiver structure for old USB phy 86538beaec6SJohn Youn * control. 86638beaec6SJohn Youn * @plat: The platform specific configuration data. This can be 86738beaec6SJohn Youn * removed once all SoCs support usb transceiver. 86809a75e85SMarek Szyprowski * @supplies: Definition of USB power supplies 869531ef5ebSAmelie Delaunay * @vbus_supply: Regulator supplying vbus. 870a415083aSAmelie Delaunay * @usb33d: Optional 3.3v regulator used on some stm32 devices to 871a415083aSAmelie Delaunay * supply ID and VBUS detection hardware. 872941fcce4SDinh Nguyen * @lock: Spinlock that protects all the driver data structures 873941fcce4SDinh Nguyen * @priv: Stores a pointer to the struct usb_hcd 874197ba5f4SPaul Zimmerman * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 875197ba5f4SPaul Zimmerman * transfer are in process of being queued 876197ba5f4SPaul Zimmerman * @srp_success: Stores status of SRP request in the case of a FS PHY 877197ba5f4SPaul Zimmerman * with an I2C interface 878197ba5f4SPaul Zimmerman * @wq_otg: Workqueue object used for handling of some interrupts 879197ba5f4SPaul Zimmerman * @wf_otg: Work object for handling Connector ID Status Change 880197ba5f4SPaul Zimmerman * interrupt 881197ba5f4SPaul Zimmerman * @wkp_timer: Timer object for handling Wakeup Detected interrupt 882197ba5f4SPaul Zimmerman * @lx_state: Lx state of connected device 8836fb914d7SGrigor Tovmasyan * @gr_backup: Backup of global registers during suspend 8846fb914d7SGrigor Tovmasyan * @dr_backup: Backup of device registers during suspend 8856fb914d7SGrigor Tovmasyan * @hr_backup: Backup of host registers during suspend 886fe369e18SGevorg Sahakyan * @needs_byte_swap: Specifies whether the opposite endianness. 887941fcce4SDinh Nguyen * 888941fcce4SDinh Nguyen * These are for host mode: 889941fcce4SDinh Nguyen * 890197ba5f4SPaul Zimmerman * @flags: Flags for handling root port state changes 8916fb914d7SGrigor Tovmasyan * @flags.d32: Contain all root port flags 8926fb914d7SGrigor Tovmasyan * @flags.b: Separate root port flags from each other 8936fb914d7SGrigor Tovmasyan * @flags.b.port_connect_status_change: True if root port connect status 8946fb914d7SGrigor Tovmasyan * changed 8956fb914d7SGrigor Tovmasyan * @flags.b.port_connect_status: True if device connected to root port 8966fb914d7SGrigor Tovmasyan * @flags.b.port_reset_change: True if root port reset status changed 8976fb914d7SGrigor Tovmasyan * @flags.b.port_enable_change: True if root port enable status changed 8986fb914d7SGrigor Tovmasyan * @flags.b.port_suspend_change: True if root port suspend status changed 8996fb914d7SGrigor Tovmasyan * @flags.b.port_over_current_change: True if root port over current state 9006fb914d7SGrigor Tovmasyan * changed. 9016fb914d7SGrigor Tovmasyan * @flags.b.port_l1_change: True if root port l1 status changed 9026fb914d7SGrigor Tovmasyan * @flags.b.reserved: Reserved bits of root port register 903197ba5f4SPaul Zimmerman * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 904197ba5f4SPaul Zimmerman * Transfers associated with these QHs are not currently 905197ba5f4SPaul Zimmerman * assigned to a host channel. 906197ba5f4SPaul Zimmerman * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 907197ba5f4SPaul Zimmerman * Transfers associated with these QHs are currently 908197ba5f4SPaul Zimmerman * assigned to a host channel. 909197ba5f4SPaul Zimmerman * @non_periodic_qh_ptr: Pointer to next QH to process in the active 910197ba5f4SPaul Zimmerman * non-periodic schedule 9116fb914d7SGrigor Tovmasyan * @non_periodic_sched_waiting: Waiting QHs in the non-periodic schedule. 9126fb914d7SGrigor Tovmasyan * Transfers associated with these QHs are not currently 9136fb914d7SGrigor Tovmasyan * assigned to a host channel. 914197ba5f4SPaul Zimmerman * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 915197ba5f4SPaul Zimmerman * list of QHs for periodic transfers that are _not_ 916197ba5f4SPaul Zimmerman * scheduled for the next frame. Each QH in the list has an 917197ba5f4SPaul Zimmerman * interval counter that determines when it needs to be 918197ba5f4SPaul Zimmerman * scheduled for execution. This scheduling mechanism 919197ba5f4SPaul Zimmerman * allows only a simple calculation for periodic bandwidth 920197ba5f4SPaul Zimmerman * used (i.e. must assume that all periodic transfers may 921197ba5f4SPaul Zimmerman * need to execute in the same frame). However, it greatly 922197ba5f4SPaul Zimmerman * simplifies scheduling and should be sufficient for the 923197ba5f4SPaul Zimmerman * vast majority of OTG hosts, which need to connect to a 924197ba5f4SPaul Zimmerman * small number of peripherals at one time. Items move from 925197ba5f4SPaul Zimmerman * this list to periodic_sched_ready when the QH interval 926197ba5f4SPaul Zimmerman * counter is 0 at SOF. 927197ba5f4SPaul Zimmerman * @periodic_sched_ready: List of periodic QHs that are ready for execution in 928197ba5f4SPaul Zimmerman * the next frame, but have not yet been assigned to host 929197ba5f4SPaul Zimmerman * channels. Items move from this list to 930197ba5f4SPaul Zimmerman * periodic_sched_assigned as host channels become 931197ba5f4SPaul Zimmerman * available during the current frame. 932197ba5f4SPaul Zimmerman * @periodic_sched_assigned: List of periodic QHs to be executed in the next 933197ba5f4SPaul Zimmerman * frame that are assigned to host channels. Items move 934197ba5f4SPaul Zimmerman * from this list to periodic_sched_queued as the 935197ba5f4SPaul Zimmerman * transactions for the QH are queued to the DWC_otg 936197ba5f4SPaul Zimmerman * controller. 937197ba5f4SPaul Zimmerman * @periodic_sched_queued: List of periodic QHs that have been queued for 938197ba5f4SPaul Zimmerman * execution. Items move from this list to either 939197ba5f4SPaul Zimmerman * periodic_sched_inactive or periodic_sched_ready when the 940197ba5f4SPaul Zimmerman * channel associated with the transfer is released. If the 941197ba5f4SPaul Zimmerman * interval for the QH is 1, the item moves to 942197ba5f4SPaul Zimmerman * periodic_sched_ready because it must be rescheduled for 943197ba5f4SPaul Zimmerman * the next frame. Otherwise, the item moves to 944197ba5f4SPaul Zimmerman * periodic_sched_inactive. 945c9c8ac01SDouglas Anderson * @split_order: List keeping track of channels doing splits, in order. 946197ba5f4SPaul Zimmerman * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 947197ba5f4SPaul Zimmerman * This value is in microseconds per (micro)frame. The 948197ba5f4SPaul Zimmerman * assumption is that all periodic transfers may occur in 949197ba5f4SPaul Zimmerman * the same (micro)frame. 9509f9f09b0SDouglas Anderson * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the 9519f9f09b0SDouglas Anderson * host is in high speed mode; low speed schedules are 9529f9f09b0SDouglas Anderson * stored elsewhere since we need one per TT. 953197ba5f4SPaul Zimmerman * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 954197ba5f4SPaul Zimmerman * SOF enable/disable. 955197ba5f4SPaul Zimmerman * @free_hc_list: Free host channels in the controller. This is a list of 956197ba5f4SPaul Zimmerman * struct dwc2_host_chan items. 957197ba5f4SPaul Zimmerman * @periodic_channels: Number of host channels assigned to periodic transfers. 958197ba5f4SPaul Zimmerman * Currently assuming that there is a dedicated host 959197ba5f4SPaul Zimmerman * channel for each periodic transaction and at least one 960197ba5f4SPaul Zimmerman * host channel is available for non-periodic transactions. 961197ba5f4SPaul Zimmerman * @non_periodic_channels: Number of host channels assigned to non-periodic 962197ba5f4SPaul Zimmerman * transfers 9636fb914d7SGrigor Tovmasyan * @available_host_channels: Number of host channels available for the 9646fb914d7SGrigor Tovmasyan * microframe scheduler to use 965197ba5f4SPaul Zimmerman * @hc_ptr_array: Array of pointers to the host channel descriptors. 966197ba5f4SPaul Zimmerman * Allows accessing a host channel descriptor given the 967197ba5f4SPaul Zimmerman * host channel number. This is useful in interrupt 968197ba5f4SPaul Zimmerman * handlers. 969197ba5f4SPaul Zimmerman * @status_buf: Buffer used for data received during the status phase of 970197ba5f4SPaul Zimmerman * a control transfer. 971197ba5f4SPaul Zimmerman * @status_buf_dma: DMA address for status_buf 972197ba5f4SPaul Zimmerman * @start_work: Delayed work for handling host A-cable connection 973197ba5f4SPaul Zimmerman * @reset_work: Delayed work for handling a port reset 974c40cf770SDouglas Anderson * @phy_reset_work: Work structure for doing a PHY reset 975197ba5f4SPaul Zimmerman * @otg_port: OTG port number 976197ba5f4SPaul Zimmerman * @frame_list: Frame list 977197ba5f4SPaul Zimmerman * @frame_list_dma: Frame list DMA address 97895105a99SGregory Herrero * @frame_list_sz: Frame list size 9793b5fcc9aSGregory Herrero * @desc_gen_cache: Kmem cache for generic descriptors 9803b5fcc9aSGregory Herrero * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors 981af424a41SWilliam Wu * @unaligned_cache: Kmem cache for DMA mode to handle non-aligned buf 982941fcce4SDinh Nguyen * 983941fcce4SDinh Nguyen * These are for peripheral mode: 984941fcce4SDinh Nguyen * 985941fcce4SDinh Nguyen * @driver: USB gadget driver 986941fcce4SDinh Nguyen * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 987941fcce4SDinh Nguyen * @num_of_eps: Number of available EPs (excluding EP0) 988941fcce4SDinh Nguyen * @debug_root: Root directrory for debugfs. 989941fcce4SDinh Nguyen * @ep0_reply: Request used for ep0 reply. 990941fcce4SDinh Nguyen * @ep0_buff: Buffer for EP0 reply data, if needed. 991941fcce4SDinh Nguyen * @ctrl_buff: Buffer for EP0 control requests. 992941fcce4SDinh Nguyen * @ctrl_req: Request for EP0 control packets. 993fe0b94abSMian Yousaf Kaukab * @ep0_state: EP0 control transfers state 994b4c53b4aSMinas Harutyunyan * @delayed_status: true when gadget driver asks for delayed status 9959e14d0a5SGregory Herrero * @test_mode: USB test mode requested by the host 996fa389a6dSVardan Mikayelyan * @remote_wakeup_allowed: True if device is allowed to wake-up host by 997fa389a6dSVardan Mikayelyan * remote-wakeup signalling 9980f6b80c0SVahram Aharonyan * @setup_desc_dma: EP0 setup stage desc chain DMA address 9990f6b80c0SVahram Aharonyan * @setup_desc: EP0 setup stage desc chain pointer 10000f6b80c0SVahram Aharonyan * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address 10010f6b80c0SVahram Aharonyan * @ctrl_in_desc: EP0 IN data phase desc chain pointer 10020f6b80c0SVahram Aharonyan * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address 10030f6b80c0SVahram Aharonyan * @ctrl_out_desc: EP0 OUT data phase desc chain pointer 10046fb914d7SGrigor Tovmasyan * @irq: Interrupt request line number 10056fb914d7SGrigor Tovmasyan * @clk: Pointer to otg clock 100602329adeSFabrice Gasnier * @utmi_clk: Pointer to utmi_clk clock 10076fb914d7SGrigor Tovmasyan * @reset: Pointer to dwc2 reset controller 10086fb914d7SGrigor Tovmasyan * @reset_ecc: Pointer to dwc2 optional reset controller in Stratix10. 10096fb914d7SGrigor Tovmasyan * @regset: A pointer to a struct debugfs_regset32, which contains 10106fb914d7SGrigor Tovmasyan * a pointer to an array of register definitions, the 10116fb914d7SGrigor Tovmasyan * array size and the base address where the register bank 10126fb914d7SGrigor Tovmasyan * is to be found. 10136fb914d7SGrigor Tovmasyan * @last_frame_num: Number of last frame. Range from 0 to 32768 10146fb914d7SGrigor Tovmasyan * @frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is 10156fb914d7SGrigor Tovmasyan * defined, for missed SOFs tracking. Array holds that 10166fb914d7SGrigor Tovmasyan * frame numbers, which not equal to last_frame_num +1 10176fb914d7SGrigor Tovmasyan * @last_frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is 10186fb914d7SGrigor Tovmasyan * defined, for missed SOFs tracking. 10196fb914d7SGrigor Tovmasyan * If current_frame_number != last_frame_num+1 10206fb914d7SGrigor Tovmasyan * then last_frame_num added to this array 10216fb914d7SGrigor Tovmasyan * @frame_num_idx: Actual size of frame_num_array and last_frame_num_array 10226fb914d7SGrigor Tovmasyan * @dumped_frame_num_array: 1 - if missed SOFs frame numbers dumbed 10236fb914d7SGrigor Tovmasyan * 0 - if missed SOFs frame numbers not dumbed 10246fb914d7SGrigor Tovmasyan * @fifo_mem: Total internal RAM for FIFOs (bytes) 10256fb914d7SGrigor Tovmasyan * @fifo_map: Each bit intend for concrete fifo. If that bit is set, 10266fb914d7SGrigor Tovmasyan * then that fifo is used 1027b9b70170SGreg Kroah-Hartman * @gadget: Represents a usb gadget device 10286fb914d7SGrigor Tovmasyan * @connected: Used in slave mode. True if device connected with host 10296fb914d7SGrigor Tovmasyan * @eps_in: The IN endpoints being supplied to the gadget framework 10306fb914d7SGrigor Tovmasyan * @eps_out: The OUT endpoints being supplied to the gadget framework 10316fb914d7SGrigor Tovmasyan * @new_connection: Used in host mode. True if there are new connected 10326fb914d7SGrigor Tovmasyan * device 10336fb914d7SGrigor Tovmasyan * @enabled: Indicates the enabling state of controller 10346fb914d7SGrigor Tovmasyan * 1035197ba5f4SPaul Zimmerman */ 1036197ba5f4SPaul Zimmerman struct dwc2_hsotg { 1037197ba5f4SPaul Zimmerman struct device *dev; 1038197ba5f4SPaul Zimmerman void __iomem *regs; 1039197ba5f4SPaul Zimmerman /** Params detected from hardware */ 1040197ba5f4SPaul Zimmerman struct dwc2_hw_params hw_params; 1041197ba5f4SPaul Zimmerman /** Params to actually use */ 1042bea8e86cSJohn Youn struct dwc2_core_params params; 1043197ba5f4SPaul Zimmerman enum usb_otg_state op_state; 1044c0155b9dSKever Yang enum usb_dr_mode dr_mode; 104517f93402SAmelie Delaunay struct usb_role_switch *role_sw; 1046e14acb87SFabrice Gasnier enum usb_dr_mode role_sw_default_mode; 1047e39af88fSMarek Szyprowski unsigned int hcd_enabled:1; 1048e39af88fSMarek Szyprowski unsigned int gadget_enabled:1; 104909a75e85SMarek Szyprowski unsigned int ll_hw_enabled:1; 105020fe4409SVardan Mikayelyan unsigned int hibernated:1; 1051be2b960eSArtur Petrosyan unsigned int in_ppd:1; 1052012466fcSArtur Petrosyan bool bus_suspended; 1053c40cf770SDouglas Anderson unsigned int reset_phy_on_wake:1; 1054c846b03fSDouglas Anderson unsigned int need_phy_for_wake:1; 1055c846b03fSDouglas Anderson unsigned int phy_off_for_suspend:1; 1056c7c24e7aSArtur Petrosyan u16 frame_number; 1057197ba5f4SPaul Zimmerman 1058941fcce4SDinh Nguyen struct phy *phy; 1059941fcce4SDinh Nguyen struct usb_phy *uphy; 106009a75e85SMarek Szyprowski struct dwc2_hsotg_plat *plat; 1061b98866c2SJohn Youn struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES]; 1062531ef5ebSAmelie Delaunay struct regulator *vbus_supply; 1063a415083aSAmelie Delaunay struct regulator *usb33d; 1064941fcce4SDinh Nguyen 1065941fcce4SDinh Nguyen spinlock_t lock; 1066941fcce4SDinh Nguyen void *priv; 1067941fcce4SDinh Nguyen int irq; 1068941fcce4SDinh Nguyen struct clk *clk; 106902329adeSFabrice Gasnier struct clk *utmi_clk; 107083f8da56SDinh Nguyen struct reset_control *reset; 1071f2830ad4SDinh Nguyen struct reset_control *reset_ecc; 1072941fcce4SDinh Nguyen 1073197ba5f4SPaul Zimmerman unsigned int queuing_high_bandwidth:1; 1074197ba5f4SPaul Zimmerman unsigned int srp_success:1; 1075197ba5f4SPaul Zimmerman 1076197ba5f4SPaul Zimmerman struct workqueue_struct *wq_otg; 1077197ba5f4SPaul Zimmerman struct work_struct wf_otg; 1078197ba5f4SPaul Zimmerman struct timer_list wkp_timer; 1079197ba5f4SPaul Zimmerman enum dwc2_lx_state lx_state; 1080cc1e204cSMian Yousaf Kaukab struct dwc2_gregs_backup gr_backup; 1081cc1e204cSMian Yousaf Kaukab struct dwc2_dregs_backup dr_backup; 1082cc1e204cSMian Yousaf Kaukab struct dwc2_hregs_backup hr_backup; 1083197ba5f4SPaul Zimmerman 1084941fcce4SDinh Nguyen struct dentry *debug_root; 1085563cf017SMian Yousaf Kaukab struct debugfs_regset32 *regset; 1086fe369e18SGevorg Sahakyan bool needs_byte_swap; 1087941fcce4SDinh Nguyen 1088941fcce4SDinh Nguyen /* DWC OTG HW Release versions */ 1089ba2951ecSMinas Harutyunyan #define DWC2_CORE_REV_4_30a 0x4f54430a 1090941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_71a 0x4f54271a 10915295322aSArtur Petrosyan #define DWC2_CORE_REV_2_72a 0x4f54272a 10926f80b6deSSevak Arakelyan #define DWC2_CORE_REV_2_80a 0x4f54280a 1093941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_90a 0x4f54290a 1094e1f411d1SSevak Arakelyan #define DWC2_CORE_REV_2_91a 0x4f54291a 1095941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_92a 0x4f54292a 1096941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_94a 0x4f54294a 1097941fcce4SDinh Nguyen #define DWC2_CORE_REV_3_00a 0x4f54300a 1098fef6bc37SJohn Youn #define DWC2_CORE_REV_3_10a 0x4f54310a 10995295322aSArtur Petrosyan #define DWC2_CORE_REV_4_00a 0x4f54400a 110065dc2e72SMinas Harutyunyan #define DWC2_CORE_REV_4_20a 0x4f54420a 11011e6b98ebSVardan Mikayelyan #define DWC2_FS_IOT_REV_1_00a 0x5531100a 11021e6b98ebSVardan Mikayelyan #define DWC2_HS_IOT_REV_1_00a 0x5532100a 110365dc2e72SMinas Harutyunyan #define DWC2_CORE_REV_MASK 0x0000ffff 1104941fcce4SDinh Nguyen 1105d14ccabaSGevorg Sahakyan /* DWC OTG HW Core ID */ 1106d14ccabaSGevorg Sahakyan #define DWC2_OTG_ID 0x4f540000 1107d14ccabaSGevorg Sahakyan #define DWC2_FS_IOT_ID 0x55310000 1108d14ccabaSGevorg Sahakyan #define DWC2_HS_IOT_ID 0x55320000 1109d14ccabaSGevorg Sahakyan 1110941fcce4SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1111197ba5f4SPaul Zimmerman union dwc2_hcd_internal_flags { 1112197ba5f4SPaul Zimmerman u32 d32; 1113197ba5f4SPaul Zimmerman struct { 1114197ba5f4SPaul Zimmerman unsigned port_connect_status_change:1; 1115197ba5f4SPaul Zimmerman unsigned port_connect_status:1; 1116197ba5f4SPaul Zimmerman unsigned port_reset_change:1; 1117197ba5f4SPaul Zimmerman unsigned port_enable_change:1; 1118197ba5f4SPaul Zimmerman unsigned port_suspend_change:1; 1119197ba5f4SPaul Zimmerman unsigned port_over_current_change:1; 1120197ba5f4SPaul Zimmerman unsigned port_l1_change:1; 1121fd4850cfSCharles Manning unsigned reserved:25; 1122197ba5f4SPaul Zimmerman } b; 1123197ba5f4SPaul Zimmerman } flags; 1124197ba5f4SPaul Zimmerman 1125197ba5f4SPaul Zimmerman struct list_head non_periodic_sched_inactive; 112638d2b5fbSDouglas Anderson struct list_head non_periodic_sched_waiting; 1127197ba5f4SPaul Zimmerman struct list_head non_periodic_sched_active; 1128197ba5f4SPaul Zimmerman struct list_head *non_periodic_qh_ptr; 1129197ba5f4SPaul Zimmerman struct list_head periodic_sched_inactive; 1130197ba5f4SPaul Zimmerman struct list_head periodic_sched_ready; 1131197ba5f4SPaul Zimmerman struct list_head periodic_sched_assigned; 1132197ba5f4SPaul Zimmerman struct list_head periodic_sched_queued; 1133c9c8ac01SDouglas Anderson struct list_head split_order; 1134197ba5f4SPaul Zimmerman u16 periodic_usecs; 1135db3e8244SChristophe JAILLET DECLARE_BITMAP(hs_periodic_bitmap, DWC2_HS_SCHEDULE_US); 1136197ba5f4SPaul Zimmerman u16 periodic_qh_count; 1137fbb9e22bSMian Yousaf Kaukab bool new_connection; 1138197ba5f4SPaul Zimmerman 1139483bb254SDouglas Anderson u16 last_frame_num; 1140483bb254SDouglas Anderson 1141197ba5f4SPaul Zimmerman #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 1142197ba5f4SPaul Zimmerman #define FRAME_NUM_ARRAY_SIZE 1000 1143197ba5f4SPaul Zimmerman u16 *frame_num_array; 1144197ba5f4SPaul Zimmerman u16 *last_frame_num_array; 1145197ba5f4SPaul Zimmerman int frame_num_idx; 1146197ba5f4SPaul Zimmerman int dumped_frame_num_array; 1147197ba5f4SPaul Zimmerman #endif 1148197ba5f4SPaul Zimmerman 1149197ba5f4SPaul Zimmerman struct list_head free_hc_list; 1150197ba5f4SPaul Zimmerman int periodic_channels; 1151197ba5f4SPaul Zimmerman int non_periodic_channels; 1152197ba5f4SPaul Zimmerman int available_host_channels; 1153197ba5f4SPaul Zimmerman struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 1154197ba5f4SPaul Zimmerman u8 *status_buf; 1155197ba5f4SPaul Zimmerman dma_addr_t status_buf_dma; 1156197ba5f4SPaul Zimmerman #define DWC2_HCD_STATUS_BUF_SIZE 64 1157197ba5f4SPaul Zimmerman 1158197ba5f4SPaul Zimmerman struct delayed_work start_work; 1159197ba5f4SPaul Zimmerman struct delayed_work reset_work; 1160c40cf770SDouglas Anderson struct work_struct phy_reset_work; 1161197ba5f4SPaul Zimmerman u8 otg_port; 1162197ba5f4SPaul Zimmerman u32 *frame_list; 1163197ba5f4SPaul Zimmerman dma_addr_t frame_list_dma; 116495105a99SGregory Herrero u32 frame_list_sz; 11653b5fcc9aSGregory Herrero struct kmem_cache *desc_gen_cache; 11663b5fcc9aSGregory Herrero struct kmem_cache *desc_hsisoc_cache; 1167af424a41SWilliam Wu struct kmem_cache *unaligned_cache; 1168af424a41SWilliam Wu #define DWC2_KMEM_UNALIGNED_BUF_SIZE 1024 1169197ba5f4SPaul Zimmerman 1170941fcce4SDinh Nguyen #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ 1171941fcce4SDinh Nguyen 1172b98866c2SJohn Youn #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1173b98866c2SJohn Youn IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1174941fcce4SDinh Nguyen /* Gadget structures */ 1175941fcce4SDinh Nguyen struct usb_gadget_driver *driver; 1176941fcce4SDinh Nguyen int fifo_mem; 1177941fcce4SDinh Nguyen unsigned int dedicated_fifos:1; 1178941fcce4SDinh Nguyen unsigned char num_of_eps; 1179941fcce4SDinh Nguyen u32 fifo_map; 1180941fcce4SDinh Nguyen 1181941fcce4SDinh Nguyen struct usb_request *ep0_reply; 1182941fcce4SDinh Nguyen struct usb_request *ctrl_req; 11833f95001dSMian Yousaf Kaukab void *ep0_buff; 11843f95001dSMian Yousaf Kaukab void *ctrl_buff; 1185fe0b94abSMian Yousaf Kaukab enum dwc2_ep0_state ep0_state; 1186b4c53b4aSMinas Harutyunyan unsigned delayed_status : 1; 11879e14d0a5SGregory Herrero u8 test_mode; 1188941fcce4SDinh Nguyen 11890f6b80c0SVahram Aharonyan dma_addr_t setup_desc_dma[2]; 11900f6b80c0SVahram Aharonyan struct dwc2_dma_desc *setup_desc[2]; 11910f6b80c0SVahram Aharonyan dma_addr_t ctrl_in_desc_dma; 11920f6b80c0SVahram Aharonyan struct dwc2_dma_desc *ctrl_in_desc; 11930f6b80c0SVahram Aharonyan dma_addr_t ctrl_out_desc_dma; 11940f6b80c0SVahram Aharonyan struct dwc2_dma_desc *ctrl_out_desc; 11950f6b80c0SVahram Aharonyan 1196941fcce4SDinh Nguyen struct usb_gadget gadget; 1197dc6e69e6SMarek Szyprowski unsigned int enabled:1; 11984ace06e8SMarek Szyprowski unsigned int connected:1; 1199fa389a6dSVardan Mikayelyan unsigned int remote_wakeup_allowed:1; 12001f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS]; 12011f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS]; 1202941fcce4SDinh Nguyen #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 1203197ba5f4SPaul Zimmerman }; 1204197ba5f4SPaul Zimmerman 12050f548098SGevorg Sahakyan /* Normal architectures just use readl/write */ 1206f25c42b8SGevorg Sahakyan static inline u32 dwc2_readl(struct dwc2_hsotg *hsotg, u32 offset) 12070f548098SGevorg Sahakyan { 1208fe369e18SGevorg Sahakyan u32 val; 1209fe369e18SGevorg Sahakyan 1210fe369e18SGevorg Sahakyan val = readl(hsotg->regs + offset); 1211fe369e18SGevorg Sahakyan if (hsotg->needs_byte_swap) 1212fe369e18SGevorg Sahakyan return swab32(val); 1213fe369e18SGevorg Sahakyan else 1214fe369e18SGevorg Sahakyan return val; 12150f548098SGevorg Sahakyan } 12160f548098SGevorg Sahakyan 1217f25c42b8SGevorg Sahakyan static inline void dwc2_writel(struct dwc2_hsotg *hsotg, u32 value, u32 offset) 12180f548098SGevorg Sahakyan { 1219fe369e18SGevorg Sahakyan if (hsotg->needs_byte_swap) 1220fe369e18SGevorg Sahakyan writel(swab32(value), hsotg->regs + offset); 1221fe369e18SGevorg Sahakyan else 1222f25c42b8SGevorg Sahakyan writel(value, hsotg->regs + offset); 12230f548098SGevorg Sahakyan 12240f548098SGevorg Sahakyan #ifdef DWC2_LOG_WRITES 1225f25c42b8SGevorg Sahakyan pr_info("info:: wrote %08x to %p\n", value, hsotg->regs + offset); 12260f548098SGevorg Sahakyan #endif 12270f548098SGevorg Sahakyan } 1228342ccce1SGevorg Sahakyan 1229342ccce1SGevorg Sahakyan static inline void dwc2_readl_rep(struct dwc2_hsotg *hsotg, u32 offset, 1230342ccce1SGevorg Sahakyan void *buffer, unsigned int count) 1231342ccce1SGevorg Sahakyan { 1232342ccce1SGevorg Sahakyan if (count) { 1233342ccce1SGevorg Sahakyan u32 *buf = buffer; 1234342ccce1SGevorg Sahakyan 1235342ccce1SGevorg Sahakyan do { 1236342ccce1SGevorg Sahakyan u32 x = dwc2_readl(hsotg, offset); 1237342ccce1SGevorg Sahakyan *buf++ = x; 1238342ccce1SGevorg Sahakyan } while (--count); 1239342ccce1SGevorg Sahakyan } 1240342ccce1SGevorg Sahakyan } 1241342ccce1SGevorg Sahakyan 1242342ccce1SGevorg Sahakyan static inline void dwc2_writel_rep(struct dwc2_hsotg *hsotg, u32 offset, 1243342ccce1SGevorg Sahakyan const void *buffer, unsigned int count) 1244342ccce1SGevorg Sahakyan { 1245342ccce1SGevorg Sahakyan if (count) { 1246342ccce1SGevorg Sahakyan const u32 *buf = buffer; 1247342ccce1SGevorg Sahakyan 1248342ccce1SGevorg Sahakyan do { 1249342ccce1SGevorg Sahakyan dwc2_writel(hsotg, *buf++, offset); 1250342ccce1SGevorg Sahakyan } while (--count); 1251342ccce1SGevorg Sahakyan } 1252342ccce1SGevorg Sahakyan } 12530f548098SGevorg Sahakyan 1254197ba5f4SPaul Zimmerman /* Reasons for halting a host channel */ 1255197ba5f4SPaul Zimmerman enum dwc2_halt_status { 1256197ba5f4SPaul Zimmerman DWC2_HC_XFER_NO_HALT_STATUS, 1257197ba5f4SPaul Zimmerman DWC2_HC_XFER_COMPLETE, 1258197ba5f4SPaul Zimmerman DWC2_HC_XFER_URB_COMPLETE, 1259197ba5f4SPaul Zimmerman DWC2_HC_XFER_ACK, 1260197ba5f4SPaul Zimmerman DWC2_HC_XFER_NAK, 1261197ba5f4SPaul Zimmerman DWC2_HC_XFER_NYET, 1262197ba5f4SPaul Zimmerman DWC2_HC_XFER_STALL, 1263197ba5f4SPaul Zimmerman DWC2_HC_XFER_XACT_ERR, 1264197ba5f4SPaul Zimmerman DWC2_HC_XFER_FRAME_OVERRUN, 1265197ba5f4SPaul Zimmerman DWC2_HC_XFER_BABBLE_ERR, 1266197ba5f4SPaul Zimmerman DWC2_HC_XFER_DATA_TOGGLE_ERR, 1267197ba5f4SPaul Zimmerman DWC2_HC_XFER_AHB_ERR, 1268197ba5f4SPaul Zimmerman DWC2_HC_XFER_PERIODIC_INCOMPLETE, 1269197ba5f4SPaul Zimmerman DWC2_HC_XFER_URB_DEQUEUE, 1270197ba5f4SPaul Zimmerman }; 1271197ba5f4SPaul Zimmerman 12721e6b98ebSVardan Mikayelyan /* Core version information */ 12731e6b98ebSVardan Mikayelyan static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg) 12741e6b98ebSVardan Mikayelyan { 12751e6b98ebSVardan Mikayelyan return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000; 12761e6b98ebSVardan Mikayelyan } 12771e6b98ebSVardan Mikayelyan 12781e6b98ebSVardan Mikayelyan static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg) 12791e6b98ebSVardan Mikayelyan { 12801e6b98ebSVardan Mikayelyan return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000; 12811e6b98ebSVardan Mikayelyan } 12821e6b98ebSVardan Mikayelyan 12831e6b98ebSVardan Mikayelyan static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg) 12841e6b98ebSVardan Mikayelyan { 12851e6b98ebSVardan Mikayelyan return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000; 12861e6b98ebSVardan Mikayelyan } 12871e6b98ebSVardan Mikayelyan 1288197ba5f4SPaul Zimmerman /* 1289197ba5f4SPaul Zimmerman * The following functions support initialization of the core driver component 1290197ba5f4SPaul Zimmerman * and the DWC_otg controller 1291197ba5f4SPaul Zimmerman */ 12926e6360b6SJohn Stultz int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait); 129341ba9b9bSVardan Mikayelyan int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg); 1294c9c394abSArtur Petrosyan int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, int rem_wakeup, 1295c9c394abSArtur Petrosyan bool restore); 1296624815ceSVardan Mikayelyan int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host); 1297624815ceSVardan Mikayelyan int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup, 1298624815ceSVardan Mikayelyan int reset, int is_host); 1299059d8d52SJules Maselbas void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg); 1300059d8d52SJules Maselbas int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy); 1301197ba5f4SPaul Zimmerman 130213b1f8e2SVardan Mikayelyan void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host); 130309c96980SJohn Youn void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg); 130409c96980SJohn Youn 13059da51974SJohn Youn bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 1306197ba5f4SPaul Zimmerman 130765dc2e72SMinas Harutyunyan int dwc2_check_core_version(struct dwc2_hsotg *hsotg); 130865dc2e72SMinas Harutyunyan 1309197ba5f4SPaul Zimmerman /* 1310197ba5f4SPaul Zimmerman * Common core Functions. 1311197ba5f4SPaul Zimmerman * The following functions support managing the DWC_otg controller in either 1312197ba5f4SPaul Zimmerman * device or host mode. 1313197ba5f4SPaul Zimmerman */ 13149da51974SJohn Youn void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 13159da51974SJohn Youn void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 13169da51974SJohn Youn void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 1317197ba5f4SPaul Zimmerman 13189da51974SJohn Youn void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 13199da51974SJohn Youn void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 1320197ba5f4SPaul Zimmerman 132194d2666cSVardan Mikayelyan void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup, 132294d2666cSVardan Mikayelyan int is_host); 1323c5c403dcSVardan Mikayelyan int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg); 1324c5c403dcSVardan Mikayelyan int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg); 132594d2666cSVardan Mikayelyan 132666e77a24SRazmik Karapetyan void dwc2_enable_acg(struct dwc2_hsotg *hsotg); 132766e77a24SRazmik Karapetyan 1328197ba5f4SPaul Zimmerman /* This function should be called on every hardware interrupt. */ 13299da51974SJohn Youn irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 1330197ba5f4SPaul Zimmerman 1331323230efSJohn Youn /* The device ID match table */ 1332323230efSJohn Youn extern const struct of_device_id dwc2_of_match_table[]; 13332e5db2c0SJeremy Linton extern const struct acpi_device_id dwc2_acpi_match[]; 1334e16d5f14SYinbo Zhu extern const struct pci_device_id dwc2_pci_ids[]; 1335323230efSJohn Youn 13369da51974SJohn Youn int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg); 13379da51974SJohn Youn int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg); 1338ecb176c6SMian Yousaf Kaukab 133979d6b8c5SSevak Arakelyan /* Common polling functions */ 134079d6b8c5SSevak Arakelyan int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit, 134179d6b8c5SSevak Arakelyan u32 timeout); 134279d6b8c5SSevak Arakelyan int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit, 134379d6b8c5SSevak Arakelyan u32 timeout); 1344334bbd4eSJohn Youn /* Parameters */ 1345c1d286cfSJohn Youn int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); 1346334bbd4eSJohn Youn int dwc2_init_params(struct dwc2_hsotg *hsotg); 1347334bbd4eSJohn Youn 1348197ba5f4SPaul Zimmerman /* 13496bea9620SJohn Youn * The following functions check the controller's OTG operation mode 13506bea9620SJohn Youn * capability (GHWCFG2.OTG_MODE). 13516bea9620SJohn Youn * 13526bea9620SJohn Youn * These functions can be used before the internal hsotg->hw_params 13536bea9620SJohn Youn * are read in and cached so they always read directly from the 13546bea9620SJohn Youn * GHWCFG2 register. 13556bea9620SJohn Youn */ 13569da51974SJohn Youn unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg); 13576bea9620SJohn Youn bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg); 13586bea9620SJohn Youn bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg); 13596bea9620SJohn Youn bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg); 13606bea9620SJohn Youn 13616bea9620SJohn Youn /* 13621696d5abSJohn Youn * Returns the mode of operation, host or device 13631696d5abSJohn Youn */ 13641696d5abSJohn Youn static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) 13651696d5abSJohn Youn { 1366f25c42b8SGevorg Sahakyan return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) != 0; 13671696d5abSJohn Youn } 13689da51974SJohn Youn 13691696d5abSJohn Youn static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) 13701696d5abSJohn Youn { 1371f25c42b8SGevorg Sahakyan return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) == 0; 13721696d5abSJohn Youn } 13731696d5abSJohn Youn 137417f93402SAmelie Delaunay int dwc2_drd_init(struct dwc2_hsotg *hsotg); 137517f93402SAmelie Delaunay void dwc2_drd_suspend(struct dwc2_hsotg *hsotg); 137617f93402SAmelie Delaunay void dwc2_drd_resume(struct dwc2_hsotg *hsotg); 137717f93402SAmelie Delaunay void dwc2_drd_exit(struct dwc2_hsotg *hsotg); 137817f93402SAmelie Delaunay 13791696d5abSJohn Youn /* 1380197ba5f4SPaul Zimmerman * Dump core registers and SPRAM 1381197ba5f4SPaul Zimmerman */ 13829da51974SJohn Youn void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 13839da51974SJohn Youn void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 13849da51974SJohn Youn void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 1385197ba5f4SPaul Zimmerman 1386117777b2SDinh Nguyen /* Gadget defines */ 1387b98866c2SJohn Youn #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1388b98866c2SJohn Youn IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 13899da51974SJohn Youn int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg); 13909da51974SJohn Youn int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2); 13919da51974SJohn Youn int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2); 1392f3768997SVardan Mikayelyan int dwc2_gadget_init(struct dwc2_hsotg *hsotg); 13939da51974SJohn Youn void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1394643cc4deSGregory Herrero bool reset); 139517f93402SAmelie Delaunay void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg); 13969da51974SJohn Youn void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg); 13979da51974SJohn Youn void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2); 13989da51974SJohn Youn int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode); 1399f81f46e1SGregory Herrero #define dwc2_is_device_connected(hsotg) (hsotg->connected) 140032fde843SFabrice Gasnier #define dwc2_is_device_enabled(hsotg) (hsotg->enabled) 140158e52ff6SJohn Youn int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg); 14029a5d2816SVardan Mikayelyan int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup); 1403c5c403dcSVardan Mikayelyan int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg); 1404c5c403dcSVardan Mikayelyan int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, 1405c5c403dcSVardan Mikayelyan int rem_wakeup, int reset); 1406be2b960eSArtur Petrosyan int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg); 1407be2b960eSArtur Petrosyan int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg, 1408be2b960eSArtur Petrosyan bool restore); 1409012466fcSArtur Petrosyan void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg); 1410012466fcSArtur Petrosyan void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, 1411012466fcSArtur Petrosyan int rem_wakeup); 1412c138ecfaSSevak Arakelyan int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg); 1413c138ecfaSSevak Arakelyan int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg); 1414c138ecfaSSevak Arakelyan int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg); 141521b03405SSevak Arakelyan void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg); 141615d9dbf8SGrigor Tovmasyan void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg); 1417238f65aeSArtur Petrosyan static inline void dwc2_clear_fifo_map(struct dwc2_hsotg *hsotg) 1418238f65aeSArtur Petrosyan { hsotg->fifo_map = 0; } 1419117777b2SDinh Nguyen #else 14201f91b4ccSFelipe Balbi static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2) 1421117777b2SDinh Nguyen { return 0; } 14221f91b4ccSFelipe Balbi static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2) 1423117777b2SDinh Nguyen { return 0; } 14241f91b4ccSFelipe Balbi static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2) 1425117777b2SDinh Nguyen { return 0; } 1426f3768997SVardan Mikayelyan static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg) 1427117777b2SDinh Nguyen { return 0; } 14281f91b4ccSFelipe Balbi static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1429643cc4deSGregory Herrero bool reset) {} 143017f93402SAmelie Delaunay static inline void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) {} 14311f91b4ccSFelipe Balbi static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} 14321f91b4ccSFelipe Balbi static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} 14331f91b4ccSFelipe Balbi static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, 1434f91eea44SMian Yousaf Kaukab int testmode) 1435f91eea44SMian Yousaf Kaukab { return 0; } 1436f81f46e1SGregory Herrero #define dwc2_is_device_connected(hsotg) (0) 143732fde843SFabrice Gasnier #define dwc2_is_device_enabled(hsotg) (0) 143858e52ff6SJohn Youn static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) 143958e52ff6SJohn Youn { return 0; } 14409a5d2816SVardan Mikayelyan static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, 14419a5d2816SVardan Mikayelyan int remote_wakeup) 144258e52ff6SJohn Youn { return 0; } 1443c5c403dcSVardan Mikayelyan static inline int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg) 1444c5c403dcSVardan Mikayelyan { return 0; } 1445c5c403dcSVardan Mikayelyan static inline int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, 1446c5c403dcSVardan Mikayelyan int rem_wakeup, int reset) 1447c5c403dcSVardan Mikayelyan { return 0; } 1448be2b960eSArtur Petrosyan static inline int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg) 1449be2b960eSArtur Petrosyan { return 0; } 1450be2b960eSArtur Petrosyan static inline int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg, 1451be2b960eSArtur Petrosyan bool restore) 1452be2b960eSArtur Petrosyan { return 0; } 1453012466fcSArtur Petrosyan static inline void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg) {} 1454012466fcSArtur Petrosyan static inline void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, 1455012466fcSArtur Petrosyan int rem_wakeup) {} 1456c138ecfaSSevak Arakelyan static inline int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg) 1457c138ecfaSSevak Arakelyan { return 0; } 1458c138ecfaSSevak Arakelyan static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) 1459c138ecfaSSevak Arakelyan { return 0; } 1460c138ecfaSSevak Arakelyan static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg) 1461c138ecfaSSevak Arakelyan { return 0; } 146221b03405SSevak Arakelyan static inline void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) {} 146315d9dbf8SGrigor Tovmasyan static inline void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg) {} 1464238f65aeSArtur Petrosyan static inline void dwc2_clear_fifo_map(struct dwc2_hsotg *hsotg) {} 1465117777b2SDinh Nguyen #endif 1466117777b2SDinh Nguyen 1467117777b2SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 14689da51974SJohn Youn int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 14699da51974SJohn Youn int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us); 14709da51974SJohn Youn void dwc2_hcd_connect(struct dwc2_hsotg *hsotg); 14719da51974SJohn Youn void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force); 14729da51974SJohn Youn void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 147365c9c4c6SVardan Mikayelyan int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup); 147422ff0c8eSArtur Petrosyan int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex); 14751e0890ebSArtur Petrosyan int dwc2_port_resume(struct dwc2_hsotg *hsotg); 147658e52ff6SJohn Youn int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg); 147758e52ff6SJohn Youn int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg); 1478c5c403dcSVardan Mikayelyan int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg); 1479c5c403dcSVardan Mikayelyan int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, 1480c5c403dcSVardan Mikayelyan int rem_wakeup, int reset); 14819ce9e5adSArtur Petrosyan int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg); 14829ce9e5adSArtur Petrosyan int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg, 14839ce9e5adSArtur Petrosyan int rem_wakeup, bool restore); 148479c87c3cSArtur Petrosyan void dwc2_host_enter_clock_gating(struct dwc2_hsotg *hsotg); 148579c87c3cSArtur Petrosyan void dwc2_host_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup); 1486c846b03fSDouglas Anderson bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2); 1487c40cf770SDouglas Anderson static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) 1488c40cf770SDouglas Anderson { schedule_work(&hsotg->phy_reset_work); } 1489117777b2SDinh Nguyen #else 1490117777b2SDinh Nguyen static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1491117777b2SDinh Nguyen { return 0; } 1492fae4e826SDouglas Anderson static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, 1493fae4e826SDouglas Anderson int us) 1494fae4e826SDouglas Anderson { return 0; } 14956a659531SDouglas Anderson static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {} 14966a659531SDouglas Anderson static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {} 1497117777b2SDinh Nguyen static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} 1498117777b2SDinh Nguyen static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} 149965c9c4c6SVardan Mikayelyan static inline int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) 150065c9c4c6SVardan Mikayelyan { return 0; } 150122ff0c8eSArtur Petrosyan static inline int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 150222ff0c8eSArtur Petrosyan { return 0; } 15031e0890ebSArtur Petrosyan static inline int dwc2_port_resume(struct dwc2_hsotg *hsotg) 15041e0890ebSArtur Petrosyan { return 0; } 15054fe160d5SHeiner Kallweit static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg) 1506117777b2SDinh Nguyen { return 0; } 150758e52ff6SJohn Youn static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 150858e52ff6SJohn Youn { return 0; } 150958e52ff6SJohn Youn static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 151058e52ff6SJohn Youn { return 0; } 1511c5c403dcSVardan Mikayelyan static inline int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg) 1512c5c403dcSVardan Mikayelyan { return 0; } 1513c5c403dcSVardan Mikayelyan static inline int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, 1514c5c403dcSVardan Mikayelyan int rem_wakeup, int reset) 1515c5c403dcSVardan Mikayelyan { return 0; } 15169ce9e5adSArtur Petrosyan static inline int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg) 15179ce9e5adSArtur Petrosyan { return 0; } 15189ce9e5adSArtur Petrosyan static inline int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg, 15199ce9e5adSArtur Petrosyan int rem_wakeup, bool restore) 15209ce9e5adSArtur Petrosyan { return 0; } 152179c87c3cSArtur Petrosyan static inline void dwc2_host_enter_clock_gating(struct dwc2_hsotg *hsotg) {} 152279c87c3cSArtur Petrosyan static inline void dwc2_host_exit_clock_gating(struct dwc2_hsotg *hsotg, 152379c87c3cSArtur Petrosyan int rem_wakeup) {} 1524c846b03fSDouglas Anderson static inline bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2) 1525c846b03fSDouglas Anderson { return false; } 1526c40cf770SDouglas Anderson static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) {} 152758e52ff6SJohn Youn 1528117777b2SDinh Nguyen #endif 1529117777b2SDinh Nguyen 1530197ba5f4SPaul Zimmerman #endif /* __DWC2_CORE_H__ */ 1531