1197ba5f4SPaul Zimmerman /* 2197ba5f4SPaul Zimmerman * core.h - DesignWare HS OTG Controller common declarations 3197ba5f4SPaul Zimmerman * 4197ba5f4SPaul Zimmerman * Copyright (C) 2004-2013 Synopsys, Inc. 5197ba5f4SPaul Zimmerman * 6197ba5f4SPaul Zimmerman * Redistribution and use in source and binary forms, with or without 7197ba5f4SPaul Zimmerman * modification, are permitted provided that the following conditions 8197ba5f4SPaul Zimmerman * are met: 9197ba5f4SPaul Zimmerman * 1. Redistributions of source code must retain the above copyright 10197ba5f4SPaul Zimmerman * notice, this list of conditions, and the following disclaimer, 11197ba5f4SPaul Zimmerman * without modification. 12197ba5f4SPaul Zimmerman * 2. Redistributions in binary form must reproduce the above copyright 13197ba5f4SPaul Zimmerman * notice, this list of conditions and the following disclaimer in the 14197ba5f4SPaul Zimmerman * documentation and/or other materials provided with the distribution. 15197ba5f4SPaul Zimmerman * 3. The names of the above-listed copyright holders may not be used 16197ba5f4SPaul Zimmerman * to endorse or promote products derived from this software without 17197ba5f4SPaul Zimmerman * specific prior written permission. 18197ba5f4SPaul Zimmerman * 19197ba5f4SPaul Zimmerman * ALTERNATIVELY, this software may be distributed under the terms of the 20197ba5f4SPaul Zimmerman * GNU General Public License ("GPL") as published by the Free Software 21197ba5f4SPaul Zimmerman * Foundation; either version 2 of the License, or (at your option) any 22197ba5f4SPaul Zimmerman * later version. 23197ba5f4SPaul Zimmerman * 24197ba5f4SPaul Zimmerman * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25197ba5f4SPaul Zimmerman * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26197ba5f4SPaul Zimmerman * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27197ba5f4SPaul Zimmerman * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28197ba5f4SPaul Zimmerman * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29197ba5f4SPaul Zimmerman * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30197ba5f4SPaul Zimmerman * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31197ba5f4SPaul Zimmerman * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32197ba5f4SPaul Zimmerman * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33197ba5f4SPaul Zimmerman * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34197ba5f4SPaul Zimmerman * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35197ba5f4SPaul Zimmerman */ 36197ba5f4SPaul Zimmerman 37197ba5f4SPaul Zimmerman #ifndef __DWC2_CORE_H__ 38197ba5f4SPaul Zimmerman #define __DWC2_CORE_H__ 39197ba5f4SPaul Zimmerman 40f7c0b143SDinh Nguyen #include <linux/phy/phy.h> 41f7c0b143SDinh Nguyen #include <linux/regulator/consumer.h> 42f7c0b143SDinh Nguyen #include <linux/usb/gadget.h> 43f7c0b143SDinh Nguyen #include <linux/usb/otg.h> 44197ba5f4SPaul Zimmerman #include <linux/usb/phy.h> 45197ba5f4SPaul Zimmerman #include "hw.h" 46197ba5f4SPaul Zimmerman 47197ba5f4SPaul Zimmerman #ifdef DWC2_LOG_WRITES 48197ba5f4SPaul Zimmerman static inline void do_write(u32 value, void *addr) 49197ba5f4SPaul Zimmerman { 50197ba5f4SPaul Zimmerman writel(value, addr); 51197ba5f4SPaul Zimmerman pr_info("INFO:: wrote %08x to %p\n", value, addr); 52197ba5f4SPaul Zimmerman } 53197ba5f4SPaul Zimmerman 54197ba5f4SPaul Zimmerman #undef writel 55197ba5f4SPaul Zimmerman #define writel(v, a) do_write(v, a) 56197ba5f4SPaul Zimmerman #endif 57197ba5f4SPaul Zimmerman 58197ba5f4SPaul Zimmerman /* Maximum number of Endpoints/HostChannels */ 59197ba5f4SPaul Zimmerman #define MAX_EPS_CHANNELS 16 60197ba5f4SPaul Zimmerman 61f7c0b143SDinh Nguyen /* s3c-hsotg declarations */ 62f7c0b143SDinh Nguyen static const char * const s3c_hsotg_supply_names[] = { 63f7c0b143SDinh Nguyen "vusb_d", /* digital USB supply, 1.2V */ 64f7c0b143SDinh Nguyen "vusb_a", /* analog USB supply, 1.1V */ 65f7c0b143SDinh Nguyen }; 66f7c0b143SDinh Nguyen 67f7c0b143SDinh Nguyen /* 68f7c0b143SDinh Nguyen * EP0_MPS_LIMIT 69f7c0b143SDinh Nguyen * 70f7c0b143SDinh Nguyen * Unfortunately there seems to be a limit of the amount of data that can 71f7c0b143SDinh Nguyen * be transferred by IN transactions on EP0. This is either 127 bytes or 3 72f7c0b143SDinh Nguyen * packets (which practically means 1 packet and 63 bytes of data) when the 73f7c0b143SDinh Nguyen * MPS is set to 64. 74f7c0b143SDinh Nguyen * 75f7c0b143SDinh Nguyen * This means if we are wanting to move >127 bytes of data, we need to 76f7c0b143SDinh Nguyen * split the transactions up, but just doing one packet at a time does 77f7c0b143SDinh Nguyen * not work (this may be an implicit DATA0 PID on first packet of the 78f7c0b143SDinh Nguyen * transaction) and doing 2 packets is outside the controller's limits. 79f7c0b143SDinh Nguyen * 80f7c0b143SDinh Nguyen * If we try to lower the MPS size for EP0, then no transfers work properly 81f7c0b143SDinh Nguyen * for EP0, and the system will fail basic enumeration. As no cause for this 82f7c0b143SDinh Nguyen * has currently been found, we cannot support any large IN transfers for 83f7c0b143SDinh Nguyen * EP0. 84f7c0b143SDinh Nguyen */ 85f7c0b143SDinh Nguyen #define EP0_MPS_LIMIT 64 86f7c0b143SDinh Nguyen 87f7c0b143SDinh Nguyen struct s3c_hsotg; 88f7c0b143SDinh Nguyen struct s3c_hsotg_req; 89f7c0b143SDinh Nguyen 90f7c0b143SDinh Nguyen /** 91f7c0b143SDinh Nguyen * struct s3c_hsotg_ep - driver endpoint definition. 92f7c0b143SDinh Nguyen * @ep: The gadget layer representation of the endpoint. 93f7c0b143SDinh Nguyen * @name: The driver generated name for the endpoint. 94f7c0b143SDinh Nguyen * @queue: Queue of requests for this endpoint. 95f7c0b143SDinh Nguyen * @parent: Reference back to the parent device structure. 96f7c0b143SDinh Nguyen * @req: The current request that the endpoint is processing. This is 97f7c0b143SDinh Nguyen * used to indicate an request has been loaded onto the endpoint 98f7c0b143SDinh Nguyen * and has yet to be completed (maybe due to data move, or simply 99f7c0b143SDinh Nguyen * awaiting an ack from the core all the data has been completed). 100f7c0b143SDinh Nguyen * @debugfs: File entry for debugfs file for this endpoint. 101f7c0b143SDinh Nguyen * @lock: State lock to protect contents of endpoint. 102f7c0b143SDinh Nguyen * @dir_in: Set to true if this endpoint is of the IN direction, which 103f7c0b143SDinh Nguyen * means that it is sending data to the Host. 104f7c0b143SDinh Nguyen * @index: The index for the endpoint registers. 105f7c0b143SDinh Nguyen * @mc: Multi Count - number of transactions per microframe 106f7c0b143SDinh Nguyen * @interval - Interval for periodic endpoints 107f7c0b143SDinh Nguyen * @name: The name array passed to the USB core. 108f7c0b143SDinh Nguyen * @halted: Set if the endpoint has been halted. 109f7c0b143SDinh Nguyen * @periodic: Set if this is a periodic ep, such as Interrupt 110f7c0b143SDinh Nguyen * @isochronous: Set if this is a isochronous ep 111f7c0b143SDinh Nguyen * @sent_zlp: Set if we've sent a zero-length packet. 112f7c0b143SDinh Nguyen * @total_data: The total number of data bytes done. 113f7c0b143SDinh Nguyen * @fifo_size: The size of the FIFO (for periodic IN endpoints) 114f7c0b143SDinh Nguyen * @fifo_load: The amount of data loaded into the FIFO (periodic IN) 115f7c0b143SDinh Nguyen * @last_load: The offset of data for the last start of request. 116f7c0b143SDinh Nguyen * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN 117f7c0b143SDinh Nguyen * 118f7c0b143SDinh Nguyen * This is the driver's state for each registered enpoint, allowing it 119f7c0b143SDinh Nguyen * to keep track of transactions that need doing. Each endpoint has a 120f7c0b143SDinh Nguyen * lock to protect the state, to try and avoid using an overall lock 121f7c0b143SDinh Nguyen * for the host controller as much as possible. 122f7c0b143SDinh Nguyen * 123f7c0b143SDinh Nguyen * For periodic IN endpoints, we have fifo_size and fifo_load to try 124f7c0b143SDinh Nguyen * and keep track of the amount of data in the periodic FIFO for each 125f7c0b143SDinh Nguyen * of these as we don't have a status register that tells us how much 126f7c0b143SDinh Nguyen * is in each of them. (note, this may actually be useless information 127f7c0b143SDinh Nguyen * as in shared-fifo mode periodic in acts like a single-frame packet 128f7c0b143SDinh Nguyen * buffer than a fifo) 129f7c0b143SDinh Nguyen */ 130f7c0b143SDinh Nguyen struct s3c_hsotg_ep { 131f7c0b143SDinh Nguyen struct usb_ep ep; 132f7c0b143SDinh Nguyen struct list_head queue; 133f7c0b143SDinh Nguyen struct s3c_hsotg *parent; 134f7c0b143SDinh Nguyen struct s3c_hsotg_req *req; 135f7c0b143SDinh Nguyen struct dentry *debugfs; 136f7c0b143SDinh Nguyen 137f7c0b143SDinh Nguyen unsigned long total_data; 138f7c0b143SDinh Nguyen unsigned int size_loaded; 139f7c0b143SDinh Nguyen unsigned int last_load; 140f7c0b143SDinh Nguyen unsigned int fifo_load; 141f7c0b143SDinh Nguyen unsigned short fifo_size; 142b203d0a2SRobert Baldyga unsigned short fifo_index; 143f7c0b143SDinh Nguyen 144f7c0b143SDinh Nguyen unsigned char dir_in; 145f7c0b143SDinh Nguyen unsigned char index; 146f7c0b143SDinh Nguyen unsigned char mc; 147f7c0b143SDinh Nguyen unsigned char interval; 148f7c0b143SDinh Nguyen 149f7c0b143SDinh Nguyen unsigned int halted:1; 150f7c0b143SDinh Nguyen unsigned int periodic:1; 151f7c0b143SDinh Nguyen unsigned int isochronous:1; 152f7c0b143SDinh Nguyen unsigned int sent_zlp:1; 153f7c0b143SDinh Nguyen 154f7c0b143SDinh Nguyen char name[10]; 155f7c0b143SDinh Nguyen }; 156f7c0b143SDinh Nguyen 157f7c0b143SDinh Nguyen /** 158f7c0b143SDinh Nguyen * struct s3c_hsotg - driver state. 159f7c0b143SDinh Nguyen * @dev: The parent device supplied to the probe function 160f7c0b143SDinh Nguyen * @driver: USB gadget driver 161f7c0b143SDinh Nguyen * @phy: The otg phy transceiver structure for phy control. 162f7c0b143SDinh Nguyen * @uphy: The otg phy transceiver structure for old USB phy control. 163f7c0b143SDinh Nguyen * @plat: The platform specific configuration data. This can be removed once 164f7c0b143SDinh Nguyen * all SoCs support usb transceiver. 165f7c0b143SDinh Nguyen * @regs: The memory area mapped for accessing registers. 166f7c0b143SDinh Nguyen * @irq: The IRQ number we are using 167f7c0b143SDinh Nguyen * @supplies: Definition of USB power supplies 168f7c0b143SDinh Nguyen * @phyif: PHY interface width 169f7c0b143SDinh Nguyen * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 170f7c0b143SDinh Nguyen * @num_of_eps: Number of available EPs (excluding EP0) 171f7c0b143SDinh Nguyen * @debug_root: root directrory for debugfs. 172f7c0b143SDinh Nguyen * @debug_file: main status file for debugfs. 173f7c0b143SDinh Nguyen * @debug_fifo: FIFO status file for debugfs. 174f7c0b143SDinh Nguyen * @ep0_reply: Request used for ep0 reply. 175f7c0b143SDinh Nguyen * @ep0_buff: Buffer for EP0 reply data, if needed. 176f7c0b143SDinh Nguyen * @ctrl_buff: Buffer for EP0 control requests. 177f7c0b143SDinh Nguyen * @ctrl_req: Request for EP0 control packets. 178f7c0b143SDinh Nguyen * @setup: NAK management for EP0 SETUP 179f7c0b143SDinh Nguyen * @last_rst: Time of last reset 180f7c0b143SDinh Nguyen * @eps: The endpoints being supplied to the gadget framework 181f7c0b143SDinh Nguyen */ 182f7c0b143SDinh Nguyen struct s3c_hsotg { 183f7c0b143SDinh Nguyen struct device *dev; 184f7c0b143SDinh Nguyen struct usb_gadget_driver *driver; 185f7c0b143SDinh Nguyen struct phy *phy; 186f7c0b143SDinh Nguyen struct usb_phy *uphy; 187f7c0b143SDinh Nguyen struct s3c_hsotg_plat *plat; 188f7c0b143SDinh Nguyen 189f7c0b143SDinh Nguyen spinlock_t lock; 190f7c0b143SDinh Nguyen 191f7c0b143SDinh Nguyen void __iomem *regs; 192f7c0b143SDinh Nguyen int irq; 193f7c0b143SDinh Nguyen struct clk *clk; 194f7c0b143SDinh Nguyen 195f7c0b143SDinh Nguyen struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsotg_supply_names)]; 196f7c0b143SDinh Nguyen 197f7c0b143SDinh Nguyen u32 phyif; 198cff9eb75SMarek Szyprowski int fifo_mem; 199f7c0b143SDinh Nguyen unsigned int dedicated_fifos:1; 200f7c0b143SDinh Nguyen unsigned char num_of_eps; 201b203d0a2SRobert Baldyga u32 fifo_map; 202f7c0b143SDinh Nguyen 203f7c0b143SDinh Nguyen struct dentry *debug_root; 204f7c0b143SDinh Nguyen struct dentry *debug_file; 205f7c0b143SDinh Nguyen struct dentry *debug_fifo; 206f7c0b143SDinh Nguyen 207f7c0b143SDinh Nguyen struct usb_request *ep0_reply; 208f7c0b143SDinh Nguyen struct usb_request *ctrl_req; 209f7c0b143SDinh Nguyen u8 ep0_buff[8]; 210f7c0b143SDinh Nguyen u8 ctrl_buff[8]; 211f7c0b143SDinh Nguyen 212f7c0b143SDinh Nguyen struct usb_gadget gadget; 213f7c0b143SDinh Nguyen unsigned int setup; 214f7c0b143SDinh Nguyen unsigned long last_rst; 215f7c0b143SDinh Nguyen struct s3c_hsotg_ep *eps; 216f7c0b143SDinh Nguyen }; 217f7c0b143SDinh Nguyen 218f7c0b143SDinh Nguyen /** 219f7c0b143SDinh Nguyen * struct s3c_hsotg_req - data transfer request 220f7c0b143SDinh Nguyen * @req: The USB gadget request 221f7c0b143SDinh Nguyen * @queue: The list of requests for the endpoint this is queued for. 222f7c0b143SDinh Nguyen * @in_progress: Has already had size/packets written to core 223f7c0b143SDinh Nguyen * @mapped: DMA buffer for this request has been mapped via dma_map_single(). 224f7c0b143SDinh Nguyen */ 225f7c0b143SDinh Nguyen struct s3c_hsotg_req { 226f7c0b143SDinh Nguyen struct usb_request req; 227f7c0b143SDinh Nguyen struct list_head queue; 228f7c0b143SDinh Nguyen unsigned char in_progress; 229f7c0b143SDinh Nguyen unsigned char mapped; 230f7c0b143SDinh Nguyen }; 231f7c0b143SDinh Nguyen 232f7c0b143SDinh Nguyen #define call_gadget(_hs, _entry) \ 233f7c0b143SDinh Nguyen do { \ 234f7c0b143SDinh Nguyen if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ 235f7c0b143SDinh Nguyen (_hs)->driver && (_hs)->driver->_entry) { \ 236f7c0b143SDinh Nguyen spin_unlock(&_hs->lock); \ 237f7c0b143SDinh Nguyen (_hs)->driver->_entry(&(_hs)->gadget); \ 238f7c0b143SDinh Nguyen spin_lock(&_hs->lock); \ 239f7c0b143SDinh Nguyen } \ 240f7c0b143SDinh Nguyen } while (0) 241f7c0b143SDinh Nguyen 242197ba5f4SPaul Zimmerman struct dwc2_hsotg; 243197ba5f4SPaul Zimmerman struct dwc2_host_chan; 244197ba5f4SPaul Zimmerman 245197ba5f4SPaul Zimmerman /* Device States */ 246197ba5f4SPaul Zimmerman enum dwc2_lx_state { 247197ba5f4SPaul Zimmerman DWC2_L0, /* On state */ 248197ba5f4SPaul Zimmerman DWC2_L1, /* LPM sleep state */ 249197ba5f4SPaul Zimmerman DWC2_L2, /* USB suspend state */ 250197ba5f4SPaul Zimmerman DWC2_L3, /* Off state */ 251197ba5f4SPaul Zimmerman }; 252197ba5f4SPaul Zimmerman 253197ba5f4SPaul Zimmerman /** 254197ba5f4SPaul Zimmerman * struct dwc2_core_params - Parameters for configuring the core 255197ba5f4SPaul Zimmerman * 256197ba5f4SPaul Zimmerman * @otg_cap: Specifies the OTG capabilities. 257197ba5f4SPaul Zimmerman * 0 - HNP and SRP capable 258197ba5f4SPaul Zimmerman * 1 - SRP Only capable 259197ba5f4SPaul Zimmerman * 2 - No HNP/SRP capable (always available) 260197ba5f4SPaul Zimmerman * Defaults to best available option (0, 1, then 2) 261197ba5f4SPaul Zimmerman * @otg_ver: OTG version supported 262197ba5f4SPaul Zimmerman * 0 - 1.3 (default) 263197ba5f4SPaul Zimmerman * 1 - 2.0 264197ba5f4SPaul Zimmerman * @dma_enable: Specifies whether to use slave or DMA mode for accessing 265197ba5f4SPaul Zimmerman * the data FIFOs. The driver will automatically detect the 266197ba5f4SPaul Zimmerman * value for this parameter if none is specified. 267197ba5f4SPaul Zimmerman * 0 - Slave (always available) 268197ba5f4SPaul Zimmerman * 1 - DMA (default, if available) 269197ba5f4SPaul Zimmerman * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 270197ba5f4SPaul Zimmerman * address DMA mode or descriptor DMA mode for accessing 271197ba5f4SPaul Zimmerman * the data FIFOs. The driver will automatically detect the 272197ba5f4SPaul Zimmerman * value for this if none is specified. 273197ba5f4SPaul Zimmerman * 0 - Address DMA 274197ba5f4SPaul Zimmerman * 1 - Descriptor DMA (default, if available) 275197ba5f4SPaul Zimmerman * @speed: Specifies the maximum speed of operation in host and 276197ba5f4SPaul Zimmerman * device mode. The actual speed depends on the speed of 277197ba5f4SPaul Zimmerman * the attached device and the value of phy_type. 278197ba5f4SPaul Zimmerman * 0 - High Speed 279197ba5f4SPaul Zimmerman * (default when phy_type is UTMI+ or ULPI) 280197ba5f4SPaul Zimmerman * 1 - Full Speed 281197ba5f4SPaul Zimmerman * (default when phy_type is Full Speed) 282197ba5f4SPaul Zimmerman * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 283197ba5f4SPaul Zimmerman * 1 - Allow dynamic FIFO sizing (default, if available) 284197ba5f4SPaul Zimmerman * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 285197ba5f4SPaul Zimmerman * are enabled 286197ba5f4SPaul Zimmerman * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 287197ba5f4SPaul Zimmerman * dynamic FIFO sizing is enabled 288197ba5f4SPaul Zimmerman * 16 to 32768 289197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 290197ba5f4SPaul Zimmerman * the default. 291197ba5f4SPaul Zimmerman * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 292197ba5f4SPaul Zimmerman * in host mode when dynamic FIFO sizing is enabled 293197ba5f4SPaul Zimmerman * 16 to 32768 294197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 295197ba5f4SPaul Zimmerman * the default. 296197ba5f4SPaul Zimmerman * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 297197ba5f4SPaul Zimmerman * host mode when dynamic FIFO sizing is enabled 298197ba5f4SPaul Zimmerman * 16 to 32768 299197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 300197ba5f4SPaul Zimmerman * the default. 301197ba5f4SPaul Zimmerman * @max_transfer_size: The maximum transfer size supported, in bytes 302197ba5f4SPaul Zimmerman * 2047 to 65,535 303197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 304197ba5f4SPaul Zimmerman * the default. 305197ba5f4SPaul Zimmerman * @max_packet_count: The maximum number of packets in a transfer 306197ba5f4SPaul Zimmerman * 15 to 511 307197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 308197ba5f4SPaul Zimmerman * the default. 309197ba5f4SPaul Zimmerman * @host_channels: The number of host channel registers to use 310197ba5f4SPaul Zimmerman * 1 to 16 311197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 312197ba5f4SPaul Zimmerman * the default. 313197ba5f4SPaul Zimmerman * @phy_type: Specifies the type of PHY interface to use. By default, 314197ba5f4SPaul Zimmerman * the driver will automatically detect the phy_type. 315197ba5f4SPaul Zimmerman * 0 - Full Speed Phy 316197ba5f4SPaul Zimmerman * 1 - UTMI+ Phy 317197ba5f4SPaul Zimmerman * 2 - ULPI Phy 318197ba5f4SPaul Zimmerman * Defaults to best available option (2, 1, then 0) 319197ba5f4SPaul Zimmerman * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 320197ba5f4SPaul Zimmerman * is applicable for a phy_type of UTMI+ or ULPI. (For a 321197ba5f4SPaul Zimmerman * ULPI phy_type, this parameter indicates the data width 322197ba5f4SPaul Zimmerman * between the MAC and the ULPI Wrapper.) Also, this 323197ba5f4SPaul Zimmerman * parameter is applicable only if the OTG_HSPHY_WIDTH cC 324197ba5f4SPaul Zimmerman * parameter was set to "8 and 16 bits", meaning that the 325197ba5f4SPaul Zimmerman * core has been configured to work at either data path 326197ba5f4SPaul Zimmerman * width. 327197ba5f4SPaul Zimmerman * 8 or 16 (default 16 if available) 328197ba5f4SPaul Zimmerman * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 329197ba5f4SPaul Zimmerman * data rate. This parameter is only applicable if phy_type 330197ba5f4SPaul Zimmerman * is ULPI. 331197ba5f4SPaul Zimmerman * 0 - single data rate ULPI interface with 8 bit wide 332197ba5f4SPaul Zimmerman * data bus (default) 333197ba5f4SPaul Zimmerman * 1 - double data rate ULPI interface with 4 bit wide 334197ba5f4SPaul Zimmerman * data bus 335197ba5f4SPaul Zimmerman * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 336197ba5f4SPaul Zimmerman * external supply to drive the VBus 337197ba5f4SPaul Zimmerman * 0 - Internal supply (default) 338197ba5f4SPaul Zimmerman * 1 - External supply 339197ba5f4SPaul Zimmerman * @i2c_enable: Specifies whether to use the I2Cinterface for a full 340197ba5f4SPaul Zimmerman * speed PHY. This parameter is only applicable if phy_type 341197ba5f4SPaul Zimmerman * is FS. 342197ba5f4SPaul Zimmerman * 0 - No (default) 343197ba5f4SPaul Zimmerman * 1 - Yes 344197ba5f4SPaul Zimmerman * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 345197ba5f4SPaul Zimmerman * 0 - No (default) 346197ba5f4SPaul Zimmerman * 1 - Yes 347197ba5f4SPaul Zimmerman * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 348197ba5f4SPaul Zimmerman * when attached to a Full Speed or Low Speed device in 349197ba5f4SPaul Zimmerman * host mode. 350197ba5f4SPaul Zimmerman * 0 - Don't support low power mode (default) 351197ba5f4SPaul Zimmerman * 1 - Support low power mode 352197ba5f4SPaul Zimmerman * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 353197ba5f4SPaul Zimmerman * when connected to a Low Speed device in host 354197ba5f4SPaul Zimmerman * mode. This parameter is applicable only if 355197ba5f4SPaul Zimmerman * host_support_fs_ls_low_power is enabled. 356197ba5f4SPaul Zimmerman * 0 - 48 MHz 357197ba5f4SPaul Zimmerman * (default when phy_type is UTMI+ or ULPI) 358197ba5f4SPaul Zimmerman * 1 - 6 MHz 359197ba5f4SPaul Zimmerman * (default when phy_type is Full Speed) 360197ba5f4SPaul Zimmerman * @ts_dline: Enable Term Select Dline pulsing 361197ba5f4SPaul Zimmerman * 0 - No (default) 362197ba5f4SPaul Zimmerman * 1 - Yes 363197ba5f4SPaul Zimmerman * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 364197ba5f4SPaul Zimmerman * 0 - No (default for core < 2.92a) 365197ba5f4SPaul Zimmerman * 1 - Yes (default for core >= 2.92a) 366197ba5f4SPaul Zimmerman * @ahbcfg: This field allows the default value of the GAHBCFG 367197ba5f4SPaul Zimmerman * register to be overridden 368197ba5f4SPaul Zimmerman * -1 - GAHBCFG value will be set to 0x06 369197ba5f4SPaul Zimmerman * (INCR4, default) 370197ba5f4SPaul Zimmerman * all others - GAHBCFG value will be overridden with 371197ba5f4SPaul Zimmerman * this value 372197ba5f4SPaul Zimmerman * Not all bits can be controlled like this, the 373197ba5f4SPaul Zimmerman * bits defined by GAHBCFG_CTRL_MASK are controlled 374197ba5f4SPaul Zimmerman * by the driver and are ignored in this 375197ba5f4SPaul Zimmerman * configuration value. 376197ba5f4SPaul Zimmerman * @uframe_sched: True to enable the microframe scheduler 377197ba5f4SPaul Zimmerman * 378197ba5f4SPaul Zimmerman * The following parameters may be specified when starting the module. These 379197ba5f4SPaul Zimmerman * parameters define how the DWC_otg controller should be configured. A 380197ba5f4SPaul Zimmerman * value of -1 (or any other out of range value) for any parameter means 381197ba5f4SPaul Zimmerman * to read the value from hardware (if possible) or use the builtin 382197ba5f4SPaul Zimmerman * default described above. 383197ba5f4SPaul Zimmerman */ 384197ba5f4SPaul Zimmerman struct dwc2_core_params { 385197ba5f4SPaul Zimmerman /* 386197ba5f4SPaul Zimmerman * Don't add any non-int members here, this will break 387197ba5f4SPaul Zimmerman * dwc2_set_all_params! 388197ba5f4SPaul Zimmerman */ 389197ba5f4SPaul Zimmerman int otg_cap; 390197ba5f4SPaul Zimmerman int otg_ver; 391197ba5f4SPaul Zimmerman int dma_enable; 392197ba5f4SPaul Zimmerman int dma_desc_enable; 393197ba5f4SPaul Zimmerman int speed; 394197ba5f4SPaul Zimmerman int enable_dynamic_fifo; 395197ba5f4SPaul Zimmerman int en_multiple_tx_fifo; 396197ba5f4SPaul Zimmerman int host_rx_fifo_size; 397197ba5f4SPaul Zimmerman int host_nperio_tx_fifo_size; 398197ba5f4SPaul Zimmerman int host_perio_tx_fifo_size; 399197ba5f4SPaul Zimmerman int max_transfer_size; 400197ba5f4SPaul Zimmerman int max_packet_count; 401197ba5f4SPaul Zimmerman int host_channels; 402197ba5f4SPaul Zimmerman int phy_type; 403197ba5f4SPaul Zimmerman int phy_utmi_width; 404197ba5f4SPaul Zimmerman int phy_ulpi_ddr; 405197ba5f4SPaul Zimmerman int phy_ulpi_ext_vbus; 406197ba5f4SPaul Zimmerman int i2c_enable; 407197ba5f4SPaul Zimmerman int ulpi_fs_ls; 408197ba5f4SPaul Zimmerman int host_support_fs_ls_low_power; 409197ba5f4SPaul Zimmerman int host_ls_low_power_phy_clk; 410197ba5f4SPaul Zimmerman int ts_dline; 411197ba5f4SPaul Zimmerman int reload_ctl; 412197ba5f4SPaul Zimmerman int ahbcfg; 413197ba5f4SPaul Zimmerman int uframe_sched; 414197ba5f4SPaul Zimmerman }; 415197ba5f4SPaul Zimmerman 416197ba5f4SPaul Zimmerman /** 417197ba5f4SPaul Zimmerman * struct dwc2_hw_params - Autodetected parameters. 418197ba5f4SPaul Zimmerman * 419197ba5f4SPaul Zimmerman * These parameters are the various parameters read from hardware 420197ba5f4SPaul Zimmerman * registers during initialization. They typically contain the best 421197ba5f4SPaul Zimmerman * supported or maximum value that can be configured in the 422197ba5f4SPaul Zimmerman * corresponding dwc2_core_params value. 423197ba5f4SPaul Zimmerman * 424197ba5f4SPaul Zimmerman * The values that are not in dwc2_core_params are documented below. 425197ba5f4SPaul Zimmerman * 426197ba5f4SPaul Zimmerman * @op_mode Mode of Operation 427197ba5f4SPaul Zimmerman * 0 - HNP- and SRP-Capable OTG (Host & Device) 428197ba5f4SPaul Zimmerman * 1 - SRP-Capable OTG (Host & Device) 429197ba5f4SPaul Zimmerman * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 430197ba5f4SPaul Zimmerman * 3 - SRP-Capable Device 431197ba5f4SPaul Zimmerman * 4 - Non-OTG Device 432197ba5f4SPaul Zimmerman * 5 - SRP-Capable Host 433197ba5f4SPaul Zimmerman * 6 - Non-OTG Host 434197ba5f4SPaul Zimmerman * @arch Architecture 435197ba5f4SPaul Zimmerman * 0 - Slave only 436197ba5f4SPaul Zimmerman * 1 - External DMA 437197ba5f4SPaul Zimmerman * 2 - Internal DMA 438197ba5f4SPaul Zimmerman * @power_optimized Are power optimizations enabled? 439197ba5f4SPaul Zimmerman * @num_dev_ep Number of device endpoints available 440197ba5f4SPaul Zimmerman * @num_dev_perio_in_ep Number of device periodic IN endpoints 441197ba5f4SPaul Zimmerman * avaialable 442197ba5f4SPaul Zimmerman * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue 443197ba5f4SPaul Zimmerman * Depth 444197ba5f4SPaul Zimmerman * 0 to 30 445197ba5f4SPaul Zimmerman * @host_perio_tx_q_depth 446197ba5f4SPaul Zimmerman * Host Mode Periodic Request Queue Depth 447197ba5f4SPaul Zimmerman * 2, 4 or 8 448197ba5f4SPaul Zimmerman * @nperio_tx_q_depth 449197ba5f4SPaul Zimmerman * Non-Periodic Request Queue Depth 450197ba5f4SPaul Zimmerman * 2, 4 or 8 451197ba5f4SPaul Zimmerman * @hs_phy_type High-speed PHY interface type 452197ba5f4SPaul Zimmerman * 0 - High-speed interface not supported 453197ba5f4SPaul Zimmerman * 1 - UTMI+ 454197ba5f4SPaul Zimmerman * 2 - ULPI 455197ba5f4SPaul Zimmerman * 3 - UTMI+ and ULPI 456197ba5f4SPaul Zimmerman * @fs_phy_type Full-speed PHY interface type 457197ba5f4SPaul Zimmerman * 0 - Full speed interface not supported 458197ba5f4SPaul Zimmerman * 1 - Dedicated full speed interface 459197ba5f4SPaul Zimmerman * 2 - FS pins shared with UTMI+ pins 460197ba5f4SPaul Zimmerman * 3 - FS pins shared with ULPI pins 461197ba5f4SPaul Zimmerman * @total_fifo_size: Total internal RAM for FIFOs (bytes) 462197ba5f4SPaul Zimmerman * @utmi_phy_data_width UTMI+ PHY data width 463197ba5f4SPaul Zimmerman * 0 - 8 bits 464197ba5f4SPaul Zimmerman * 1 - 16 bits 465197ba5f4SPaul Zimmerman * 2 - 8 or 16 bits 466197ba5f4SPaul Zimmerman * @snpsid: Value from SNPSID register 467197ba5f4SPaul Zimmerman */ 468197ba5f4SPaul Zimmerman struct dwc2_hw_params { 469197ba5f4SPaul Zimmerman unsigned op_mode:3; 470197ba5f4SPaul Zimmerman unsigned arch:2; 471197ba5f4SPaul Zimmerman unsigned dma_desc_enable:1; 472197ba5f4SPaul Zimmerman unsigned enable_dynamic_fifo:1; 473197ba5f4SPaul Zimmerman unsigned en_multiple_tx_fifo:1; 474197ba5f4SPaul Zimmerman unsigned host_rx_fifo_size:16; 475197ba5f4SPaul Zimmerman unsigned host_nperio_tx_fifo_size:16; 476197ba5f4SPaul Zimmerman unsigned host_perio_tx_fifo_size:16; 477197ba5f4SPaul Zimmerman unsigned nperio_tx_q_depth:3; 478197ba5f4SPaul Zimmerman unsigned host_perio_tx_q_depth:3; 479197ba5f4SPaul Zimmerman unsigned dev_token_q_depth:5; 480197ba5f4SPaul Zimmerman unsigned max_transfer_size:26; 481197ba5f4SPaul Zimmerman unsigned max_packet_count:11; 482197ba5f4SPaul Zimmerman unsigned host_channels:5; 483197ba5f4SPaul Zimmerman unsigned hs_phy_type:2; 484197ba5f4SPaul Zimmerman unsigned fs_phy_type:2; 485197ba5f4SPaul Zimmerman unsigned i2c_enable:1; 486197ba5f4SPaul Zimmerman unsigned num_dev_ep:4; 487197ba5f4SPaul Zimmerman unsigned num_dev_perio_in_ep:4; 488197ba5f4SPaul Zimmerman unsigned total_fifo_size:16; 489197ba5f4SPaul Zimmerman unsigned power_optimized:1; 490197ba5f4SPaul Zimmerman unsigned utmi_phy_data_width:2; 491197ba5f4SPaul Zimmerman u32 snpsid; 492197ba5f4SPaul Zimmerman }; 493197ba5f4SPaul Zimmerman 494197ba5f4SPaul Zimmerman /** 495197ba5f4SPaul Zimmerman * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 496197ba5f4SPaul Zimmerman * and periodic schedules 497197ba5f4SPaul Zimmerman * 498197ba5f4SPaul Zimmerman * @dev: The struct device pointer 499197ba5f4SPaul Zimmerman * @regs: Pointer to controller regs 500197ba5f4SPaul Zimmerman * @core_params: Parameters that define how the core should be configured 501197ba5f4SPaul Zimmerman * @hw_params: Parameters that were autodetected from the 502197ba5f4SPaul Zimmerman * hardware registers 503197ba5f4SPaul Zimmerman * @op_state: The operational State, during transitions (a_host=> 504197ba5f4SPaul Zimmerman * a_peripheral and b_device=>b_host) this may not match 505197ba5f4SPaul Zimmerman * the core, but allows the software to determine 506197ba5f4SPaul Zimmerman * transitions 507c0155b9dSKever Yang * @dr_mode: Requested mode of operation, one of following: 508c0155b9dSKever Yang * - USB_DR_MODE_PERIPHERAL 509c0155b9dSKever Yang * - USB_DR_MODE_HOST 510c0155b9dSKever Yang * - USB_DR_MODE_OTG 511197ba5f4SPaul Zimmerman * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 512197ba5f4SPaul Zimmerman * transfer are in process of being queued 513197ba5f4SPaul Zimmerman * @srp_success: Stores status of SRP request in the case of a FS PHY 514197ba5f4SPaul Zimmerman * with an I2C interface 515197ba5f4SPaul Zimmerman * @wq_otg: Workqueue object used for handling of some interrupts 516197ba5f4SPaul Zimmerman * @wf_otg: Work object for handling Connector ID Status Change 517197ba5f4SPaul Zimmerman * interrupt 518197ba5f4SPaul Zimmerman * @wkp_timer: Timer object for handling Wakeup Detected interrupt 519197ba5f4SPaul Zimmerman * @lx_state: Lx state of connected device 520197ba5f4SPaul Zimmerman * @flags: Flags for handling root port state changes 521197ba5f4SPaul Zimmerman * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 522197ba5f4SPaul Zimmerman * Transfers associated with these QHs are not currently 523197ba5f4SPaul Zimmerman * assigned to a host channel. 524197ba5f4SPaul Zimmerman * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 525197ba5f4SPaul Zimmerman * Transfers associated with these QHs are currently 526197ba5f4SPaul Zimmerman * assigned to a host channel. 527197ba5f4SPaul Zimmerman * @non_periodic_qh_ptr: Pointer to next QH to process in the active 528197ba5f4SPaul Zimmerman * non-periodic schedule 529197ba5f4SPaul Zimmerman * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 530197ba5f4SPaul Zimmerman * list of QHs for periodic transfers that are _not_ 531197ba5f4SPaul Zimmerman * scheduled for the next frame. Each QH in the list has an 532197ba5f4SPaul Zimmerman * interval counter that determines when it needs to be 533197ba5f4SPaul Zimmerman * scheduled for execution. This scheduling mechanism 534197ba5f4SPaul Zimmerman * allows only a simple calculation for periodic bandwidth 535197ba5f4SPaul Zimmerman * used (i.e. must assume that all periodic transfers may 536197ba5f4SPaul Zimmerman * need to execute in the same frame). However, it greatly 537197ba5f4SPaul Zimmerman * simplifies scheduling and should be sufficient for the 538197ba5f4SPaul Zimmerman * vast majority of OTG hosts, which need to connect to a 539197ba5f4SPaul Zimmerman * small number of peripherals at one time. Items move from 540197ba5f4SPaul Zimmerman * this list to periodic_sched_ready when the QH interval 541197ba5f4SPaul Zimmerman * counter is 0 at SOF. 542197ba5f4SPaul Zimmerman * @periodic_sched_ready: List of periodic QHs that are ready for execution in 543197ba5f4SPaul Zimmerman * the next frame, but have not yet been assigned to host 544197ba5f4SPaul Zimmerman * channels. Items move from this list to 545197ba5f4SPaul Zimmerman * periodic_sched_assigned as host channels become 546197ba5f4SPaul Zimmerman * available during the current frame. 547197ba5f4SPaul Zimmerman * @periodic_sched_assigned: List of periodic QHs to be executed in the next 548197ba5f4SPaul Zimmerman * frame that are assigned to host channels. Items move 549197ba5f4SPaul Zimmerman * from this list to periodic_sched_queued as the 550197ba5f4SPaul Zimmerman * transactions for the QH are queued to the DWC_otg 551197ba5f4SPaul Zimmerman * controller. 552197ba5f4SPaul Zimmerman * @periodic_sched_queued: List of periodic QHs that have been queued for 553197ba5f4SPaul Zimmerman * execution. Items move from this list to either 554197ba5f4SPaul Zimmerman * periodic_sched_inactive or periodic_sched_ready when the 555197ba5f4SPaul Zimmerman * channel associated with the transfer is released. If the 556197ba5f4SPaul Zimmerman * interval for the QH is 1, the item moves to 557197ba5f4SPaul Zimmerman * periodic_sched_ready because it must be rescheduled for 558197ba5f4SPaul Zimmerman * the next frame. Otherwise, the item moves to 559197ba5f4SPaul Zimmerman * periodic_sched_inactive. 560197ba5f4SPaul Zimmerman * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 561197ba5f4SPaul Zimmerman * This value is in microseconds per (micro)frame. The 562197ba5f4SPaul Zimmerman * assumption is that all periodic transfers may occur in 563197ba5f4SPaul Zimmerman * the same (micro)frame. 564197ba5f4SPaul Zimmerman * @frame_usecs: Internal variable used by the microframe scheduler 565197ba5f4SPaul Zimmerman * @frame_number: Frame number read from the core at SOF. The value ranges 566197ba5f4SPaul Zimmerman * from 0 to HFNUM_MAX_FRNUM. 567197ba5f4SPaul Zimmerman * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 568197ba5f4SPaul Zimmerman * SOF enable/disable. 569197ba5f4SPaul Zimmerman * @free_hc_list: Free host channels in the controller. This is a list of 570197ba5f4SPaul Zimmerman * struct dwc2_host_chan items. 571197ba5f4SPaul Zimmerman * @periodic_channels: Number of host channels assigned to periodic transfers. 572197ba5f4SPaul Zimmerman * Currently assuming that there is a dedicated host 573197ba5f4SPaul Zimmerman * channel for each periodic transaction and at least one 574197ba5f4SPaul Zimmerman * host channel is available for non-periodic transactions. 575197ba5f4SPaul Zimmerman * @non_periodic_channels: Number of host channels assigned to non-periodic 576197ba5f4SPaul Zimmerman * transfers 577197ba5f4SPaul Zimmerman * @available_host_channels Number of host channels available for the microframe 578197ba5f4SPaul Zimmerman * scheduler to use 579197ba5f4SPaul Zimmerman * @hc_ptr_array: Array of pointers to the host channel descriptors. 580197ba5f4SPaul Zimmerman * Allows accessing a host channel descriptor given the 581197ba5f4SPaul Zimmerman * host channel number. This is useful in interrupt 582197ba5f4SPaul Zimmerman * handlers. 583197ba5f4SPaul Zimmerman * @status_buf: Buffer used for data received during the status phase of 584197ba5f4SPaul Zimmerman * a control transfer. 585197ba5f4SPaul Zimmerman * @status_buf_dma: DMA address for status_buf 586197ba5f4SPaul Zimmerman * @start_work: Delayed work for handling host A-cable connection 587197ba5f4SPaul Zimmerman * @reset_work: Delayed work for handling a port reset 588197ba5f4SPaul Zimmerman * @lock: Spinlock that protects all the driver data structures 589197ba5f4SPaul Zimmerman * @priv: Stores a pointer to the struct usb_hcd 590197ba5f4SPaul Zimmerman * @otg_port: OTG port number 591197ba5f4SPaul Zimmerman * @frame_list: Frame list 592197ba5f4SPaul Zimmerman * @frame_list_dma: Frame list DMA address 593197ba5f4SPaul Zimmerman */ 594197ba5f4SPaul Zimmerman struct dwc2_hsotg { 595197ba5f4SPaul Zimmerman struct device *dev; 596197ba5f4SPaul Zimmerman void __iomem *regs; 597197ba5f4SPaul Zimmerman /** Params detected from hardware */ 598197ba5f4SPaul Zimmerman struct dwc2_hw_params hw_params; 599197ba5f4SPaul Zimmerman /** Params to actually use */ 600197ba5f4SPaul Zimmerman struct dwc2_core_params *core_params; 601197ba5f4SPaul Zimmerman enum usb_otg_state op_state; 602c0155b9dSKever Yang enum usb_dr_mode dr_mode; 603197ba5f4SPaul Zimmerman 604197ba5f4SPaul Zimmerman unsigned int queuing_high_bandwidth:1; 605197ba5f4SPaul Zimmerman unsigned int srp_success:1; 606197ba5f4SPaul Zimmerman 607197ba5f4SPaul Zimmerman struct workqueue_struct *wq_otg; 608197ba5f4SPaul Zimmerman struct work_struct wf_otg; 609197ba5f4SPaul Zimmerman struct timer_list wkp_timer; 610197ba5f4SPaul Zimmerman enum dwc2_lx_state lx_state; 611197ba5f4SPaul Zimmerman 612197ba5f4SPaul Zimmerman union dwc2_hcd_internal_flags { 613197ba5f4SPaul Zimmerman u32 d32; 614197ba5f4SPaul Zimmerman struct { 615197ba5f4SPaul Zimmerman unsigned port_connect_status_change:1; 616197ba5f4SPaul Zimmerman unsigned port_connect_status:1; 617197ba5f4SPaul Zimmerman unsigned port_reset_change:1; 618197ba5f4SPaul Zimmerman unsigned port_enable_change:1; 619197ba5f4SPaul Zimmerman unsigned port_suspend_change:1; 620197ba5f4SPaul Zimmerman unsigned port_over_current_change:1; 621197ba5f4SPaul Zimmerman unsigned port_l1_change:1; 622197ba5f4SPaul Zimmerman unsigned reserved:26; 623197ba5f4SPaul Zimmerman } b; 624197ba5f4SPaul Zimmerman } flags; 625197ba5f4SPaul Zimmerman 626197ba5f4SPaul Zimmerman struct list_head non_periodic_sched_inactive; 627197ba5f4SPaul Zimmerman struct list_head non_periodic_sched_active; 628197ba5f4SPaul Zimmerman struct list_head *non_periodic_qh_ptr; 629197ba5f4SPaul Zimmerman struct list_head periodic_sched_inactive; 630197ba5f4SPaul Zimmerman struct list_head periodic_sched_ready; 631197ba5f4SPaul Zimmerman struct list_head periodic_sched_assigned; 632197ba5f4SPaul Zimmerman struct list_head periodic_sched_queued; 633197ba5f4SPaul Zimmerman u16 periodic_usecs; 634197ba5f4SPaul Zimmerman u16 frame_usecs[8]; 635197ba5f4SPaul Zimmerman u16 frame_number; 636197ba5f4SPaul Zimmerman u16 periodic_qh_count; 637197ba5f4SPaul Zimmerman 638197ba5f4SPaul Zimmerman #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 639197ba5f4SPaul Zimmerman #define FRAME_NUM_ARRAY_SIZE 1000 640197ba5f4SPaul Zimmerman u16 last_frame_num; 641197ba5f4SPaul Zimmerman u16 *frame_num_array; 642197ba5f4SPaul Zimmerman u16 *last_frame_num_array; 643197ba5f4SPaul Zimmerman int frame_num_idx; 644197ba5f4SPaul Zimmerman int dumped_frame_num_array; 645197ba5f4SPaul Zimmerman #endif 646197ba5f4SPaul Zimmerman 647197ba5f4SPaul Zimmerman struct list_head free_hc_list; 648197ba5f4SPaul Zimmerman int periodic_channels; 649197ba5f4SPaul Zimmerman int non_periodic_channels; 650197ba5f4SPaul Zimmerman int available_host_channels; 651197ba5f4SPaul Zimmerman struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 652197ba5f4SPaul Zimmerman u8 *status_buf; 653197ba5f4SPaul Zimmerman dma_addr_t status_buf_dma; 654197ba5f4SPaul Zimmerman #define DWC2_HCD_STATUS_BUF_SIZE 64 655197ba5f4SPaul Zimmerman 656197ba5f4SPaul Zimmerman struct delayed_work start_work; 657197ba5f4SPaul Zimmerman struct delayed_work reset_work; 658197ba5f4SPaul Zimmerman spinlock_t lock; 659197ba5f4SPaul Zimmerman void *priv; 660197ba5f4SPaul Zimmerman u8 otg_port; 661197ba5f4SPaul Zimmerman u32 *frame_list; 662197ba5f4SPaul Zimmerman dma_addr_t frame_list_dma; 663197ba5f4SPaul Zimmerman 664197ba5f4SPaul Zimmerman /* DWC OTG HW Release versions */ 665197ba5f4SPaul Zimmerman #define DWC2_CORE_REV_2_71a 0x4f54271a 666197ba5f4SPaul Zimmerman #define DWC2_CORE_REV_2_90a 0x4f54290a 667197ba5f4SPaul Zimmerman #define DWC2_CORE_REV_2_92a 0x4f54292a 668197ba5f4SPaul Zimmerman #define DWC2_CORE_REV_2_94a 0x4f54294a 669197ba5f4SPaul Zimmerman #define DWC2_CORE_REV_3_00a 0x4f54300a 670197ba5f4SPaul Zimmerman 671197ba5f4SPaul Zimmerman #ifdef DEBUG 672197ba5f4SPaul Zimmerman u32 frrem_samples; 673197ba5f4SPaul Zimmerman u64 frrem_accum; 674197ba5f4SPaul Zimmerman 675197ba5f4SPaul Zimmerman u32 hfnum_7_samples_a; 676197ba5f4SPaul Zimmerman u64 hfnum_7_frrem_accum_a; 677197ba5f4SPaul Zimmerman u32 hfnum_0_samples_a; 678197ba5f4SPaul Zimmerman u64 hfnum_0_frrem_accum_a; 679197ba5f4SPaul Zimmerman u32 hfnum_other_samples_a; 680197ba5f4SPaul Zimmerman u64 hfnum_other_frrem_accum_a; 681197ba5f4SPaul Zimmerman 682197ba5f4SPaul Zimmerman u32 hfnum_7_samples_b; 683197ba5f4SPaul Zimmerman u64 hfnum_7_frrem_accum_b; 684197ba5f4SPaul Zimmerman u32 hfnum_0_samples_b; 685197ba5f4SPaul Zimmerman u64 hfnum_0_frrem_accum_b; 686197ba5f4SPaul Zimmerman u32 hfnum_other_samples_b; 687197ba5f4SPaul Zimmerman u64 hfnum_other_frrem_accum_b; 688197ba5f4SPaul Zimmerman #endif 689197ba5f4SPaul Zimmerman }; 690197ba5f4SPaul Zimmerman 691197ba5f4SPaul Zimmerman /* Reasons for halting a host channel */ 692197ba5f4SPaul Zimmerman enum dwc2_halt_status { 693197ba5f4SPaul Zimmerman DWC2_HC_XFER_NO_HALT_STATUS, 694197ba5f4SPaul Zimmerman DWC2_HC_XFER_COMPLETE, 695197ba5f4SPaul Zimmerman DWC2_HC_XFER_URB_COMPLETE, 696197ba5f4SPaul Zimmerman DWC2_HC_XFER_ACK, 697197ba5f4SPaul Zimmerman DWC2_HC_XFER_NAK, 698197ba5f4SPaul Zimmerman DWC2_HC_XFER_NYET, 699197ba5f4SPaul Zimmerman DWC2_HC_XFER_STALL, 700197ba5f4SPaul Zimmerman DWC2_HC_XFER_XACT_ERR, 701197ba5f4SPaul Zimmerman DWC2_HC_XFER_FRAME_OVERRUN, 702197ba5f4SPaul Zimmerman DWC2_HC_XFER_BABBLE_ERR, 703197ba5f4SPaul Zimmerman DWC2_HC_XFER_DATA_TOGGLE_ERR, 704197ba5f4SPaul Zimmerman DWC2_HC_XFER_AHB_ERR, 705197ba5f4SPaul Zimmerman DWC2_HC_XFER_PERIODIC_INCOMPLETE, 706197ba5f4SPaul Zimmerman DWC2_HC_XFER_URB_DEQUEUE, 707197ba5f4SPaul Zimmerman }; 708197ba5f4SPaul Zimmerman 709197ba5f4SPaul Zimmerman /* 710197ba5f4SPaul Zimmerman * The following functions support initialization of the core driver component 711197ba5f4SPaul Zimmerman * and the DWC_otg controller 712197ba5f4SPaul Zimmerman */ 713197ba5f4SPaul Zimmerman extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg); 714197ba5f4SPaul Zimmerman 715197ba5f4SPaul Zimmerman /* 716197ba5f4SPaul Zimmerman * Host core Functions. 717197ba5f4SPaul Zimmerman * The following functions support managing the DWC_otg controller in host 718197ba5f4SPaul Zimmerman * mode. 719197ba5f4SPaul Zimmerman */ 720197ba5f4SPaul Zimmerman extern void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan); 721197ba5f4SPaul Zimmerman extern void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 722197ba5f4SPaul Zimmerman enum dwc2_halt_status halt_status); 723197ba5f4SPaul Zimmerman extern void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, 724197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan); 725197ba5f4SPaul Zimmerman extern void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 726197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan); 727197ba5f4SPaul Zimmerman extern void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 728197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan); 729197ba5f4SPaul Zimmerman extern int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 730197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan); 731197ba5f4SPaul Zimmerman extern void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, 732197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan); 733197ba5f4SPaul Zimmerman extern void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg); 734197ba5f4SPaul Zimmerman extern void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg); 735197ba5f4SPaul Zimmerman 736197ba5f4SPaul Zimmerman extern u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg); 737197ba5f4SPaul Zimmerman extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 738197ba5f4SPaul Zimmerman 739197ba5f4SPaul Zimmerman /* 740197ba5f4SPaul Zimmerman * Common core Functions. 741197ba5f4SPaul Zimmerman * The following functions support managing the DWC_otg controller in either 742197ba5f4SPaul Zimmerman * device or host mode. 743197ba5f4SPaul Zimmerman */ 744197ba5f4SPaul Zimmerman extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 745197ba5f4SPaul Zimmerman extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 746197ba5f4SPaul Zimmerman extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 747197ba5f4SPaul Zimmerman 748197ba5f4SPaul Zimmerman extern int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq); 749197ba5f4SPaul Zimmerman extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 750197ba5f4SPaul Zimmerman extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 751197ba5f4SPaul Zimmerman 752197ba5f4SPaul Zimmerman /* This function should be called on every hardware interrupt. */ 753197ba5f4SPaul Zimmerman extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 754197ba5f4SPaul Zimmerman 755197ba5f4SPaul Zimmerman /* OTG Core Parameters */ 756197ba5f4SPaul Zimmerman 757197ba5f4SPaul Zimmerman /* 758197ba5f4SPaul Zimmerman * Specifies the OTG capabilities. The driver will automatically 759197ba5f4SPaul Zimmerman * detect the value for this parameter if none is specified. 760197ba5f4SPaul Zimmerman * 0 - HNP and SRP capable (default) 761197ba5f4SPaul Zimmerman * 1 - SRP Only capable 762197ba5f4SPaul Zimmerman * 2 - No HNP/SRP capable 763197ba5f4SPaul Zimmerman */ 764197ba5f4SPaul Zimmerman extern void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val); 765197ba5f4SPaul Zimmerman #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 766197ba5f4SPaul Zimmerman #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 767197ba5f4SPaul Zimmerman #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 768197ba5f4SPaul Zimmerman 769197ba5f4SPaul Zimmerman /* 770197ba5f4SPaul Zimmerman * Specifies whether to use slave or DMA mode for accessing the data 771197ba5f4SPaul Zimmerman * FIFOs. The driver will automatically detect the value for this 772197ba5f4SPaul Zimmerman * parameter if none is specified. 773197ba5f4SPaul Zimmerman * 0 - Slave 774197ba5f4SPaul Zimmerman * 1 - DMA (default, if available) 775197ba5f4SPaul Zimmerman */ 776197ba5f4SPaul Zimmerman extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val); 777197ba5f4SPaul Zimmerman 778197ba5f4SPaul Zimmerman /* 779197ba5f4SPaul Zimmerman * When DMA mode is enabled specifies whether to use 780197ba5f4SPaul Zimmerman * address DMA or DMA Descritor mode for accessing the data 781197ba5f4SPaul Zimmerman * FIFOs in device mode. The driver will automatically detect 782197ba5f4SPaul Zimmerman * the value for this parameter if none is specified. 783197ba5f4SPaul Zimmerman * 0 - address DMA 784197ba5f4SPaul Zimmerman * 1 - DMA Descriptor(default, if available) 785197ba5f4SPaul Zimmerman */ 786197ba5f4SPaul Zimmerman extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val); 787197ba5f4SPaul Zimmerman 788197ba5f4SPaul Zimmerman /* 789197ba5f4SPaul Zimmerman * Specifies the maximum speed of operation in host and device mode. 790197ba5f4SPaul Zimmerman * The actual speed depends on the speed of the attached device and 791197ba5f4SPaul Zimmerman * the value of phy_type. The actual speed depends on the speed of the 792197ba5f4SPaul Zimmerman * attached device. 793197ba5f4SPaul Zimmerman * 0 - High Speed (default) 794197ba5f4SPaul Zimmerman * 1 - Full Speed 795197ba5f4SPaul Zimmerman */ 796197ba5f4SPaul Zimmerman extern void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val); 797197ba5f4SPaul Zimmerman #define DWC2_SPEED_PARAM_HIGH 0 798197ba5f4SPaul Zimmerman #define DWC2_SPEED_PARAM_FULL 1 799197ba5f4SPaul Zimmerman 800197ba5f4SPaul Zimmerman /* 801197ba5f4SPaul Zimmerman * Specifies whether low power mode is supported when attached 802197ba5f4SPaul Zimmerman * to a Full Speed or Low Speed device in host mode. 803197ba5f4SPaul Zimmerman * 804197ba5f4SPaul Zimmerman * 0 - Don't support low power mode (default) 805197ba5f4SPaul Zimmerman * 1 - Support low power mode 806197ba5f4SPaul Zimmerman */ 807197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_support_fs_ls_low_power( 808197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg, int val); 809197ba5f4SPaul Zimmerman 810197ba5f4SPaul Zimmerman /* 811197ba5f4SPaul Zimmerman * Specifies the PHY clock rate in low power mode when connected to a 812197ba5f4SPaul Zimmerman * Low Speed device in host mode. This parameter is applicable only if 813197ba5f4SPaul Zimmerman * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS 814197ba5f4SPaul Zimmerman * then defaults to 6 MHZ otherwise 48 MHZ. 815197ba5f4SPaul Zimmerman * 816197ba5f4SPaul Zimmerman * 0 - 48 MHz 817197ba5f4SPaul Zimmerman * 1 - 6 MHz 818197ba5f4SPaul Zimmerman */ 819197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, 820197ba5f4SPaul Zimmerman int val); 821197ba5f4SPaul Zimmerman #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 822197ba5f4SPaul Zimmerman #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 823197ba5f4SPaul Zimmerman 824197ba5f4SPaul Zimmerman /* 825197ba5f4SPaul Zimmerman * 0 - Use cC FIFO size parameters 826197ba5f4SPaul Zimmerman * 1 - Allow dynamic FIFO sizing (default) 827197ba5f4SPaul Zimmerman */ 828197ba5f4SPaul Zimmerman extern void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, 829197ba5f4SPaul Zimmerman int val); 830197ba5f4SPaul Zimmerman 831197ba5f4SPaul Zimmerman /* 832197ba5f4SPaul Zimmerman * Number of 4-byte words in the Rx FIFO in host mode when dynamic 833197ba5f4SPaul Zimmerman * FIFO sizing is enabled. 834197ba5f4SPaul Zimmerman * 16 to 32768 (default 1024) 835197ba5f4SPaul Zimmerman */ 836197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val); 837197ba5f4SPaul Zimmerman 838197ba5f4SPaul Zimmerman /* 839197ba5f4SPaul Zimmerman * Number of 4-byte words in the non-periodic Tx FIFO in host mode 840197ba5f4SPaul Zimmerman * when Dynamic FIFO sizing is enabled in the core. 841197ba5f4SPaul Zimmerman * 16 to 32768 (default 256) 842197ba5f4SPaul Zimmerman */ 843197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, 844197ba5f4SPaul Zimmerman int val); 845197ba5f4SPaul Zimmerman 846197ba5f4SPaul Zimmerman /* 847197ba5f4SPaul Zimmerman * Number of 4-byte words in the host periodic Tx FIFO when dynamic 848197ba5f4SPaul Zimmerman * FIFO sizing is enabled. 849197ba5f4SPaul Zimmerman * 16 to 32768 (default 256) 850197ba5f4SPaul Zimmerman */ 851197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, 852197ba5f4SPaul Zimmerman int val); 853197ba5f4SPaul Zimmerman 854197ba5f4SPaul Zimmerman /* 855197ba5f4SPaul Zimmerman * The maximum transfer size supported in bytes. 856197ba5f4SPaul Zimmerman * 2047 to 65,535 (default 65,535) 857197ba5f4SPaul Zimmerman */ 858197ba5f4SPaul Zimmerman extern void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val); 859197ba5f4SPaul Zimmerman 860197ba5f4SPaul Zimmerman /* 861197ba5f4SPaul Zimmerman * The maximum number of packets in a transfer. 862197ba5f4SPaul Zimmerman * 15 to 511 (default 511) 863197ba5f4SPaul Zimmerman */ 864197ba5f4SPaul Zimmerman extern void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val); 865197ba5f4SPaul Zimmerman 866197ba5f4SPaul Zimmerman /* 867197ba5f4SPaul Zimmerman * The number of host channel registers to use. 868197ba5f4SPaul Zimmerman * 1 to 16 (default 11) 869197ba5f4SPaul Zimmerman * Note: The FPGA configuration supports a maximum of 11 host channels. 870197ba5f4SPaul Zimmerman */ 871197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val); 872197ba5f4SPaul Zimmerman 873197ba5f4SPaul Zimmerman /* 874197ba5f4SPaul Zimmerman * Specifies the type of PHY interface to use. By default, the driver 875197ba5f4SPaul Zimmerman * will automatically detect the phy_type. 876197ba5f4SPaul Zimmerman * 877197ba5f4SPaul Zimmerman * 0 - Full Speed PHY 878197ba5f4SPaul Zimmerman * 1 - UTMI+ (default) 879197ba5f4SPaul Zimmerman * 2 - ULPI 880197ba5f4SPaul Zimmerman */ 881197ba5f4SPaul Zimmerman extern void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val); 882197ba5f4SPaul Zimmerman #define DWC2_PHY_TYPE_PARAM_FS 0 883197ba5f4SPaul Zimmerman #define DWC2_PHY_TYPE_PARAM_UTMI 1 884197ba5f4SPaul Zimmerman #define DWC2_PHY_TYPE_PARAM_ULPI 2 885197ba5f4SPaul Zimmerman 886197ba5f4SPaul Zimmerman /* 887197ba5f4SPaul Zimmerman * Specifies the UTMI+ Data Width. This parameter is 888197ba5f4SPaul Zimmerman * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI 889197ba5f4SPaul Zimmerman * PHY_TYPE, this parameter indicates the data width between 890197ba5f4SPaul Zimmerman * the MAC and the ULPI Wrapper.) Also, this parameter is 891197ba5f4SPaul Zimmerman * applicable only if the OTG_HSPHY_WIDTH cC parameter was set 892197ba5f4SPaul Zimmerman * to "8 and 16 bits", meaning that the core has been 893197ba5f4SPaul Zimmerman * configured to work at either data path width. 894197ba5f4SPaul Zimmerman * 895197ba5f4SPaul Zimmerman * 8 or 16 bits (default 16) 896197ba5f4SPaul Zimmerman */ 897197ba5f4SPaul Zimmerman extern void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val); 898197ba5f4SPaul Zimmerman 899197ba5f4SPaul Zimmerman /* 900197ba5f4SPaul Zimmerman * Specifies whether the ULPI operates at double or single 901197ba5f4SPaul Zimmerman * data rate. This parameter is only applicable if PHY_TYPE is 902197ba5f4SPaul Zimmerman * ULPI. 903197ba5f4SPaul Zimmerman * 904197ba5f4SPaul Zimmerman * 0 - single data rate ULPI interface with 8 bit wide data 905197ba5f4SPaul Zimmerman * bus (default) 906197ba5f4SPaul Zimmerman * 1 - double data rate ULPI interface with 4 bit wide data 907197ba5f4SPaul Zimmerman * bus 908197ba5f4SPaul Zimmerman */ 909197ba5f4SPaul Zimmerman extern void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val); 910197ba5f4SPaul Zimmerman 911197ba5f4SPaul Zimmerman /* 912197ba5f4SPaul Zimmerman * Specifies whether to use the internal or external supply to 913197ba5f4SPaul Zimmerman * drive the vbus with a ULPI phy. 914197ba5f4SPaul Zimmerman */ 915197ba5f4SPaul Zimmerman extern void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val); 916197ba5f4SPaul Zimmerman #define DWC2_PHY_ULPI_INTERNAL_VBUS 0 917197ba5f4SPaul Zimmerman #define DWC2_PHY_ULPI_EXTERNAL_VBUS 1 918197ba5f4SPaul Zimmerman 919197ba5f4SPaul Zimmerman /* 920197ba5f4SPaul Zimmerman * Specifies whether to use the I2Cinterface for full speed PHY. This 921197ba5f4SPaul Zimmerman * parameter is only applicable if PHY_TYPE is FS. 922197ba5f4SPaul Zimmerman * 0 - No (default) 923197ba5f4SPaul Zimmerman * 1 - Yes 924197ba5f4SPaul Zimmerman */ 925197ba5f4SPaul Zimmerman extern void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val); 926197ba5f4SPaul Zimmerman 927197ba5f4SPaul Zimmerman extern void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val); 928197ba5f4SPaul Zimmerman 929197ba5f4SPaul Zimmerman extern void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val); 930197ba5f4SPaul Zimmerman 931197ba5f4SPaul Zimmerman /* 932197ba5f4SPaul Zimmerman * Specifies whether dedicated transmit FIFOs are 933197ba5f4SPaul Zimmerman * enabled for non periodic IN endpoints in device mode 934197ba5f4SPaul Zimmerman * 0 - No 935197ba5f4SPaul Zimmerman * 1 - Yes 936197ba5f4SPaul Zimmerman */ 937197ba5f4SPaul Zimmerman extern void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, 938197ba5f4SPaul Zimmerman int val); 939197ba5f4SPaul Zimmerman 940197ba5f4SPaul Zimmerman extern void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val); 941197ba5f4SPaul Zimmerman 942197ba5f4SPaul Zimmerman extern void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val); 943197ba5f4SPaul Zimmerman 944197ba5f4SPaul Zimmerman extern void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val); 945197ba5f4SPaul Zimmerman 946197ba5f4SPaul Zimmerman /* 947197ba5f4SPaul Zimmerman * Dump core registers and SPRAM 948197ba5f4SPaul Zimmerman */ 949197ba5f4SPaul Zimmerman extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 950197ba5f4SPaul Zimmerman extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 951197ba5f4SPaul Zimmerman extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 952197ba5f4SPaul Zimmerman 953197ba5f4SPaul Zimmerman /* 954197ba5f4SPaul Zimmerman * Return OTG version - either 1.3 or 2.0 955197ba5f4SPaul Zimmerman */ 956197ba5f4SPaul Zimmerman extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg); 957197ba5f4SPaul Zimmerman 958197ba5f4SPaul Zimmerman #endif /* __DWC2_CORE_H__ */ 959