1197ba5f4SPaul Zimmerman /* 2197ba5f4SPaul Zimmerman * core.h - DesignWare HS OTG Controller common declarations 3197ba5f4SPaul Zimmerman * 4197ba5f4SPaul Zimmerman * Copyright (C) 2004-2013 Synopsys, Inc. 5197ba5f4SPaul Zimmerman * 6197ba5f4SPaul Zimmerman * Redistribution and use in source and binary forms, with or without 7197ba5f4SPaul Zimmerman * modification, are permitted provided that the following conditions 8197ba5f4SPaul Zimmerman * are met: 9197ba5f4SPaul Zimmerman * 1. Redistributions of source code must retain the above copyright 10197ba5f4SPaul Zimmerman * notice, this list of conditions, and the following disclaimer, 11197ba5f4SPaul Zimmerman * without modification. 12197ba5f4SPaul Zimmerman * 2. Redistributions in binary form must reproduce the above copyright 13197ba5f4SPaul Zimmerman * notice, this list of conditions and the following disclaimer in the 14197ba5f4SPaul Zimmerman * documentation and/or other materials provided with the distribution. 15197ba5f4SPaul Zimmerman * 3. The names of the above-listed copyright holders may not be used 16197ba5f4SPaul Zimmerman * to endorse or promote products derived from this software without 17197ba5f4SPaul Zimmerman * specific prior written permission. 18197ba5f4SPaul Zimmerman * 19197ba5f4SPaul Zimmerman * ALTERNATIVELY, this software may be distributed under the terms of the 20197ba5f4SPaul Zimmerman * GNU General Public License ("GPL") as published by the Free Software 21197ba5f4SPaul Zimmerman * Foundation; either version 2 of the License, or (at your option) any 22197ba5f4SPaul Zimmerman * later version. 23197ba5f4SPaul Zimmerman * 24197ba5f4SPaul Zimmerman * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25197ba5f4SPaul Zimmerman * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26197ba5f4SPaul Zimmerman * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27197ba5f4SPaul Zimmerman * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28197ba5f4SPaul Zimmerman * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29197ba5f4SPaul Zimmerman * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30197ba5f4SPaul Zimmerman * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31197ba5f4SPaul Zimmerman * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32197ba5f4SPaul Zimmerman * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33197ba5f4SPaul Zimmerman * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34197ba5f4SPaul Zimmerman * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35197ba5f4SPaul Zimmerman */ 36197ba5f4SPaul Zimmerman 37197ba5f4SPaul Zimmerman #ifndef __DWC2_CORE_H__ 38197ba5f4SPaul Zimmerman #define __DWC2_CORE_H__ 39197ba5f4SPaul Zimmerman 40f7c0b143SDinh Nguyen #include <linux/phy/phy.h> 41f7c0b143SDinh Nguyen #include <linux/regulator/consumer.h> 42f7c0b143SDinh Nguyen #include <linux/usb/gadget.h> 43f7c0b143SDinh Nguyen #include <linux/usb/otg.h> 44197ba5f4SPaul Zimmerman #include <linux/usb/phy.h> 45197ba5f4SPaul Zimmerman #include "hw.h" 46197ba5f4SPaul Zimmerman 4795c8bc36SAntti Seppälä static inline u32 dwc2_readl(const void __iomem *addr) 48197ba5f4SPaul Zimmerman { 4995c8bc36SAntti Seppälä u32 value = __raw_readl(addr); 5095c8bc36SAntti Seppälä 5195c8bc36SAntti Seppälä /* In order to preserve endianness __raw_* operation is used. Therefore 5295c8bc36SAntti Seppälä * a barrier is needed to ensure IO access is not re-ordered across 5395c8bc36SAntti Seppälä * reads or writes 5495c8bc36SAntti Seppälä */ 5595c8bc36SAntti Seppälä mb(); 5695c8bc36SAntti Seppälä return value; 57197ba5f4SPaul Zimmerman } 58197ba5f4SPaul Zimmerman 5995c8bc36SAntti Seppälä static inline void dwc2_writel(u32 value, void __iomem *addr) 6095c8bc36SAntti Seppälä { 6195c8bc36SAntti Seppälä __raw_writel(value, addr); 6295c8bc36SAntti Seppälä 6395c8bc36SAntti Seppälä /* 6495c8bc36SAntti Seppälä * In order to preserve endianness __raw_* operation is used. Therefore 6595c8bc36SAntti Seppälä * a barrier is needed to ensure IO access is not re-ordered across 6695c8bc36SAntti Seppälä * reads or writes 6795c8bc36SAntti Seppälä */ 6895c8bc36SAntti Seppälä mb(); 6995c8bc36SAntti Seppälä #ifdef DWC2_LOG_WRITES 7095c8bc36SAntti Seppälä pr_info("INFO:: wrote %08x to %p\n", value, addr); 71197ba5f4SPaul Zimmerman #endif 7295c8bc36SAntti Seppälä } 73197ba5f4SPaul Zimmerman 74197ba5f4SPaul Zimmerman /* Maximum number of Endpoints/HostChannels */ 75197ba5f4SPaul Zimmerman #define MAX_EPS_CHANNELS 16 76197ba5f4SPaul Zimmerman 771f91b4ccSFelipe Balbi /* dwc2-hsotg declarations */ 781f91b4ccSFelipe Balbi static const char * const dwc2_hsotg_supply_names[] = { 79f7c0b143SDinh Nguyen "vusb_d", /* digital USB supply, 1.2V */ 80f7c0b143SDinh Nguyen "vusb_a", /* analog USB supply, 1.1V */ 81f7c0b143SDinh Nguyen }; 82f7c0b143SDinh Nguyen 83f7c0b143SDinh Nguyen /* 84f7c0b143SDinh Nguyen * EP0_MPS_LIMIT 85f7c0b143SDinh Nguyen * 86f7c0b143SDinh Nguyen * Unfortunately there seems to be a limit of the amount of data that can 87f7c0b143SDinh Nguyen * be transferred by IN transactions on EP0. This is either 127 bytes or 3 88f7c0b143SDinh Nguyen * packets (which practically means 1 packet and 63 bytes of data) when the 89f7c0b143SDinh Nguyen * MPS is set to 64. 90f7c0b143SDinh Nguyen * 91f7c0b143SDinh Nguyen * This means if we are wanting to move >127 bytes of data, we need to 92f7c0b143SDinh Nguyen * split the transactions up, but just doing one packet at a time does 93f7c0b143SDinh Nguyen * not work (this may be an implicit DATA0 PID on first packet of the 94f7c0b143SDinh Nguyen * transaction) and doing 2 packets is outside the controller's limits. 95f7c0b143SDinh Nguyen * 96f7c0b143SDinh Nguyen * If we try to lower the MPS size for EP0, then no transfers work properly 97f7c0b143SDinh Nguyen * for EP0, and the system will fail basic enumeration. As no cause for this 98f7c0b143SDinh Nguyen * has currently been found, we cannot support any large IN transfers for 99f7c0b143SDinh Nguyen * EP0. 100f7c0b143SDinh Nguyen */ 101f7c0b143SDinh Nguyen #define EP0_MPS_LIMIT 64 102f7c0b143SDinh Nguyen 103941fcce4SDinh Nguyen struct dwc2_hsotg; 1041f91b4ccSFelipe Balbi struct dwc2_hsotg_req; 105f7c0b143SDinh Nguyen 106f7c0b143SDinh Nguyen /** 1071f91b4ccSFelipe Balbi * struct dwc2_hsotg_ep - driver endpoint definition. 108f7c0b143SDinh Nguyen * @ep: The gadget layer representation of the endpoint. 109f7c0b143SDinh Nguyen * @name: The driver generated name for the endpoint. 110f7c0b143SDinh Nguyen * @queue: Queue of requests for this endpoint. 111f7c0b143SDinh Nguyen * @parent: Reference back to the parent device structure. 112f7c0b143SDinh Nguyen * @req: The current request that the endpoint is processing. This is 113f7c0b143SDinh Nguyen * used to indicate an request has been loaded onto the endpoint 114f7c0b143SDinh Nguyen * and has yet to be completed (maybe due to data move, or simply 115f7c0b143SDinh Nguyen * awaiting an ack from the core all the data has been completed). 116f7c0b143SDinh Nguyen * @debugfs: File entry for debugfs file for this endpoint. 117f7c0b143SDinh Nguyen * @lock: State lock to protect contents of endpoint. 118f7c0b143SDinh Nguyen * @dir_in: Set to true if this endpoint is of the IN direction, which 119f7c0b143SDinh Nguyen * means that it is sending data to the Host. 120f7c0b143SDinh Nguyen * @index: The index for the endpoint registers. 121f7c0b143SDinh Nguyen * @mc: Multi Count - number of transactions per microframe 122f7c0b143SDinh Nguyen * @interval - Interval for periodic endpoints 123f7c0b143SDinh Nguyen * @name: The name array passed to the USB core. 124f7c0b143SDinh Nguyen * @halted: Set if the endpoint has been halted. 125f7c0b143SDinh Nguyen * @periodic: Set if this is a periodic ep, such as Interrupt 126f7c0b143SDinh Nguyen * @isochronous: Set if this is a isochronous ep 1278a20fa45SMian Yousaf Kaukab * @send_zlp: Set if we need to send a zero-length packet. 128f7c0b143SDinh Nguyen * @total_data: The total number of data bytes done. 129f7c0b143SDinh Nguyen * @fifo_size: The size of the FIFO (for periodic IN endpoints) 130f7c0b143SDinh Nguyen * @fifo_load: The amount of data loaded into the FIFO (periodic IN) 131f7c0b143SDinh Nguyen * @last_load: The offset of data for the last start of request. 132f7c0b143SDinh Nguyen * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN 133f7c0b143SDinh Nguyen * 134f7c0b143SDinh Nguyen * This is the driver's state for each registered enpoint, allowing it 135f7c0b143SDinh Nguyen * to keep track of transactions that need doing. Each endpoint has a 136f7c0b143SDinh Nguyen * lock to protect the state, to try and avoid using an overall lock 137f7c0b143SDinh Nguyen * for the host controller as much as possible. 138f7c0b143SDinh Nguyen * 139f7c0b143SDinh Nguyen * For periodic IN endpoints, we have fifo_size and fifo_load to try 140f7c0b143SDinh Nguyen * and keep track of the amount of data in the periodic FIFO for each 141f7c0b143SDinh Nguyen * of these as we don't have a status register that tells us how much 142f7c0b143SDinh Nguyen * is in each of them. (note, this may actually be useless information 143f7c0b143SDinh Nguyen * as in shared-fifo mode periodic in acts like a single-frame packet 144f7c0b143SDinh Nguyen * buffer than a fifo) 145f7c0b143SDinh Nguyen */ 1461f91b4ccSFelipe Balbi struct dwc2_hsotg_ep { 147f7c0b143SDinh Nguyen struct usb_ep ep; 148f7c0b143SDinh Nguyen struct list_head queue; 149941fcce4SDinh Nguyen struct dwc2_hsotg *parent; 1501f91b4ccSFelipe Balbi struct dwc2_hsotg_req *req; 151f7c0b143SDinh Nguyen struct dentry *debugfs; 152f7c0b143SDinh Nguyen 153f7c0b143SDinh Nguyen unsigned long total_data; 154f7c0b143SDinh Nguyen unsigned int size_loaded; 155f7c0b143SDinh Nguyen unsigned int last_load; 156f7c0b143SDinh Nguyen unsigned int fifo_load; 157f7c0b143SDinh Nguyen unsigned short fifo_size; 158b203d0a2SRobert Baldyga unsigned short fifo_index; 159f7c0b143SDinh Nguyen 160f7c0b143SDinh Nguyen unsigned char dir_in; 161f7c0b143SDinh Nguyen unsigned char index; 162f7c0b143SDinh Nguyen unsigned char mc; 163f7c0b143SDinh Nguyen unsigned char interval; 164f7c0b143SDinh Nguyen 165f7c0b143SDinh Nguyen unsigned int halted:1; 166f7c0b143SDinh Nguyen unsigned int periodic:1; 167f7c0b143SDinh Nguyen unsigned int isochronous:1; 1688a20fa45SMian Yousaf Kaukab unsigned int send_zlp:1; 169f7c0b143SDinh Nguyen 170f7c0b143SDinh Nguyen char name[10]; 171f7c0b143SDinh Nguyen }; 172f7c0b143SDinh Nguyen 173f7c0b143SDinh Nguyen /** 1741f91b4ccSFelipe Balbi * struct dwc2_hsotg_req - data transfer request 175f7c0b143SDinh Nguyen * @req: The USB gadget request 176f7c0b143SDinh Nguyen * @queue: The list of requests for the endpoint this is queued for. 1777d24c1b5SMian Yousaf Kaukab * @saved_req_buf: variable to save req.buf when bounce buffers are used. 178f7c0b143SDinh Nguyen */ 1791f91b4ccSFelipe Balbi struct dwc2_hsotg_req { 180f7c0b143SDinh Nguyen struct usb_request req; 181f7c0b143SDinh Nguyen struct list_head queue; 1827d24c1b5SMian Yousaf Kaukab void *saved_req_buf; 183f7c0b143SDinh Nguyen }; 184f7c0b143SDinh Nguyen 185941fcce4SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 186f7c0b143SDinh Nguyen #define call_gadget(_hs, _entry) \ 187f7c0b143SDinh Nguyen do { \ 188f7c0b143SDinh Nguyen if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ 189f7c0b143SDinh Nguyen (_hs)->driver && (_hs)->driver->_entry) { \ 190f7c0b143SDinh Nguyen spin_unlock(&_hs->lock); \ 191f7c0b143SDinh Nguyen (_hs)->driver->_entry(&(_hs)->gadget); \ 192f7c0b143SDinh Nguyen spin_lock(&_hs->lock); \ 193f7c0b143SDinh Nguyen } \ 194f7c0b143SDinh Nguyen } while (0) 195941fcce4SDinh Nguyen #else 196941fcce4SDinh Nguyen #define call_gadget(_hs, _entry) do {} while (0) 197941fcce4SDinh Nguyen #endif 198f7c0b143SDinh Nguyen 199197ba5f4SPaul Zimmerman struct dwc2_hsotg; 200197ba5f4SPaul Zimmerman struct dwc2_host_chan; 201197ba5f4SPaul Zimmerman 202197ba5f4SPaul Zimmerman /* Device States */ 203197ba5f4SPaul Zimmerman enum dwc2_lx_state { 204197ba5f4SPaul Zimmerman DWC2_L0, /* On state */ 205197ba5f4SPaul Zimmerman DWC2_L1, /* LPM sleep state */ 206197ba5f4SPaul Zimmerman DWC2_L2, /* USB suspend state */ 207197ba5f4SPaul Zimmerman DWC2_L3, /* Off state */ 208197ba5f4SPaul Zimmerman }; 209197ba5f4SPaul Zimmerman 2100a176279SGregory Herrero /* 2110a176279SGregory Herrero * Gadget periodic tx fifo sizes as used by legacy driver 2120a176279SGregory Herrero * EP0 is not included 2130a176279SGregory Herrero */ 2140a176279SGregory Herrero #define DWC2_G_P_LEGACY_TX_FIFO_SIZE {256, 256, 256, 256, 768, 768, 768, \ 2150a176279SGregory Herrero 768, 0, 0, 0, 0, 0, 0, 0} 2160a176279SGregory Herrero 217fe0b94abSMian Yousaf Kaukab /* Gadget ep0 states */ 218fe0b94abSMian Yousaf Kaukab enum dwc2_ep0_state { 219fe0b94abSMian Yousaf Kaukab DWC2_EP0_SETUP, 220fe0b94abSMian Yousaf Kaukab DWC2_EP0_DATA_IN, 221fe0b94abSMian Yousaf Kaukab DWC2_EP0_DATA_OUT, 222fe0b94abSMian Yousaf Kaukab DWC2_EP0_STATUS_IN, 223fe0b94abSMian Yousaf Kaukab DWC2_EP0_STATUS_OUT, 224fe0b94abSMian Yousaf Kaukab }; 225fe0b94abSMian Yousaf Kaukab 226197ba5f4SPaul Zimmerman /** 227197ba5f4SPaul Zimmerman * struct dwc2_core_params - Parameters for configuring the core 228197ba5f4SPaul Zimmerman * 229197ba5f4SPaul Zimmerman * @otg_cap: Specifies the OTG capabilities. 230197ba5f4SPaul Zimmerman * 0 - HNP and SRP capable 231197ba5f4SPaul Zimmerman * 1 - SRP Only capable 232197ba5f4SPaul Zimmerman * 2 - No HNP/SRP capable (always available) 233197ba5f4SPaul Zimmerman * Defaults to best available option (0, 1, then 2) 234197ba5f4SPaul Zimmerman * @otg_ver: OTG version supported 235197ba5f4SPaul Zimmerman * 0 - 1.3 (default) 236197ba5f4SPaul Zimmerman * 1 - 2.0 237197ba5f4SPaul Zimmerman * @dma_enable: Specifies whether to use slave or DMA mode for accessing 238197ba5f4SPaul Zimmerman * the data FIFOs. The driver will automatically detect the 239197ba5f4SPaul Zimmerman * value for this parameter if none is specified. 240197ba5f4SPaul Zimmerman * 0 - Slave (always available) 241197ba5f4SPaul Zimmerman * 1 - DMA (default, if available) 242197ba5f4SPaul Zimmerman * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 243197ba5f4SPaul Zimmerman * address DMA mode or descriptor DMA mode for accessing 244197ba5f4SPaul Zimmerman * the data FIFOs. The driver will automatically detect the 245197ba5f4SPaul Zimmerman * value for this if none is specified. 246197ba5f4SPaul Zimmerman * 0 - Address DMA 247197ba5f4SPaul Zimmerman * 1 - Descriptor DMA (default, if available) 248197ba5f4SPaul Zimmerman * @speed: Specifies the maximum speed of operation in host and 249197ba5f4SPaul Zimmerman * device mode. The actual speed depends on the speed of 250197ba5f4SPaul Zimmerman * the attached device and the value of phy_type. 251197ba5f4SPaul Zimmerman * 0 - High Speed 252197ba5f4SPaul Zimmerman * (default when phy_type is UTMI+ or ULPI) 253197ba5f4SPaul Zimmerman * 1 - Full Speed 254197ba5f4SPaul Zimmerman * (default when phy_type is Full Speed) 255197ba5f4SPaul Zimmerman * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 256197ba5f4SPaul Zimmerman * 1 - Allow dynamic FIFO sizing (default, if available) 257197ba5f4SPaul Zimmerman * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 258197ba5f4SPaul Zimmerman * are enabled 259197ba5f4SPaul Zimmerman * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 260197ba5f4SPaul Zimmerman * dynamic FIFO sizing is enabled 261197ba5f4SPaul Zimmerman * 16 to 32768 262197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 263197ba5f4SPaul Zimmerman * the default. 264197ba5f4SPaul Zimmerman * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 265197ba5f4SPaul Zimmerman * in host mode when dynamic FIFO sizing is enabled 266197ba5f4SPaul Zimmerman * 16 to 32768 267197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 268197ba5f4SPaul Zimmerman * the default. 269197ba5f4SPaul Zimmerman * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 270197ba5f4SPaul Zimmerman * host mode when dynamic FIFO sizing is enabled 271197ba5f4SPaul Zimmerman * 16 to 32768 272197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 273197ba5f4SPaul Zimmerman * the default. 274197ba5f4SPaul Zimmerman * @max_transfer_size: The maximum transfer size supported, in bytes 275197ba5f4SPaul Zimmerman * 2047 to 65,535 276197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 277197ba5f4SPaul Zimmerman * the default. 278197ba5f4SPaul Zimmerman * @max_packet_count: The maximum number of packets in a transfer 279197ba5f4SPaul Zimmerman * 15 to 511 280197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 281197ba5f4SPaul Zimmerman * the default. 282197ba5f4SPaul Zimmerman * @host_channels: The number of host channel registers to use 283197ba5f4SPaul Zimmerman * 1 to 16 284197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 285197ba5f4SPaul Zimmerman * the default. 286197ba5f4SPaul Zimmerman * @phy_type: Specifies the type of PHY interface to use. By default, 287197ba5f4SPaul Zimmerman * the driver will automatically detect the phy_type. 288197ba5f4SPaul Zimmerman * 0 - Full Speed Phy 289197ba5f4SPaul Zimmerman * 1 - UTMI+ Phy 290197ba5f4SPaul Zimmerman * 2 - ULPI Phy 291197ba5f4SPaul Zimmerman * Defaults to best available option (2, 1, then 0) 292197ba5f4SPaul Zimmerman * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 293197ba5f4SPaul Zimmerman * is applicable for a phy_type of UTMI+ or ULPI. (For a 294197ba5f4SPaul Zimmerman * ULPI phy_type, this parameter indicates the data width 295197ba5f4SPaul Zimmerman * between the MAC and the ULPI Wrapper.) Also, this 296197ba5f4SPaul Zimmerman * parameter is applicable only if the OTG_HSPHY_WIDTH cC 297197ba5f4SPaul Zimmerman * parameter was set to "8 and 16 bits", meaning that the 298197ba5f4SPaul Zimmerman * core has been configured to work at either data path 299197ba5f4SPaul Zimmerman * width. 300197ba5f4SPaul Zimmerman * 8 or 16 (default 16 if available) 301197ba5f4SPaul Zimmerman * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 302197ba5f4SPaul Zimmerman * data rate. This parameter is only applicable if phy_type 303197ba5f4SPaul Zimmerman * is ULPI. 304197ba5f4SPaul Zimmerman * 0 - single data rate ULPI interface with 8 bit wide 305197ba5f4SPaul Zimmerman * data bus (default) 306197ba5f4SPaul Zimmerman * 1 - double data rate ULPI interface with 4 bit wide 307197ba5f4SPaul Zimmerman * data bus 308197ba5f4SPaul Zimmerman * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 309197ba5f4SPaul Zimmerman * external supply to drive the VBus 310197ba5f4SPaul Zimmerman * 0 - Internal supply (default) 311197ba5f4SPaul Zimmerman * 1 - External supply 312197ba5f4SPaul Zimmerman * @i2c_enable: Specifies whether to use the I2Cinterface for a full 313197ba5f4SPaul Zimmerman * speed PHY. This parameter is only applicable if phy_type 314197ba5f4SPaul Zimmerman * is FS. 315197ba5f4SPaul Zimmerman * 0 - No (default) 316197ba5f4SPaul Zimmerman * 1 - Yes 317197ba5f4SPaul Zimmerman * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 318197ba5f4SPaul Zimmerman * 0 - No (default) 319197ba5f4SPaul Zimmerman * 1 - Yes 320197ba5f4SPaul Zimmerman * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 321197ba5f4SPaul Zimmerman * when attached to a Full Speed or Low Speed device in 322197ba5f4SPaul Zimmerman * host mode. 323197ba5f4SPaul Zimmerman * 0 - Don't support low power mode (default) 324197ba5f4SPaul Zimmerman * 1 - Support low power mode 325197ba5f4SPaul Zimmerman * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 326197ba5f4SPaul Zimmerman * when connected to a Low Speed device in host 327197ba5f4SPaul Zimmerman * mode. This parameter is applicable only if 328197ba5f4SPaul Zimmerman * host_support_fs_ls_low_power is enabled. 329197ba5f4SPaul Zimmerman * 0 - 48 MHz 330197ba5f4SPaul Zimmerman * (default when phy_type is UTMI+ or ULPI) 331197ba5f4SPaul Zimmerman * 1 - 6 MHz 332197ba5f4SPaul Zimmerman * (default when phy_type is Full Speed) 333197ba5f4SPaul Zimmerman * @ts_dline: Enable Term Select Dline pulsing 334197ba5f4SPaul Zimmerman * 0 - No (default) 335197ba5f4SPaul Zimmerman * 1 - Yes 336197ba5f4SPaul Zimmerman * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 337197ba5f4SPaul Zimmerman * 0 - No (default for core < 2.92a) 338197ba5f4SPaul Zimmerman * 1 - Yes (default for core >= 2.92a) 339197ba5f4SPaul Zimmerman * @ahbcfg: This field allows the default value of the GAHBCFG 340197ba5f4SPaul Zimmerman * register to be overridden 341197ba5f4SPaul Zimmerman * -1 - GAHBCFG value will be set to 0x06 342197ba5f4SPaul Zimmerman * (INCR4, default) 343197ba5f4SPaul Zimmerman * all others - GAHBCFG value will be overridden with 344197ba5f4SPaul Zimmerman * this value 345197ba5f4SPaul Zimmerman * Not all bits can be controlled like this, the 346197ba5f4SPaul Zimmerman * bits defined by GAHBCFG_CTRL_MASK are controlled 347197ba5f4SPaul Zimmerman * by the driver and are ignored in this 348197ba5f4SPaul Zimmerman * configuration value. 349197ba5f4SPaul Zimmerman * @uframe_sched: True to enable the microframe scheduler 350a6d249d8SGregory Herrero * @external_id_pin_ctl: Specifies whether ID pin is handled externally. 351a6d249d8SGregory Herrero * Disable CONIDSTSCHNG controller interrupt in such 352a6d249d8SGregory Herrero * case. 353a6d249d8SGregory Herrero * 0 - No (default) 354a6d249d8SGregory Herrero * 1 - Yes 355285046aaSGregory Herrero * @hibernation: Specifies whether the controller support hibernation. 356285046aaSGregory Herrero * If hibernation is enabled, the controller will enter 357285046aaSGregory Herrero * hibernation in both peripheral and host mode when 358285046aaSGregory Herrero * needed. 359285046aaSGregory Herrero * 0 - No (default) 360285046aaSGregory Herrero * 1 - Yes 361197ba5f4SPaul Zimmerman * 362197ba5f4SPaul Zimmerman * The following parameters may be specified when starting the module. These 363197ba5f4SPaul Zimmerman * parameters define how the DWC_otg controller should be configured. A 364197ba5f4SPaul Zimmerman * value of -1 (or any other out of range value) for any parameter means 365197ba5f4SPaul Zimmerman * to read the value from hardware (if possible) or use the builtin 366197ba5f4SPaul Zimmerman * default described above. 367197ba5f4SPaul Zimmerman */ 368197ba5f4SPaul Zimmerman struct dwc2_core_params { 369197ba5f4SPaul Zimmerman /* 370197ba5f4SPaul Zimmerman * Don't add any non-int members here, this will break 371197ba5f4SPaul Zimmerman * dwc2_set_all_params! 372197ba5f4SPaul Zimmerman */ 373197ba5f4SPaul Zimmerman int otg_cap; 374197ba5f4SPaul Zimmerman int otg_ver; 375197ba5f4SPaul Zimmerman int dma_enable; 376197ba5f4SPaul Zimmerman int dma_desc_enable; 377197ba5f4SPaul Zimmerman int speed; 378197ba5f4SPaul Zimmerman int enable_dynamic_fifo; 379197ba5f4SPaul Zimmerman int en_multiple_tx_fifo; 380197ba5f4SPaul Zimmerman int host_rx_fifo_size; 381197ba5f4SPaul Zimmerman int host_nperio_tx_fifo_size; 382197ba5f4SPaul Zimmerman int host_perio_tx_fifo_size; 383197ba5f4SPaul Zimmerman int max_transfer_size; 384197ba5f4SPaul Zimmerman int max_packet_count; 385197ba5f4SPaul Zimmerman int host_channels; 386197ba5f4SPaul Zimmerman int phy_type; 387197ba5f4SPaul Zimmerman int phy_utmi_width; 388197ba5f4SPaul Zimmerman int phy_ulpi_ddr; 389197ba5f4SPaul Zimmerman int phy_ulpi_ext_vbus; 390197ba5f4SPaul Zimmerman int i2c_enable; 391197ba5f4SPaul Zimmerman int ulpi_fs_ls; 392197ba5f4SPaul Zimmerman int host_support_fs_ls_low_power; 393197ba5f4SPaul Zimmerman int host_ls_low_power_phy_clk; 394197ba5f4SPaul Zimmerman int ts_dline; 395197ba5f4SPaul Zimmerman int reload_ctl; 396197ba5f4SPaul Zimmerman int ahbcfg; 397197ba5f4SPaul Zimmerman int uframe_sched; 398a6d249d8SGregory Herrero int external_id_pin_ctl; 399285046aaSGregory Herrero int hibernation; 400197ba5f4SPaul Zimmerman }; 401197ba5f4SPaul Zimmerman 402197ba5f4SPaul Zimmerman /** 403197ba5f4SPaul Zimmerman * struct dwc2_hw_params - Autodetected parameters. 404197ba5f4SPaul Zimmerman * 405197ba5f4SPaul Zimmerman * These parameters are the various parameters read from hardware 406197ba5f4SPaul Zimmerman * registers during initialization. They typically contain the best 407197ba5f4SPaul Zimmerman * supported or maximum value that can be configured in the 408197ba5f4SPaul Zimmerman * corresponding dwc2_core_params value. 409197ba5f4SPaul Zimmerman * 410197ba5f4SPaul Zimmerman * The values that are not in dwc2_core_params are documented below. 411197ba5f4SPaul Zimmerman * 412197ba5f4SPaul Zimmerman * @op_mode Mode of Operation 413197ba5f4SPaul Zimmerman * 0 - HNP- and SRP-Capable OTG (Host & Device) 414197ba5f4SPaul Zimmerman * 1 - SRP-Capable OTG (Host & Device) 415197ba5f4SPaul Zimmerman * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 416197ba5f4SPaul Zimmerman * 3 - SRP-Capable Device 417197ba5f4SPaul Zimmerman * 4 - Non-OTG Device 418197ba5f4SPaul Zimmerman * 5 - SRP-Capable Host 419197ba5f4SPaul Zimmerman * 6 - Non-OTG Host 420197ba5f4SPaul Zimmerman * @arch Architecture 421197ba5f4SPaul Zimmerman * 0 - Slave only 422197ba5f4SPaul Zimmerman * 1 - External DMA 423197ba5f4SPaul Zimmerman * 2 - Internal DMA 424197ba5f4SPaul Zimmerman * @power_optimized Are power optimizations enabled? 425197ba5f4SPaul Zimmerman * @num_dev_ep Number of device endpoints available 426197ba5f4SPaul Zimmerman * @num_dev_perio_in_ep Number of device periodic IN endpoints 427997f4f81SMickael Maison * available 428197ba5f4SPaul Zimmerman * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue 429197ba5f4SPaul Zimmerman * Depth 430197ba5f4SPaul Zimmerman * 0 to 30 431197ba5f4SPaul Zimmerman * @host_perio_tx_q_depth 432197ba5f4SPaul Zimmerman * Host Mode Periodic Request Queue Depth 433197ba5f4SPaul Zimmerman * 2, 4 or 8 434197ba5f4SPaul Zimmerman * @nperio_tx_q_depth 435197ba5f4SPaul Zimmerman * Non-Periodic Request Queue Depth 436197ba5f4SPaul Zimmerman * 2, 4 or 8 437197ba5f4SPaul Zimmerman * @hs_phy_type High-speed PHY interface type 438197ba5f4SPaul Zimmerman * 0 - High-speed interface not supported 439197ba5f4SPaul Zimmerman * 1 - UTMI+ 440197ba5f4SPaul Zimmerman * 2 - ULPI 441197ba5f4SPaul Zimmerman * 3 - UTMI+ and ULPI 442197ba5f4SPaul Zimmerman * @fs_phy_type Full-speed PHY interface type 443197ba5f4SPaul Zimmerman * 0 - Full speed interface not supported 444197ba5f4SPaul Zimmerman * 1 - Dedicated full speed interface 445197ba5f4SPaul Zimmerman * 2 - FS pins shared with UTMI+ pins 446197ba5f4SPaul Zimmerman * 3 - FS pins shared with ULPI pins 447197ba5f4SPaul Zimmerman * @total_fifo_size: Total internal RAM for FIFOs (bytes) 448197ba5f4SPaul Zimmerman * @utmi_phy_data_width UTMI+ PHY data width 449197ba5f4SPaul Zimmerman * 0 - 8 bits 450197ba5f4SPaul Zimmerman * 1 - 16 bits 451197ba5f4SPaul Zimmerman * 2 - 8 or 16 bits 452197ba5f4SPaul Zimmerman * @snpsid: Value from SNPSID register 453197ba5f4SPaul Zimmerman */ 454197ba5f4SPaul Zimmerman struct dwc2_hw_params { 455197ba5f4SPaul Zimmerman unsigned op_mode:3; 456197ba5f4SPaul Zimmerman unsigned arch:2; 457197ba5f4SPaul Zimmerman unsigned dma_desc_enable:1; 458197ba5f4SPaul Zimmerman unsigned enable_dynamic_fifo:1; 459197ba5f4SPaul Zimmerman unsigned en_multiple_tx_fifo:1; 460197ba5f4SPaul Zimmerman unsigned host_rx_fifo_size:16; 461197ba5f4SPaul Zimmerman unsigned host_nperio_tx_fifo_size:16; 462197ba5f4SPaul Zimmerman unsigned host_perio_tx_fifo_size:16; 463197ba5f4SPaul Zimmerman unsigned nperio_tx_q_depth:3; 464197ba5f4SPaul Zimmerman unsigned host_perio_tx_q_depth:3; 465197ba5f4SPaul Zimmerman unsigned dev_token_q_depth:5; 466197ba5f4SPaul Zimmerman unsigned max_transfer_size:26; 467197ba5f4SPaul Zimmerman unsigned max_packet_count:11; 468197ba5f4SPaul Zimmerman unsigned host_channels:5; 469197ba5f4SPaul Zimmerman unsigned hs_phy_type:2; 470197ba5f4SPaul Zimmerman unsigned fs_phy_type:2; 471197ba5f4SPaul Zimmerman unsigned i2c_enable:1; 472197ba5f4SPaul Zimmerman unsigned num_dev_ep:4; 473197ba5f4SPaul Zimmerman unsigned num_dev_perio_in_ep:4; 474197ba5f4SPaul Zimmerman unsigned total_fifo_size:16; 475197ba5f4SPaul Zimmerman unsigned power_optimized:1; 476197ba5f4SPaul Zimmerman unsigned utmi_phy_data_width:2; 477197ba5f4SPaul Zimmerman u32 snpsid; 478197ba5f4SPaul Zimmerman }; 479197ba5f4SPaul Zimmerman 4803f95001dSMian Yousaf Kaukab /* Size of control and EP0 buffers */ 4813f95001dSMian Yousaf Kaukab #define DWC2_CTRL_BUFF_SIZE 8 4823f95001dSMian Yousaf Kaukab 483197ba5f4SPaul Zimmerman /** 484d17ee77bSGregory Herrero * struct dwc2_gregs_backup - Holds global registers state before entering partial 485d17ee77bSGregory Herrero * power down 486d17ee77bSGregory Herrero * @gotgctl: Backup of GOTGCTL register 487d17ee77bSGregory Herrero * @gintmsk: Backup of GINTMSK register 488d17ee77bSGregory Herrero * @gahbcfg: Backup of GAHBCFG register 489d17ee77bSGregory Herrero * @gusbcfg: Backup of GUSBCFG register 490d17ee77bSGregory Herrero * @grxfsiz: Backup of GRXFSIZ register 491d17ee77bSGregory Herrero * @gnptxfsiz: Backup of GNPTXFSIZ register 492d17ee77bSGregory Herrero * @gi2cctl: Backup of GI2CCTL register 493d17ee77bSGregory Herrero * @hptxfsiz: Backup of HPTXFSIZ register 494d17ee77bSGregory Herrero * @gdfifocfg: Backup of GDFIFOCFG register 495d17ee77bSGregory Herrero * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 496d17ee77bSGregory Herrero * @gpwrdn: Backup of GPWRDN register 497d17ee77bSGregory Herrero */ 498d17ee77bSGregory Herrero struct dwc2_gregs_backup { 499d17ee77bSGregory Herrero u32 gotgctl; 500d17ee77bSGregory Herrero u32 gintmsk; 501d17ee77bSGregory Herrero u32 gahbcfg; 502d17ee77bSGregory Herrero u32 gusbcfg; 503d17ee77bSGregory Herrero u32 grxfsiz; 504d17ee77bSGregory Herrero u32 gnptxfsiz; 505d17ee77bSGregory Herrero u32 gi2cctl; 506d17ee77bSGregory Herrero u32 hptxfsiz; 507d17ee77bSGregory Herrero u32 pcgcctl; 508d17ee77bSGregory Herrero u32 gdfifocfg; 509d17ee77bSGregory Herrero u32 dtxfsiz[MAX_EPS_CHANNELS]; 510d17ee77bSGregory Herrero u32 gpwrdn; 511cc1e204cSMian Yousaf Kaukab bool valid; 512d17ee77bSGregory Herrero }; 513d17ee77bSGregory Herrero 514d17ee77bSGregory Herrero /** 515d17ee77bSGregory Herrero * struct dwc2_dregs_backup - Holds device registers state before entering partial 516d17ee77bSGregory Herrero * power down 517d17ee77bSGregory Herrero * @dcfg: Backup of DCFG register 518d17ee77bSGregory Herrero * @dctl: Backup of DCTL register 519d17ee77bSGregory Herrero * @daintmsk: Backup of DAINTMSK register 520d17ee77bSGregory Herrero * @diepmsk: Backup of DIEPMSK register 521d17ee77bSGregory Herrero * @doepmsk: Backup of DOEPMSK register 522d17ee77bSGregory Herrero * @diepctl: Backup of DIEPCTL register 523d17ee77bSGregory Herrero * @dieptsiz: Backup of DIEPTSIZ register 524d17ee77bSGregory Herrero * @diepdma: Backup of DIEPDMA register 525d17ee77bSGregory Herrero * @doepctl: Backup of DOEPCTL register 526d17ee77bSGregory Herrero * @doeptsiz: Backup of DOEPTSIZ register 527d17ee77bSGregory Herrero * @doepdma: Backup of DOEPDMA register 528d17ee77bSGregory Herrero */ 529d17ee77bSGregory Herrero struct dwc2_dregs_backup { 530d17ee77bSGregory Herrero u32 dcfg; 531d17ee77bSGregory Herrero u32 dctl; 532d17ee77bSGregory Herrero u32 daintmsk; 533d17ee77bSGregory Herrero u32 diepmsk; 534d17ee77bSGregory Herrero u32 doepmsk; 535d17ee77bSGregory Herrero u32 diepctl[MAX_EPS_CHANNELS]; 536d17ee77bSGregory Herrero u32 dieptsiz[MAX_EPS_CHANNELS]; 537d17ee77bSGregory Herrero u32 diepdma[MAX_EPS_CHANNELS]; 538d17ee77bSGregory Herrero u32 doepctl[MAX_EPS_CHANNELS]; 539d17ee77bSGregory Herrero u32 doeptsiz[MAX_EPS_CHANNELS]; 540d17ee77bSGregory Herrero u32 doepdma[MAX_EPS_CHANNELS]; 541cc1e204cSMian Yousaf Kaukab bool valid; 542d17ee77bSGregory Herrero }; 543d17ee77bSGregory Herrero 544d17ee77bSGregory Herrero /** 545d17ee77bSGregory Herrero * struct dwc2_hregs_backup - Holds host registers state before entering partial 546d17ee77bSGregory Herrero * power down 547d17ee77bSGregory Herrero * @hcfg: Backup of HCFG register 548d17ee77bSGregory Herrero * @haintmsk: Backup of HAINTMSK register 549d17ee77bSGregory Herrero * @hcintmsk: Backup of HCINTMSK register 550d17ee77bSGregory Herrero * @hptr0: Backup of HPTR0 register 551d17ee77bSGregory Herrero * @hfir: Backup of HFIR register 552d17ee77bSGregory Herrero */ 553d17ee77bSGregory Herrero struct dwc2_hregs_backup { 554d17ee77bSGregory Herrero u32 hcfg; 555d17ee77bSGregory Herrero u32 haintmsk; 556d17ee77bSGregory Herrero u32 hcintmsk[MAX_EPS_CHANNELS]; 557d17ee77bSGregory Herrero u32 hprt0; 558d17ee77bSGregory Herrero u32 hfir; 559cc1e204cSMian Yousaf Kaukab bool valid; 560d17ee77bSGregory Herrero }; 561d17ee77bSGregory Herrero 562d17ee77bSGregory Herrero /** 563197ba5f4SPaul Zimmerman * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 564197ba5f4SPaul Zimmerman * and periodic schedules 565197ba5f4SPaul Zimmerman * 566941fcce4SDinh Nguyen * These are common for both host and peripheral modes: 567941fcce4SDinh Nguyen * 568197ba5f4SPaul Zimmerman * @dev: The struct device pointer 569197ba5f4SPaul Zimmerman * @regs: Pointer to controller regs 570197ba5f4SPaul Zimmerman * @hw_params: Parameters that were autodetected from the 571197ba5f4SPaul Zimmerman * hardware registers 572941fcce4SDinh Nguyen * @core_params: Parameters that define how the core should be configured 573197ba5f4SPaul Zimmerman * @op_state: The operational State, during transitions (a_host=> 574197ba5f4SPaul Zimmerman * a_peripheral and b_device=>b_host) this may not match 575197ba5f4SPaul Zimmerman * the core, but allows the software to determine 576197ba5f4SPaul Zimmerman * transitions 577c0155b9dSKever Yang * @dr_mode: Requested mode of operation, one of following: 578c0155b9dSKever Yang * - USB_DR_MODE_PERIPHERAL 579c0155b9dSKever Yang * - USB_DR_MODE_HOST 580c0155b9dSKever Yang * - USB_DR_MODE_OTG 581941fcce4SDinh Nguyen * @lock: Spinlock that protects all the driver data structures 582941fcce4SDinh Nguyen * @priv: Stores a pointer to the struct usb_hcd 583197ba5f4SPaul Zimmerman * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 584197ba5f4SPaul Zimmerman * transfer are in process of being queued 585197ba5f4SPaul Zimmerman * @srp_success: Stores status of SRP request in the case of a FS PHY 586197ba5f4SPaul Zimmerman * with an I2C interface 587197ba5f4SPaul Zimmerman * @wq_otg: Workqueue object used for handling of some interrupts 588197ba5f4SPaul Zimmerman * @wf_otg: Work object for handling Connector ID Status Change 589197ba5f4SPaul Zimmerman * interrupt 590197ba5f4SPaul Zimmerman * @wkp_timer: Timer object for handling Wakeup Detected interrupt 591197ba5f4SPaul Zimmerman * @lx_state: Lx state of connected device 592d17ee77bSGregory Herrero * @gregs_backup: Backup of global registers during suspend 593d17ee77bSGregory Herrero * @dregs_backup: Backup of device registers during suspend 594d17ee77bSGregory Herrero * @hregs_backup: Backup of host registers during suspend 595941fcce4SDinh Nguyen * 596941fcce4SDinh Nguyen * These are for host mode: 597941fcce4SDinh Nguyen * 598197ba5f4SPaul Zimmerman * @flags: Flags for handling root port state changes 599197ba5f4SPaul Zimmerman * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 600197ba5f4SPaul Zimmerman * Transfers associated with these QHs are not currently 601197ba5f4SPaul Zimmerman * assigned to a host channel. 602197ba5f4SPaul Zimmerman * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 603197ba5f4SPaul Zimmerman * Transfers associated with these QHs are currently 604197ba5f4SPaul Zimmerman * assigned to a host channel. 605197ba5f4SPaul Zimmerman * @non_periodic_qh_ptr: Pointer to next QH to process in the active 606197ba5f4SPaul Zimmerman * non-periodic schedule 607197ba5f4SPaul Zimmerman * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 608197ba5f4SPaul Zimmerman * list of QHs for periodic transfers that are _not_ 609197ba5f4SPaul Zimmerman * scheduled for the next frame. Each QH in the list has an 610197ba5f4SPaul Zimmerman * interval counter that determines when it needs to be 611197ba5f4SPaul Zimmerman * scheduled for execution. This scheduling mechanism 612197ba5f4SPaul Zimmerman * allows only a simple calculation for periodic bandwidth 613197ba5f4SPaul Zimmerman * used (i.e. must assume that all periodic transfers may 614197ba5f4SPaul Zimmerman * need to execute in the same frame). However, it greatly 615197ba5f4SPaul Zimmerman * simplifies scheduling and should be sufficient for the 616197ba5f4SPaul Zimmerman * vast majority of OTG hosts, which need to connect to a 617197ba5f4SPaul Zimmerman * small number of peripherals at one time. Items move from 618197ba5f4SPaul Zimmerman * this list to periodic_sched_ready when the QH interval 619197ba5f4SPaul Zimmerman * counter is 0 at SOF. 620197ba5f4SPaul Zimmerman * @periodic_sched_ready: List of periodic QHs that are ready for execution in 621197ba5f4SPaul Zimmerman * the next frame, but have not yet been assigned to host 622197ba5f4SPaul Zimmerman * channels. Items move from this list to 623197ba5f4SPaul Zimmerman * periodic_sched_assigned as host channels become 624197ba5f4SPaul Zimmerman * available during the current frame. 625197ba5f4SPaul Zimmerman * @periodic_sched_assigned: List of periodic QHs to be executed in the next 626197ba5f4SPaul Zimmerman * frame that are assigned to host channels. Items move 627197ba5f4SPaul Zimmerman * from this list to periodic_sched_queued as the 628197ba5f4SPaul Zimmerman * transactions for the QH are queued to the DWC_otg 629197ba5f4SPaul Zimmerman * controller. 630197ba5f4SPaul Zimmerman * @periodic_sched_queued: List of periodic QHs that have been queued for 631197ba5f4SPaul Zimmerman * execution. Items move from this list to either 632197ba5f4SPaul Zimmerman * periodic_sched_inactive or periodic_sched_ready when the 633197ba5f4SPaul Zimmerman * channel associated with the transfer is released. If the 634197ba5f4SPaul Zimmerman * interval for the QH is 1, the item moves to 635197ba5f4SPaul Zimmerman * periodic_sched_ready because it must be rescheduled for 636197ba5f4SPaul Zimmerman * the next frame. Otherwise, the item moves to 637197ba5f4SPaul Zimmerman * periodic_sched_inactive. 638197ba5f4SPaul Zimmerman * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 639197ba5f4SPaul Zimmerman * This value is in microseconds per (micro)frame. The 640197ba5f4SPaul Zimmerman * assumption is that all periodic transfers may occur in 641197ba5f4SPaul Zimmerman * the same (micro)frame. 642197ba5f4SPaul Zimmerman * @frame_usecs: Internal variable used by the microframe scheduler 643197ba5f4SPaul Zimmerman * @frame_number: Frame number read from the core at SOF. The value ranges 644197ba5f4SPaul Zimmerman * from 0 to HFNUM_MAX_FRNUM. 645197ba5f4SPaul Zimmerman * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 646197ba5f4SPaul Zimmerman * SOF enable/disable. 647197ba5f4SPaul Zimmerman * @free_hc_list: Free host channels in the controller. This is a list of 648197ba5f4SPaul Zimmerman * struct dwc2_host_chan items. 649197ba5f4SPaul Zimmerman * @periodic_channels: Number of host channels assigned to periodic transfers. 650197ba5f4SPaul Zimmerman * Currently assuming that there is a dedicated host 651197ba5f4SPaul Zimmerman * channel for each periodic transaction and at least one 652197ba5f4SPaul Zimmerman * host channel is available for non-periodic transactions. 653197ba5f4SPaul Zimmerman * @non_periodic_channels: Number of host channels assigned to non-periodic 654197ba5f4SPaul Zimmerman * transfers 655197ba5f4SPaul Zimmerman * @available_host_channels Number of host channels available for the microframe 656197ba5f4SPaul Zimmerman * scheduler to use 657197ba5f4SPaul Zimmerman * @hc_ptr_array: Array of pointers to the host channel descriptors. 658197ba5f4SPaul Zimmerman * Allows accessing a host channel descriptor given the 659197ba5f4SPaul Zimmerman * host channel number. This is useful in interrupt 660197ba5f4SPaul Zimmerman * handlers. 661197ba5f4SPaul Zimmerman * @status_buf: Buffer used for data received during the status phase of 662197ba5f4SPaul Zimmerman * a control transfer. 663197ba5f4SPaul Zimmerman * @status_buf_dma: DMA address for status_buf 664197ba5f4SPaul Zimmerman * @start_work: Delayed work for handling host A-cable connection 665197ba5f4SPaul Zimmerman * @reset_work: Delayed work for handling a port reset 666197ba5f4SPaul Zimmerman * @otg_port: OTG port number 667197ba5f4SPaul Zimmerman * @frame_list: Frame list 668197ba5f4SPaul Zimmerman * @frame_list_dma: Frame list DMA address 669941fcce4SDinh Nguyen * 670941fcce4SDinh Nguyen * These are for peripheral mode: 671941fcce4SDinh Nguyen * 672941fcce4SDinh Nguyen * @driver: USB gadget driver 673941fcce4SDinh Nguyen * @phy: The otg phy transceiver structure for phy control. 674941fcce4SDinh Nguyen * @uphy: The otg phy transceiver structure for old USB phy control. 675941fcce4SDinh Nguyen * @plat: The platform specific configuration data. This can be removed once 676941fcce4SDinh Nguyen * all SoCs support usb transceiver. 677941fcce4SDinh Nguyen * @supplies: Definition of USB power supplies 678941fcce4SDinh Nguyen * @phyif: PHY interface width 679941fcce4SDinh Nguyen * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 680941fcce4SDinh Nguyen * @num_of_eps: Number of available EPs (excluding EP0) 681941fcce4SDinh Nguyen * @debug_root: Root directrory for debugfs. 682941fcce4SDinh Nguyen * @debug_file: Main status file for debugfs. 6839e14d0a5SGregory Herrero * @debug_testmode: Testmode status file for debugfs. 684941fcce4SDinh Nguyen * @debug_fifo: FIFO status file for debugfs. 685941fcce4SDinh Nguyen * @ep0_reply: Request used for ep0 reply. 686941fcce4SDinh Nguyen * @ep0_buff: Buffer for EP0 reply data, if needed. 687941fcce4SDinh Nguyen * @ctrl_buff: Buffer for EP0 control requests. 688941fcce4SDinh Nguyen * @ctrl_req: Request for EP0 control packets. 689fe0b94abSMian Yousaf Kaukab * @ep0_state: EP0 control transfers state 6909e14d0a5SGregory Herrero * @test_mode: USB test mode requested by the host 691941fcce4SDinh Nguyen * @last_rst: Time of last reset 692941fcce4SDinh Nguyen * @eps: The endpoints being supplied to the gadget framework 693edd74be8SGregory Herrero * @g_using_dma: Indicate if dma usage is enabled 6940a176279SGregory Herrero * @g_rx_fifo_sz: Contains rx fifo size value 6950a176279SGregory Herrero * @g_np_g_tx_fifo_sz: Contains Non-Periodic tx fifo size value 6960a176279SGregory Herrero * @g_tx_fifo_sz: Contains tx fifo size value per endpoints 697197ba5f4SPaul Zimmerman */ 698197ba5f4SPaul Zimmerman struct dwc2_hsotg { 699197ba5f4SPaul Zimmerman struct device *dev; 700197ba5f4SPaul Zimmerman void __iomem *regs; 701197ba5f4SPaul Zimmerman /** Params detected from hardware */ 702197ba5f4SPaul Zimmerman struct dwc2_hw_params hw_params; 703197ba5f4SPaul Zimmerman /** Params to actually use */ 704197ba5f4SPaul Zimmerman struct dwc2_core_params *core_params; 705197ba5f4SPaul Zimmerman enum usb_otg_state op_state; 706c0155b9dSKever Yang enum usb_dr_mode dr_mode; 707e39af88fSMarek Szyprowski unsigned int hcd_enabled:1; 708e39af88fSMarek Szyprowski unsigned int gadget_enabled:1; 709197ba5f4SPaul Zimmerman 710941fcce4SDinh Nguyen struct phy *phy; 711941fcce4SDinh Nguyen struct usb_phy *uphy; 7121f91b4ccSFelipe Balbi struct regulator_bulk_data supplies[ARRAY_SIZE(dwc2_hsotg_supply_names)]; 713941fcce4SDinh Nguyen 714941fcce4SDinh Nguyen spinlock_t lock; 7157ad8096eSMarek Szyprowski struct mutex init_mutex; 716941fcce4SDinh Nguyen void *priv; 717941fcce4SDinh Nguyen int irq; 718941fcce4SDinh Nguyen struct clk *clk; 719941fcce4SDinh Nguyen 720197ba5f4SPaul Zimmerman unsigned int queuing_high_bandwidth:1; 721197ba5f4SPaul Zimmerman unsigned int srp_success:1; 722197ba5f4SPaul Zimmerman 723197ba5f4SPaul Zimmerman struct workqueue_struct *wq_otg; 724197ba5f4SPaul Zimmerman struct work_struct wf_otg; 725197ba5f4SPaul Zimmerman struct timer_list wkp_timer; 726197ba5f4SPaul Zimmerman enum dwc2_lx_state lx_state; 727cc1e204cSMian Yousaf Kaukab struct dwc2_gregs_backup gr_backup; 728cc1e204cSMian Yousaf Kaukab struct dwc2_dregs_backup dr_backup; 729cc1e204cSMian Yousaf Kaukab struct dwc2_hregs_backup hr_backup; 730197ba5f4SPaul Zimmerman 731941fcce4SDinh Nguyen struct dentry *debug_root; 732563cf017SMian Yousaf Kaukab struct debugfs_regset32 *regset; 733941fcce4SDinh Nguyen 734941fcce4SDinh Nguyen /* DWC OTG HW Release versions */ 735941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_71a 0x4f54271a 736941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_90a 0x4f54290a 737941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_92a 0x4f54292a 738941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_94a 0x4f54294a 739941fcce4SDinh Nguyen #define DWC2_CORE_REV_3_00a 0x4f54300a 740941fcce4SDinh Nguyen 741941fcce4SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 742197ba5f4SPaul Zimmerman union dwc2_hcd_internal_flags { 743197ba5f4SPaul Zimmerman u32 d32; 744197ba5f4SPaul Zimmerman struct { 745197ba5f4SPaul Zimmerman unsigned port_connect_status_change:1; 746197ba5f4SPaul Zimmerman unsigned port_connect_status:1; 747197ba5f4SPaul Zimmerman unsigned port_reset_change:1; 748197ba5f4SPaul Zimmerman unsigned port_enable_change:1; 749197ba5f4SPaul Zimmerman unsigned port_suspend_change:1; 750197ba5f4SPaul Zimmerman unsigned port_over_current_change:1; 751197ba5f4SPaul Zimmerman unsigned port_l1_change:1; 752fd4850cfSCharles Manning unsigned reserved:25; 753197ba5f4SPaul Zimmerman } b; 754197ba5f4SPaul Zimmerman } flags; 755197ba5f4SPaul Zimmerman 756197ba5f4SPaul Zimmerman struct list_head non_periodic_sched_inactive; 757197ba5f4SPaul Zimmerman struct list_head non_periodic_sched_active; 758197ba5f4SPaul Zimmerman struct list_head *non_periodic_qh_ptr; 759197ba5f4SPaul Zimmerman struct list_head periodic_sched_inactive; 760197ba5f4SPaul Zimmerman struct list_head periodic_sched_ready; 761197ba5f4SPaul Zimmerman struct list_head periodic_sched_assigned; 762197ba5f4SPaul Zimmerman struct list_head periodic_sched_queued; 763197ba5f4SPaul Zimmerman u16 periodic_usecs; 764197ba5f4SPaul Zimmerman u16 frame_usecs[8]; 765197ba5f4SPaul Zimmerman u16 frame_number; 766197ba5f4SPaul Zimmerman u16 periodic_qh_count; 767197ba5f4SPaul Zimmerman 768197ba5f4SPaul Zimmerman #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 769197ba5f4SPaul Zimmerman #define FRAME_NUM_ARRAY_SIZE 1000 770197ba5f4SPaul Zimmerman u16 last_frame_num; 771197ba5f4SPaul Zimmerman u16 *frame_num_array; 772197ba5f4SPaul Zimmerman u16 *last_frame_num_array; 773197ba5f4SPaul Zimmerman int frame_num_idx; 774197ba5f4SPaul Zimmerman int dumped_frame_num_array; 775197ba5f4SPaul Zimmerman #endif 776197ba5f4SPaul Zimmerman 777197ba5f4SPaul Zimmerman struct list_head free_hc_list; 778197ba5f4SPaul Zimmerman int periodic_channels; 779197ba5f4SPaul Zimmerman int non_periodic_channels; 780197ba5f4SPaul Zimmerman int available_host_channels; 781197ba5f4SPaul Zimmerman struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 782197ba5f4SPaul Zimmerman u8 *status_buf; 783197ba5f4SPaul Zimmerman dma_addr_t status_buf_dma; 784197ba5f4SPaul Zimmerman #define DWC2_HCD_STATUS_BUF_SIZE 64 785197ba5f4SPaul Zimmerman 786197ba5f4SPaul Zimmerman struct delayed_work start_work; 787197ba5f4SPaul Zimmerman struct delayed_work reset_work; 788197ba5f4SPaul Zimmerman u8 otg_port; 789197ba5f4SPaul Zimmerman u32 *frame_list; 790197ba5f4SPaul Zimmerman dma_addr_t frame_list_dma; 791197ba5f4SPaul Zimmerman 792197ba5f4SPaul Zimmerman #ifdef DEBUG 793197ba5f4SPaul Zimmerman u32 frrem_samples; 794197ba5f4SPaul Zimmerman u64 frrem_accum; 795197ba5f4SPaul Zimmerman 796197ba5f4SPaul Zimmerman u32 hfnum_7_samples_a; 797197ba5f4SPaul Zimmerman u64 hfnum_7_frrem_accum_a; 798197ba5f4SPaul Zimmerman u32 hfnum_0_samples_a; 799197ba5f4SPaul Zimmerman u64 hfnum_0_frrem_accum_a; 800197ba5f4SPaul Zimmerman u32 hfnum_other_samples_a; 801197ba5f4SPaul Zimmerman u64 hfnum_other_frrem_accum_a; 802197ba5f4SPaul Zimmerman 803197ba5f4SPaul Zimmerman u32 hfnum_7_samples_b; 804197ba5f4SPaul Zimmerman u64 hfnum_7_frrem_accum_b; 805197ba5f4SPaul Zimmerman u32 hfnum_0_samples_b; 806197ba5f4SPaul Zimmerman u64 hfnum_0_frrem_accum_b; 807197ba5f4SPaul Zimmerman u32 hfnum_other_samples_b; 808197ba5f4SPaul Zimmerman u64 hfnum_other_frrem_accum_b; 809197ba5f4SPaul Zimmerman #endif 810941fcce4SDinh Nguyen #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ 811941fcce4SDinh Nguyen 812941fcce4SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 813941fcce4SDinh Nguyen /* Gadget structures */ 814941fcce4SDinh Nguyen struct usb_gadget_driver *driver; 8151f91b4ccSFelipe Balbi struct dwc2_hsotg_plat *plat; 816941fcce4SDinh Nguyen 817941fcce4SDinh Nguyen u32 phyif; 818941fcce4SDinh Nguyen int fifo_mem; 819941fcce4SDinh Nguyen unsigned int dedicated_fifos:1; 820941fcce4SDinh Nguyen unsigned char num_of_eps; 821941fcce4SDinh Nguyen u32 fifo_map; 822941fcce4SDinh Nguyen 823941fcce4SDinh Nguyen struct usb_request *ep0_reply; 824941fcce4SDinh Nguyen struct usb_request *ctrl_req; 8253f95001dSMian Yousaf Kaukab void *ep0_buff; 8263f95001dSMian Yousaf Kaukab void *ctrl_buff; 827fe0b94abSMian Yousaf Kaukab enum dwc2_ep0_state ep0_state; 8289e14d0a5SGregory Herrero u8 test_mode; 829941fcce4SDinh Nguyen 830941fcce4SDinh Nguyen struct usb_gadget gadget; 831dc6e69e6SMarek Szyprowski unsigned int enabled:1; 8324ace06e8SMarek Szyprowski unsigned int connected:1; 833941fcce4SDinh Nguyen unsigned long last_rst; 8341f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS]; 8351f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS]; 836edd74be8SGregory Herrero u32 g_using_dma; 8370a176279SGregory Herrero u32 g_rx_fifo_sz; 8380a176279SGregory Herrero u32 g_np_g_tx_fifo_sz; 8390a176279SGregory Herrero u32 g_tx_fifo_sz[MAX_EPS_CHANNELS]; 840941fcce4SDinh Nguyen #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 841197ba5f4SPaul Zimmerman }; 842197ba5f4SPaul Zimmerman 843197ba5f4SPaul Zimmerman /* Reasons for halting a host channel */ 844197ba5f4SPaul Zimmerman enum dwc2_halt_status { 845197ba5f4SPaul Zimmerman DWC2_HC_XFER_NO_HALT_STATUS, 846197ba5f4SPaul Zimmerman DWC2_HC_XFER_COMPLETE, 847197ba5f4SPaul Zimmerman DWC2_HC_XFER_URB_COMPLETE, 848197ba5f4SPaul Zimmerman DWC2_HC_XFER_ACK, 849197ba5f4SPaul Zimmerman DWC2_HC_XFER_NAK, 850197ba5f4SPaul Zimmerman DWC2_HC_XFER_NYET, 851197ba5f4SPaul Zimmerman DWC2_HC_XFER_STALL, 852197ba5f4SPaul Zimmerman DWC2_HC_XFER_XACT_ERR, 853197ba5f4SPaul Zimmerman DWC2_HC_XFER_FRAME_OVERRUN, 854197ba5f4SPaul Zimmerman DWC2_HC_XFER_BABBLE_ERR, 855197ba5f4SPaul Zimmerman DWC2_HC_XFER_DATA_TOGGLE_ERR, 856197ba5f4SPaul Zimmerman DWC2_HC_XFER_AHB_ERR, 857197ba5f4SPaul Zimmerman DWC2_HC_XFER_PERIODIC_INCOMPLETE, 858197ba5f4SPaul Zimmerman DWC2_HC_XFER_URB_DEQUEUE, 859197ba5f4SPaul Zimmerman }; 860197ba5f4SPaul Zimmerman 861197ba5f4SPaul Zimmerman /* 862197ba5f4SPaul Zimmerman * The following functions support initialization of the core driver component 863197ba5f4SPaul Zimmerman * and the DWC_otg controller 864197ba5f4SPaul Zimmerman */ 865197ba5f4SPaul Zimmerman extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg); 866d17ee77bSGregory Herrero extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg); 867d17ee77bSGregory Herrero extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore); 868197ba5f4SPaul Zimmerman 869197ba5f4SPaul Zimmerman /* 870197ba5f4SPaul Zimmerman * Host core Functions. 871197ba5f4SPaul Zimmerman * The following functions support managing the DWC_otg controller in host 872197ba5f4SPaul Zimmerman * mode. 873197ba5f4SPaul Zimmerman */ 874197ba5f4SPaul Zimmerman extern void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan); 875197ba5f4SPaul Zimmerman extern void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 876197ba5f4SPaul Zimmerman enum dwc2_halt_status halt_status); 877197ba5f4SPaul Zimmerman extern void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, 878197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan); 879197ba5f4SPaul Zimmerman extern void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 880197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan); 881197ba5f4SPaul Zimmerman extern void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 882197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan); 883197ba5f4SPaul Zimmerman extern int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 884197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan); 885197ba5f4SPaul Zimmerman extern void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, 886197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan); 887197ba5f4SPaul Zimmerman extern void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg); 888197ba5f4SPaul Zimmerman extern void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg); 889197ba5f4SPaul Zimmerman 890197ba5f4SPaul Zimmerman extern u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg); 891197ba5f4SPaul Zimmerman extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 892197ba5f4SPaul Zimmerman 893197ba5f4SPaul Zimmerman /* 894197ba5f4SPaul Zimmerman * Common core Functions. 895197ba5f4SPaul Zimmerman * The following functions support managing the DWC_otg controller in either 896197ba5f4SPaul Zimmerman * device or host mode. 897197ba5f4SPaul Zimmerman */ 898197ba5f4SPaul Zimmerman extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 899197ba5f4SPaul Zimmerman extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 900197ba5f4SPaul Zimmerman extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 901197ba5f4SPaul Zimmerman 902197ba5f4SPaul Zimmerman extern int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq); 903197ba5f4SPaul Zimmerman extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 904197ba5f4SPaul Zimmerman extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 905197ba5f4SPaul Zimmerman 906197ba5f4SPaul Zimmerman /* This function should be called on every hardware interrupt. */ 907197ba5f4SPaul Zimmerman extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 908197ba5f4SPaul Zimmerman 909197ba5f4SPaul Zimmerman /* OTG Core Parameters */ 910197ba5f4SPaul Zimmerman 911197ba5f4SPaul Zimmerman /* 912197ba5f4SPaul Zimmerman * Specifies the OTG capabilities. The driver will automatically 913197ba5f4SPaul Zimmerman * detect the value for this parameter if none is specified. 914197ba5f4SPaul Zimmerman * 0 - HNP and SRP capable (default) 915197ba5f4SPaul Zimmerman * 1 - SRP Only capable 916197ba5f4SPaul Zimmerman * 2 - No HNP/SRP capable 917197ba5f4SPaul Zimmerman */ 918197ba5f4SPaul Zimmerman extern void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val); 919197ba5f4SPaul Zimmerman #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 920197ba5f4SPaul Zimmerman #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 921197ba5f4SPaul Zimmerman #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 922197ba5f4SPaul Zimmerman 923197ba5f4SPaul Zimmerman /* 924197ba5f4SPaul Zimmerman * Specifies whether to use slave or DMA mode for accessing the data 925197ba5f4SPaul Zimmerman * FIFOs. The driver will automatically detect the value for this 926197ba5f4SPaul Zimmerman * parameter if none is specified. 927197ba5f4SPaul Zimmerman * 0 - Slave 928197ba5f4SPaul Zimmerman * 1 - DMA (default, if available) 929197ba5f4SPaul Zimmerman */ 930197ba5f4SPaul Zimmerman extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val); 931197ba5f4SPaul Zimmerman 932197ba5f4SPaul Zimmerman /* 933197ba5f4SPaul Zimmerman * When DMA mode is enabled specifies whether to use 934197ba5f4SPaul Zimmerman * address DMA or DMA Descritor mode for accessing the data 935197ba5f4SPaul Zimmerman * FIFOs in device mode. The driver will automatically detect 936197ba5f4SPaul Zimmerman * the value for this parameter if none is specified. 937197ba5f4SPaul Zimmerman * 0 - address DMA 938197ba5f4SPaul Zimmerman * 1 - DMA Descriptor(default, if available) 939197ba5f4SPaul Zimmerman */ 940197ba5f4SPaul Zimmerman extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val); 941197ba5f4SPaul Zimmerman 942197ba5f4SPaul Zimmerman /* 943197ba5f4SPaul Zimmerman * Specifies the maximum speed of operation in host and device mode. 944197ba5f4SPaul Zimmerman * The actual speed depends on the speed of the attached device and 945197ba5f4SPaul Zimmerman * the value of phy_type. The actual speed depends on the speed of the 946197ba5f4SPaul Zimmerman * attached device. 947197ba5f4SPaul Zimmerman * 0 - High Speed (default) 948197ba5f4SPaul Zimmerman * 1 - Full Speed 949197ba5f4SPaul Zimmerman */ 950197ba5f4SPaul Zimmerman extern void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val); 951197ba5f4SPaul Zimmerman #define DWC2_SPEED_PARAM_HIGH 0 952197ba5f4SPaul Zimmerman #define DWC2_SPEED_PARAM_FULL 1 953197ba5f4SPaul Zimmerman 954197ba5f4SPaul Zimmerman /* 955197ba5f4SPaul Zimmerman * Specifies whether low power mode is supported when attached 956197ba5f4SPaul Zimmerman * to a Full Speed or Low Speed device in host mode. 957197ba5f4SPaul Zimmerman * 958197ba5f4SPaul Zimmerman * 0 - Don't support low power mode (default) 959197ba5f4SPaul Zimmerman * 1 - Support low power mode 960197ba5f4SPaul Zimmerman */ 961197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_support_fs_ls_low_power( 962197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg, int val); 963197ba5f4SPaul Zimmerman 964197ba5f4SPaul Zimmerman /* 965197ba5f4SPaul Zimmerman * Specifies the PHY clock rate in low power mode when connected to a 966197ba5f4SPaul Zimmerman * Low Speed device in host mode. This parameter is applicable only if 967197ba5f4SPaul Zimmerman * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS 968197ba5f4SPaul Zimmerman * then defaults to 6 MHZ otherwise 48 MHZ. 969197ba5f4SPaul Zimmerman * 970197ba5f4SPaul Zimmerman * 0 - 48 MHz 971197ba5f4SPaul Zimmerman * 1 - 6 MHz 972197ba5f4SPaul Zimmerman */ 973197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, 974197ba5f4SPaul Zimmerman int val); 975197ba5f4SPaul Zimmerman #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 976197ba5f4SPaul Zimmerman #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 977197ba5f4SPaul Zimmerman 978197ba5f4SPaul Zimmerman /* 979197ba5f4SPaul Zimmerman * 0 - Use cC FIFO size parameters 980197ba5f4SPaul Zimmerman * 1 - Allow dynamic FIFO sizing (default) 981197ba5f4SPaul Zimmerman */ 982197ba5f4SPaul Zimmerman extern void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, 983197ba5f4SPaul Zimmerman int val); 984197ba5f4SPaul Zimmerman 985197ba5f4SPaul Zimmerman /* 986197ba5f4SPaul Zimmerman * Number of 4-byte words in the Rx FIFO in host mode when dynamic 987197ba5f4SPaul Zimmerman * FIFO sizing is enabled. 988197ba5f4SPaul Zimmerman * 16 to 32768 (default 1024) 989197ba5f4SPaul Zimmerman */ 990197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val); 991197ba5f4SPaul Zimmerman 992197ba5f4SPaul Zimmerman /* 993197ba5f4SPaul Zimmerman * Number of 4-byte words in the non-periodic Tx FIFO in host mode 994197ba5f4SPaul Zimmerman * when Dynamic FIFO sizing is enabled in the core. 995197ba5f4SPaul Zimmerman * 16 to 32768 (default 256) 996197ba5f4SPaul Zimmerman */ 997197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, 998197ba5f4SPaul Zimmerman int val); 999197ba5f4SPaul Zimmerman 1000197ba5f4SPaul Zimmerman /* 1001197ba5f4SPaul Zimmerman * Number of 4-byte words in the host periodic Tx FIFO when dynamic 1002197ba5f4SPaul Zimmerman * FIFO sizing is enabled. 1003197ba5f4SPaul Zimmerman * 16 to 32768 (default 256) 1004197ba5f4SPaul Zimmerman */ 1005197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, 1006197ba5f4SPaul Zimmerman int val); 1007197ba5f4SPaul Zimmerman 1008197ba5f4SPaul Zimmerman /* 1009197ba5f4SPaul Zimmerman * The maximum transfer size supported in bytes. 1010197ba5f4SPaul Zimmerman * 2047 to 65,535 (default 65,535) 1011197ba5f4SPaul Zimmerman */ 1012197ba5f4SPaul Zimmerman extern void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val); 1013197ba5f4SPaul Zimmerman 1014197ba5f4SPaul Zimmerman /* 1015197ba5f4SPaul Zimmerman * The maximum number of packets in a transfer. 1016197ba5f4SPaul Zimmerman * 15 to 511 (default 511) 1017197ba5f4SPaul Zimmerman */ 1018197ba5f4SPaul Zimmerman extern void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val); 1019197ba5f4SPaul Zimmerman 1020197ba5f4SPaul Zimmerman /* 1021197ba5f4SPaul Zimmerman * The number of host channel registers to use. 1022197ba5f4SPaul Zimmerman * 1 to 16 (default 11) 1023197ba5f4SPaul Zimmerman * Note: The FPGA configuration supports a maximum of 11 host channels. 1024197ba5f4SPaul Zimmerman */ 1025197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val); 1026197ba5f4SPaul Zimmerman 1027197ba5f4SPaul Zimmerman /* 1028197ba5f4SPaul Zimmerman * Specifies the type of PHY interface to use. By default, the driver 1029197ba5f4SPaul Zimmerman * will automatically detect the phy_type. 1030197ba5f4SPaul Zimmerman * 1031197ba5f4SPaul Zimmerman * 0 - Full Speed PHY 1032197ba5f4SPaul Zimmerman * 1 - UTMI+ (default) 1033197ba5f4SPaul Zimmerman * 2 - ULPI 1034197ba5f4SPaul Zimmerman */ 1035197ba5f4SPaul Zimmerman extern void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val); 1036197ba5f4SPaul Zimmerman #define DWC2_PHY_TYPE_PARAM_FS 0 1037197ba5f4SPaul Zimmerman #define DWC2_PHY_TYPE_PARAM_UTMI 1 1038197ba5f4SPaul Zimmerman #define DWC2_PHY_TYPE_PARAM_ULPI 2 1039197ba5f4SPaul Zimmerman 1040197ba5f4SPaul Zimmerman /* 1041197ba5f4SPaul Zimmerman * Specifies the UTMI+ Data Width. This parameter is 1042197ba5f4SPaul Zimmerman * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI 1043197ba5f4SPaul Zimmerman * PHY_TYPE, this parameter indicates the data width between 1044197ba5f4SPaul Zimmerman * the MAC and the ULPI Wrapper.) Also, this parameter is 1045197ba5f4SPaul Zimmerman * applicable only if the OTG_HSPHY_WIDTH cC parameter was set 1046197ba5f4SPaul Zimmerman * to "8 and 16 bits", meaning that the core has been 1047197ba5f4SPaul Zimmerman * configured to work at either data path width. 1048197ba5f4SPaul Zimmerman * 1049197ba5f4SPaul Zimmerman * 8 or 16 bits (default 16) 1050197ba5f4SPaul Zimmerman */ 1051197ba5f4SPaul Zimmerman extern void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val); 1052197ba5f4SPaul Zimmerman 1053197ba5f4SPaul Zimmerman /* 1054197ba5f4SPaul Zimmerman * Specifies whether the ULPI operates at double or single 1055197ba5f4SPaul Zimmerman * data rate. This parameter is only applicable if PHY_TYPE is 1056197ba5f4SPaul Zimmerman * ULPI. 1057197ba5f4SPaul Zimmerman * 1058197ba5f4SPaul Zimmerman * 0 - single data rate ULPI interface with 8 bit wide data 1059197ba5f4SPaul Zimmerman * bus (default) 1060197ba5f4SPaul Zimmerman * 1 - double data rate ULPI interface with 4 bit wide data 1061197ba5f4SPaul Zimmerman * bus 1062197ba5f4SPaul Zimmerman */ 1063197ba5f4SPaul Zimmerman extern void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val); 1064197ba5f4SPaul Zimmerman 1065197ba5f4SPaul Zimmerman /* 1066197ba5f4SPaul Zimmerman * Specifies whether to use the internal or external supply to 1067197ba5f4SPaul Zimmerman * drive the vbus with a ULPI phy. 1068197ba5f4SPaul Zimmerman */ 1069197ba5f4SPaul Zimmerman extern void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val); 1070197ba5f4SPaul Zimmerman #define DWC2_PHY_ULPI_INTERNAL_VBUS 0 1071197ba5f4SPaul Zimmerman #define DWC2_PHY_ULPI_EXTERNAL_VBUS 1 1072197ba5f4SPaul Zimmerman 1073197ba5f4SPaul Zimmerman /* 1074197ba5f4SPaul Zimmerman * Specifies whether to use the I2Cinterface for full speed PHY. This 1075197ba5f4SPaul Zimmerman * parameter is only applicable if PHY_TYPE is FS. 1076197ba5f4SPaul Zimmerman * 0 - No (default) 1077197ba5f4SPaul Zimmerman * 1 - Yes 1078197ba5f4SPaul Zimmerman */ 1079197ba5f4SPaul Zimmerman extern void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val); 1080197ba5f4SPaul Zimmerman 1081197ba5f4SPaul Zimmerman extern void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val); 1082197ba5f4SPaul Zimmerman 1083197ba5f4SPaul Zimmerman extern void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val); 1084197ba5f4SPaul Zimmerman 1085197ba5f4SPaul Zimmerman /* 1086197ba5f4SPaul Zimmerman * Specifies whether dedicated transmit FIFOs are 1087197ba5f4SPaul Zimmerman * enabled for non periodic IN endpoints in device mode 1088197ba5f4SPaul Zimmerman * 0 - No 1089197ba5f4SPaul Zimmerman * 1 - Yes 1090197ba5f4SPaul Zimmerman */ 1091197ba5f4SPaul Zimmerman extern void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, 1092197ba5f4SPaul Zimmerman int val); 1093197ba5f4SPaul Zimmerman 1094197ba5f4SPaul Zimmerman extern void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val); 1095197ba5f4SPaul Zimmerman 1096197ba5f4SPaul Zimmerman extern void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val); 1097197ba5f4SPaul Zimmerman 1098197ba5f4SPaul Zimmerman extern void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val); 1099197ba5f4SPaul Zimmerman 1100ecb176c6SMian Yousaf Kaukab extern void dwc2_set_parameters(struct dwc2_hsotg *hsotg, 1101ecb176c6SMian Yousaf Kaukab const struct dwc2_core_params *params); 1102ecb176c6SMian Yousaf Kaukab 1103ecb176c6SMian Yousaf Kaukab extern void dwc2_set_all_params(struct dwc2_core_params *params, int value); 1104ecb176c6SMian Yousaf Kaukab 1105ecb176c6SMian Yousaf Kaukab extern int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); 1106ecb176c6SMian Yousaf Kaukab 1107ecb176c6SMian Yousaf Kaukab 1108ecb176c6SMian Yousaf Kaukab 1109197ba5f4SPaul Zimmerman /* 1110197ba5f4SPaul Zimmerman * Dump core registers and SPRAM 1111197ba5f4SPaul Zimmerman */ 1112197ba5f4SPaul Zimmerman extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 1113197ba5f4SPaul Zimmerman extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 1114197ba5f4SPaul Zimmerman extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 1115197ba5f4SPaul Zimmerman 1116197ba5f4SPaul Zimmerman /* 1117197ba5f4SPaul Zimmerman * Return OTG version - either 1.3 or 2.0 1118197ba5f4SPaul Zimmerman */ 1119197ba5f4SPaul Zimmerman extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg); 1120197ba5f4SPaul Zimmerman 1121117777b2SDinh Nguyen /* Gadget defines */ 1122117777b2SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 11231f91b4ccSFelipe Balbi extern int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg); 11241f91b4ccSFelipe Balbi extern int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2); 11251f91b4ccSFelipe Balbi extern int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2); 1126117777b2SDinh Nguyen extern int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq); 11271f91b4ccSFelipe Balbi extern void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1128643cc4deSGregory Herrero bool reset); 11291f91b4ccSFelipe Balbi extern void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg); 11301f91b4ccSFelipe Balbi extern void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2); 11311f91b4ccSFelipe Balbi extern int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode); 1132f81f46e1SGregory Herrero #define dwc2_is_device_connected(hsotg) (hsotg->connected) 1133117777b2SDinh Nguyen #else 11341f91b4ccSFelipe Balbi static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2) 1135117777b2SDinh Nguyen { return 0; } 11361f91b4ccSFelipe Balbi static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2) 1137117777b2SDinh Nguyen { return 0; } 11381f91b4ccSFelipe Balbi static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2) 1139117777b2SDinh Nguyen { return 0; } 1140117777b2SDinh Nguyen static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) 1141117777b2SDinh Nguyen { return 0; } 11421f91b4ccSFelipe Balbi static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1143643cc4deSGregory Herrero bool reset) {} 11441f91b4ccSFelipe Balbi static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} 11451f91b4ccSFelipe Balbi static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} 11461f91b4ccSFelipe Balbi static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, 1147f91eea44SMian Yousaf Kaukab int testmode) 1148f91eea44SMian Yousaf Kaukab { return 0; } 1149f81f46e1SGregory Herrero #define dwc2_is_device_connected(hsotg) (0) 1150117777b2SDinh Nguyen #endif 1151117777b2SDinh Nguyen 1152117777b2SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1153117777b2SDinh Nguyen extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 1154117777b2SDinh Nguyen extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg); 1155117777b2SDinh Nguyen extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 1156117777b2SDinh Nguyen #else 1157117777b2SDinh Nguyen static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1158117777b2SDinh Nguyen { return 0; } 1159117777b2SDinh Nguyen static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg) {} 1160117777b2SDinh Nguyen static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} 1161117777b2SDinh Nguyen static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} 1162ecb176c6SMian Yousaf Kaukab static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) 1163117777b2SDinh Nguyen { return 0; } 1164117777b2SDinh Nguyen #endif 1165117777b2SDinh Nguyen 1166197ba5f4SPaul Zimmerman #endif /* __DWC2_CORE_H__ */ 1167