1197ba5f4SPaul Zimmerman /* 2197ba5f4SPaul Zimmerman * core.h - DesignWare HS OTG Controller common declarations 3197ba5f4SPaul Zimmerman * 4197ba5f4SPaul Zimmerman * Copyright (C) 2004-2013 Synopsys, Inc. 5197ba5f4SPaul Zimmerman * 6197ba5f4SPaul Zimmerman * Redistribution and use in source and binary forms, with or without 7197ba5f4SPaul Zimmerman * modification, are permitted provided that the following conditions 8197ba5f4SPaul Zimmerman * are met: 9197ba5f4SPaul Zimmerman * 1. Redistributions of source code must retain the above copyright 10197ba5f4SPaul Zimmerman * notice, this list of conditions, and the following disclaimer, 11197ba5f4SPaul Zimmerman * without modification. 12197ba5f4SPaul Zimmerman * 2. Redistributions in binary form must reproduce the above copyright 13197ba5f4SPaul Zimmerman * notice, this list of conditions and the following disclaimer in the 14197ba5f4SPaul Zimmerman * documentation and/or other materials provided with the distribution. 15197ba5f4SPaul Zimmerman * 3. The names of the above-listed copyright holders may not be used 16197ba5f4SPaul Zimmerman * to endorse or promote products derived from this software without 17197ba5f4SPaul Zimmerman * specific prior written permission. 18197ba5f4SPaul Zimmerman * 19197ba5f4SPaul Zimmerman * ALTERNATIVELY, this software may be distributed under the terms of the 20197ba5f4SPaul Zimmerman * GNU General Public License ("GPL") as published by the Free Software 21197ba5f4SPaul Zimmerman * Foundation; either version 2 of the License, or (at your option) any 22197ba5f4SPaul Zimmerman * later version. 23197ba5f4SPaul Zimmerman * 24197ba5f4SPaul Zimmerman * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25197ba5f4SPaul Zimmerman * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26197ba5f4SPaul Zimmerman * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27197ba5f4SPaul Zimmerman * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28197ba5f4SPaul Zimmerman * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29197ba5f4SPaul Zimmerman * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30197ba5f4SPaul Zimmerman * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31197ba5f4SPaul Zimmerman * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32197ba5f4SPaul Zimmerman * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33197ba5f4SPaul Zimmerman * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34197ba5f4SPaul Zimmerman * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35197ba5f4SPaul Zimmerman */ 36197ba5f4SPaul Zimmerman 37197ba5f4SPaul Zimmerman #ifndef __DWC2_CORE_H__ 38197ba5f4SPaul Zimmerman #define __DWC2_CORE_H__ 39197ba5f4SPaul Zimmerman 40f7c0b143SDinh Nguyen #include <linux/phy/phy.h> 41f7c0b143SDinh Nguyen #include <linux/regulator/consumer.h> 42f7c0b143SDinh Nguyen #include <linux/usb/gadget.h> 43f7c0b143SDinh Nguyen #include <linux/usb/otg.h> 44197ba5f4SPaul Zimmerman #include <linux/usb/phy.h> 45197ba5f4SPaul Zimmerman #include "hw.h" 46197ba5f4SPaul Zimmerman 47197ba5f4SPaul Zimmerman #ifdef DWC2_LOG_WRITES 48197ba5f4SPaul Zimmerman static inline void do_write(u32 value, void *addr) 49197ba5f4SPaul Zimmerman { 50197ba5f4SPaul Zimmerman writel(value, addr); 51197ba5f4SPaul Zimmerman pr_info("INFO:: wrote %08x to %p\n", value, addr); 52197ba5f4SPaul Zimmerman } 53197ba5f4SPaul Zimmerman 54197ba5f4SPaul Zimmerman #undef writel 55197ba5f4SPaul Zimmerman #define writel(v, a) do_write(v, a) 56197ba5f4SPaul Zimmerman #endif 57197ba5f4SPaul Zimmerman 58197ba5f4SPaul Zimmerman /* Maximum number of Endpoints/HostChannels */ 59197ba5f4SPaul Zimmerman #define MAX_EPS_CHANNELS 16 60197ba5f4SPaul Zimmerman 61f7c0b143SDinh Nguyen /* s3c-hsotg declarations */ 62f7c0b143SDinh Nguyen static const char * const s3c_hsotg_supply_names[] = { 63f7c0b143SDinh Nguyen "vusb_d", /* digital USB supply, 1.2V */ 64f7c0b143SDinh Nguyen "vusb_a", /* analog USB supply, 1.1V */ 65f7c0b143SDinh Nguyen }; 66f7c0b143SDinh Nguyen 67f7c0b143SDinh Nguyen /* 68f7c0b143SDinh Nguyen * EP0_MPS_LIMIT 69f7c0b143SDinh Nguyen * 70f7c0b143SDinh Nguyen * Unfortunately there seems to be a limit of the amount of data that can 71f7c0b143SDinh Nguyen * be transferred by IN transactions on EP0. This is either 127 bytes or 3 72f7c0b143SDinh Nguyen * packets (which practically means 1 packet and 63 bytes of data) when the 73f7c0b143SDinh Nguyen * MPS is set to 64. 74f7c0b143SDinh Nguyen * 75f7c0b143SDinh Nguyen * This means if we are wanting to move >127 bytes of data, we need to 76f7c0b143SDinh Nguyen * split the transactions up, but just doing one packet at a time does 77f7c0b143SDinh Nguyen * not work (this may be an implicit DATA0 PID on first packet of the 78f7c0b143SDinh Nguyen * transaction) and doing 2 packets is outside the controller's limits. 79f7c0b143SDinh Nguyen * 80f7c0b143SDinh Nguyen * If we try to lower the MPS size for EP0, then no transfers work properly 81f7c0b143SDinh Nguyen * for EP0, and the system will fail basic enumeration. As no cause for this 82f7c0b143SDinh Nguyen * has currently been found, we cannot support any large IN transfers for 83f7c0b143SDinh Nguyen * EP0. 84f7c0b143SDinh Nguyen */ 85f7c0b143SDinh Nguyen #define EP0_MPS_LIMIT 64 86f7c0b143SDinh Nguyen 87941fcce4SDinh Nguyen struct dwc2_hsotg; 88f7c0b143SDinh Nguyen struct s3c_hsotg_req; 89f7c0b143SDinh Nguyen 90f7c0b143SDinh Nguyen /** 91f7c0b143SDinh Nguyen * struct s3c_hsotg_ep - driver endpoint definition. 92f7c0b143SDinh Nguyen * @ep: The gadget layer representation of the endpoint. 93f7c0b143SDinh Nguyen * @name: The driver generated name for the endpoint. 94f7c0b143SDinh Nguyen * @queue: Queue of requests for this endpoint. 95f7c0b143SDinh Nguyen * @parent: Reference back to the parent device structure. 96f7c0b143SDinh Nguyen * @req: The current request that the endpoint is processing. This is 97f7c0b143SDinh Nguyen * used to indicate an request has been loaded onto the endpoint 98f7c0b143SDinh Nguyen * and has yet to be completed (maybe due to data move, or simply 99f7c0b143SDinh Nguyen * awaiting an ack from the core all the data has been completed). 100f7c0b143SDinh Nguyen * @debugfs: File entry for debugfs file for this endpoint. 101f7c0b143SDinh Nguyen * @lock: State lock to protect contents of endpoint. 102f7c0b143SDinh Nguyen * @dir_in: Set to true if this endpoint is of the IN direction, which 103f7c0b143SDinh Nguyen * means that it is sending data to the Host. 104f7c0b143SDinh Nguyen * @index: The index for the endpoint registers. 105f7c0b143SDinh Nguyen * @mc: Multi Count - number of transactions per microframe 106f7c0b143SDinh Nguyen * @interval - Interval for periodic endpoints 107f7c0b143SDinh Nguyen * @name: The name array passed to the USB core. 108f7c0b143SDinh Nguyen * @halted: Set if the endpoint has been halted. 109f7c0b143SDinh Nguyen * @periodic: Set if this is a periodic ep, such as Interrupt 110f7c0b143SDinh Nguyen * @isochronous: Set if this is a isochronous ep 1118a20fa45SMian Yousaf Kaukab * @send_zlp: Set if we need to send a zero-length packet. 112f7c0b143SDinh Nguyen * @total_data: The total number of data bytes done. 113f7c0b143SDinh Nguyen * @fifo_size: The size of the FIFO (for periodic IN endpoints) 114f7c0b143SDinh Nguyen * @fifo_load: The amount of data loaded into the FIFO (periodic IN) 115f7c0b143SDinh Nguyen * @last_load: The offset of data for the last start of request. 116f7c0b143SDinh Nguyen * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN 117f7c0b143SDinh Nguyen * 118f7c0b143SDinh Nguyen * This is the driver's state for each registered enpoint, allowing it 119f7c0b143SDinh Nguyen * to keep track of transactions that need doing. Each endpoint has a 120f7c0b143SDinh Nguyen * lock to protect the state, to try and avoid using an overall lock 121f7c0b143SDinh Nguyen * for the host controller as much as possible. 122f7c0b143SDinh Nguyen * 123f7c0b143SDinh Nguyen * For periodic IN endpoints, we have fifo_size and fifo_load to try 124f7c0b143SDinh Nguyen * and keep track of the amount of data in the periodic FIFO for each 125f7c0b143SDinh Nguyen * of these as we don't have a status register that tells us how much 126f7c0b143SDinh Nguyen * is in each of them. (note, this may actually be useless information 127f7c0b143SDinh Nguyen * as in shared-fifo mode periodic in acts like a single-frame packet 128f7c0b143SDinh Nguyen * buffer than a fifo) 129f7c0b143SDinh Nguyen */ 130f7c0b143SDinh Nguyen struct s3c_hsotg_ep { 131f7c0b143SDinh Nguyen struct usb_ep ep; 132f7c0b143SDinh Nguyen struct list_head queue; 133941fcce4SDinh Nguyen struct dwc2_hsotg *parent; 134f7c0b143SDinh Nguyen struct s3c_hsotg_req *req; 135f7c0b143SDinh Nguyen struct dentry *debugfs; 136f7c0b143SDinh Nguyen 137f7c0b143SDinh Nguyen unsigned long total_data; 138f7c0b143SDinh Nguyen unsigned int size_loaded; 139f7c0b143SDinh Nguyen unsigned int last_load; 140f7c0b143SDinh Nguyen unsigned int fifo_load; 141f7c0b143SDinh Nguyen unsigned short fifo_size; 142b203d0a2SRobert Baldyga unsigned short fifo_index; 143f7c0b143SDinh Nguyen 144f7c0b143SDinh Nguyen unsigned char dir_in; 145f7c0b143SDinh Nguyen unsigned char index; 146f7c0b143SDinh Nguyen unsigned char mc; 147f7c0b143SDinh Nguyen unsigned char interval; 148f7c0b143SDinh Nguyen 149f7c0b143SDinh Nguyen unsigned int halted:1; 150f7c0b143SDinh Nguyen unsigned int periodic:1; 151f7c0b143SDinh Nguyen unsigned int isochronous:1; 1528a20fa45SMian Yousaf Kaukab unsigned int send_zlp:1; 153f7c0b143SDinh Nguyen 154f7c0b143SDinh Nguyen char name[10]; 155f7c0b143SDinh Nguyen }; 156f7c0b143SDinh Nguyen 157f7c0b143SDinh Nguyen /** 158f7c0b143SDinh Nguyen * struct s3c_hsotg_req - data transfer request 159f7c0b143SDinh Nguyen * @req: The USB gadget request 160f7c0b143SDinh Nguyen * @queue: The list of requests for the endpoint this is queued for. 1617d24c1b5SMian Yousaf Kaukab * @saved_req_buf: variable to save req.buf when bounce buffers are used. 162f7c0b143SDinh Nguyen */ 163f7c0b143SDinh Nguyen struct s3c_hsotg_req { 164f7c0b143SDinh Nguyen struct usb_request req; 165f7c0b143SDinh Nguyen struct list_head queue; 1667d24c1b5SMian Yousaf Kaukab void *saved_req_buf; 167f7c0b143SDinh Nguyen }; 168f7c0b143SDinh Nguyen 169941fcce4SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 170f7c0b143SDinh Nguyen #define call_gadget(_hs, _entry) \ 171f7c0b143SDinh Nguyen do { \ 172f7c0b143SDinh Nguyen if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ 173f7c0b143SDinh Nguyen (_hs)->driver && (_hs)->driver->_entry) { \ 174f7c0b143SDinh Nguyen spin_unlock(&_hs->lock); \ 175f7c0b143SDinh Nguyen (_hs)->driver->_entry(&(_hs)->gadget); \ 176f7c0b143SDinh Nguyen spin_lock(&_hs->lock); \ 177f7c0b143SDinh Nguyen } \ 178f7c0b143SDinh Nguyen } while (0) 179941fcce4SDinh Nguyen #else 180941fcce4SDinh Nguyen #define call_gadget(_hs, _entry) do {} while (0) 181941fcce4SDinh Nguyen #endif 182f7c0b143SDinh Nguyen 183197ba5f4SPaul Zimmerman struct dwc2_hsotg; 184197ba5f4SPaul Zimmerman struct dwc2_host_chan; 185197ba5f4SPaul Zimmerman 186197ba5f4SPaul Zimmerman /* Device States */ 187197ba5f4SPaul Zimmerman enum dwc2_lx_state { 188197ba5f4SPaul Zimmerman DWC2_L0, /* On state */ 189197ba5f4SPaul Zimmerman DWC2_L1, /* LPM sleep state */ 190197ba5f4SPaul Zimmerman DWC2_L2, /* USB suspend state */ 191197ba5f4SPaul Zimmerman DWC2_L3, /* Off state */ 192197ba5f4SPaul Zimmerman }; 193197ba5f4SPaul Zimmerman 1940a176279SGregory Herrero /* 1950a176279SGregory Herrero * Gadget periodic tx fifo sizes as used by legacy driver 1960a176279SGregory Herrero * EP0 is not included 1970a176279SGregory Herrero */ 1980a176279SGregory Herrero #define DWC2_G_P_LEGACY_TX_FIFO_SIZE {256, 256, 256, 256, 768, 768, 768, \ 1990a176279SGregory Herrero 768, 0, 0, 0, 0, 0, 0, 0} 2000a176279SGregory Herrero 201fe0b94abSMian Yousaf Kaukab /* Gadget ep0 states */ 202fe0b94abSMian Yousaf Kaukab enum dwc2_ep0_state { 203fe0b94abSMian Yousaf Kaukab DWC2_EP0_SETUP, 204fe0b94abSMian Yousaf Kaukab DWC2_EP0_DATA_IN, 205fe0b94abSMian Yousaf Kaukab DWC2_EP0_DATA_OUT, 206fe0b94abSMian Yousaf Kaukab DWC2_EP0_STATUS_IN, 207fe0b94abSMian Yousaf Kaukab DWC2_EP0_STATUS_OUT, 208fe0b94abSMian Yousaf Kaukab }; 209fe0b94abSMian Yousaf Kaukab 210197ba5f4SPaul Zimmerman /** 211197ba5f4SPaul Zimmerman * struct dwc2_core_params - Parameters for configuring the core 212197ba5f4SPaul Zimmerman * 213197ba5f4SPaul Zimmerman * @otg_cap: Specifies the OTG capabilities. 214197ba5f4SPaul Zimmerman * 0 - HNP and SRP capable 215197ba5f4SPaul Zimmerman * 1 - SRP Only capable 216197ba5f4SPaul Zimmerman * 2 - No HNP/SRP capable (always available) 217197ba5f4SPaul Zimmerman * Defaults to best available option (0, 1, then 2) 218197ba5f4SPaul Zimmerman * @otg_ver: OTG version supported 219197ba5f4SPaul Zimmerman * 0 - 1.3 (default) 220197ba5f4SPaul Zimmerman * 1 - 2.0 221197ba5f4SPaul Zimmerman * @dma_enable: Specifies whether to use slave or DMA mode for accessing 222197ba5f4SPaul Zimmerman * the data FIFOs. The driver will automatically detect the 223197ba5f4SPaul Zimmerman * value for this parameter if none is specified. 224197ba5f4SPaul Zimmerman * 0 - Slave (always available) 225197ba5f4SPaul Zimmerman * 1 - DMA (default, if available) 226197ba5f4SPaul Zimmerman * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 227197ba5f4SPaul Zimmerman * address DMA mode or descriptor DMA mode for accessing 228197ba5f4SPaul Zimmerman * the data FIFOs. The driver will automatically detect the 229197ba5f4SPaul Zimmerman * value for this if none is specified. 230197ba5f4SPaul Zimmerman * 0 - Address DMA 231197ba5f4SPaul Zimmerman * 1 - Descriptor DMA (default, if available) 232197ba5f4SPaul Zimmerman * @speed: Specifies the maximum speed of operation in host and 233197ba5f4SPaul Zimmerman * device mode. The actual speed depends on the speed of 234197ba5f4SPaul Zimmerman * the attached device and the value of phy_type. 235197ba5f4SPaul Zimmerman * 0 - High Speed 236197ba5f4SPaul Zimmerman * (default when phy_type is UTMI+ or ULPI) 237197ba5f4SPaul Zimmerman * 1 - Full Speed 238197ba5f4SPaul Zimmerman * (default when phy_type is Full Speed) 239197ba5f4SPaul Zimmerman * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 240197ba5f4SPaul Zimmerman * 1 - Allow dynamic FIFO sizing (default, if available) 241197ba5f4SPaul Zimmerman * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 242197ba5f4SPaul Zimmerman * are enabled 243197ba5f4SPaul Zimmerman * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 244197ba5f4SPaul Zimmerman * dynamic FIFO sizing is enabled 245197ba5f4SPaul Zimmerman * 16 to 32768 246197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 247197ba5f4SPaul Zimmerman * the default. 248197ba5f4SPaul Zimmerman * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 249197ba5f4SPaul Zimmerman * in host mode when dynamic FIFO sizing is enabled 250197ba5f4SPaul Zimmerman * 16 to 32768 251197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 252197ba5f4SPaul Zimmerman * the default. 253197ba5f4SPaul Zimmerman * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 254197ba5f4SPaul Zimmerman * host mode when dynamic FIFO sizing is enabled 255197ba5f4SPaul Zimmerman * 16 to 32768 256197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 257197ba5f4SPaul Zimmerman * the default. 258197ba5f4SPaul Zimmerman * @max_transfer_size: The maximum transfer size supported, in bytes 259197ba5f4SPaul Zimmerman * 2047 to 65,535 260197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 261197ba5f4SPaul Zimmerman * the default. 262197ba5f4SPaul Zimmerman * @max_packet_count: The maximum number of packets in a transfer 263197ba5f4SPaul Zimmerman * 15 to 511 264197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 265197ba5f4SPaul Zimmerman * the default. 266197ba5f4SPaul Zimmerman * @host_channels: The number of host channel registers to use 267197ba5f4SPaul Zimmerman * 1 to 16 268197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 269197ba5f4SPaul Zimmerman * the default. 270197ba5f4SPaul Zimmerman * @phy_type: Specifies the type of PHY interface to use. By default, 271197ba5f4SPaul Zimmerman * the driver will automatically detect the phy_type. 272197ba5f4SPaul Zimmerman * 0 - Full Speed Phy 273197ba5f4SPaul Zimmerman * 1 - UTMI+ Phy 274197ba5f4SPaul Zimmerman * 2 - ULPI Phy 275197ba5f4SPaul Zimmerman * Defaults to best available option (2, 1, then 0) 276197ba5f4SPaul Zimmerman * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 277197ba5f4SPaul Zimmerman * is applicable for a phy_type of UTMI+ or ULPI. (For a 278197ba5f4SPaul Zimmerman * ULPI phy_type, this parameter indicates the data width 279197ba5f4SPaul Zimmerman * between the MAC and the ULPI Wrapper.) Also, this 280197ba5f4SPaul Zimmerman * parameter is applicable only if the OTG_HSPHY_WIDTH cC 281197ba5f4SPaul Zimmerman * parameter was set to "8 and 16 bits", meaning that the 282197ba5f4SPaul Zimmerman * core has been configured to work at either data path 283197ba5f4SPaul Zimmerman * width. 284197ba5f4SPaul Zimmerman * 8 or 16 (default 16 if available) 285197ba5f4SPaul Zimmerman * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 286197ba5f4SPaul Zimmerman * data rate. This parameter is only applicable if phy_type 287197ba5f4SPaul Zimmerman * is ULPI. 288197ba5f4SPaul Zimmerman * 0 - single data rate ULPI interface with 8 bit wide 289197ba5f4SPaul Zimmerman * data bus (default) 290197ba5f4SPaul Zimmerman * 1 - double data rate ULPI interface with 4 bit wide 291197ba5f4SPaul Zimmerman * data bus 292197ba5f4SPaul Zimmerman * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 293197ba5f4SPaul Zimmerman * external supply to drive the VBus 294197ba5f4SPaul Zimmerman * 0 - Internal supply (default) 295197ba5f4SPaul Zimmerman * 1 - External supply 296197ba5f4SPaul Zimmerman * @i2c_enable: Specifies whether to use the I2Cinterface for a full 297197ba5f4SPaul Zimmerman * speed PHY. This parameter is only applicable if phy_type 298197ba5f4SPaul Zimmerman * is FS. 299197ba5f4SPaul Zimmerman * 0 - No (default) 300197ba5f4SPaul Zimmerman * 1 - Yes 301197ba5f4SPaul Zimmerman * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 302197ba5f4SPaul Zimmerman * 0 - No (default) 303197ba5f4SPaul Zimmerman * 1 - Yes 304197ba5f4SPaul Zimmerman * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 305197ba5f4SPaul Zimmerman * when attached to a Full Speed or Low Speed device in 306197ba5f4SPaul Zimmerman * host mode. 307197ba5f4SPaul Zimmerman * 0 - Don't support low power mode (default) 308197ba5f4SPaul Zimmerman * 1 - Support low power mode 309197ba5f4SPaul Zimmerman * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 310197ba5f4SPaul Zimmerman * when connected to a Low Speed device in host 311197ba5f4SPaul Zimmerman * mode. This parameter is applicable only if 312197ba5f4SPaul Zimmerman * host_support_fs_ls_low_power is enabled. 313197ba5f4SPaul Zimmerman * 0 - 48 MHz 314197ba5f4SPaul Zimmerman * (default when phy_type is UTMI+ or ULPI) 315197ba5f4SPaul Zimmerman * 1 - 6 MHz 316197ba5f4SPaul Zimmerman * (default when phy_type is Full Speed) 317197ba5f4SPaul Zimmerman * @ts_dline: Enable Term Select Dline pulsing 318197ba5f4SPaul Zimmerman * 0 - No (default) 319197ba5f4SPaul Zimmerman * 1 - Yes 320197ba5f4SPaul Zimmerman * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 321197ba5f4SPaul Zimmerman * 0 - No (default for core < 2.92a) 322197ba5f4SPaul Zimmerman * 1 - Yes (default for core >= 2.92a) 323197ba5f4SPaul Zimmerman * @ahbcfg: This field allows the default value of the GAHBCFG 324197ba5f4SPaul Zimmerman * register to be overridden 325197ba5f4SPaul Zimmerman * -1 - GAHBCFG value will be set to 0x06 326197ba5f4SPaul Zimmerman * (INCR4, default) 327197ba5f4SPaul Zimmerman * all others - GAHBCFG value will be overridden with 328197ba5f4SPaul Zimmerman * this value 329197ba5f4SPaul Zimmerman * Not all bits can be controlled like this, the 330197ba5f4SPaul Zimmerman * bits defined by GAHBCFG_CTRL_MASK are controlled 331197ba5f4SPaul Zimmerman * by the driver and are ignored in this 332197ba5f4SPaul Zimmerman * configuration value. 333197ba5f4SPaul Zimmerman * @uframe_sched: True to enable the microframe scheduler 334197ba5f4SPaul Zimmerman * 335197ba5f4SPaul Zimmerman * The following parameters may be specified when starting the module. These 336197ba5f4SPaul Zimmerman * parameters define how the DWC_otg controller should be configured. A 337197ba5f4SPaul Zimmerman * value of -1 (or any other out of range value) for any parameter means 338197ba5f4SPaul Zimmerman * to read the value from hardware (if possible) or use the builtin 339197ba5f4SPaul Zimmerman * default described above. 340197ba5f4SPaul Zimmerman */ 341197ba5f4SPaul Zimmerman struct dwc2_core_params { 342197ba5f4SPaul Zimmerman /* 343197ba5f4SPaul Zimmerman * Don't add any non-int members here, this will break 344197ba5f4SPaul Zimmerman * dwc2_set_all_params! 345197ba5f4SPaul Zimmerman */ 346197ba5f4SPaul Zimmerman int otg_cap; 347197ba5f4SPaul Zimmerman int otg_ver; 348197ba5f4SPaul Zimmerman int dma_enable; 349197ba5f4SPaul Zimmerman int dma_desc_enable; 350197ba5f4SPaul Zimmerman int speed; 351197ba5f4SPaul Zimmerman int enable_dynamic_fifo; 352197ba5f4SPaul Zimmerman int en_multiple_tx_fifo; 353197ba5f4SPaul Zimmerman int host_rx_fifo_size; 354197ba5f4SPaul Zimmerman int host_nperio_tx_fifo_size; 355197ba5f4SPaul Zimmerman int host_perio_tx_fifo_size; 356197ba5f4SPaul Zimmerman int max_transfer_size; 357197ba5f4SPaul Zimmerman int max_packet_count; 358197ba5f4SPaul Zimmerman int host_channels; 359197ba5f4SPaul Zimmerman int phy_type; 360197ba5f4SPaul Zimmerman int phy_utmi_width; 361197ba5f4SPaul Zimmerman int phy_ulpi_ddr; 362197ba5f4SPaul Zimmerman int phy_ulpi_ext_vbus; 363197ba5f4SPaul Zimmerman int i2c_enable; 364197ba5f4SPaul Zimmerman int ulpi_fs_ls; 365197ba5f4SPaul Zimmerman int host_support_fs_ls_low_power; 366197ba5f4SPaul Zimmerman int host_ls_low_power_phy_clk; 367197ba5f4SPaul Zimmerman int ts_dline; 368197ba5f4SPaul Zimmerman int reload_ctl; 369197ba5f4SPaul Zimmerman int ahbcfg; 370197ba5f4SPaul Zimmerman int uframe_sched; 371197ba5f4SPaul Zimmerman }; 372197ba5f4SPaul Zimmerman 373197ba5f4SPaul Zimmerman /** 374197ba5f4SPaul Zimmerman * struct dwc2_hw_params - Autodetected parameters. 375197ba5f4SPaul Zimmerman * 376197ba5f4SPaul Zimmerman * These parameters are the various parameters read from hardware 377197ba5f4SPaul Zimmerman * registers during initialization. They typically contain the best 378197ba5f4SPaul Zimmerman * supported or maximum value that can be configured in the 379197ba5f4SPaul Zimmerman * corresponding dwc2_core_params value. 380197ba5f4SPaul Zimmerman * 381197ba5f4SPaul Zimmerman * The values that are not in dwc2_core_params are documented below. 382197ba5f4SPaul Zimmerman * 383197ba5f4SPaul Zimmerman * @op_mode Mode of Operation 384197ba5f4SPaul Zimmerman * 0 - HNP- and SRP-Capable OTG (Host & Device) 385197ba5f4SPaul Zimmerman * 1 - SRP-Capable OTG (Host & Device) 386197ba5f4SPaul Zimmerman * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 387197ba5f4SPaul Zimmerman * 3 - SRP-Capable Device 388197ba5f4SPaul Zimmerman * 4 - Non-OTG Device 389197ba5f4SPaul Zimmerman * 5 - SRP-Capable Host 390197ba5f4SPaul Zimmerman * 6 - Non-OTG Host 391197ba5f4SPaul Zimmerman * @arch Architecture 392197ba5f4SPaul Zimmerman * 0 - Slave only 393197ba5f4SPaul Zimmerman * 1 - External DMA 394197ba5f4SPaul Zimmerman * 2 - Internal DMA 395197ba5f4SPaul Zimmerman * @power_optimized Are power optimizations enabled? 396197ba5f4SPaul Zimmerman * @num_dev_ep Number of device endpoints available 397197ba5f4SPaul Zimmerman * @num_dev_perio_in_ep Number of device periodic IN endpoints 398997f4f81SMickael Maison * available 399197ba5f4SPaul Zimmerman * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue 400197ba5f4SPaul Zimmerman * Depth 401197ba5f4SPaul Zimmerman * 0 to 30 402197ba5f4SPaul Zimmerman * @host_perio_tx_q_depth 403197ba5f4SPaul Zimmerman * Host Mode Periodic Request Queue Depth 404197ba5f4SPaul Zimmerman * 2, 4 or 8 405197ba5f4SPaul Zimmerman * @nperio_tx_q_depth 406197ba5f4SPaul Zimmerman * Non-Periodic Request Queue Depth 407197ba5f4SPaul Zimmerman * 2, 4 or 8 408197ba5f4SPaul Zimmerman * @hs_phy_type High-speed PHY interface type 409197ba5f4SPaul Zimmerman * 0 - High-speed interface not supported 410197ba5f4SPaul Zimmerman * 1 - UTMI+ 411197ba5f4SPaul Zimmerman * 2 - ULPI 412197ba5f4SPaul Zimmerman * 3 - UTMI+ and ULPI 413197ba5f4SPaul Zimmerman * @fs_phy_type Full-speed PHY interface type 414197ba5f4SPaul Zimmerman * 0 - Full speed interface not supported 415197ba5f4SPaul Zimmerman * 1 - Dedicated full speed interface 416197ba5f4SPaul Zimmerman * 2 - FS pins shared with UTMI+ pins 417197ba5f4SPaul Zimmerman * 3 - FS pins shared with ULPI pins 418197ba5f4SPaul Zimmerman * @total_fifo_size: Total internal RAM for FIFOs (bytes) 419197ba5f4SPaul Zimmerman * @utmi_phy_data_width UTMI+ PHY data width 420197ba5f4SPaul Zimmerman * 0 - 8 bits 421197ba5f4SPaul Zimmerman * 1 - 16 bits 422197ba5f4SPaul Zimmerman * 2 - 8 or 16 bits 423197ba5f4SPaul Zimmerman * @snpsid: Value from SNPSID register 424197ba5f4SPaul Zimmerman */ 425197ba5f4SPaul Zimmerman struct dwc2_hw_params { 426197ba5f4SPaul Zimmerman unsigned op_mode:3; 427197ba5f4SPaul Zimmerman unsigned arch:2; 428197ba5f4SPaul Zimmerman unsigned dma_desc_enable:1; 429197ba5f4SPaul Zimmerman unsigned enable_dynamic_fifo:1; 430197ba5f4SPaul Zimmerman unsigned en_multiple_tx_fifo:1; 431197ba5f4SPaul Zimmerman unsigned host_rx_fifo_size:16; 432197ba5f4SPaul Zimmerman unsigned host_nperio_tx_fifo_size:16; 433197ba5f4SPaul Zimmerman unsigned host_perio_tx_fifo_size:16; 434197ba5f4SPaul Zimmerman unsigned nperio_tx_q_depth:3; 435197ba5f4SPaul Zimmerman unsigned host_perio_tx_q_depth:3; 436197ba5f4SPaul Zimmerman unsigned dev_token_q_depth:5; 437197ba5f4SPaul Zimmerman unsigned max_transfer_size:26; 438197ba5f4SPaul Zimmerman unsigned max_packet_count:11; 439197ba5f4SPaul Zimmerman unsigned host_channels:5; 440197ba5f4SPaul Zimmerman unsigned hs_phy_type:2; 441197ba5f4SPaul Zimmerman unsigned fs_phy_type:2; 442197ba5f4SPaul Zimmerman unsigned i2c_enable:1; 443197ba5f4SPaul Zimmerman unsigned num_dev_ep:4; 444197ba5f4SPaul Zimmerman unsigned num_dev_perio_in_ep:4; 445197ba5f4SPaul Zimmerman unsigned total_fifo_size:16; 446197ba5f4SPaul Zimmerman unsigned power_optimized:1; 447197ba5f4SPaul Zimmerman unsigned utmi_phy_data_width:2; 448197ba5f4SPaul Zimmerman u32 snpsid; 449197ba5f4SPaul Zimmerman }; 450197ba5f4SPaul Zimmerman 4513f95001dSMian Yousaf Kaukab /* Size of control and EP0 buffers */ 4523f95001dSMian Yousaf Kaukab #define DWC2_CTRL_BUFF_SIZE 8 4533f95001dSMian Yousaf Kaukab 454197ba5f4SPaul Zimmerman /** 455197ba5f4SPaul Zimmerman * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 456197ba5f4SPaul Zimmerman * and periodic schedules 457197ba5f4SPaul Zimmerman * 458941fcce4SDinh Nguyen * These are common for both host and peripheral modes: 459941fcce4SDinh Nguyen * 460197ba5f4SPaul Zimmerman * @dev: The struct device pointer 461197ba5f4SPaul Zimmerman * @regs: Pointer to controller regs 462197ba5f4SPaul Zimmerman * @hw_params: Parameters that were autodetected from the 463197ba5f4SPaul Zimmerman * hardware registers 464941fcce4SDinh Nguyen * @core_params: Parameters that define how the core should be configured 465197ba5f4SPaul Zimmerman * @op_state: The operational State, during transitions (a_host=> 466197ba5f4SPaul Zimmerman * a_peripheral and b_device=>b_host) this may not match 467197ba5f4SPaul Zimmerman * the core, but allows the software to determine 468197ba5f4SPaul Zimmerman * transitions 469c0155b9dSKever Yang * @dr_mode: Requested mode of operation, one of following: 470c0155b9dSKever Yang * - USB_DR_MODE_PERIPHERAL 471c0155b9dSKever Yang * - USB_DR_MODE_HOST 472c0155b9dSKever Yang * - USB_DR_MODE_OTG 473941fcce4SDinh Nguyen * @lock: Spinlock that protects all the driver data structures 474941fcce4SDinh Nguyen * @priv: Stores a pointer to the struct usb_hcd 475197ba5f4SPaul Zimmerman * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 476197ba5f4SPaul Zimmerman * transfer are in process of being queued 477197ba5f4SPaul Zimmerman * @srp_success: Stores status of SRP request in the case of a FS PHY 478197ba5f4SPaul Zimmerman * with an I2C interface 479197ba5f4SPaul Zimmerman * @wq_otg: Workqueue object used for handling of some interrupts 480197ba5f4SPaul Zimmerman * @wf_otg: Work object for handling Connector ID Status Change 481197ba5f4SPaul Zimmerman * interrupt 482197ba5f4SPaul Zimmerman * @wkp_timer: Timer object for handling Wakeup Detected interrupt 483197ba5f4SPaul Zimmerman * @lx_state: Lx state of connected device 484941fcce4SDinh Nguyen * 485941fcce4SDinh Nguyen * These are for host mode: 486941fcce4SDinh Nguyen * 487197ba5f4SPaul Zimmerman * @flags: Flags for handling root port state changes 488197ba5f4SPaul Zimmerman * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 489197ba5f4SPaul Zimmerman * Transfers associated with these QHs are not currently 490197ba5f4SPaul Zimmerman * assigned to a host channel. 491197ba5f4SPaul Zimmerman * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 492197ba5f4SPaul Zimmerman * Transfers associated with these QHs are currently 493197ba5f4SPaul Zimmerman * assigned to a host channel. 494197ba5f4SPaul Zimmerman * @non_periodic_qh_ptr: Pointer to next QH to process in the active 495197ba5f4SPaul Zimmerman * non-periodic schedule 496197ba5f4SPaul Zimmerman * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 497197ba5f4SPaul Zimmerman * list of QHs for periodic transfers that are _not_ 498197ba5f4SPaul Zimmerman * scheduled for the next frame. Each QH in the list has an 499197ba5f4SPaul Zimmerman * interval counter that determines when it needs to be 500197ba5f4SPaul Zimmerman * scheduled for execution. This scheduling mechanism 501197ba5f4SPaul Zimmerman * allows only a simple calculation for periodic bandwidth 502197ba5f4SPaul Zimmerman * used (i.e. must assume that all periodic transfers may 503197ba5f4SPaul Zimmerman * need to execute in the same frame). However, it greatly 504197ba5f4SPaul Zimmerman * simplifies scheduling and should be sufficient for the 505197ba5f4SPaul Zimmerman * vast majority of OTG hosts, which need to connect to a 506197ba5f4SPaul Zimmerman * small number of peripherals at one time. Items move from 507197ba5f4SPaul Zimmerman * this list to periodic_sched_ready when the QH interval 508197ba5f4SPaul Zimmerman * counter is 0 at SOF. 509197ba5f4SPaul Zimmerman * @periodic_sched_ready: List of periodic QHs that are ready for execution in 510197ba5f4SPaul Zimmerman * the next frame, but have not yet been assigned to host 511197ba5f4SPaul Zimmerman * channels. Items move from this list to 512197ba5f4SPaul Zimmerman * periodic_sched_assigned as host channels become 513197ba5f4SPaul Zimmerman * available during the current frame. 514197ba5f4SPaul Zimmerman * @periodic_sched_assigned: List of periodic QHs to be executed in the next 515197ba5f4SPaul Zimmerman * frame that are assigned to host channels. Items move 516197ba5f4SPaul Zimmerman * from this list to periodic_sched_queued as the 517197ba5f4SPaul Zimmerman * transactions for the QH are queued to the DWC_otg 518197ba5f4SPaul Zimmerman * controller. 519197ba5f4SPaul Zimmerman * @periodic_sched_queued: List of periodic QHs that have been queued for 520197ba5f4SPaul Zimmerman * execution. Items move from this list to either 521197ba5f4SPaul Zimmerman * periodic_sched_inactive or periodic_sched_ready when the 522197ba5f4SPaul Zimmerman * channel associated with the transfer is released. If the 523197ba5f4SPaul Zimmerman * interval for the QH is 1, the item moves to 524197ba5f4SPaul Zimmerman * periodic_sched_ready because it must be rescheduled for 525197ba5f4SPaul Zimmerman * the next frame. Otherwise, the item moves to 526197ba5f4SPaul Zimmerman * periodic_sched_inactive. 527197ba5f4SPaul Zimmerman * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 528197ba5f4SPaul Zimmerman * This value is in microseconds per (micro)frame. The 529197ba5f4SPaul Zimmerman * assumption is that all periodic transfers may occur in 530197ba5f4SPaul Zimmerman * the same (micro)frame. 531197ba5f4SPaul Zimmerman * @frame_usecs: Internal variable used by the microframe scheduler 532197ba5f4SPaul Zimmerman * @frame_number: Frame number read from the core at SOF. The value ranges 533197ba5f4SPaul Zimmerman * from 0 to HFNUM_MAX_FRNUM. 534197ba5f4SPaul Zimmerman * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 535197ba5f4SPaul Zimmerman * SOF enable/disable. 536197ba5f4SPaul Zimmerman * @free_hc_list: Free host channels in the controller. This is a list of 537197ba5f4SPaul Zimmerman * struct dwc2_host_chan items. 538197ba5f4SPaul Zimmerman * @periodic_channels: Number of host channels assigned to periodic transfers. 539197ba5f4SPaul Zimmerman * Currently assuming that there is a dedicated host 540197ba5f4SPaul Zimmerman * channel for each periodic transaction and at least one 541197ba5f4SPaul Zimmerman * host channel is available for non-periodic transactions. 542197ba5f4SPaul Zimmerman * @non_periodic_channels: Number of host channels assigned to non-periodic 543197ba5f4SPaul Zimmerman * transfers 544197ba5f4SPaul Zimmerman * @available_host_channels Number of host channels available for the microframe 545197ba5f4SPaul Zimmerman * scheduler to use 546197ba5f4SPaul Zimmerman * @hc_ptr_array: Array of pointers to the host channel descriptors. 547197ba5f4SPaul Zimmerman * Allows accessing a host channel descriptor given the 548197ba5f4SPaul Zimmerman * host channel number. This is useful in interrupt 549197ba5f4SPaul Zimmerman * handlers. 550197ba5f4SPaul Zimmerman * @status_buf: Buffer used for data received during the status phase of 551197ba5f4SPaul Zimmerman * a control transfer. 552197ba5f4SPaul Zimmerman * @status_buf_dma: DMA address for status_buf 553197ba5f4SPaul Zimmerman * @start_work: Delayed work for handling host A-cable connection 554197ba5f4SPaul Zimmerman * @reset_work: Delayed work for handling a port reset 555197ba5f4SPaul Zimmerman * @otg_port: OTG port number 556197ba5f4SPaul Zimmerman * @frame_list: Frame list 557197ba5f4SPaul Zimmerman * @frame_list_dma: Frame list DMA address 558941fcce4SDinh Nguyen * 559941fcce4SDinh Nguyen * These are for peripheral mode: 560941fcce4SDinh Nguyen * 561941fcce4SDinh Nguyen * @driver: USB gadget driver 562941fcce4SDinh Nguyen * @phy: The otg phy transceiver structure for phy control. 563941fcce4SDinh Nguyen * @uphy: The otg phy transceiver structure for old USB phy control. 564941fcce4SDinh Nguyen * @plat: The platform specific configuration data. This can be removed once 565941fcce4SDinh Nguyen * all SoCs support usb transceiver. 566941fcce4SDinh Nguyen * @supplies: Definition of USB power supplies 567941fcce4SDinh Nguyen * @phyif: PHY interface width 568941fcce4SDinh Nguyen * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 569941fcce4SDinh Nguyen * @num_of_eps: Number of available EPs (excluding EP0) 570941fcce4SDinh Nguyen * @debug_root: Root directrory for debugfs. 571941fcce4SDinh Nguyen * @debug_file: Main status file for debugfs. 5729e14d0a5SGregory Herrero * @debug_testmode: Testmode status file for debugfs. 573941fcce4SDinh Nguyen * @debug_fifo: FIFO status file for debugfs. 574941fcce4SDinh Nguyen * @ep0_reply: Request used for ep0 reply. 575941fcce4SDinh Nguyen * @ep0_buff: Buffer for EP0 reply data, if needed. 576941fcce4SDinh Nguyen * @ctrl_buff: Buffer for EP0 control requests. 577941fcce4SDinh Nguyen * @ctrl_req: Request for EP0 control packets. 578fe0b94abSMian Yousaf Kaukab * @ep0_state: EP0 control transfers state 5799e14d0a5SGregory Herrero * @test_mode: USB test mode requested by the host 580941fcce4SDinh Nguyen * @last_rst: Time of last reset 581941fcce4SDinh Nguyen * @eps: The endpoints being supplied to the gadget framework 582edd74be8SGregory Herrero * @g_using_dma: Indicate if dma usage is enabled 5830a176279SGregory Herrero * @g_rx_fifo_sz: Contains rx fifo size value 5840a176279SGregory Herrero * @g_np_g_tx_fifo_sz: Contains Non-Periodic tx fifo size value 5850a176279SGregory Herrero * @g_tx_fifo_sz: Contains tx fifo size value per endpoints 586197ba5f4SPaul Zimmerman */ 587197ba5f4SPaul Zimmerman struct dwc2_hsotg { 588197ba5f4SPaul Zimmerman struct device *dev; 589197ba5f4SPaul Zimmerman void __iomem *regs; 590197ba5f4SPaul Zimmerman /** Params detected from hardware */ 591197ba5f4SPaul Zimmerman struct dwc2_hw_params hw_params; 592197ba5f4SPaul Zimmerman /** Params to actually use */ 593197ba5f4SPaul Zimmerman struct dwc2_core_params *core_params; 594197ba5f4SPaul Zimmerman enum usb_otg_state op_state; 595c0155b9dSKever Yang enum usb_dr_mode dr_mode; 596197ba5f4SPaul Zimmerman 597941fcce4SDinh Nguyen struct phy *phy; 598941fcce4SDinh Nguyen struct usb_phy *uphy; 599941fcce4SDinh Nguyen struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsotg_supply_names)]; 600941fcce4SDinh Nguyen 601941fcce4SDinh Nguyen spinlock_t lock; 6027ad8096eSMarek Szyprowski struct mutex init_mutex; 603941fcce4SDinh Nguyen void *priv; 604941fcce4SDinh Nguyen int irq; 605941fcce4SDinh Nguyen struct clk *clk; 606941fcce4SDinh Nguyen 607197ba5f4SPaul Zimmerman unsigned int queuing_high_bandwidth:1; 608197ba5f4SPaul Zimmerman unsigned int srp_success:1; 609197ba5f4SPaul Zimmerman 610197ba5f4SPaul Zimmerman struct workqueue_struct *wq_otg; 611197ba5f4SPaul Zimmerman struct work_struct wf_otg; 612197ba5f4SPaul Zimmerman struct timer_list wkp_timer; 613197ba5f4SPaul Zimmerman enum dwc2_lx_state lx_state; 614197ba5f4SPaul Zimmerman 615941fcce4SDinh Nguyen struct dentry *debug_root; 616941fcce4SDinh Nguyen struct dentry *debug_file; 6179e14d0a5SGregory Herrero struct dentry *debug_testmode; 618941fcce4SDinh Nguyen struct dentry *debug_fifo; 619941fcce4SDinh Nguyen 620941fcce4SDinh Nguyen /* DWC OTG HW Release versions */ 621941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_71a 0x4f54271a 622941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_90a 0x4f54290a 623941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_92a 0x4f54292a 624941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_94a 0x4f54294a 625941fcce4SDinh Nguyen #define DWC2_CORE_REV_3_00a 0x4f54300a 626941fcce4SDinh Nguyen 627941fcce4SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 628197ba5f4SPaul Zimmerman union dwc2_hcd_internal_flags { 629197ba5f4SPaul Zimmerman u32 d32; 630197ba5f4SPaul Zimmerman struct { 631197ba5f4SPaul Zimmerman unsigned port_connect_status_change:1; 632197ba5f4SPaul Zimmerman unsigned port_connect_status:1; 633197ba5f4SPaul Zimmerman unsigned port_reset_change:1; 634197ba5f4SPaul Zimmerman unsigned port_enable_change:1; 635197ba5f4SPaul Zimmerman unsigned port_suspend_change:1; 636197ba5f4SPaul Zimmerman unsigned port_over_current_change:1; 637197ba5f4SPaul Zimmerman unsigned port_l1_change:1; 638fd4850cfSCharles Manning unsigned reserved:25; 639197ba5f4SPaul Zimmerman } b; 640197ba5f4SPaul Zimmerman } flags; 641197ba5f4SPaul Zimmerman 642197ba5f4SPaul Zimmerman struct list_head non_periodic_sched_inactive; 643197ba5f4SPaul Zimmerman struct list_head non_periodic_sched_active; 644197ba5f4SPaul Zimmerman struct list_head *non_periodic_qh_ptr; 645197ba5f4SPaul Zimmerman struct list_head periodic_sched_inactive; 646197ba5f4SPaul Zimmerman struct list_head periodic_sched_ready; 647197ba5f4SPaul Zimmerman struct list_head periodic_sched_assigned; 648197ba5f4SPaul Zimmerman struct list_head periodic_sched_queued; 649197ba5f4SPaul Zimmerman u16 periodic_usecs; 650197ba5f4SPaul Zimmerman u16 frame_usecs[8]; 651197ba5f4SPaul Zimmerman u16 frame_number; 652197ba5f4SPaul Zimmerman u16 periodic_qh_count; 653197ba5f4SPaul Zimmerman 654197ba5f4SPaul Zimmerman #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 655197ba5f4SPaul Zimmerman #define FRAME_NUM_ARRAY_SIZE 1000 656197ba5f4SPaul Zimmerman u16 last_frame_num; 657197ba5f4SPaul Zimmerman u16 *frame_num_array; 658197ba5f4SPaul Zimmerman u16 *last_frame_num_array; 659197ba5f4SPaul Zimmerman int frame_num_idx; 660197ba5f4SPaul Zimmerman int dumped_frame_num_array; 661197ba5f4SPaul Zimmerman #endif 662197ba5f4SPaul Zimmerman 663197ba5f4SPaul Zimmerman struct list_head free_hc_list; 664197ba5f4SPaul Zimmerman int periodic_channels; 665197ba5f4SPaul Zimmerman int non_periodic_channels; 666197ba5f4SPaul Zimmerman int available_host_channels; 667197ba5f4SPaul Zimmerman struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 668197ba5f4SPaul Zimmerman u8 *status_buf; 669197ba5f4SPaul Zimmerman dma_addr_t status_buf_dma; 670197ba5f4SPaul Zimmerman #define DWC2_HCD_STATUS_BUF_SIZE 64 671197ba5f4SPaul Zimmerman 672197ba5f4SPaul Zimmerman struct delayed_work start_work; 673197ba5f4SPaul Zimmerman struct delayed_work reset_work; 674197ba5f4SPaul Zimmerman u8 otg_port; 675197ba5f4SPaul Zimmerman u32 *frame_list; 676197ba5f4SPaul Zimmerman dma_addr_t frame_list_dma; 677197ba5f4SPaul Zimmerman 678197ba5f4SPaul Zimmerman #ifdef DEBUG 679197ba5f4SPaul Zimmerman u32 frrem_samples; 680197ba5f4SPaul Zimmerman u64 frrem_accum; 681197ba5f4SPaul Zimmerman 682197ba5f4SPaul Zimmerman u32 hfnum_7_samples_a; 683197ba5f4SPaul Zimmerman u64 hfnum_7_frrem_accum_a; 684197ba5f4SPaul Zimmerman u32 hfnum_0_samples_a; 685197ba5f4SPaul Zimmerman u64 hfnum_0_frrem_accum_a; 686197ba5f4SPaul Zimmerman u32 hfnum_other_samples_a; 687197ba5f4SPaul Zimmerman u64 hfnum_other_frrem_accum_a; 688197ba5f4SPaul Zimmerman 689197ba5f4SPaul Zimmerman u32 hfnum_7_samples_b; 690197ba5f4SPaul Zimmerman u64 hfnum_7_frrem_accum_b; 691197ba5f4SPaul Zimmerman u32 hfnum_0_samples_b; 692197ba5f4SPaul Zimmerman u64 hfnum_0_frrem_accum_b; 693197ba5f4SPaul Zimmerman u32 hfnum_other_samples_b; 694197ba5f4SPaul Zimmerman u64 hfnum_other_frrem_accum_b; 695197ba5f4SPaul Zimmerman #endif 696941fcce4SDinh Nguyen #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ 697941fcce4SDinh Nguyen 698941fcce4SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 699941fcce4SDinh Nguyen /* Gadget structures */ 700941fcce4SDinh Nguyen struct usb_gadget_driver *driver; 701941fcce4SDinh Nguyen struct s3c_hsotg_plat *plat; 702941fcce4SDinh Nguyen 703941fcce4SDinh Nguyen u32 phyif; 704941fcce4SDinh Nguyen int fifo_mem; 705941fcce4SDinh Nguyen unsigned int dedicated_fifos:1; 706941fcce4SDinh Nguyen unsigned char num_of_eps; 707941fcce4SDinh Nguyen u32 fifo_map; 708941fcce4SDinh Nguyen 709941fcce4SDinh Nguyen struct usb_request *ep0_reply; 710941fcce4SDinh Nguyen struct usb_request *ctrl_req; 7113f95001dSMian Yousaf Kaukab void *ep0_buff; 7123f95001dSMian Yousaf Kaukab void *ctrl_buff; 713fe0b94abSMian Yousaf Kaukab enum dwc2_ep0_state ep0_state; 7149e14d0a5SGregory Herrero u8 test_mode; 715941fcce4SDinh Nguyen 716941fcce4SDinh Nguyen struct usb_gadget gadget; 717dc6e69e6SMarek Szyprowski unsigned int enabled:1; 7184ace06e8SMarek Szyprowski unsigned int connected:1; 719941fcce4SDinh Nguyen unsigned long last_rst; 720c6f5c050SMian Yousaf Kaukab struct s3c_hsotg_ep *eps_in[MAX_EPS_CHANNELS]; 721c6f5c050SMian Yousaf Kaukab struct s3c_hsotg_ep *eps_out[MAX_EPS_CHANNELS]; 722edd74be8SGregory Herrero u32 g_using_dma; 7230a176279SGregory Herrero u32 g_rx_fifo_sz; 7240a176279SGregory Herrero u32 g_np_g_tx_fifo_sz; 7250a176279SGregory Herrero u32 g_tx_fifo_sz[MAX_EPS_CHANNELS]; 726941fcce4SDinh Nguyen #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 727197ba5f4SPaul Zimmerman }; 728197ba5f4SPaul Zimmerman 729197ba5f4SPaul Zimmerman /* Reasons for halting a host channel */ 730197ba5f4SPaul Zimmerman enum dwc2_halt_status { 731197ba5f4SPaul Zimmerman DWC2_HC_XFER_NO_HALT_STATUS, 732197ba5f4SPaul Zimmerman DWC2_HC_XFER_COMPLETE, 733197ba5f4SPaul Zimmerman DWC2_HC_XFER_URB_COMPLETE, 734197ba5f4SPaul Zimmerman DWC2_HC_XFER_ACK, 735197ba5f4SPaul Zimmerman DWC2_HC_XFER_NAK, 736197ba5f4SPaul Zimmerman DWC2_HC_XFER_NYET, 737197ba5f4SPaul Zimmerman DWC2_HC_XFER_STALL, 738197ba5f4SPaul Zimmerman DWC2_HC_XFER_XACT_ERR, 739197ba5f4SPaul Zimmerman DWC2_HC_XFER_FRAME_OVERRUN, 740197ba5f4SPaul Zimmerman DWC2_HC_XFER_BABBLE_ERR, 741197ba5f4SPaul Zimmerman DWC2_HC_XFER_DATA_TOGGLE_ERR, 742197ba5f4SPaul Zimmerman DWC2_HC_XFER_AHB_ERR, 743197ba5f4SPaul Zimmerman DWC2_HC_XFER_PERIODIC_INCOMPLETE, 744197ba5f4SPaul Zimmerman DWC2_HC_XFER_URB_DEQUEUE, 745197ba5f4SPaul Zimmerman }; 746197ba5f4SPaul Zimmerman 747197ba5f4SPaul Zimmerman /* 748197ba5f4SPaul Zimmerman * The following functions support initialization of the core driver component 749197ba5f4SPaul Zimmerman * and the DWC_otg controller 750197ba5f4SPaul Zimmerman */ 751197ba5f4SPaul Zimmerman extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg); 752197ba5f4SPaul Zimmerman 753197ba5f4SPaul Zimmerman /* 754197ba5f4SPaul Zimmerman * Host core Functions. 755197ba5f4SPaul Zimmerman * The following functions support managing the DWC_otg controller in host 756197ba5f4SPaul Zimmerman * mode. 757197ba5f4SPaul Zimmerman */ 758197ba5f4SPaul Zimmerman extern void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan); 759197ba5f4SPaul Zimmerman extern void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 760197ba5f4SPaul Zimmerman enum dwc2_halt_status halt_status); 761197ba5f4SPaul Zimmerman extern void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, 762197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan); 763197ba5f4SPaul Zimmerman extern void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 764197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan); 765197ba5f4SPaul Zimmerman extern void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 766197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan); 767197ba5f4SPaul Zimmerman extern int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 768197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan); 769197ba5f4SPaul Zimmerman extern void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, 770197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan); 771197ba5f4SPaul Zimmerman extern void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg); 772197ba5f4SPaul Zimmerman extern void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg); 773197ba5f4SPaul Zimmerman 774197ba5f4SPaul Zimmerman extern u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg); 775197ba5f4SPaul Zimmerman extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 776197ba5f4SPaul Zimmerman 777197ba5f4SPaul Zimmerman /* 778197ba5f4SPaul Zimmerman * Common core Functions. 779197ba5f4SPaul Zimmerman * The following functions support managing the DWC_otg controller in either 780197ba5f4SPaul Zimmerman * device or host mode. 781197ba5f4SPaul Zimmerman */ 782197ba5f4SPaul Zimmerman extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 783197ba5f4SPaul Zimmerman extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 784197ba5f4SPaul Zimmerman extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 785197ba5f4SPaul Zimmerman 786197ba5f4SPaul Zimmerman extern int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq); 787197ba5f4SPaul Zimmerman extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 788197ba5f4SPaul Zimmerman extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 789197ba5f4SPaul Zimmerman 790197ba5f4SPaul Zimmerman /* This function should be called on every hardware interrupt. */ 791197ba5f4SPaul Zimmerman extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 792197ba5f4SPaul Zimmerman 793197ba5f4SPaul Zimmerman /* OTG Core Parameters */ 794197ba5f4SPaul Zimmerman 795197ba5f4SPaul Zimmerman /* 796197ba5f4SPaul Zimmerman * Specifies the OTG capabilities. The driver will automatically 797197ba5f4SPaul Zimmerman * detect the value for this parameter if none is specified. 798197ba5f4SPaul Zimmerman * 0 - HNP and SRP capable (default) 799197ba5f4SPaul Zimmerman * 1 - SRP Only capable 800197ba5f4SPaul Zimmerman * 2 - No HNP/SRP capable 801197ba5f4SPaul Zimmerman */ 802197ba5f4SPaul Zimmerman extern void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val); 803197ba5f4SPaul Zimmerman #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 804197ba5f4SPaul Zimmerman #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 805197ba5f4SPaul Zimmerman #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 806197ba5f4SPaul Zimmerman 807197ba5f4SPaul Zimmerman /* 808197ba5f4SPaul Zimmerman * Specifies whether to use slave or DMA mode for accessing the data 809197ba5f4SPaul Zimmerman * FIFOs. The driver will automatically detect the value for this 810197ba5f4SPaul Zimmerman * parameter if none is specified. 811197ba5f4SPaul Zimmerman * 0 - Slave 812197ba5f4SPaul Zimmerman * 1 - DMA (default, if available) 813197ba5f4SPaul Zimmerman */ 814197ba5f4SPaul Zimmerman extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val); 815197ba5f4SPaul Zimmerman 816197ba5f4SPaul Zimmerman /* 817197ba5f4SPaul Zimmerman * When DMA mode is enabled specifies whether to use 818197ba5f4SPaul Zimmerman * address DMA or DMA Descritor mode for accessing the data 819197ba5f4SPaul Zimmerman * FIFOs in device mode. The driver will automatically detect 820197ba5f4SPaul Zimmerman * the value for this parameter if none is specified. 821197ba5f4SPaul Zimmerman * 0 - address DMA 822197ba5f4SPaul Zimmerman * 1 - DMA Descriptor(default, if available) 823197ba5f4SPaul Zimmerman */ 824197ba5f4SPaul Zimmerman extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val); 825197ba5f4SPaul Zimmerman 826197ba5f4SPaul Zimmerman /* 827197ba5f4SPaul Zimmerman * Specifies the maximum speed of operation in host and device mode. 828197ba5f4SPaul Zimmerman * The actual speed depends on the speed of the attached device and 829197ba5f4SPaul Zimmerman * the value of phy_type. The actual speed depends on the speed of the 830197ba5f4SPaul Zimmerman * attached device. 831197ba5f4SPaul Zimmerman * 0 - High Speed (default) 832197ba5f4SPaul Zimmerman * 1 - Full Speed 833197ba5f4SPaul Zimmerman */ 834197ba5f4SPaul Zimmerman extern void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val); 835197ba5f4SPaul Zimmerman #define DWC2_SPEED_PARAM_HIGH 0 836197ba5f4SPaul Zimmerman #define DWC2_SPEED_PARAM_FULL 1 837197ba5f4SPaul Zimmerman 838197ba5f4SPaul Zimmerman /* 839197ba5f4SPaul Zimmerman * Specifies whether low power mode is supported when attached 840197ba5f4SPaul Zimmerman * to a Full Speed or Low Speed device in host mode. 841197ba5f4SPaul Zimmerman * 842197ba5f4SPaul Zimmerman * 0 - Don't support low power mode (default) 843197ba5f4SPaul Zimmerman * 1 - Support low power mode 844197ba5f4SPaul Zimmerman */ 845197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_support_fs_ls_low_power( 846197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg, int val); 847197ba5f4SPaul Zimmerman 848197ba5f4SPaul Zimmerman /* 849197ba5f4SPaul Zimmerman * Specifies the PHY clock rate in low power mode when connected to a 850197ba5f4SPaul Zimmerman * Low Speed device in host mode. This parameter is applicable only if 851197ba5f4SPaul Zimmerman * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS 852197ba5f4SPaul Zimmerman * then defaults to 6 MHZ otherwise 48 MHZ. 853197ba5f4SPaul Zimmerman * 854197ba5f4SPaul Zimmerman * 0 - 48 MHz 855197ba5f4SPaul Zimmerman * 1 - 6 MHz 856197ba5f4SPaul Zimmerman */ 857197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, 858197ba5f4SPaul Zimmerman int val); 859197ba5f4SPaul Zimmerman #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 860197ba5f4SPaul Zimmerman #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 861197ba5f4SPaul Zimmerman 862197ba5f4SPaul Zimmerman /* 863197ba5f4SPaul Zimmerman * 0 - Use cC FIFO size parameters 864197ba5f4SPaul Zimmerman * 1 - Allow dynamic FIFO sizing (default) 865197ba5f4SPaul Zimmerman */ 866197ba5f4SPaul Zimmerman extern void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, 867197ba5f4SPaul Zimmerman int val); 868197ba5f4SPaul Zimmerman 869197ba5f4SPaul Zimmerman /* 870197ba5f4SPaul Zimmerman * Number of 4-byte words in the Rx FIFO in host mode when dynamic 871197ba5f4SPaul Zimmerman * FIFO sizing is enabled. 872197ba5f4SPaul Zimmerman * 16 to 32768 (default 1024) 873197ba5f4SPaul Zimmerman */ 874197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val); 875197ba5f4SPaul Zimmerman 876197ba5f4SPaul Zimmerman /* 877197ba5f4SPaul Zimmerman * Number of 4-byte words in the non-periodic Tx FIFO in host mode 878197ba5f4SPaul Zimmerman * when Dynamic FIFO sizing is enabled in the core. 879197ba5f4SPaul Zimmerman * 16 to 32768 (default 256) 880197ba5f4SPaul Zimmerman */ 881197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, 882197ba5f4SPaul Zimmerman int val); 883197ba5f4SPaul Zimmerman 884197ba5f4SPaul Zimmerman /* 885197ba5f4SPaul Zimmerman * Number of 4-byte words in the host periodic Tx FIFO when dynamic 886197ba5f4SPaul Zimmerman * FIFO sizing is enabled. 887197ba5f4SPaul Zimmerman * 16 to 32768 (default 256) 888197ba5f4SPaul Zimmerman */ 889197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, 890197ba5f4SPaul Zimmerman int val); 891197ba5f4SPaul Zimmerman 892197ba5f4SPaul Zimmerman /* 893197ba5f4SPaul Zimmerman * The maximum transfer size supported in bytes. 894197ba5f4SPaul Zimmerman * 2047 to 65,535 (default 65,535) 895197ba5f4SPaul Zimmerman */ 896197ba5f4SPaul Zimmerman extern void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val); 897197ba5f4SPaul Zimmerman 898197ba5f4SPaul Zimmerman /* 899197ba5f4SPaul Zimmerman * The maximum number of packets in a transfer. 900197ba5f4SPaul Zimmerman * 15 to 511 (default 511) 901197ba5f4SPaul Zimmerman */ 902197ba5f4SPaul Zimmerman extern void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val); 903197ba5f4SPaul Zimmerman 904197ba5f4SPaul Zimmerman /* 905197ba5f4SPaul Zimmerman * The number of host channel registers to use. 906197ba5f4SPaul Zimmerman * 1 to 16 (default 11) 907197ba5f4SPaul Zimmerman * Note: The FPGA configuration supports a maximum of 11 host channels. 908197ba5f4SPaul Zimmerman */ 909197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val); 910197ba5f4SPaul Zimmerman 911197ba5f4SPaul Zimmerman /* 912197ba5f4SPaul Zimmerman * Specifies the type of PHY interface to use. By default, the driver 913197ba5f4SPaul Zimmerman * will automatically detect the phy_type. 914197ba5f4SPaul Zimmerman * 915197ba5f4SPaul Zimmerman * 0 - Full Speed PHY 916197ba5f4SPaul Zimmerman * 1 - UTMI+ (default) 917197ba5f4SPaul Zimmerman * 2 - ULPI 918197ba5f4SPaul Zimmerman */ 919197ba5f4SPaul Zimmerman extern void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val); 920197ba5f4SPaul Zimmerman #define DWC2_PHY_TYPE_PARAM_FS 0 921197ba5f4SPaul Zimmerman #define DWC2_PHY_TYPE_PARAM_UTMI 1 922197ba5f4SPaul Zimmerman #define DWC2_PHY_TYPE_PARAM_ULPI 2 923197ba5f4SPaul Zimmerman 924197ba5f4SPaul Zimmerman /* 925197ba5f4SPaul Zimmerman * Specifies the UTMI+ Data Width. This parameter is 926197ba5f4SPaul Zimmerman * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI 927197ba5f4SPaul Zimmerman * PHY_TYPE, this parameter indicates the data width between 928197ba5f4SPaul Zimmerman * the MAC and the ULPI Wrapper.) Also, this parameter is 929197ba5f4SPaul Zimmerman * applicable only if the OTG_HSPHY_WIDTH cC parameter was set 930197ba5f4SPaul Zimmerman * to "8 and 16 bits", meaning that the core has been 931197ba5f4SPaul Zimmerman * configured to work at either data path width. 932197ba5f4SPaul Zimmerman * 933197ba5f4SPaul Zimmerman * 8 or 16 bits (default 16) 934197ba5f4SPaul Zimmerman */ 935197ba5f4SPaul Zimmerman extern void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val); 936197ba5f4SPaul Zimmerman 937197ba5f4SPaul Zimmerman /* 938197ba5f4SPaul Zimmerman * Specifies whether the ULPI operates at double or single 939197ba5f4SPaul Zimmerman * data rate. This parameter is only applicable if PHY_TYPE is 940197ba5f4SPaul Zimmerman * ULPI. 941197ba5f4SPaul Zimmerman * 942197ba5f4SPaul Zimmerman * 0 - single data rate ULPI interface with 8 bit wide data 943197ba5f4SPaul Zimmerman * bus (default) 944197ba5f4SPaul Zimmerman * 1 - double data rate ULPI interface with 4 bit wide data 945197ba5f4SPaul Zimmerman * bus 946197ba5f4SPaul Zimmerman */ 947197ba5f4SPaul Zimmerman extern void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val); 948197ba5f4SPaul Zimmerman 949197ba5f4SPaul Zimmerman /* 950197ba5f4SPaul Zimmerman * Specifies whether to use the internal or external supply to 951197ba5f4SPaul Zimmerman * drive the vbus with a ULPI phy. 952197ba5f4SPaul Zimmerman */ 953197ba5f4SPaul Zimmerman extern void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val); 954197ba5f4SPaul Zimmerman #define DWC2_PHY_ULPI_INTERNAL_VBUS 0 955197ba5f4SPaul Zimmerman #define DWC2_PHY_ULPI_EXTERNAL_VBUS 1 956197ba5f4SPaul Zimmerman 957197ba5f4SPaul Zimmerman /* 958197ba5f4SPaul Zimmerman * Specifies whether to use the I2Cinterface for full speed PHY. This 959197ba5f4SPaul Zimmerman * parameter is only applicable if PHY_TYPE is FS. 960197ba5f4SPaul Zimmerman * 0 - No (default) 961197ba5f4SPaul Zimmerman * 1 - Yes 962197ba5f4SPaul Zimmerman */ 963197ba5f4SPaul Zimmerman extern void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val); 964197ba5f4SPaul Zimmerman 965197ba5f4SPaul Zimmerman extern void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val); 966197ba5f4SPaul Zimmerman 967197ba5f4SPaul Zimmerman extern void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val); 968197ba5f4SPaul Zimmerman 969197ba5f4SPaul Zimmerman /* 970197ba5f4SPaul Zimmerman * Specifies whether dedicated transmit FIFOs are 971197ba5f4SPaul Zimmerman * enabled for non periodic IN endpoints in device mode 972197ba5f4SPaul Zimmerman * 0 - No 973197ba5f4SPaul Zimmerman * 1 - Yes 974197ba5f4SPaul Zimmerman */ 975197ba5f4SPaul Zimmerman extern void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, 976197ba5f4SPaul Zimmerman int val); 977197ba5f4SPaul Zimmerman 978197ba5f4SPaul Zimmerman extern void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val); 979197ba5f4SPaul Zimmerman 980197ba5f4SPaul Zimmerman extern void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val); 981197ba5f4SPaul Zimmerman 982197ba5f4SPaul Zimmerman extern void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val); 983197ba5f4SPaul Zimmerman 984197ba5f4SPaul Zimmerman /* 985197ba5f4SPaul Zimmerman * Dump core registers and SPRAM 986197ba5f4SPaul Zimmerman */ 987197ba5f4SPaul Zimmerman extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 988197ba5f4SPaul Zimmerman extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 989197ba5f4SPaul Zimmerman extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 990197ba5f4SPaul Zimmerman 991197ba5f4SPaul Zimmerman /* 992197ba5f4SPaul Zimmerman * Return OTG version - either 1.3 or 2.0 993197ba5f4SPaul Zimmerman */ 994197ba5f4SPaul Zimmerman extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg); 995197ba5f4SPaul Zimmerman 996117777b2SDinh Nguyen /* Gadget defines */ 997117777b2SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 998117777b2SDinh Nguyen extern int s3c_hsotg_remove(struct dwc2_hsotg *hsotg); 999117777b2SDinh Nguyen extern int s3c_hsotg_suspend(struct dwc2_hsotg *dwc2); 1000117777b2SDinh Nguyen extern int s3c_hsotg_resume(struct dwc2_hsotg *dwc2); 1001117777b2SDinh Nguyen extern int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq); 1002510ffaa4SDinh Nguyen extern void s3c_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2); 1003510ffaa4SDinh Nguyen extern void s3c_hsotg_core_connect(struct dwc2_hsotg *hsotg); 10044ace06e8SMarek Szyprowski extern void s3c_hsotg_disconnect(struct dwc2_hsotg *dwc2); 1005117777b2SDinh Nguyen #else 1006117777b2SDinh Nguyen static inline int s3c_hsotg_remove(struct dwc2_hsotg *dwc2) 1007117777b2SDinh Nguyen { return 0; } 1008117777b2SDinh Nguyen static inline int s3c_hsotg_suspend(struct dwc2_hsotg *dwc2) 1009117777b2SDinh Nguyen { return 0; } 1010117777b2SDinh Nguyen static inline int s3c_hsotg_resume(struct dwc2_hsotg *dwc2) 1011117777b2SDinh Nguyen { return 0; } 1012117777b2SDinh Nguyen static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) 1013117777b2SDinh Nguyen { return 0; } 1014510ffaa4SDinh Nguyen static inline void s3c_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2) {} 1015510ffaa4SDinh Nguyen static inline void s3c_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} 10164ace06e8SMarek Szyprowski static inline void s3c_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} 1017117777b2SDinh Nguyen #endif 1018117777b2SDinh Nguyen 1019117777b2SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1020117777b2SDinh Nguyen extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 1021117777b2SDinh Nguyen extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg); 1022117777b2SDinh Nguyen extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 1023117777b2SDinh Nguyen #else 1024117777b2SDinh Nguyen static inline void dwc2_set_all_params(struct dwc2_core_params *params, int value) {} 1025117777b2SDinh Nguyen static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1026117777b2SDinh Nguyen { return 0; } 1027117777b2SDinh Nguyen static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg) {} 1028117777b2SDinh Nguyen static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} 1029117777b2SDinh Nguyen static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} 1030117777b2SDinh Nguyen static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq, 1031117777b2SDinh Nguyen const struct dwc2_core_params *params) 1032117777b2SDinh Nguyen { return 0; } 1033117777b2SDinh Nguyen #endif 1034117777b2SDinh Nguyen 1035197ba5f4SPaul Zimmerman #endif /* __DWC2_CORE_H__ */ 1036