1197ba5f4SPaul Zimmerman /* 2197ba5f4SPaul Zimmerman * core.h - DesignWare HS OTG Controller common declarations 3197ba5f4SPaul Zimmerman * 4197ba5f4SPaul Zimmerman * Copyright (C) 2004-2013 Synopsys, Inc. 5197ba5f4SPaul Zimmerman * 6197ba5f4SPaul Zimmerman * Redistribution and use in source and binary forms, with or without 7197ba5f4SPaul Zimmerman * modification, are permitted provided that the following conditions 8197ba5f4SPaul Zimmerman * are met: 9197ba5f4SPaul Zimmerman * 1. Redistributions of source code must retain the above copyright 10197ba5f4SPaul Zimmerman * notice, this list of conditions, and the following disclaimer, 11197ba5f4SPaul Zimmerman * without modification. 12197ba5f4SPaul Zimmerman * 2. Redistributions in binary form must reproduce the above copyright 13197ba5f4SPaul Zimmerman * notice, this list of conditions and the following disclaimer in the 14197ba5f4SPaul Zimmerman * documentation and/or other materials provided with the distribution. 15197ba5f4SPaul Zimmerman * 3. The names of the above-listed copyright holders may not be used 16197ba5f4SPaul Zimmerman * to endorse or promote products derived from this software without 17197ba5f4SPaul Zimmerman * specific prior written permission. 18197ba5f4SPaul Zimmerman * 19197ba5f4SPaul Zimmerman * ALTERNATIVELY, this software may be distributed under the terms of the 20197ba5f4SPaul Zimmerman * GNU General Public License ("GPL") as published by the Free Software 21197ba5f4SPaul Zimmerman * Foundation; either version 2 of the License, or (at your option) any 22197ba5f4SPaul Zimmerman * later version. 23197ba5f4SPaul Zimmerman * 24197ba5f4SPaul Zimmerman * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25197ba5f4SPaul Zimmerman * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26197ba5f4SPaul Zimmerman * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27197ba5f4SPaul Zimmerman * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28197ba5f4SPaul Zimmerman * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29197ba5f4SPaul Zimmerman * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30197ba5f4SPaul Zimmerman * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31197ba5f4SPaul Zimmerman * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32197ba5f4SPaul Zimmerman * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33197ba5f4SPaul Zimmerman * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34197ba5f4SPaul Zimmerman * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35197ba5f4SPaul Zimmerman */ 36197ba5f4SPaul Zimmerman 37197ba5f4SPaul Zimmerman #ifndef __DWC2_CORE_H__ 38197ba5f4SPaul Zimmerman #define __DWC2_CORE_H__ 39197ba5f4SPaul Zimmerman 40f7c0b143SDinh Nguyen #include <linux/phy/phy.h> 41f7c0b143SDinh Nguyen #include <linux/regulator/consumer.h> 42f7c0b143SDinh Nguyen #include <linux/usb/gadget.h> 43f7c0b143SDinh Nguyen #include <linux/usb/otg.h> 44197ba5f4SPaul Zimmerman #include <linux/usb/phy.h> 45197ba5f4SPaul Zimmerman #include "hw.h" 46197ba5f4SPaul Zimmerman 4774fc4a75SDouglas Anderson /* 4874fc4a75SDouglas Anderson * Suggested defines for tracers: 4974fc4a75SDouglas Anderson * - no_printk: Disable tracing 5074fc4a75SDouglas Anderson * - pr_info: Print this info to the console 5174fc4a75SDouglas Anderson * - trace_printk: Print this info to trace buffer (good for verbose logging) 5274fc4a75SDouglas Anderson */ 5374fc4a75SDouglas Anderson 5474fc4a75SDouglas Anderson #define DWC2_TRACE_SCHEDULER no_printk 5574fc4a75SDouglas Anderson #define DWC2_TRACE_SCHEDULER_VB no_printk 5674fc4a75SDouglas Anderson 5774fc4a75SDouglas Anderson /* Detailed scheduler tracing, but won't overwhelm console */ 5874fc4a75SDouglas Anderson #define dwc2_sch_dbg(hsotg, fmt, ...) \ 5974fc4a75SDouglas Anderson DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \ 6074fc4a75SDouglas Anderson dev_name(hsotg->dev), ##__VA_ARGS__) 6174fc4a75SDouglas Anderson 6274fc4a75SDouglas Anderson /* Verbose scheduler tracing */ 6374fc4a75SDouglas Anderson #define dwc2_sch_vdbg(hsotg, fmt, ...) \ 6474fc4a75SDouglas Anderson DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \ 6574fc4a75SDouglas Anderson dev_name(hsotg->dev), ##__VA_ARGS__) 6674fc4a75SDouglas Anderson 6795c8bc36SAntti Seppälä static inline u32 dwc2_readl(const void __iomem *addr) 68197ba5f4SPaul Zimmerman { 6995c8bc36SAntti Seppälä u32 value = __raw_readl(addr); 7095c8bc36SAntti Seppälä 7195c8bc36SAntti Seppälä /* In order to preserve endianness __raw_* operation is used. Therefore 7295c8bc36SAntti Seppälä * a barrier is needed to ensure IO access is not re-ordered across 7395c8bc36SAntti Seppälä * reads or writes 7495c8bc36SAntti Seppälä */ 7595c8bc36SAntti Seppälä mb(); 7695c8bc36SAntti Seppälä return value; 77197ba5f4SPaul Zimmerman } 78197ba5f4SPaul Zimmerman 7995c8bc36SAntti Seppälä static inline void dwc2_writel(u32 value, void __iomem *addr) 8095c8bc36SAntti Seppälä { 8195c8bc36SAntti Seppälä __raw_writel(value, addr); 8295c8bc36SAntti Seppälä 8395c8bc36SAntti Seppälä /* 8495c8bc36SAntti Seppälä * In order to preserve endianness __raw_* operation is used. Therefore 8595c8bc36SAntti Seppälä * a barrier is needed to ensure IO access is not re-ordered across 8695c8bc36SAntti Seppälä * reads or writes 8795c8bc36SAntti Seppälä */ 8895c8bc36SAntti Seppälä mb(); 8995c8bc36SAntti Seppälä #ifdef DWC2_LOG_WRITES 9095c8bc36SAntti Seppälä pr_info("INFO:: wrote %08x to %p\n", value, addr); 91197ba5f4SPaul Zimmerman #endif 9295c8bc36SAntti Seppälä } 93197ba5f4SPaul Zimmerman 94197ba5f4SPaul Zimmerman /* Maximum number of Endpoints/HostChannels */ 95197ba5f4SPaul Zimmerman #define MAX_EPS_CHANNELS 16 96197ba5f4SPaul Zimmerman 971f91b4ccSFelipe Balbi /* dwc2-hsotg declarations */ 981f91b4ccSFelipe Balbi static const char * const dwc2_hsotg_supply_names[] = { 99f7c0b143SDinh Nguyen "vusb_d", /* digital USB supply, 1.2V */ 100f7c0b143SDinh Nguyen "vusb_a", /* analog USB supply, 1.1V */ 101f7c0b143SDinh Nguyen }; 102f7c0b143SDinh Nguyen 103f7c0b143SDinh Nguyen /* 104f7c0b143SDinh Nguyen * EP0_MPS_LIMIT 105f7c0b143SDinh Nguyen * 106f7c0b143SDinh Nguyen * Unfortunately there seems to be a limit of the amount of data that can 107f7c0b143SDinh Nguyen * be transferred by IN transactions on EP0. This is either 127 bytes or 3 108f7c0b143SDinh Nguyen * packets (which practically means 1 packet and 63 bytes of data) when the 109f7c0b143SDinh Nguyen * MPS is set to 64. 110f7c0b143SDinh Nguyen * 111f7c0b143SDinh Nguyen * This means if we are wanting to move >127 bytes of data, we need to 112f7c0b143SDinh Nguyen * split the transactions up, but just doing one packet at a time does 113f7c0b143SDinh Nguyen * not work (this may be an implicit DATA0 PID on first packet of the 114f7c0b143SDinh Nguyen * transaction) and doing 2 packets is outside the controller's limits. 115f7c0b143SDinh Nguyen * 116f7c0b143SDinh Nguyen * If we try to lower the MPS size for EP0, then no transfers work properly 117f7c0b143SDinh Nguyen * for EP0, and the system will fail basic enumeration. As no cause for this 118f7c0b143SDinh Nguyen * has currently been found, we cannot support any large IN transfers for 119f7c0b143SDinh Nguyen * EP0. 120f7c0b143SDinh Nguyen */ 121f7c0b143SDinh Nguyen #define EP0_MPS_LIMIT 64 122f7c0b143SDinh Nguyen 123941fcce4SDinh Nguyen struct dwc2_hsotg; 1241f91b4ccSFelipe Balbi struct dwc2_hsotg_req; 125f7c0b143SDinh Nguyen 126f7c0b143SDinh Nguyen /** 1271f91b4ccSFelipe Balbi * struct dwc2_hsotg_ep - driver endpoint definition. 128f7c0b143SDinh Nguyen * @ep: The gadget layer representation of the endpoint. 129f7c0b143SDinh Nguyen * @name: The driver generated name for the endpoint. 130f7c0b143SDinh Nguyen * @queue: Queue of requests for this endpoint. 131f7c0b143SDinh Nguyen * @parent: Reference back to the parent device structure. 132f7c0b143SDinh Nguyen * @req: The current request that the endpoint is processing. This is 133f7c0b143SDinh Nguyen * used to indicate an request has been loaded onto the endpoint 134f7c0b143SDinh Nguyen * and has yet to be completed (maybe due to data move, or simply 135f7c0b143SDinh Nguyen * awaiting an ack from the core all the data has been completed). 136f7c0b143SDinh Nguyen * @debugfs: File entry for debugfs file for this endpoint. 137f7c0b143SDinh Nguyen * @lock: State lock to protect contents of endpoint. 138f7c0b143SDinh Nguyen * @dir_in: Set to true if this endpoint is of the IN direction, which 139f7c0b143SDinh Nguyen * means that it is sending data to the Host. 140f7c0b143SDinh Nguyen * @index: The index for the endpoint registers. 141f7c0b143SDinh Nguyen * @mc: Multi Count - number of transactions per microframe 142f7c0b143SDinh Nguyen * @interval - Interval for periodic endpoints 143f7c0b143SDinh Nguyen * @name: The name array passed to the USB core. 144f7c0b143SDinh Nguyen * @halted: Set if the endpoint has been halted. 145f7c0b143SDinh Nguyen * @periodic: Set if this is a periodic ep, such as Interrupt 146f7c0b143SDinh Nguyen * @isochronous: Set if this is a isochronous ep 1478a20fa45SMian Yousaf Kaukab * @send_zlp: Set if we need to send a zero-length packet. 148f7c0b143SDinh Nguyen * @total_data: The total number of data bytes done. 149f7c0b143SDinh Nguyen * @fifo_size: The size of the FIFO (for periodic IN endpoints) 150f7c0b143SDinh Nguyen * @fifo_load: The amount of data loaded into the FIFO (periodic IN) 151f7c0b143SDinh Nguyen * @last_load: The offset of data for the last start of request. 152f7c0b143SDinh Nguyen * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN 153f7c0b143SDinh Nguyen * 154f7c0b143SDinh Nguyen * This is the driver's state for each registered enpoint, allowing it 155f7c0b143SDinh Nguyen * to keep track of transactions that need doing. Each endpoint has a 156f7c0b143SDinh Nguyen * lock to protect the state, to try and avoid using an overall lock 157f7c0b143SDinh Nguyen * for the host controller as much as possible. 158f7c0b143SDinh Nguyen * 159f7c0b143SDinh Nguyen * For periodic IN endpoints, we have fifo_size and fifo_load to try 160f7c0b143SDinh Nguyen * and keep track of the amount of data in the periodic FIFO for each 161f7c0b143SDinh Nguyen * of these as we don't have a status register that tells us how much 162f7c0b143SDinh Nguyen * is in each of them. (note, this may actually be useless information 163f7c0b143SDinh Nguyen * as in shared-fifo mode periodic in acts like a single-frame packet 164f7c0b143SDinh Nguyen * buffer than a fifo) 165f7c0b143SDinh Nguyen */ 1661f91b4ccSFelipe Balbi struct dwc2_hsotg_ep { 167f7c0b143SDinh Nguyen struct usb_ep ep; 168f7c0b143SDinh Nguyen struct list_head queue; 169941fcce4SDinh Nguyen struct dwc2_hsotg *parent; 1701f91b4ccSFelipe Balbi struct dwc2_hsotg_req *req; 171f7c0b143SDinh Nguyen struct dentry *debugfs; 172f7c0b143SDinh Nguyen 173f7c0b143SDinh Nguyen unsigned long total_data; 174f7c0b143SDinh Nguyen unsigned int size_loaded; 175f7c0b143SDinh Nguyen unsigned int last_load; 176f7c0b143SDinh Nguyen unsigned int fifo_load; 177f7c0b143SDinh Nguyen unsigned short fifo_size; 178b203d0a2SRobert Baldyga unsigned short fifo_index; 179f7c0b143SDinh Nguyen 180f7c0b143SDinh Nguyen unsigned char dir_in; 181f7c0b143SDinh Nguyen unsigned char index; 182f7c0b143SDinh Nguyen unsigned char mc; 183f7c0b143SDinh Nguyen unsigned char interval; 184f7c0b143SDinh Nguyen 185f7c0b143SDinh Nguyen unsigned int halted:1; 186f7c0b143SDinh Nguyen unsigned int periodic:1; 187f7c0b143SDinh Nguyen unsigned int isochronous:1; 1888a20fa45SMian Yousaf Kaukab unsigned int send_zlp:1; 189ec1f9d9fSRoman Bacik unsigned int has_correct_parity:1; 190f7c0b143SDinh Nguyen 191f7c0b143SDinh Nguyen char name[10]; 192f7c0b143SDinh Nguyen }; 193f7c0b143SDinh Nguyen 194f7c0b143SDinh Nguyen /** 1951f91b4ccSFelipe Balbi * struct dwc2_hsotg_req - data transfer request 196f7c0b143SDinh Nguyen * @req: The USB gadget request 197f7c0b143SDinh Nguyen * @queue: The list of requests for the endpoint this is queued for. 1987d24c1b5SMian Yousaf Kaukab * @saved_req_buf: variable to save req.buf when bounce buffers are used. 199f7c0b143SDinh Nguyen */ 2001f91b4ccSFelipe Balbi struct dwc2_hsotg_req { 201f7c0b143SDinh Nguyen struct usb_request req; 202f7c0b143SDinh Nguyen struct list_head queue; 2037d24c1b5SMian Yousaf Kaukab void *saved_req_buf; 204f7c0b143SDinh Nguyen }; 205f7c0b143SDinh Nguyen 206941fcce4SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 207f7c0b143SDinh Nguyen #define call_gadget(_hs, _entry) \ 208f7c0b143SDinh Nguyen do { \ 209f7c0b143SDinh Nguyen if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ 210f7c0b143SDinh Nguyen (_hs)->driver && (_hs)->driver->_entry) { \ 211f7c0b143SDinh Nguyen spin_unlock(&_hs->lock); \ 212f7c0b143SDinh Nguyen (_hs)->driver->_entry(&(_hs)->gadget); \ 213f7c0b143SDinh Nguyen spin_lock(&_hs->lock); \ 214f7c0b143SDinh Nguyen } \ 215f7c0b143SDinh Nguyen } while (0) 216941fcce4SDinh Nguyen #else 217941fcce4SDinh Nguyen #define call_gadget(_hs, _entry) do {} while (0) 218941fcce4SDinh Nguyen #endif 219f7c0b143SDinh Nguyen 220197ba5f4SPaul Zimmerman struct dwc2_hsotg; 221197ba5f4SPaul Zimmerman struct dwc2_host_chan; 222197ba5f4SPaul Zimmerman 223197ba5f4SPaul Zimmerman /* Device States */ 224197ba5f4SPaul Zimmerman enum dwc2_lx_state { 225197ba5f4SPaul Zimmerman DWC2_L0, /* On state */ 226197ba5f4SPaul Zimmerman DWC2_L1, /* LPM sleep state */ 227197ba5f4SPaul Zimmerman DWC2_L2, /* USB suspend state */ 228197ba5f4SPaul Zimmerman DWC2_L3, /* Off state */ 229197ba5f4SPaul Zimmerman }; 230197ba5f4SPaul Zimmerman 2310a176279SGregory Herrero /* 2320a176279SGregory Herrero * Gadget periodic tx fifo sizes as used by legacy driver 2330a176279SGregory Herrero * EP0 is not included 2340a176279SGregory Herrero */ 2350a176279SGregory Herrero #define DWC2_G_P_LEGACY_TX_FIFO_SIZE {256, 256, 256, 256, 768, 768, 768, \ 2360a176279SGregory Herrero 768, 0, 0, 0, 0, 0, 0, 0} 2370a176279SGregory Herrero 238fe0b94abSMian Yousaf Kaukab /* Gadget ep0 states */ 239fe0b94abSMian Yousaf Kaukab enum dwc2_ep0_state { 240fe0b94abSMian Yousaf Kaukab DWC2_EP0_SETUP, 241fe0b94abSMian Yousaf Kaukab DWC2_EP0_DATA_IN, 242fe0b94abSMian Yousaf Kaukab DWC2_EP0_DATA_OUT, 243fe0b94abSMian Yousaf Kaukab DWC2_EP0_STATUS_IN, 244fe0b94abSMian Yousaf Kaukab DWC2_EP0_STATUS_OUT, 245fe0b94abSMian Yousaf Kaukab }; 246fe0b94abSMian Yousaf Kaukab 247197ba5f4SPaul Zimmerman /** 248197ba5f4SPaul Zimmerman * struct dwc2_core_params - Parameters for configuring the core 249197ba5f4SPaul Zimmerman * 250197ba5f4SPaul Zimmerman * @otg_cap: Specifies the OTG capabilities. 251197ba5f4SPaul Zimmerman * 0 - HNP and SRP capable 252197ba5f4SPaul Zimmerman * 1 - SRP Only capable 253197ba5f4SPaul Zimmerman * 2 - No HNP/SRP capable (always available) 254197ba5f4SPaul Zimmerman * Defaults to best available option (0, 1, then 2) 255197ba5f4SPaul Zimmerman * @otg_ver: OTG version supported 256197ba5f4SPaul Zimmerman * 0 - 1.3 (default) 257197ba5f4SPaul Zimmerman * 1 - 2.0 258197ba5f4SPaul Zimmerman * @dma_enable: Specifies whether to use slave or DMA mode for accessing 259197ba5f4SPaul Zimmerman * the data FIFOs. The driver will automatically detect the 260197ba5f4SPaul Zimmerman * value for this parameter if none is specified. 261197ba5f4SPaul Zimmerman * 0 - Slave (always available) 262197ba5f4SPaul Zimmerman * 1 - DMA (default, if available) 263197ba5f4SPaul Zimmerman * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 264197ba5f4SPaul Zimmerman * address DMA mode or descriptor DMA mode for accessing 265197ba5f4SPaul Zimmerman * the data FIFOs. The driver will automatically detect the 266197ba5f4SPaul Zimmerman * value for this if none is specified. 267197ba5f4SPaul Zimmerman * 0 - Address DMA 268197ba5f4SPaul Zimmerman * 1 - Descriptor DMA (default, if available) 269fbb9e22bSMian Yousaf Kaukab * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use 270fbb9e22bSMian Yousaf Kaukab * address DMA mode or descriptor DMA mode for accessing 271fbb9e22bSMian Yousaf Kaukab * the data FIFOs in Full Speed mode only. The driver 272fbb9e22bSMian Yousaf Kaukab * will automatically detect the value for this if none is 273fbb9e22bSMian Yousaf Kaukab * specified. 274fbb9e22bSMian Yousaf Kaukab * 0 - Address DMA 275fbb9e22bSMian Yousaf Kaukab * 1 - Descriptor DMA in FS (default, if available) 276197ba5f4SPaul Zimmerman * @speed: Specifies the maximum speed of operation in host and 277197ba5f4SPaul Zimmerman * device mode. The actual speed depends on the speed of 278197ba5f4SPaul Zimmerman * the attached device and the value of phy_type. 279197ba5f4SPaul Zimmerman * 0 - High Speed 280197ba5f4SPaul Zimmerman * (default when phy_type is UTMI+ or ULPI) 281197ba5f4SPaul Zimmerman * 1 - Full Speed 282197ba5f4SPaul Zimmerman * (default when phy_type is Full Speed) 283197ba5f4SPaul Zimmerman * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 284197ba5f4SPaul Zimmerman * 1 - Allow dynamic FIFO sizing (default, if available) 285197ba5f4SPaul Zimmerman * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 286197ba5f4SPaul Zimmerman * are enabled 287197ba5f4SPaul Zimmerman * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 288197ba5f4SPaul Zimmerman * dynamic FIFO sizing is enabled 289197ba5f4SPaul Zimmerman * 16 to 32768 290197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 291197ba5f4SPaul Zimmerman * the default. 292197ba5f4SPaul Zimmerman * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 293197ba5f4SPaul Zimmerman * in host mode when dynamic FIFO sizing is enabled 294197ba5f4SPaul Zimmerman * 16 to 32768 295197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 296197ba5f4SPaul Zimmerman * the default. 297197ba5f4SPaul Zimmerman * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 298197ba5f4SPaul Zimmerman * host mode when dynamic FIFO sizing is enabled 299197ba5f4SPaul Zimmerman * 16 to 32768 300197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 301197ba5f4SPaul Zimmerman * the default. 302197ba5f4SPaul Zimmerman * @max_transfer_size: The maximum transfer size supported, in bytes 303197ba5f4SPaul Zimmerman * 2047 to 65,535 304197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 305197ba5f4SPaul Zimmerman * the default. 306197ba5f4SPaul Zimmerman * @max_packet_count: The maximum number of packets in a transfer 307197ba5f4SPaul Zimmerman * 15 to 511 308197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 309197ba5f4SPaul Zimmerman * the default. 310197ba5f4SPaul Zimmerman * @host_channels: The number of host channel registers to use 311197ba5f4SPaul Zimmerman * 1 to 16 312197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 313197ba5f4SPaul Zimmerman * the default. 314197ba5f4SPaul Zimmerman * @phy_type: Specifies the type of PHY interface to use. By default, 315197ba5f4SPaul Zimmerman * the driver will automatically detect the phy_type. 316197ba5f4SPaul Zimmerman * 0 - Full Speed Phy 317197ba5f4SPaul Zimmerman * 1 - UTMI+ Phy 318197ba5f4SPaul Zimmerman * 2 - ULPI Phy 319197ba5f4SPaul Zimmerman * Defaults to best available option (2, 1, then 0) 320197ba5f4SPaul Zimmerman * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 321197ba5f4SPaul Zimmerman * is applicable for a phy_type of UTMI+ or ULPI. (For a 322197ba5f4SPaul Zimmerman * ULPI phy_type, this parameter indicates the data width 323197ba5f4SPaul Zimmerman * between the MAC and the ULPI Wrapper.) Also, this 324197ba5f4SPaul Zimmerman * parameter is applicable only if the OTG_HSPHY_WIDTH cC 325197ba5f4SPaul Zimmerman * parameter was set to "8 and 16 bits", meaning that the 326197ba5f4SPaul Zimmerman * core has been configured to work at either data path 327197ba5f4SPaul Zimmerman * width. 328197ba5f4SPaul Zimmerman * 8 or 16 (default 16 if available) 329197ba5f4SPaul Zimmerman * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 330197ba5f4SPaul Zimmerman * data rate. This parameter is only applicable if phy_type 331197ba5f4SPaul Zimmerman * is ULPI. 332197ba5f4SPaul Zimmerman * 0 - single data rate ULPI interface with 8 bit wide 333197ba5f4SPaul Zimmerman * data bus (default) 334197ba5f4SPaul Zimmerman * 1 - double data rate ULPI interface with 4 bit wide 335197ba5f4SPaul Zimmerman * data bus 336197ba5f4SPaul Zimmerman * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 337197ba5f4SPaul Zimmerman * external supply to drive the VBus 338197ba5f4SPaul Zimmerman * 0 - Internal supply (default) 339197ba5f4SPaul Zimmerman * 1 - External supply 340197ba5f4SPaul Zimmerman * @i2c_enable: Specifies whether to use the I2Cinterface for a full 341197ba5f4SPaul Zimmerman * speed PHY. This parameter is only applicable if phy_type 342197ba5f4SPaul Zimmerman * is FS. 343197ba5f4SPaul Zimmerman * 0 - No (default) 344197ba5f4SPaul Zimmerman * 1 - Yes 345197ba5f4SPaul Zimmerman * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 346197ba5f4SPaul Zimmerman * 0 - No (default) 347197ba5f4SPaul Zimmerman * 1 - Yes 348197ba5f4SPaul Zimmerman * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 349197ba5f4SPaul Zimmerman * when attached to a Full Speed or Low Speed device in 350197ba5f4SPaul Zimmerman * host mode. 351197ba5f4SPaul Zimmerman * 0 - Don't support low power mode (default) 352197ba5f4SPaul Zimmerman * 1 - Support low power mode 353197ba5f4SPaul Zimmerman * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 354197ba5f4SPaul Zimmerman * when connected to a Low Speed device in host 355197ba5f4SPaul Zimmerman * mode. This parameter is applicable only if 356197ba5f4SPaul Zimmerman * host_support_fs_ls_low_power is enabled. 357197ba5f4SPaul Zimmerman * 0 - 48 MHz 358197ba5f4SPaul Zimmerman * (default when phy_type is UTMI+ or ULPI) 359197ba5f4SPaul Zimmerman * 1 - 6 MHz 360197ba5f4SPaul Zimmerman * (default when phy_type is Full Speed) 361197ba5f4SPaul Zimmerman * @ts_dline: Enable Term Select Dline pulsing 362197ba5f4SPaul Zimmerman * 0 - No (default) 363197ba5f4SPaul Zimmerman * 1 - Yes 364197ba5f4SPaul Zimmerman * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 365197ba5f4SPaul Zimmerman * 0 - No (default for core < 2.92a) 366197ba5f4SPaul Zimmerman * 1 - Yes (default for core >= 2.92a) 367197ba5f4SPaul Zimmerman * @ahbcfg: This field allows the default value of the GAHBCFG 368197ba5f4SPaul Zimmerman * register to be overridden 369197ba5f4SPaul Zimmerman * -1 - GAHBCFG value will be set to 0x06 370197ba5f4SPaul Zimmerman * (INCR4, default) 371197ba5f4SPaul Zimmerman * all others - GAHBCFG value will be overridden with 372197ba5f4SPaul Zimmerman * this value 373197ba5f4SPaul Zimmerman * Not all bits can be controlled like this, the 374197ba5f4SPaul Zimmerman * bits defined by GAHBCFG_CTRL_MASK are controlled 375197ba5f4SPaul Zimmerman * by the driver and are ignored in this 376197ba5f4SPaul Zimmerman * configuration value. 377197ba5f4SPaul Zimmerman * @uframe_sched: True to enable the microframe scheduler 378a6d249d8SGregory Herrero * @external_id_pin_ctl: Specifies whether ID pin is handled externally. 379a6d249d8SGregory Herrero * Disable CONIDSTSCHNG controller interrupt in such 380a6d249d8SGregory Herrero * case. 381a6d249d8SGregory Herrero * 0 - No (default) 382a6d249d8SGregory Herrero * 1 - Yes 383285046aaSGregory Herrero * @hibernation: Specifies whether the controller support hibernation. 384285046aaSGregory Herrero * If hibernation is enabled, the controller will enter 385285046aaSGregory Herrero * hibernation in both peripheral and host mode when 386285046aaSGregory Herrero * needed. 387285046aaSGregory Herrero * 0 - No (default) 388285046aaSGregory Herrero * 1 - Yes 389197ba5f4SPaul Zimmerman * 390197ba5f4SPaul Zimmerman * The following parameters may be specified when starting the module. These 391197ba5f4SPaul Zimmerman * parameters define how the DWC_otg controller should be configured. A 392197ba5f4SPaul Zimmerman * value of -1 (or any other out of range value) for any parameter means 393197ba5f4SPaul Zimmerman * to read the value from hardware (if possible) or use the builtin 394197ba5f4SPaul Zimmerman * default described above. 395197ba5f4SPaul Zimmerman */ 396197ba5f4SPaul Zimmerman struct dwc2_core_params { 397197ba5f4SPaul Zimmerman /* 398197ba5f4SPaul Zimmerman * Don't add any non-int members here, this will break 399197ba5f4SPaul Zimmerman * dwc2_set_all_params! 400197ba5f4SPaul Zimmerman */ 401197ba5f4SPaul Zimmerman int otg_cap; 402197ba5f4SPaul Zimmerman int otg_ver; 403197ba5f4SPaul Zimmerman int dma_enable; 404197ba5f4SPaul Zimmerman int dma_desc_enable; 405fbb9e22bSMian Yousaf Kaukab int dma_desc_fs_enable; 406197ba5f4SPaul Zimmerman int speed; 407197ba5f4SPaul Zimmerman int enable_dynamic_fifo; 408197ba5f4SPaul Zimmerman int en_multiple_tx_fifo; 409197ba5f4SPaul Zimmerman int host_rx_fifo_size; 410197ba5f4SPaul Zimmerman int host_nperio_tx_fifo_size; 411197ba5f4SPaul Zimmerman int host_perio_tx_fifo_size; 412197ba5f4SPaul Zimmerman int max_transfer_size; 413197ba5f4SPaul Zimmerman int max_packet_count; 414197ba5f4SPaul Zimmerman int host_channels; 415197ba5f4SPaul Zimmerman int phy_type; 416197ba5f4SPaul Zimmerman int phy_utmi_width; 417197ba5f4SPaul Zimmerman int phy_ulpi_ddr; 418197ba5f4SPaul Zimmerman int phy_ulpi_ext_vbus; 419197ba5f4SPaul Zimmerman int i2c_enable; 420197ba5f4SPaul Zimmerman int ulpi_fs_ls; 421197ba5f4SPaul Zimmerman int host_support_fs_ls_low_power; 422197ba5f4SPaul Zimmerman int host_ls_low_power_phy_clk; 423197ba5f4SPaul Zimmerman int ts_dline; 424197ba5f4SPaul Zimmerman int reload_ctl; 425197ba5f4SPaul Zimmerman int ahbcfg; 426197ba5f4SPaul Zimmerman int uframe_sched; 427a6d249d8SGregory Herrero int external_id_pin_ctl; 428285046aaSGregory Herrero int hibernation; 429197ba5f4SPaul Zimmerman }; 430197ba5f4SPaul Zimmerman 431197ba5f4SPaul Zimmerman /** 432197ba5f4SPaul Zimmerman * struct dwc2_hw_params - Autodetected parameters. 433197ba5f4SPaul Zimmerman * 434197ba5f4SPaul Zimmerman * These parameters are the various parameters read from hardware 435197ba5f4SPaul Zimmerman * registers during initialization. They typically contain the best 436197ba5f4SPaul Zimmerman * supported or maximum value that can be configured in the 437197ba5f4SPaul Zimmerman * corresponding dwc2_core_params value. 438197ba5f4SPaul Zimmerman * 439197ba5f4SPaul Zimmerman * The values that are not in dwc2_core_params are documented below. 440197ba5f4SPaul Zimmerman * 441197ba5f4SPaul Zimmerman * @op_mode Mode of Operation 442197ba5f4SPaul Zimmerman * 0 - HNP- and SRP-Capable OTG (Host & Device) 443197ba5f4SPaul Zimmerman * 1 - SRP-Capable OTG (Host & Device) 444197ba5f4SPaul Zimmerman * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 445197ba5f4SPaul Zimmerman * 3 - SRP-Capable Device 446197ba5f4SPaul Zimmerman * 4 - Non-OTG Device 447197ba5f4SPaul Zimmerman * 5 - SRP-Capable Host 448197ba5f4SPaul Zimmerman * 6 - Non-OTG Host 449197ba5f4SPaul Zimmerman * @arch Architecture 450197ba5f4SPaul Zimmerman * 0 - Slave only 451197ba5f4SPaul Zimmerman * 1 - External DMA 452197ba5f4SPaul Zimmerman * 2 - Internal DMA 453197ba5f4SPaul Zimmerman * @power_optimized Are power optimizations enabled? 454197ba5f4SPaul Zimmerman * @num_dev_ep Number of device endpoints available 455197ba5f4SPaul Zimmerman * @num_dev_perio_in_ep Number of device periodic IN endpoints 456997f4f81SMickael Maison * available 457197ba5f4SPaul Zimmerman * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue 458197ba5f4SPaul Zimmerman * Depth 459197ba5f4SPaul Zimmerman * 0 to 30 460197ba5f4SPaul Zimmerman * @host_perio_tx_q_depth 461197ba5f4SPaul Zimmerman * Host Mode Periodic Request Queue Depth 462197ba5f4SPaul Zimmerman * 2, 4 or 8 463197ba5f4SPaul Zimmerman * @nperio_tx_q_depth 464197ba5f4SPaul Zimmerman * Non-Periodic Request Queue Depth 465197ba5f4SPaul Zimmerman * 2, 4 or 8 466197ba5f4SPaul Zimmerman * @hs_phy_type High-speed PHY interface type 467197ba5f4SPaul Zimmerman * 0 - High-speed interface not supported 468197ba5f4SPaul Zimmerman * 1 - UTMI+ 469197ba5f4SPaul Zimmerman * 2 - ULPI 470197ba5f4SPaul Zimmerman * 3 - UTMI+ and ULPI 471197ba5f4SPaul Zimmerman * @fs_phy_type Full-speed PHY interface type 472197ba5f4SPaul Zimmerman * 0 - Full speed interface not supported 473197ba5f4SPaul Zimmerman * 1 - Dedicated full speed interface 474197ba5f4SPaul Zimmerman * 2 - FS pins shared with UTMI+ pins 475197ba5f4SPaul Zimmerman * 3 - FS pins shared with ULPI pins 476197ba5f4SPaul Zimmerman * @total_fifo_size: Total internal RAM for FIFOs (bytes) 477197ba5f4SPaul Zimmerman * @utmi_phy_data_width UTMI+ PHY data width 478197ba5f4SPaul Zimmerman * 0 - 8 bits 479197ba5f4SPaul Zimmerman * 1 - 16 bits 480197ba5f4SPaul Zimmerman * 2 - 8 or 16 bits 481197ba5f4SPaul Zimmerman * @snpsid: Value from SNPSID register 48255e1040eSJohn Youn * @dev_ep_dirs: Direction of device endpoints (GHWCFG1) 483197ba5f4SPaul Zimmerman */ 484197ba5f4SPaul Zimmerman struct dwc2_hw_params { 485197ba5f4SPaul Zimmerman unsigned op_mode:3; 486197ba5f4SPaul Zimmerman unsigned arch:2; 487197ba5f4SPaul Zimmerman unsigned dma_desc_enable:1; 488fbb9e22bSMian Yousaf Kaukab unsigned dma_desc_fs_enable:1; 489197ba5f4SPaul Zimmerman unsigned enable_dynamic_fifo:1; 490197ba5f4SPaul Zimmerman unsigned en_multiple_tx_fifo:1; 491197ba5f4SPaul Zimmerman unsigned host_rx_fifo_size:16; 492197ba5f4SPaul Zimmerman unsigned host_nperio_tx_fifo_size:16; 49355e1040eSJohn Youn unsigned dev_nperio_tx_fifo_size:16; 494197ba5f4SPaul Zimmerman unsigned host_perio_tx_fifo_size:16; 495197ba5f4SPaul Zimmerman unsigned nperio_tx_q_depth:3; 496197ba5f4SPaul Zimmerman unsigned host_perio_tx_q_depth:3; 497197ba5f4SPaul Zimmerman unsigned dev_token_q_depth:5; 498197ba5f4SPaul Zimmerman unsigned max_transfer_size:26; 499197ba5f4SPaul Zimmerman unsigned max_packet_count:11; 500197ba5f4SPaul Zimmerman unsigned host_channels:5; 501197ba5f4SPaul Zimmerman unsigned hs_phy_type:2; 502197ba5f4SPaul Zimmerman unsigned fs_phy_type:2; 503197ba5f4SPaul Zimmerman unsigned i2c_enable:1; 504197ba5f4SPaul Zimmerman unsigned num_dev_ep:4; 505197ba5f4SPaul Zimmerman unsigned num_dev_perio_in_ep:4; 506197ba5f4SPaul Zimmerman unsigned total_fifo_size:16; 507197ba5f4SPaul Zimmerman unsigned power_optimized:1; 508197ba5f4SPaul Zimmerman unsigned utmi_phy_data_width:2; 509197ba5f4SPaul Zimmerman u32 snpsid; 51055e1040eSJohn Youn u32 dev_ep_dirs; 511197ba5f4SPaul Zimmerman }; 512197ba5f4SPaul Zimmerman 5133f95001dSMian Yousaf Kaukab /* Size of control and EP0 buffers */ 5143f95001dSMian Yousaf Kaukab #define DWC2_CTRL_BUFF_SIZE 8 5153f95001dSMian Yousaf Kaukab 516197ba5f4SPaul Zimmerman /** 517d17ee77bSGregory Herrero * struct dwc2_gregs_backup - Holds global registers state before entering partial 518d17ee77bSGregory Herrero * power down 519d17ee77bSGregory Herrero * @gotgctl: Backup of GOTGCTL register 520d17ee77bSGregory Herrero * @gintmsk: Backup of GINTMSK register 521d17ee77bSGregory Herrero * @gahbcfg: Backup of GAHBCFG register 522d17ee77bSGregory Herrero * @gusbcfg: Backup of GUSBCFG register 523d17ee77bSGregory Herrero * @grxfsiz: Backup of GRXFSIZ register 524d17ee77bSGregory Herrero * @gnptxfsiz: Backup of GNPTXFSIZ register 525d17ee77bSGregory Herrero * @gi2cctl: Backup of GI2CCTL register 526d17ee77bSGregory Herrero * @hptxfsiz: Backup of HPTXFSIZ register 527d17ee77bSGregory Herrero * @gdfifocfg: Backup of GDFIFOCFG register 528d17ee77bSGregory Herrero * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 529d17ee77bSGregory Herrero * @gpwrdn: Backup of GPWRDN register 530d17ee77bSGregory Herrero */ 531d17ee77bSGregory Herrero struct dwc2_gregs_backup { 532d17ee77bSGregory Herrero u32 gotgctl; 533d17ee77bSGregory Herrero u32 gintmsk; 534d17ee77bSGregory Herrero u32 gahbcfg; 535d17ee77bSGregory Herrero u32 gusbcfg; 536d17ee77bSGregory Herrero u32 grxfsiz; 537d17ee77bSGregory Herrero u32 gnptxfsiz; 538d17ee77bSGregory Herrero u32 gi2cctl; 539d17ee77bSGregory Herrero u32 hptxfsiz; 540d17ee77bSGregory Herrero u32 pcgcctl; 541d17ee77bSGregory Herrero u32 gdfifocfg; 542d17ee77bSGregory Herrero u32 dtxfsiz[MAX_EPS_CHANNELS]; 543d17ee77bSGregory Herrero u32 gpwrdn; 544cc1e204cSMian Yousaf Kaukab bool valid; 545d17ee77bSGregory Herrero }; 546d17ee77bSGregory Herrero 547d17ee77bSGregory Herrero /** 548d17ee77bSGregory Herrero * struct dwc2_dregs_backup - Holds device registers state before entering partial 549d17ee77bSGregory Herrero * power down 550d17ee77bSGregory Herrero * @dcfg: Backup of DCFG register 551d17ee77bSGregory Herrero * @dctl: Backup of DCTL register 552d17ee77bSGregory Herrero * @daintmsk: Backup of DAINTMSK register 553d17ee77bSGregory Herrero * @diepmsk: Backup of DIEPMSK register 554d17ee77bSGregory Herrero * @doepmsk: Backup of DOEPMSK register 555d17ee77bSGregory Herrero * @diepctl: Backup of DIEPCTL register 556d17ee77bSGregory Herrero * @dieptsiz: Backup of DIEPTSIZ register 557d17ee77bSGregory Herrero * @diepdma: Backup of DIEPDMA register 558d17ee77bSGregory Herrero * @doepctl: Backup of DOEPCTL register 559d17ee77bSGregory Herrero * @doeptsiz: Backup of DOEPTSIZ register 560d17ee77bSGregory Herrero * @doepdma: Backup of DOEPDMA register 561d17ee77bSGregory Herrero */ 562d17ee77bSGregory Herrero struct dwc2_dregs_backup { 563d17ee77bSGregory Herrero u32 dcfg; 564d17ee77bSGregory Herrero u32 dctl; 565d17ee77bSGregory Herrero u32 daintmsk; 566d17ee77bSGregory Herrero u32 diepmsk; 567d17ee77bSGregory Herrero u32 doepmsk; 568d17ee77bSGregory Herrero u32 diepctl[MAX_EPS_CHANNELS]; 569d17ee77bSGregory Herrero u32 dieptsiz[MAX_EPS_CHANNELS]; 570d17ee77bSGregory Herrero u32 diepdma[MAX_EPS_CHANNELS]; 571d17ee77bSGregory Herrero u32 doepctl[MAX_EPS_CHANNELS]; 572d17ee77bSGregory Herrero u32 doeptsiz[MAX_EPS_CHANNELS]; 573d17ee77bSGregory Herrero u32 doepdma[MAX_EPS_CHANNELS]; 574cc1e204cSMian Yousaf Kaukab bool valid; 575d17ee77bSGregory Herrero }; 576d17ee77bSGregory Herrero 577d17ee77bSGregory Herrero /** 578d17ee77bSGregory Herrero * struct dwc2_hregs_backup - Holds host registers state before entering partial 579d17ee77bSGregory Herrero * power down 580d17ee77bSGregory Herrero * @hcfg: Backup of HCFG register 581d17ee77bSGregory Herrero * @haintmsk: Backup of HAINTMSK register 582d17ee77bSGregory Herrero * @hcintmsk: Backup of HCINTMSK register 583d17ee77bSGregory Herrero * @hptr0: Backup of HPTR0 register 584d17ee77bSGregory Herrero * @hfir: Backup of HFIR register 585d17ee77bSGregory Herrero */ 586d17ee77bSGregory Herrero struct dwc2_hregs_backup { 587d17ee77bSGregory Herrero u32 hcfg; 588d17ee77bSGregory Herrero u32 haintmsk; 589d17ee77bSGregory Herrero u32 hcintmsk[MAX_EPS_CHANNELS]; 590d17ee77bSGregory Herrero u32 hprt0; 591d17ee77bSGregory Herrero u32 hfir; 592cc1e204cSMian Yousaf Kaukab bool valid; 593d17ee77bSGregory Herrero }; 594d17ee77bSGregory Herrero 595d17ee77bSGregory Herrero /** 596197ba5f4SPaul Zimmerman * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 597197ba5f4SPaul Zimmerman * and periodic schedules 598197ba5f4SPaul Zimmerman * 599941fcce4SDinh Nguyen * These are common for both host and peripheral modes: 600941fcce4SDinh Nguyen * 601197ba5f4SPaul Zimmerman * @dev: The struct device pointer 602197ba5f4SPaul Zimmerman * @regs: Pointer to controller regs 603197ba5f4SPaul Zimmerman * @hw_params: Parameters that were autodetected from the 604197ba5f4SPaul Zimmerman * hardware registers 605941fcce4SDinh Nguyen * @core_params: Parameters that define how the core should be configured 606197ba5f4SPaul Zimmerman * @op_state: The operational State, during transitions (a_host=> 607197ba5f4SPaul Zimmerman * a_peripheral and b_device=>b_host) this may not match 608197ba5f4SPaul Zimmerman * the core, but allows the software to determine 609197ba5f4SPaul Zimmerman * transitions 610c0155b9dSKever Yang * @dr_mode: Requested mode of operation, one of following: 611c0155b9dSKever Yang * - USB_DR_MODE_PERIPHERAL 612c0155b9dSKever Yang * - USB_DR_MODE_HOST 613c0155b9dSKever Yang * - USB_DR_MODE_OTG 61409a75e85SMarek Szyprowski * @hcd_enabled Host mode sub-driver initialization indicator. 61509a75e85SMarek Szyprowski * @gadget_enabled Peripheral mode sub-driver initialization indicator. 61609a75e85SMarek Szyprowski * @ll_hw_enabled Status of low-level hardware resources. 61709a75e85SMarek Szyprowski * @phy: The otg phy transceiver structure for phy control. 61809a75e85SMarek Szyprowski * @uphy: The otg phy transceiver structure for old USB phy control. 61909a75e85SMarek Szyprowski * @plat: The platform specific configuration data. This can be removed once 62009a75e85SMarek Szyprowski * all SoCs support usb transceiver. 62109a75e85SMarek Szyprowski * @supplies: Definition of USB power supplies 62209a75e85SMarek Szyprowski * @phyif: PHY interface width 623941fcce4SDinh Nguyen * @lock: Spinlock that protects all the driver data structures 624941fcce4SDinh Nguyen * @priv: Stores a pointer to the struct usb_hcd 625197ba5f4SPaul Zimmerman * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 626197ba5f4SPaul Zimmerman * transfer are in process of being queued 627197ba5f4SPaul Zimmerman * @srp_success: Stores status of SRP request in the case of a FS PHY 628197ba5f4SPaul Zimmerman * with an I2C interface 629197ba5f4SPaul Zimmerman * @wq_otg: Workqueue object used for handling of some interrupts 630197ba5f4SPaul Zimmerman * @wf_otg: Work object for handling Connector ID Status Change 631197ba5f4SPaul Zimmerman * interrupt 632197ba5f4SPaul Zimmerman * @wkp_timer: Timer object for handling Wakeup Detected interrupt 633197ba5f4SPaul Zimmerman * @lx_state: Lx state of connected device 634d17ee77bSGregory Herrero * @gregs_backup: Backup of global registers during suspend 635d17ee77bSGregory Herrero * @dregs_backup: Backup of device registers during suspend 636d17ee77bSGregory Herrero * @hregs_backup: Backup of host registers during suspend 637941fcce4SDinh Nguyen * 638941fcce4SDinh Nguyen * These are for host mode: 639941fcce4SDinh Nguyen * 640197ba5f4SPaul Zimmerman * @flags: Flags for handling root port state changes 641197ba5f4SPaul Zimmerman * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 642197ba5f4SPaul Zimmerman * Transfers associated with these QHs are not currently 643197ba5f4SPaul Zimmerman * assigned to a host channel. 644197ba5f4SPaul Zimmerman * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 645197ba5f4SPaul Zimmerman * Transfers associated with these QHs are currently 646197ba5f4SPaul Zimmerman * assigned to a host channel. 647197ba5f4SPaul Zimmerman * @non_periodic_qh_ptr: Pointer to next QH to process in the active 648197ba5f4SPaul Zimmerman * non-periodic schedule 649197ba5f4SPaul Zimmerman * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 650197ba5f4SPaul Zimmerman * list of QHs for periodic transfers that are _not_ 651197ba5f4SPaul Zimmerman * scheduled for the next frame. Each QH in the list has an 652197ba5f4SPaul Zimmerman * interval counter that determines when it needs to be 653197ba5f4SPaul Zimmerman * scheduled for execution. This scheduling mechanism 654197ba5f4SPaul Zimmerman * allows only a simple calculation for periodic bandwidth 655197ba5f4SPaul Zimmerman * used (i.e. must assume that all periodic transfers may 656197ba5f4SPaul Zimmerman * need to execute in the same frame). However, it greatly 657197ba5f4SPaul Zimmerman * simplifies scheduling and should be sufficient for the 658197ba5f4SPaul Zimmerman * vast majority of OTG hosts, which need to connect to a 659197ba5f4SPaul Zimmerman * small number of peripherals at one time. Items move from 660197ba5f4SPaul Zimmerman * this list to periodic_sched_ready when the QH interval 661197ba5f4SPaul Zimmerman * counter is 0 at SOF. 662197ba5f4SPaul Zimmerman * @periodic_sched_ready: List of periodic QHs that are ready for execution in 663197ba5f4SPaul Zimmerman * the next frame, but have not yet been assigned to host 664197ba5f4SPaul Zimmerman * channels. Items move from this list to 665197ba5f4SPaul Zimmerman * periodic_sched_assigned as host channels become 666197ba5f4SPaul Zimmerman * available during the current frame. 667197ba5f4SPaul Zimmerman * @periodic_sched_assigned: List of periodic QHs to be executed in the next 668197ba5f4SPaul Zimmerman * frame that are assigned to host channels. Items move 669197ba5f4SPaul Zimmerman * from this list to periodic_sched_queued as the 670197ba5f4SPaul Zimmerman * transactions for the QH are queued to the DWC_otg 671197ba5f4SPaul Zimmerman * controller. 672197ba5f4SPaul Zimmerman * @periodic_sched_queued: List of periodic QHs that have been queued for 673197ba5f4SPaul Zimmerman * execution. Items move from this list to either 674197ba5f4SPaul Zimmerman * periodic_sched_inactive or periodic_sched_ready when the 675197ba5f4SPaul Zimmerman * channel associated with the transfer is released. If the 676197ba5f4SPaul Zimmerman * interval for the QH is 1, the item moves to 677197ba5f4SPaul Zimmerman * periodic_sched_ready because it must be rescheduled for 678197ba5f4SPaul Zimmerman * the next frame. Otherwise, the item moves to 679197ba5f4SPaul Zimmerman * periodic_sched_inactive. 680c9c8ac01SDouglas Anderson * @split_order: List keeping track of channels doing splits, in order. 681197ba5f4SPaul Zimmerman * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 682197ba5f4SPaul Zimmerman * This value is in microseconds per (micro)frame. The 683197ba5f4SPaul Zimmerman * assumption is that all periodic transfers may occur in 684197ba5f4SPaul Zimmerman * the same (micro)frame. 685197ba5f4SPaul Zimmerman * @frame_usecs: Internal variable used by the microframe scheduler 686197ba5f4SPaul Zimmerman * @frame_number: Frame number read from the core at SOF. The value ranges 687197ba5f4SPaul Zimmerman * from 0 to HFNUM_MAX_FRNUM. 688197ba5f4SPaul Zimmerman * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 689197ba5f4SPaul Zimmerman * SOF enable/disable. 690197ba5f4SPaul Zimmerman * @free_hc_list: Free host channels in the controller. This is a list of 691197ba5f4SPaul Zimmerman * struct dwc2_host_chan items. 692197ba5f4SPaul Zimmerman * @periodic_channels: Number of host channels assigned to periodic transfers. 693197ba5f4SPaul Zimmerman * Currently assuming that there is a dedicated host 694197ba5f4SPaul Zimmerman * channel for each periodic transaction and at least one 695197ba5f4SPaul Zimmerman * host channel is available for non-periodic transactions. 696197ba5f4SPaul Zimmerman * @non_periodic_channels: Number of host channels assigned to non-periodic 697197ba5f4SPaul Zimmerman * transfers 698197ba5f4SPaul Zimmerman * @available_host_channels Number of host channels available for the microframe 699197ba5f4SPaul Zimmerman * scheduler to use 700197ba5f4SPaul Zimmerman * @hc_ptr_array: Array of pointers to the host channel descriptors. 701197ba5f4SPaul Zimmerman * Allows accessing a host channel descriptor given the 702197ba5f4SPaul Zimmerman * host channel number. This is useful in interrupt 703197ba5f4SPaul Zimmerman * handlers. 704197ba5f4SPaul Zimmerman * @status_buf: Buffer used for data received during the status phase of 705197ba5f4SPaul Zimmerman * a control transfer. 706197ba5f4SPaul Zimmerman * @status_buf_dma: DMA address for status_buf 707197ba5f4SPaul Zimmerman * @start_work: Delayed work for handling host A-cable connection 708197ba5f4SPaul Zimmerman * @reset_work: Delayed work for handling a port reset 709197ba5f4SPaul Zimmerman * @otg_port: OTG port number 710197ba5f4SPaul Zimmerman * @frame_list: Frame list 711197ba5f4SPaul Zimmerman * @frame_list_dma: Frame list DMA address 71295105a99SGregory Herrero * @frame_list_sz: Frame list size 7133b5fcc9aSGregory Herrero * @desc_gen_cache: Kmem cache for generic descriptors 7143b5fcc9aSGregory Herrero * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors 715941fcce4SDinh Nguyen * 716941fcce4SDinh Nguyen * These are for peripheral mode: 717941fcce4SDinh Nguyen * 718941fcce4SDinh Nguyen * @driver: USB gadget driver 719941fcce4SDinh Nguyen * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 720941fcce4SDinh Nguyen * @num_of_eps: Number of available EPs (excluding EP0) 721941fcce4SDinh Nguyen * @debug_root: Root directrory for debugfs. 722941fcce4SDinh Nguyen * @debug_file: Main status file for debugfs. 7239e14d0a5SGregory Herrero * @debug_testmode: Testmode status file for debugfs. 724941fcce4SDinh Nguyen * @debug_fifo: FIFO status file for debugfs. 725941fcce4SDinh Nguyen * @ep0_reply: Request used for ep0 reply. 726941fcce4SDinh Nguyen * @ep0_buff: Buffer for EP0 reply data, if needed. 727941fcce4SDinh Nguyen * @ctrl_buff: Buffer for EP0 control requests. 728941fcce4SDinh Nguyen * @ctrl_req: Request for EP0 control packets. 729fe0b94abSMian Yousaf Kaukab * @ep0_state: EP0 control transfers state 7309e14d0a5SGregory Herrero * @test_mode: USB test mode requested by the host 731941fcce4SDinh Nguyen * @eps: The endpoints being supplied to the gadget framework 732edd74be8SGregory Herrero * @g_using_dma: Indicate if dma usage is enabled 7330a176279SGregory Herrero * @g_rx_fifo_sz: Contains rx fifo size value 7340a176279SGregory Herrero * @g_np_g_tx_fifo_sz: Contains Non-Periodic tx fifo size value 7350a176279SGregory Herrero * @g_tx_fifo_sz: Contains tx fifo size value per endpoints 736197ba5f4SPaul Zimmerman */ 737197ba5f4SPaul Zimmerman struct dwc2_hsotg { 738197ba5f4SPaul Zimmerman struct device *dev; 739197ba5f4SPaul Zimmerman void __iomem *regs; 740197ba5f4SPaul Zimmerman /** Params detected from hardware */ 741197ba5f4SPaul Zimmerman struct dwc2_hw_params hw_params; 742197ba5f4SPaul Zimmerman /** Params to actually use */ 743197ba5f4SPaul Zimmerman struct dwc2_core_params *core_params; 744197ba5f4SPaul Zimmerman enum usb_otg_state op_state; 745c0155b9dSKever Yang enum usb_dr_mode dr_mode; 746e39af88fSMarek Szyprowski unsigned int hcd_enabled:1; 747e39af88fSMarek Szyprowski unsigned int gadget_enabled:1; 74809a75e85SMarek Szyprowski unsigned int ll_hw_enabled:1; 749197ba5f4SPaul Zimmerman 750941fcce4SDinh Nguyen struct phy *phy; 751941fcce4SDinh Nguyen struct usb_phy *uphy; 75209a75e85SMarek Szyprowski struct dwc2_hsotg_plat *plat; 7531f91b4ccSFelipe Balbi struct regulator_bulk_data supplies[ARRAY_SIZE(dwc2_hsotg_supply_names)]; 75409a75e85SMarek Szyprowski u32 phyif; 755941fcce4SDinh Nguyen 756941fcce4SDinh Nguyen spinlock_t lock; 757941fcce4SDinh Nguyen void *priv; 758941fcce4SDinh Nguyen int irq; 759941fcce4SDinh Nguyen struct clk *clk; 760941fcce4SDinh Nguyen 761197ba5f4SPaul Zimmerman unsigned int queuing_high_bandwidth:1; 762197ba5f4SPaul Zimmerman unsigned int srp_success:1; 763197ba5f4SPaul Zimmerman 764197ba5f4SPaul Zimmerman struct workqueue_struct *wq_otg; 765197ba5f4SPaul Zimmerman struct work_struct wf_otg; 766197ba5f4SPaul Zimmerman struct timer_list wkp_timer; 767197ba5f4SPaul Zimmerman enum dwc2_lx_state lx_state; 768cc1e204cSMian Yousaf Kaukab struct dwc2_gregs_backup gr_backup; 769cc1e204cSMian Yousaf Kaukab struct dwc2_dregs_backup dr_backup; 770cc1e204cSMian Yousaf Kaukab struct dwc2_hregs_backup hr_backup; 771197ba5f4SPaul Zimmerman 772941fcce4SDinh Nguyen struct dentry *debug_root; 773563cf017SMian Yousaf Kaukab struct debugfs_regset32 *regset; 774941fcce4SDinh Nguyen 775941fcce4SDinh Nguyen /* DWC OTG HW Release versions */ 776941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_71a 0x4f54271a 777941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_90a 0x4f54290a 778941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_92a 0x4f54292a 779941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_94a 0x4f54294a 780941fcce4SDinh Nguyen #define DWC2_CORE_REV_3_00a 0x4f54300a 781941fcce4SDinh Nguyen 782941fcce4SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 783197ba5f4SPaul Zimmerman union dwc2_hcd_internal_flags { 784197ba5f4SPaul Zimmerman u32 d32; 785197ba5f4SPaul Zimmerman struct { 786197ba5f4SPaul Zimmerman unsigned port_connect_status_change:1; 787197ba5f4SPaul Zimmerman unsigned port_connect_status:1; 788197ba5f4SPaul Zimmerman unsigned port_reset_change:1; 789197ba5f4SPaul Zimmerman unsigned port_enable_change:1; 790197ba5f4SPaul Zimmerman unsigned port_suspend_change:1; 791197ba5f4SPaul Zimmerman unsigned port_over_current_change:1; 792197ba5f4SPaul Zimmerman unsigned port_l1_change:1; 793fd4850cfSCharles Manning unsigned reserved:25; 794197ba5f4SPaul Zimmerman } b; 795197ba5f4SPaul Zimmerman } flags; 796197ba5f4SPaul Zimmerman 797197ba5f4SPaul Zimmerman struct list_head non_periodic_sched_inactive; 798197ba5f4SPaul Zimmerman struct list_head non_periodic_sched_active; 799197ba5f4SPaul Zimmerman struct list_head *non_periodic_qh_ptr; 800197ba5f4SPaul Zimmerman struct list_head periodic_sched_inactive; 801197ba5f4SPaul Zimmerman struct list_head periodic_sched_ready; 802197ba5f4SPaul Zimmerman struct list_head periodic_sched_assigned; 803197ba5f4SPaul Zimmerman struct list_head periodic_sched_queued; 804c9c8ac01SDouglas Anderson struct list_head split_order; 805197ba5f4SPaul Zimmerman u16 periodic_usecs; 806197ba5f4SPaul Zimmerman u16 frame_usecs[8]; 807197ba5f4SPaul Zimmerman u16 frame_number; 808197ba5f4SPaul Zimmerman u16 periodic_qh_count; 809734643dfSGregory Herrero bool bus_suspended; 810fbb9e22bSMian Yousaf Kaukab bool new_connection; 811197ba5f4SPaul Zimmerman 812197ba5f4SPaul Zimmerman #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 813197ba5f4SPaul Zimmerman #define FRAME_NUM_ARRAY_SIZE 1000 814197ba5f4SPaul Zimmerman u16 last_frame_num; 815197ba5f4SPaul Zimmerman u16 *frame_num_array; 816197ba5f4SPaul Zimmerman u16 *last_frame_num_array; 817197ba5f4SPaul Zimmerman int frame_num_idx; 818197ba5f4SPaul Zimmerman int dumped_frame_num_array; 819197ba5f4SPaul Zimmerman #endif 820197ba5f4SPaul Zimmerman 821197ba5f4SPaul Zimmerman struct list_head free_hc_list; 822197ba5f4SPaul Zimmerman int periodic_channels; 823197ba5f4SPaul Zimmerman int non_periodic_channels; 824197ba5f4SPaul Zimmerman int available_host_channels; 825197ba5f4SPaul Zimmerman struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 826197ba5f4SPaul Zimmerman u8 *status_buf; 827197ba5f4SPaul Zimmerman dma_addr_t status_buf_dma; 828197ba5f4SPaul Zimmerman #define DWC2_HCD_STATUS_BUF_SIZE 64 829197ba5f4SPaul Zimmerman 830197ba5f4SPaul Zimmerman struct delayed_work start_work; 831197ba5f4SPaul Zimmerman struct delayed_work reset_work; 832197ba5f4SPaul Zimmerman u8 otg_port; 833197ba5f4SPaul Zimmerman u32 *frame_list; 834197ba5f4SPaul Zimmerman dma_addr_t frame_list_dma; 83595105a99SGregory Herrero u32 frame_list_sz; 8363b5fcc9aSGregory Herrero struct kmem_cache *desc_gen_cache; 8373b5fcc9aSGregory Herrero struct kmem_cache *desc_hsisoc_cache; 838197ba5f4SPaul Zimmerman 839197ba5f4SPaul Zimmerman #ifdef DEBUG 840197ba5f4SPaul Zimmerman u32 frrem_samples; 841197ba5f4SPaul Zimmerman u64 frrem_accum; 842197ba5f4SPaul Zimmerman 843197ba5f4SPaul Zimmerman u32 hfnum_7_samples_a; 844197ba5f4SPaul Zimmerman u64 hfnum_7_frrem_accum_a; 845197ba5f4SPaul Zimmerman u32 hfnum_0_samples_a; 846197ba5f4SPaul Zimmerman u64 hfnum_0_frrem_accum_a; 847197ba5f4SPaul Zimmerman u32 hfnum_other_samples_a; 848197ba5f4SPaul Zimmerman u64 hfnum_other_frrem_accum_a; 849197ba5f4SPaul Zimmerman 850197ba5f4SPaul Zimmerman u32 hfnum_7_samples_b; 851197ba5f4SPaul Zimmerman u64 hfnum_7_frrem_accum_b; 852197ba5f4SPaul Zimmerman u32 hfnum_0_samples_b; 853197ba5f4SPaul Zimmerman u64 hfnum_0_frrem_accum_b; 854197ba5f4SPaul Zimmerman u32 hfnum_other_samples_b; 855197ba5f4SPaul Zimmerman u64 hfnum_other_frrem_accum_b; 856197ba5f4SPaul Zimmerman #endif 857941fcce4SDinh Nguyen #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ 858941fcce4SDinh Nguyen 859941fcce4SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 860941fcce4SDinh Nguyen /* Gadget structures */ 861941fcce4SDinh Nguyen struct usb_gadget_driver *driver; 862941fcce4SDinh Nguyen int fifo_mem; 863941fcce4SDinh Nguyen unsigned int dedicated_fifos:1; 864941fcce4SDinh Nguyen unsigned char num_of_eps; 865941fcce4SDinh Nguyen u32 fifo_map; 866941fcce4SDinh Nguyen 867941fcce4SDinh Nguyen struct usb_request *ep0_reply; 868941fcce4SDinh Nguyen struct usb_request *ctrl_req; 8693f95001dSMian Yousaf Kaukab void *ep0_buff; 8703f95001dSMian Yousaf Kaukab void *ctrl_buff; 871fe0b94abSMian Yousaf Kaukab enum dwc2_ep0_state ep0_state; 8729e14d0a5SGregory Herrero u8 test_mode; 873941fcce4SDinh Nguyen 874941fcce4SDinh Nguyen struct usb_gadget gadget; 875dc6e69e6SMarek Szyprowski unsigned int enabled:1; 8764ace06e8SMarek Szyprowski unsigned int connected:1; 8771f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS]; 8781f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS]; 879edd74be8SGregory Herrero u32 g_using_dma; 8800a176279SGregory Herrero u32 g_rx_fifo_sz; 8810a176279SGregory Herrero u32 g_np_g_tx_fifo_sz; 8820a176279SGregory Herrero u32 g_tx_fifo_sz[MAX_EPS_CHANNELS]; 883941fcce4SDinh Nguyen #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 884197ba5f4SPaul Zimmerman }; 885197ba5f4SPaul Zimmerman 886197ba5f4SPaul Zimmerman /* Reasons for halting a host channel */ 887197ba5f4SPaul Zimmerman enum dwc2_halt_status { 888197ba5f4SPaul Zimmerman DWC2_HC_XFER_NO_HALT_STATUS, 889197ba5f4SPaul Zimmerman DWC2_HC_XFER_COMPLETE, 890197ba5f4SPaul Zimmerman DWC2_HC_XFER_URB_COMPLETE, 891197ba5f4SPaul Zimmerman DWC2_HC_XFER_ACK, 892197ba5f4SPaul Zimmerman DWC2_HC_XFER_NAK, 893197ba5f4SPaul Zimmerman DWC2_HC_XFER_NYET, 894197ba5f4SPaul Zimmerman DWC2_HC_XFER_STALL, 895197ba5f4SPaul Zimmerman DWC2_HC_XFER_XACT_ERR, 896197ba5f4SPaul Zimmerman DWC2_HC_XFER_FRAME_OVERRUN, 897197ba5f4SPaul Zimmerman DWC2_HC_XFER_BABBLE_ERR, 898197ba5f4SPaul Zimmerman DWC2_HC_XFER_DATA_TOGGLE_ERR, 899197ba5f4SPaul Zimmerman DWC2_HC_XFER_AHB_ERR, 900197ba5f4SPaul Zimmerman DWC2_HC_XFER_PERIODIC_INCOMPLETE, 901197ba5f4SPaul Zimmerman DWC2_HC_XFER_URB_DEQUEUE, 902197ba5f4SPaul Zimmerman }; 903197ba5f4SPaul Zimmerman 904197ba5f4SPaul Zimmerman /* 905197ba5f4SPaul Zimmerman * The following functions support initialization of the core driver component 906197ba5f4SPaul Zimmerman * and the DWC_otg controller 907197ba5f4SPaul Zimmerman */ 908b5d308abSJohn Youn extern int dwc2_core_reset(struct dwc2_hsotg *hsotg); 9096d58f346SJohn Youn extern int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg); 910197ba5f4SPaul Zimmerman extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg); 911d17ee77bSGregory Herrero extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg); 912d17ee77bSGregory Herrero extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore); 913197ba5f4SPaul Zimmerman 91409c96980SJohn Youn void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg); 91509c96980SJohn Youn 916197ba5f4SPaul Zimmerman /* 917197ba5f4SPaul Zimmerman * Host core Functions. 918197ba5f4SPaul Zimmerman * The following functions support managing the DWC_otg controller in host 919197ba5f4SPaul Zimmerman * mode. 920197ba5f4SPaul Zimmerman */ 921197ba5f4SPaul Zimmerman extern void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan); 922197ba5f4SPaul Zimmerman extern void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 923197ba5f4SPaul Zimmerman enum dwc2_halt_status halt_status); 924197ba5f4SPaul Zimmerman extern void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, 925197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan); 926197ba5f4SPaul Zimmerman extern void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 927197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan); 928197ba5f4SPaul Zimmerman extern void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 929197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan); 930197ba5f4SPaul Zimmerman extern int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 931197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan); 932197ba5f4SPaul Zimmerman extern void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, 933197ba5f4SPaul Zimmerman struct dwc2_host_chan *chan); 934197ba5f4SPaul Zimmerman extern void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg); 935197ba5f4SPaul Zimmerman extern void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg); 936197ba5f4SPaul Zimmerman 937197ba5f4SPaul Zimmerman extern u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg); 938197ba5f4SPaul Zimmerman extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 939197ba5f4SPaul Zimmerman 940197ba5f4SPaul Zimmerman /* 941197ba5f4SPaul Zimmerman * Common core Functions. 942197ba5f4SPaul Zimmerman * The following functions support managing the DWC_otg controller in either 943197ba5f4SPaul Zimmerman * device or host mode. 944197ba5f4SPaul Zimmerman */ 945197ba5f4SPaul Zimmerman extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 946197ba5f4SPaul Zimmerman extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 947197ba5f4SPaul Zimmerman extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 948197ba5f4SPaul Zimmerman 9490fe239bcSDouglas Anderson extern int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup); 950197ba5f4SPaul Zimmerman extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 951197ba5f4SPaul Zimmerman extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 952197ba5f4SPaul Zimmerman 953197ba5f4SPaul Zimmerman /* This function should be called on every hardware interrupt. */ 954197ba5f4SPaul Zimmerman extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 955197ba5f4SPaul Zimmerman 956197ba5f4SPaul Zimmerman /* OTG Core Parameters */ 957197ba5f4SPaul Zimmerman 958197ba5f4SPaul Zimmerman /* 959197ba5f4SPaul Zimmerman * Specifies the OTG capabilities. The driver will automatically 960197ba5f4SPaul Zimmerman * detect the value for this parameter if none is specified. 961197ba5f4SPaul Zimmerman * 0 - HNP and SRP capable (default) 962197ba5f4SPaul Zimmerman * 1 - SRP Only capable 963197ba5f4SPaul Zimmerman * 2 - No HNP/SRP capable 964197ba5f4SPaul Zimmerman */ 965197ba5f4SPaul Zimmerman extern void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val); 966197ba5f4SPaul Zimmerman #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 967197ba5f4SPaul Zimmerman #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 968197ba5f4SPaul Zimmerman #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 969197ba5f4SPaul Zimmerman 970197ba5f4SPaul Zimmerman /* 971197ba5f4SPaul Zimmerman * Specifies whether to use slave or DMA mode for accessing the data 972197ba5f4SPaul Zimmerman * FIFOs. The driver will automatically detect the value for this 973197ba5f4SPaul Zimmerman * parameter if none is specified. 974197ba5f4SPaul Zimmerman * 0 - Slave 975197ba5f4SPaul Zimmerman * 1 - DMA (default, if available) 976197ba5f4SPaul Zimmerman */ 977197ba5f4SPaul Zimmerman extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val); 978197ba5f4SPaul Zimmerman 979197ba5f4SPaul Zimmerman /* 980197ba5f4SPaul Zimmerman * When DMA mode is enabled specifies whether to use 981197ba5f4SPaul Zimmerman * address DMA or DMA Descritor mode for accessing the data 982197ba5f4SPaul Zimmerman * FIFOs in device mode. The driver will automatically detect 983197ba5f4SPaul Zimmerman * the value for this parameter if none is specified. 984197ba5f4SPaul Zimmerman * 0 - address DMA 985197ba5f4SPaul Zimmerman * 1 - DMA Descriptor(default, if available) 986197ba5f4SPaul Zimmerman */ 987197ba5f4SPaul Zimmerman extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val); 988197ba5f4SPaul Zimmerman 989197ba5f4SPaul Zimmerman /* 990fbb9e22bSMian Yousaf Kaukab * When DMA mode is enabled specifies whether to use 991fbb9e22bSMian Yousaf Kaukab * address DMA or DMA Descritor mode with full speed devices 992fbb9e22bSMian Yousaf Kaukab * for accessing the data FIFOs in host mode. 993fbb9e22bSMian Yousaf Kaukab * 0 - address DMA 994fbb9e22bSMian Yousaf Kaukab * 1 - FS DMA Descriptor(default, if available) 995fbb9e22bSMian Yousaf Kaukab */ 996fbb9e22bSMian Yousaf Kaukab extern void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg, 997fbb9e22bSMian Yousaf Kaukab int val); 998fbb9e22bSMian Yousaf Kaukab 999fbb9e22bSMian Yousaf Kaukab /* 1000197ba5f4SPaul Zimmerman * Specifies the maximum speed of operation in host and device mode. 1001197ba5f4SPaul Zimmerman * The actual speed depends on the speed of the attached device and 1002197ba5f4SPaul Zimmerman * the value of phy_type. The actual speed depends on the speed of the 1003197ba5f4SPaul Zimmerman * attached device. 1004197ba5f4SPaul Zimmerman * 0 - High Speed (default) 1005197ba5f4SPaul Zimmerman * 1 - Full Speed 1006197ba5f4SPaul Zimmerman */ 1007197ba5f4SPaul Zimmerman extern void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val); 1008197ba5f4SPaul Zimmerman #define DWC2_SPEED_PARAM_HIGH 0 1009197ba5f4SPaul Zimmerman #define DWC2_SPEED_PARAM_FULL 1 1010197ba5f4SPaul Zimmerman 1011197ba5f4SPaul Zimmerman /* 1012197ba5f4SPaul Zimmerman * Specifies whether low power mode is supported when attached 1013197ba5f4SPaul Zimmerman * to a Full Speed or Low Speed device in host mode. 1014197ba5f4SPaul Zimmerman * 1015197ba5f4SPaul Zimmerman * 0 - Don't support low power mode (default) 1016197ba5f4SPaul Zimmerman * 1 - Support low power mode 1017197ba5f4SPaul Zimmerman */ 1018197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_support_fs_ls_low_power( 1019197ba5f4SPaul Zimmerman struct dwc2_hsotg *hsotg, int val); 1020197ba5f4SPaul Zimmerman 1021197ba5f4SPaul Zimmerman /* 1022197ba5f4SPaul Zimmerman * Specifies the PHY clock rate in low power mode when connected to a 1023197ba5f4SPaul Zimmerman * Low Speed device in host mode. This parameter is applicable only if 1024197ba5f4SPaul Zimmerman * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS 1025197ba5f4SPaul Zimmerman * then defaults to 6 MHZ otherwise 48 MHZ. 1026197ba5f4SPaul Zimmerman * 1027197ba5f4SPaul Zimmerman * 0 - 48 MHz 1028197ba5f4SPaul Zimmerman * 1 - 6 MHz 1029197ba5f4SPaul Zimmerman */ 1030197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, 1031197ba5f4SPaul Zimmerman int val); 1032197ba5f4SPaul Zimmerman #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 1033197ba5f4SPaul Zimmerman #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 1034197ba5f4SPaul Zimmerman 1035197ba5f4SPaul Zimmerman /* 1036197ba5f4SPaul Zimmerman * 0 - Use cC FIFO size parameters 1037197ba5f4SPaul Zimmerman * 1 - Allow dynamic FIFO sizing (default) 1038197ba5f4SPaul Zimmerman */ 1039197ba5f4SPaul Zimmerman extern void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, 1040197ba5f4SPaul Zimmerman int val); 1041197ba5f4SPaul Zimmerman 1042197ba5f4SPaul Zimmerman /* 1043197ba5f4SPaul Zimmerman * Number of 4-byte words in the Rx FIFO in host mode when dynamic 1044197ba5f4SPaul Zimmerman * FIFO sizing is enabled. 1045197ba5f4SPaul Zimmerman * 16 to 32768 (default 1024) 1046197ba5f4SPaul Zimmerman */ 1047197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val); 1048197ba5f4SPaul Zimmerman 1049197ba5f4SPaul Zimmerman /* 1050197ba5f4SPaul Zimmerman * Number of 4-byte words in the non-periodic Tx FIFO in host mode 1051197ba5f4SPaul Zimmerman * when Dynamic FIFO sizing is enabled in the core. 1052197ba5f4SPaul Zimmerman * 16 to 32768 (default 256) 1053197ba5f4SPaul Zimmerman */ 1054197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, 1055197ba5f4SPaul Zimmerman int val); 1056197ba5f4SPaul Zimmerman 1057197ba5f4SPaul Zimmerman /* 1058197ba5f4SPaul Zimmerman * Number of 4-byte words in the host periodic Tx FIFO when dynamic 1059197ba5f4SPaul Zimmerman * FIFO sizing is enabled. 1060197ba5f4SPaul Zimmerman * 16 to 32768 (default 256) 1061197ba5f4SPaul Zimmerman */ 1062197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, 1063197ba5f4SPaul Zimmerman int val); 1064197ba5f4SPaul Zimmerman 1065197ba5f4SPaul Zimmerman /* 1066197ba5f4SPaul Zimmerman * The maximum transfer size supported in bytes. 1067197ba5f4SPaul Zimmerman * 2047 to 65,535 (default 65,535) 1068197ba5f4SPaul Zimmerman */ 1069197ba5f4SPaul Zimmerman extern void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val); 1070197ba5f4SPaul Zimmerman 1071197ba5f4SPaul Zimmerman /* 1072197ba5f4SPaul Zimmerman * The maximum number of packets in a transfer. 1073197ba5f4SPaul Zimmerman * 15 to 511 (default 511) 1074197ba5f4SPaul Zimmerman */ 1075197ba5f4SPaul Zimmerman extern void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val); 1076197ba5f4SPaul Zimmerman 1077197ba5f4SPaul Zimmerman /* 1078197ba5f4SPaul Zimmerman * The number of host channel registers to use. 1079197ba5f4SPaul Zimmerman * 1 to 16 (default 11) 1080197ba5f4SPaul Zimmerman * Note: The FPGA configuration supports a maximum of 11 host channels. 1081197ba5f4SPaul Zimmerman */ 1082197ba5f4SPaul Zimmerman extern void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val); 1083197ba5f4SPaul Zimmerman 1084197ba5f4SPaul Zimmerman /* 1085197ba5f4SPaul Zimmerman * Specifies the type of PHY interface to use. By default, the driver 1086197ba5f4SPaul Zimmerman * will automatically detect the phy_type. 1087197ba5f4SPaul Zimmerman * 1088197ba5f4SPaul Zimmerman * 0 - Full Speed PHY 1089197ba5f4SPaul Zimmerman * 1 - UTMI+ (default) 1090197ba5f4SPaul Zimmerman * 2 - ULPI 1091197ba5f4SPaul Zimmerman */ 1092197ba5f4SPaul Zimmerman extern void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val); 1093197ba5f4SPaul Zimmerman #define DWC2_PHY_TYPE_PARAM_FS 0 1094197ba5f4SPaul Zimmerman #define DWC2_PHY_TYPE_PARAM_UTMI 1 1095197ba5f4SPaul Zimmerman #define DWC2_PHY_TYPE_PARAM_ULPI 2 1096197ba5f4SPaul Zimmerman 1097197ba5f4SPaul Zimmerman /* 1098197ba5f4SPaul Zimmerman * Specifies the UTMI+ Data Width. This parameter is 1099197ba5f4SPaul Zimmerman * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI 1100197ba5f4SPaul Zimmerman * PHY_TYPE, this parameter indicates the data width between 1101197ba5f4SPaul Zimmerman * the MAC and the ULPI Wrapper.) Also, this parameter is 1102197ba5f4SPaul Zimmerman * applicable only if the OTG_HSPHY_WIDTH cC parameter was set 1103197ba5f4SPaul Zimmerman * to "8 and 16 bits", meaning that the core has been 1104197ba5f4SPaul Zimmerman * configured to work at either data path width. 1105197ba5f4SPaul Zimmerman * 1106197ba5f4SPaul Zimmerman * 8 or 16 bits (default 16) 1107197ba5f4SPaul Zimmerman */ 1108197ba5f4SPaul Zimmerman extern void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val); 1109197ba5f4SPaul Zimmerman 1110197ba5f4SPaul Zimmerman /* 1111197ba5f4SPaul Zimmerman * Specifies whether the ULPI operates at double or single 1112197ba5f4SPaul Zimmerman * data rate. This parameter is only applicable if PHY_TYPE is 1113197ba5f4SPaul Zimmerman * ULPI. 1114197ba5f4SPaul Zimmerman * 1115197ba5f4SPaul Zimmerman * 0 - single data rate ULPI interface with 8 bit wide data 1116197ba5f4SPaul Zimmerman * bus (default) 1117197ba5f4SPaul Zimmerman * 1 - double data rate ULPI interface with 4 bit wide data 1118197ba5f4SPaul Zimmerman * bus 1119197ba5f4SPaul Zimmerman */ 1120197ba5f4SPaul Zimmerman extern void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val); 1121197ba5f4SPaul Zimmerman 1122197ba5f4SPaul Zimmerman /* 1123197ba5f4SPaul Zimmerman * Specifies whether to use the internal or external supply to 1124197ba5f4SPaul Zimmerman * drive the vbus with a ULPI phy. 1125197ba5f4SPaul Zimmerman */ 1126197ba5f4SPaul Zimmerman extern void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val); 1127197ba5f4SPaul Zimmerman #define DWC2_PHY_ULPI_INTERNAL_VBUS 0 1128197ba5f4SPaul Zimmerman #define DWC2_PHY_ULPI_EXTERNAL_VBUS 1 1129197ba5f4SPaul Zimmerman 1130197ba5f4SPaul Zimmerman /* 1131197ba5f4SPaul Zimmerman * Specifies whether to use the I2Cinterface for full speed PHY. This 1132197ba5f4SPaul Zimmerman * parameter is only applicable if PHY_TYPE is FS. 1133197ba5f4SPaul Zimmerman * 0 - No (default) 1134197ba5f4SPaul Zimmerman * 1 - Yes 1135197ba5f4SPaul Zimmerman */ 1136197ba5f4SPaul Zimmerman extern void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val); 1137197ba5f4SPaul Zimmerman 1138197ba5f4SPaul Zimmerman extern void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val); 1139197ba5f4SPaul Zimmerman 1140197ba5f4SPaul Zimmerman extern void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val); 1141197ba5f4SPaul Zimmerman 1142197ba5f4SPaul Zimmerman /* 1143197ba5f4SPaul Zimmerman * Specifies whether dedicated transmit FIFOs are 1144197ba5f4SPaul Zimmerman * enabled for non periodic IN endpoints in device mode 1145197ba5f4SPaul Zimmerman * 0 - No 1146197ba5f4SPaul Zimmerman * 1 - Yes 1147197ba5f4SPaul Zimmerman */ 1148197ba5f4SPaul Zimmerman extern void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, 1149197ba5f4SPaul Zimmerman int val); 1150197ba5f4SPaul Zimmerman 1151197ba5f4SPaul Zimmerman extern void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val); 1152197ba5f4SPaul Zimmerman 1153197ba5f4SPaul Zimmerman extern void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val); 1154197ba5f4SPaul Zimmerman 1155197ba5f4SPaul Zimmerman extern void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val); 1156197ba5f4SPaul Zimmerman 1157ecb176c6SMian Yousaf Kaukab extern void dwc2_set_parameters(struct dwc2_hsotg *hsotg, 1158ecb176c6SMian Yousaf Kaukab const struct dwc2_core_params *params); 1159ecb176c6SMian Yousaf Kaukab 1160ecb176c6SMian Yousaf Kaukab extern void dwc2_set_all_params(struct dwc2_core_params *params, int value); 1161ecb176c6SMian Yousaf Kaukab 1162ecb176c6SMian Yousaf Kaukab extern int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); 1163ecb176c6SMian Yousaf Kaukab 116409a75e85SMarek Szyprowski extern int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg); 116509a75e85SMarek Szyprowski extern int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg); 1166ecb176c6SMian Yousaf Kaukab 1167197ba5f4SPaul Zimmerman /* 11686bea9620SJohn Youn * The following functions check the controller's OTG operation mode 11696bea9620SJohn Youn * capability (GHWCFG2.OTG_MODE). 11706bea9620SJohn Youn * 11716bea9620SJohn Youn * These functions can be used before the internal hsotg->hw_params 11726bea9620SJohn Youn * are read in and cached so they always read directly from the 11736bea9620SJohn Youn * GHWCFG2 register. 11746bea9620SJohn Youn */ 11756bea9620SJohn Youn unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg); 11766bea9620SJohn Youn bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg); 11776bea9620SJohn Youn bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg); 11786bea9620SJohn Youn bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg); 11796bea9620SJohn Youn 11806bea9620SJohn Youn /* 11811696d5abSJohn Youn * Returns the mode of operation, host or device 11821696d5abSJohn Youn */ 11831696d5abSJohn Youn static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) 11841696d5abSJohn Youn { 11851696d5abSJohn Youn return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0; 11861696d5abSJohn Youn } 11871696d5abSJohn Youn static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) 11881696d5abSJohn Youn { 11891696d5abSJohn Youn return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0; 11901696d5abSJohn Youn } 11911696d5abSJohn Youn 11921696d5abSJohn Youn /* 1193197ba5f4SPaul Zimmerman * Dump core registers and SPRAM 1194197ba5f4SPaul Zimmerman */ 1195197ba5f4SPaul Zimmerman extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 1196197ba5f4SPaul Zimmerman extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 1197197ba5f4SPaul Zimmerman extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 1198197ba5f4SPaul Zimmerman 1199197ba5f4SPaul Zimmerman /* 1200197ba5f4SPaul Zimmerman * Return OTG version - either 1.3 or 2.0 1201197ba5f4SPaul Zimmerman */ 1202197ba5f4SPaul Zimmerman extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg); 1203197ba5f4SPaul Zimmerman 1204117777b2SDinh Nguyen /* Gadget defines */ 1205117777b2SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 12061f91b4ccSFelipe Balbi extern int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg); 12071f91b4ccSFelipe Balbi extern int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2); 12081f91b4ccSFelipe Balbi extern int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2); 1209117777b2SDinh Nguyen extern int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq); 12101f91b4ccSFelipe Balbi extern void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1211643cc4deSGregory Herrero bool reset); 12121f91b4ccSFelipe Balbi extern void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg); 12131f91b4ccSFelipe Balbi extern void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2); 12141f91b4ccSFelipe Balbi extern int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode); 1215f81f46e1SGregory Herrero #define dwc2_is_device_connected(hsotg) (hsotg->connected) 1216117777b2SDinh Nguyen #else 12171f91b4ccSFelipe Balbi static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2) 1218117777b2SDinh Nguyen { return 0; } 12191f91b4ccSFelipe Balbi static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2) 1220117777b2SDinh Nguyen { return 0; } 12211f91b4ccSFelipe Balbi static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2) 1222117777b2SDinh Nguyen { return 0; } 1223117777b2SDinh Nguyen static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) 1224117777b2SDinh Nguyen { return 0; } 12251f91b4ccSFelipe Balbi static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1226643cc4deSGregory Herrero bool reset) {} 12271f91b4ccSFelipe Balbi static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} 12281f91b4ccSFelipe Balbi static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} 12291f91b4ccSFelipe Balbi static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, 1230f91eea44SMian Yousaf Kaukab int testmode) 1231f91eea44SMian Yousaf Kaukab { return 0; } 1232f81f46e1SGregory Herrero #define dwc2_is_device_connected(hsotg) (0) 1233117777b2SDinh Nguyen #endif 1234117777b2SDinh Nguyen 1235117777b2SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1236117777b2SDinh Nguyen extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 12376a659531SDouglas Anderson extern void dwc2_hcd_connect(struct dwc2_hsotg *hsotg); 12386a659531SDouglas Anderson extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force); 1239117777b2SDinh Nguyen extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 1240117777b2SDinh Nguyen #else 1241117777b2SDinh Nguyen static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1242117777b2SDinh Nguyen { return 0; } 12436a659531SDouglas Anderson static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {} 12446a659531SDouglas Anderson static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {} 1245117777b2SDinh Nguyen static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} 1246117777b2SDinh Nguyen static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} 1247ecb176c6SMian Yousaf Kaukab static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) 1248117777b2SDinh Nguyen { return 0; } 1249117777b2SDinh Nguyen #endif 1250117777b2SDinh Nguyen 1251197ba5f4SPaul Zimmerman #endif /* __DWC2_CORE_H__ */ 1252