1197ba5f4SPaul Zimmerman /* 2197ba5f4SPaul Zimmerman * core.h - DesignWare HS OTG Controller common declarations 3197ba5f4SPaul Zimmerman * 4197ba5f4SPaul Zimmerman * Copyright (C) 2004-2013 Synopsys, Inc. 5197ba5f4SPaul Zimmerman * 6197ba5f4SPaul Zimmerman * Redistribution and use in source and binary forms, with or without 7197ba5f4SPaul Zimmerman * modification, are permitted provided that the following conditions 8197ba5f4SPaul Zimmerman * are met: 9197ba5f4SPaul Zimmerman * 1. Redistributions of source code must retain the above copyright 10197ba5f4SPaul Zimmerman * notice, this list of conditions, and the following disclaimer, 11197ba5f4SPaul Zimmerman * without modification. 12197ba5f4SPaul Zimmerman * 2. Redistributions in binary form must reproduce the above copyright 13197ba5f4SPaul Zimmerman * notice, this list of conditions and the following disclaimer in the 14197ba5f4SPaul Zimmerman * documentation and/or other materials provided with the distribution. 15197ba5f4SPaul Zimmerman * 3. The names of the above-listed copyright holders may not be used 16197ba5f4SPaul Zimmerman * to endorse or promote products derived from this software without 17197ba5f4SPaul Zimmerman * specific prior written permission. 18197ba5f4SPaul Zimmerman * 19197ba5f4SPaul Zimmerman * ALTERNATIVELY, this software may be distributed under the terms of the 20197ba5f4SPaul Zimmerman * GNU General Public License ("GPL") as published by the Free Software 21197ba5f4SPaul Zimmerman * Foundation; either version 2 of the License, or (at your option) any 22197ba5f4SPaul Zimmerman * later version. 23197ba5f4SPaul Zimmerman * 24197ba5f4SPaul Zimmerman * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25197ba5f4SPaul Zimmerman * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26197ba5f4SPaul Zimmerman * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27197ba5f4SPaul Zimmerman * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28197ba5f4SPaul Zimmerman * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29197ba5f4SPaul Zimmerman * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30197ba5f4SPaul Zimmerman * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31197ba5f4SPaul Zimmerman * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32197ba5f4SPaul Zimmerman * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33197ba5f4SPaul Zimmerman * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34197ba5f4SPaul Zimmerman * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35197ba5f4SPaul Zimmerman */ 36197ba5f4SPaul Zimmerman 37197ba5f4SPaul Zimmerman #ifndef __DWC2_CORE_H__ 38197ba5f4SPaul Zimmerman #define __DWC2_CORE_H__ 39197ba5f4SPaul Zimmerman 40f7c0b143SDinh Nguyen #include <linux/phy/phy.h> 41f7c0b143SDinh Nguyen #include <linux/regulator/consumer.h> 42f7c0b143SDinh Nguyen #include <linux/usb/gadget.h> 43f7c0b143SDinh Nguyen #include <linux/usb/otg.h> 44197ba5f4SPaul Zimmerman #include <linux/usb/phy.h> 45197ba5f4SPaul Zimmerman #include "hw.h" 46197ba5f4SPaul Zimmerman 4774fc4a75SDouglas Anderson /* 4874fc4a75SDouglas Anderson * Suggested defines for tracers: 4974fc4a75SDouglas Anderson * - no_printk: Disable tracing 5074fc4a75SDouglas Anderson * - pr_info: Print this info to the console 5174fc4a75SDouglas Anderson * - trace_printk: Print this info to trace buffer (good for verbose logging) 5274fc4a75SDouglas Anderson */ 5374fc4a75SDouglas Anderson 5474fc4a75SDouglas Anderson #define DWC2_TRACE_SCHEDULER no_printk 5574fc4a75SDouglas Anderson #define DWC2_TRACE_SCHEDULER_VB no_printk 5674fc4a75SDouglas Anderson 5774fc4a75SDouglas Anderson /* Detailed scheduler tracing, but won't overwhelm console */ 5874fc4a75SDouglas Anderson #define dwc2_sch_dbg(hsotg, fmt, ...) \ 5974fc4a75SDouglas Anderson DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \ 6074fc4a75SDouglas Anderson dev_name(hsotg->dev), ##__VA_ARGS__) 6174fc4a75SDouglas Anderson 6274fc4a75SDouglas Anderson /* Verbose scheduler tracing */ 6374fc4a75SDouglas Anderson #define dwc2_sch_vdbg(hsotg, fmt, ...) \ 6474fc4a75SDouglas Anderson DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \ 6574fc4a75SDouglas Anderson dev_name(hsotg->dev), ##__VA_ARGS__) 6674fc4a75SDouglas Anderson 6723e34392SArnd Bergmann #ifdef CONFIG_MIPS 6823e34392SArnd Bergmann /* 6923e34392SArnd Bergmann * There are some MIPS machines that can run in either big-endian 7023e34392SArnd Bergmann * or little-endian mode and that use the dwc2 register without 7123e34392SArnd Bergmann * a byteswap in both ways. 7223e34392SArnd Bergmann * Unlike other architectures, MIPS apparently does not require a 7323e34392SArnd Bergmann * barrier before the __raw_writel() to synchronize with DMA but does 7423e34392SArnd Bergmann * require the barrier after the __raw_writel() to serialize a set of 7523e34392SArnd Bergmann * writes. This set of operations was added specifically for MIPS and 7623e34392SArnd Bergmann * should only be used there. 7723e34392SArnd Bergmann */ 7895c8bc36SAntti Seppälä static inline u32 dwc2_readl(const void __iomem *addr) 79197ba5f4SPaul Zimmerman { 8095c8bc36SAntti Seppälä u32 value = __raw_readl(addr); 8195c8bc36SAntti Seppälä 8295c8bc36SAntti Seppälä /* In order to preserve endianness __raw_* operation is used. Therefore 8395c8bc36SAntti Seppälä * a barrier is needed to ensure IO access is not re-ordered across 8495c8bc36SAntti Seppälä * reads or writes 8595c8bc36SAntti Seppälä */ 8695c8bc36SAntti Seppälä mb(); 8795c8bc36SAntti Seppälä return value; 88197ba5f4SPaul Zimmerman } 89197ba5f4SPaul Zimmerman 9095c8bc36SAntti Seppälä static inline void dwc2_writel(u32 value, void __iomem *addr) 9195c8bc36SAntti Seppälä { 9295c8bc36SAntti Seppälä __raw_writel(value, addr); 9395c8bc36SAntti Seppälä 9495c8bc36SAntti Seppälä /* 9595c8bc36SAntti Seppälä * In order to preserve endianness __raw_* operation is used. Therefore 9695c8bc36SAntti Seppälä * a barrier is needed to ensure IO access is not re-ordered across 9795c8bc36SAntti Seppälä * reads or writes 9895c8bc36SAntti Seppälä */ 9995c8bc36SAntti Seppälä mb(); 10095c8bc36SAntti Seppälä #ifdef DWC2_LOG_WRITES 10195c8bc36SAntti Seppälä pr_info("INFO:: wrote %08x to %p\n", value, addr); 102197ba5f4SPaul Zimmerman #endif 10395c8bc36SAntti Seppälä } 10423e34392SArnd Bergmann #else 10523e34392SArnd Bergmann /* Normal architectures just use readl/write */ 10623e34392SArnd Bergmann static inline u32 dwc2_readl(const void __iomem *addr) 10723e34392SArnd Bergmann { 10823e34392SArnd Bergmann return readl(addr); 10923e34392SArnd Bergmann } 11023e34392SArnd Bergmann 11123e34392SArnd Bergmann static inline void dwc2_writel(u32 value, void __iomem *addr) 11223e34392SArnd Bergmann { 11323e34392SArnd Bergmann writel(value, addr); 11423e34392SArnd Bergmann 11523e34392SArnd Bergmann #ifdef DWC2_LOG_WRITES 11623e34392SArnd Bergmann pr_info("info:: wrote %08x to %p\n", value, addr); 11723e34392SArnd Bergmann #endif 11823e34392SArnd Bergmann } 11923e34392SArnd Bergmann #endif 120197ba5f4SPaul Zimmerman 121197ba5f4SPaul Zimmerman /* Maximum number of Endpoints/HostChannels */ 122197ba5f4SPaul Zimmerman #define MAX_EPS_CHANNELS 16 123197ba5f4SPaul Zimmerman 1241f91b4ccSFelipe Balbi /* dwc2-hsotg declarations */ 1251f91b4ccSFelipe Balbi static const char * const dwc2_hsotg_supply_names[] = { 126f7c0b143SDinh Nguyen "vusb_d", /* digital USB supply, 1.2V */ 127f7c0b143SDinh Nguyen "vusb_a", /* analog USB supply, 1.1V */ 128f7c0b143SDinh Nguyen }; 129f7c0b143SDinh Nguyen 130b98866c2SJohn Youn #define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names) 131b98866c2SJohn Youn 132f7c0b143SDinh Nguyen /* 133f7c0b143SDinh Nguyen * EP0_MPS_LIMIT 134f7c0b143SDinh Nguyen * 135f7c0b143SDinh Nguyen * Unfortunately there seems to be a limit of the amount of data that can 136f7c0b143SDinh Nguyen * be transferred by IN transactions on EP0. This is either 127 bytes or 3 137f7c0b143SDinh Nguyen * packets (which practically means 1 packet and 63 bytes of data) when the 138f7c0b143SDinh Nguyen * MPS is set to 64. 139f7c0b143SDinh Nguyen * 140f7c0b143SDinh Nguyen * This means if we are wanting to move >127 bytes of data, we need to 141f7c0b143SDinh Nguyen * split the transactions up, but just doing one packet at a time does 142f7c0b143SDinh Nguyen * not work (this may be an implicit DATA0 PID on first packet of the 143f7c0b143SDinh Nguyen * transaction) and doing 2 packets is outside the controller's limits. 144f7c0b143SDinh Nguyen * 145f7c0b143SDinh Nguyen * If we try to lower the MPS size for EP0, then no transfers work properly 146f7c0b143SDinh Nguyen * for EP0, and the system will fail basic enumeration. As no cause for this 147f7c0b143SDinh Nguyen * has currently been found, we cannot support any large IN transfers for 148f7c0b143SDinh Nguyen * EP0. 149f7c0b143SDinh Nguyen */ 150f7c0b143SDinh Nguyen #define EP0_MPS_LIMIT 64 151f7c0b143SDinh Nguyen 152941fcce4SDinh Nguyen struct dwc2_hsotg; 1531f91b4ccSFelipe Balbi struct dwc2_hsotg_req; 154f7c0b143SDinh Nguyen 155f7c0b143SDinh Nguyen /** 1561f91b4ccSFelipe Balbi * struct dwc2_hsotg_ep - driver endpoint definition. 157f7c0b143SDinh Nguyen * @ep: The gadget layer representation of the endpoint. 158f7c0b143SDinh Nguyen * @name: The driver generated name for the endpoint. 159f7c0b143SDinh Nguyen * @queue: Queue of requests for this endpoint. 160f7c0b143SDinh Nguyen * @parent: Reference back to the parent device structure. 161f7c0b143SDinh Nguyen * @req: The current request that the endpoint is processing. This is 162f7c0b143SDinh Nguyen * used to indicate an request has been loaded onto the endpoint 163f7c0b143SDinh Nguyen * and has yet to be completed (maybe due to data move, or simply 164f7c0b143SDinh Nguyen * awaiting an ack from the core all the data has been completed). 165f7c0b143SDinh Nguyen * @debugfs: File entry for debugfs file for this endpoint. 166f7c0b143SDinh Nguyen * @lock: State lock to protect contents of endpoint. 167f7c0b143SDinh Nguyen * @dir_in: Set to true if this endpoint is of the IN direction, which 168f7c0b143SDinh Nguyen * means that it is sending data to the Host. 169f7c0b143SDinh Nguyen * @index: The index for the endpoint registers. 170f7c0b143SDinh Nguyen * @mc: Multi Count - number of transactions per microframe 171142bd33fSVardan Mikayelyan * @interval - Interval for periodic endpoints, in frames or microframes. 172f7c0b143SDinh Nguyen * @name: The name array passed to the USB core. 173f7c0b143SDinh Nguyen * @halted: Set if the endpoint has been halted. 174f7c0b143SDinh Nguyen * @periodic: Set if this is a periodic ep, such as Interrupt 175f7c0b143SDinh Nguyen * @isochronous: Set if this is a isochronous ep 1768a20fa45SMian Yousaf Kaukab * @send_zlp: Set if we need to send a zero-length packet. 1775f54c54bSVahram Aharonyan * @desc_list_dma: The DMA address of descriptor chain currently in use. 1785f54c54bSVahram Aharonyan * @desc_list: Pointer to descriptor DMA chain head currently in use. 1795f54c54bSVahram Aharonyan * @desc_count: Count of entries within the DMA descriptor chain of EP. 180ab7d2192SVahram Aharonyan * @isoc_chain_num: Number of ISOC chain currently in use - either 0 or 1. 181ab7d2192SVahram Aharonyan * @next_desc: index of next free descriptor in the ISOC chain under SW control. 182f7c0b143SDinh Nguyen * @total_data: The total number of data bytes done. 183f7c0b143SDinh Nguyen * @fifo_size: The size of the FIFO (for periodic IN endpoints) 184f7c0b143SDinh Nguyen * @fifo_load: The amount of data loaded into the FIFO (periodic IN) 185f7c0b143SDinh Nguyen * @last_load: The offset of data for the last start of request. 186f7c0b143SDinh Nguyen * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN 18792d1635dSVardan Mikayelyan * @target_frame: Targeted frame num to setup next ISOC transfer 18892d1635dSVardan Mikayelyan * @frame_overrun: Indicates SOF number overrun in DSTS 189f7c0b143SDinh Nguyen * 190f7c0b143SDinh Nguyen * This is the driver's state for each registered enpoint, allowing it 191f7c0b143SDinh Nguyen * to keep track of transactions that need doing. Each endpoint has a 192f7c0b143SDinh Nguyen * lock to protect the state, to try and avoid using an overall lock 193f7c0b143SDinh Nguyen * for the host controller as much as possible. 194f7c0b143SDinh Nguyen * 195f7c0b143SDinh Nguyen * For periodic IN endpoints, we have fifo_size and fifo_load to try 196f7c0b143SDinh Nguyen * and keep track of the amount of data in the periodic FIFO for each 197f7c0b143SDinh Nguyen * of these as we don't have a status register that tells us how much 198f7c0b143SDinh Nguyen * is in each of them. (note, this may actually be useless information 199f7c0b143SDinh Nguyen * as in shared-fifo mode periodic in acts like a single-frame packet 200f7c0b143SDinh Nguyen * buffer than a fifo) 201f7c0b143SDinh Nguyen */ 2021f91b4ccSFelipe Balbi struct dwc2_hsotg_ep { 203f7c0b143SDinh Nguyen struct usb_ep ep; 204f7c0b143SDinh Nguyen struct list_head queue; 205941fcce4SDinh Nguyen struct dwc2_hsotg *parent; 2061f91b4ccSFelipe Balbi struct dwc2_hsotg_req *req; 207f7c0b143SDinh Nguyen struct dentry *debugfs; 208f7c0b143SDinh Nguyen 209f7c0b143SDinh Nguyen unsigned long total_data; 210f7c0b143SDinh Nguyen unsigned int size_loaded; 211f7c0b143SDinh Nguyen unsigned int last_load; 212f7c0b143SDinh Nguyen unsigned int fifo_load; 213f7c0b143SDinh Nguyen unsigned short fifo_size; 214b203d0a2SRobert Baldyga unsigned short fifo_index; 215f7c0b143SDinh Nguyen 216f7c0b143SDinh Nguyen unsigned char dir_in; 217f7c0b143SDinh Nguyen unsigned char index; 218f7c0b143SDinh Nguyen unsigned char mc; 219f7c0b143SDinh Nguyen unsigned char interval; 220f7c0b143SDinh Nguyen 221f7c0b143SDinh Nguyen unsigned int halted:1; 222f7c0b143SDinh Nguyen unsigned int periodic:1; 223f7c0b143SDinh Nguyen unsigned int isochronous:1; 2248a20fa45SMian Yousaf Kaukab unsigned int send_zlp:1; 22592d1635dSVardan Mikayelyan unsigned int target_frame; 22692d1635dSVardan Mikayelyan #define TARGET_FRAME_INITIAL 0xFFFFFFFF 22792d1635dSVardan Mikayelyan bool frame_overrun; 228f7c0b143SDinh Nguyen 2295f54c54bSVahram Aharonyan dma_addr_t desc_list_dma; 2305f54c54bSVahram Aharonyan struct dwc2_dma_desc *desc_list; 2315f54c54bSVahram Aharonyan u8 desc_count; 2325f54c54bSVahram Aharonyan 233ab7d2192SVahram Aharonyan unsigned char isoc_chain_num; 234ab7d2192SVahram Aharonyan unsigned int next_desc; 235ab7d2192SVahram Aharonyan 236f7c0b143SDinh Nguyen char name[10]; 237f7c0b143SDinh Nguyen }; 238f7c0b143SDinh Nguyen 239f7c0b143SDinh Nguyen /** 2401f91b4ccSFelipe Balbi * struct dwc2_hsotg_req - data transfer request 241f7c0b143SDinh Nguyen * @req: The USB gadget request 242f7c0b143SDinh Nguyen * @queue: The list of requests for the endpoint this is queued for. 2437d24c1b5SMian Yousaf Kaukab * @saved_req_buf: variable to save req.buf when bounce buffers are used. 244f7c0b143SDinh Nguyen */ 2451f91b4ccSFelipe Balbi struct dwc2_hsotg_req { 246f7c0b143SDinh Nguyen struct usb_request req; 247f7c0b143SDinh Nguyen struct list_head queue; 2487d24c1b5SMian Yousaf Kaukab void *saved_req_buf; 249f7c0b143SDinh Nguyen }; 250f7c0b143SDinh Nguyen 251b98866c2SJohn Youn #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 252b98866c2SJohn Youn IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 253f7c0b143SDinh Nguyen #define call_gadget(_hs, _entry) \ 254f7c0b143SDinh Nguyen do { \ 255f7c0b143SDinh Nguyen if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ 256f7c0b143SDinh Nguyen (_hs)->driver && (_hs)->driver->_entry) { \ 257f7c0b143SDinh Nguyen spin_unlock(&_hs->lock); \ 258f7c0b143SDinh Nguyen (_hs)->driver->_entry(&(_hs)->gadget); \ 259f7c0b143SDinh Nguyen spin_lock(&_hs->lock); \ 260f7c0b143SDinh Nguyen } \ 261f7c0b143SDinh Nguyen } while (0) 262941fcce4SDinh Nguyen #else 263941fcce4SDinh Nguyen #define call_gadget(_hs, _entry) do {} while (0) 264941fcce4SDinh Nguyen #endif 265f7c0b143SDinh Nguyen 266197ba5f4SPaul Zimmerman struct dwc2_hsotg; 267197ba5f4SPaul Zimmerman struct dwc2_host_chan; 268197ba5f4SPaul Zimmerman 269197ba5f4SPaul Zimmerman /* Device States */ 270197ba5f4SPaul Zimmerman enum dwc2_lx_state { 271197ba5f4SPaul Zimmerman DWC2_L0, /* On state */ 272197ba5f4SPaul Zimmerman DWC2_L1, /* LPM sleep state */ 273197ba5f4SPaul Zimmerman DWC2_L2, /* USB suspend state */ 274197ba5f4SPaul Zimmerman DWC2_L3, /* Off state */ 275197ba5f4SPaul Zimmerman }; 276197ba5f4SPaul Zimmerman 2773fa95385SJohn Youn /* 2783fa95385SJohn Youn * Gadget periodic tx fifo sizes as used by legacy driver 2793fa95385SJohn Youn * EP0 is not included 2803fa95385SJohn Youn */ 2813fa95385SJohn Youn #define DWC2_G_P_LEGACY_TX_FIFO_SIZE {256, 256, 256, 256, 768, 768, 768, \ 2823fa95385SJohn Youn 768, 0, 0, 0, 0, 0, 0, 0} 2833fa95385SJohn Youn 284fe0b94abSMian Yousaf Kaukab /* Gadget ep0 states */ 285fe0b94abSMian Yousaf Kaukab enum dwc2_ep0_state { 286fe0b94abSMian Yousaf Kaukab DWC2_EP0_SETUP, 287fe0b94abSMian Yousaf Kaukab DWC2_EP0_DATA_IN, 288fe0b94abSMian Yousaf Kaukab DWC2_EP0_DATA_OUT, 289fe0b94abSMian Yousaf Kaukab DWC2_EP0_STATUS_IN, 290fe0b94abSMian Yousaf Kaukab DWC2_EP0_STATUS_OUT, 291fe0b94abSMian Yousaf Kaukab }; 292fe0b94abSMian Yousaf Kaukab 293197ba5f4SPaul Zimmerman /** 294197ba5f4SPaul Zimmerman * struct dwc2_core_params - Parameters for configuring the core 295197ba5f4SPaul Zimmerman * 296197ba5f4SPaul Zimmerman * @otg_cap: Specifies the OTG capabilities. 297197ba5f4SPaul Zimmerman * 0 - HNP and SRP capable 298197ba5f4SPaul Zimmerman * 1 - SRP Only capable 299197ba5f4SPaul Zimmerman * 2 - No HNP/SRP capable (always available) 300197ba5f4SPaul Zimmerman * Defaults to best available option (0, 1, then 2) 301e7839f99SJohn Youn * @host_dma: Specifies whether to use slave or DMA mode for accessing 302197ba5f4SPaul Zimmerman * the data FIFOs. The driver will automatically detect the 303197ba5f4SPaul Zimmerman * value for this parameter if none is specified. 304197ba5f4SPaul Zimmerman * 0 - Slave (always available) 305197ba5f4SPaul Zimmerman * 1 - DMA (default, if available) 306197ba5f4SPaul Zimmerman * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 307197ba5f4SPaul Zimmerman * address DMA mode or descriptor DMA mode for accessing 308197ba5f4SPaul Zimmerman * the data FIFOs. The driver will automatically detect the 309197ba5f4SPaul Zimmerman * value for this if none is specified. 310197ba5f4SPaul Zimmerman * 0 - Address DMA 311197ba5f4SPaul Zimmerman * 1 - Descriptor DMA (default, if available) 312fbb9e22bSMian Yousaf Kaukab * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use 313fbb9e22bSMian Yousaf Kaukab * address DMA mode or descriptor DMA mode for accessing 314fbb9e22bSMian Yousaf Kaukab * the data FIFOs in Full Speed mode only. The driver 315fbb9e22bSMian Yousaf Kaukab * will automatically detect the value for this if none is 316fbb9e22bSMian Yousaf Kaukab * specified. 317fbb9e22bSMian Yousaf Kaukab * 0 - Address DMA 318fbb9e22bSMian Yousaf Kaukab * 1 - Descriptor DMA in FS (default, if available) 319197ba5f4SPaul Zimmerman * @speed: Specifies the maximum speed of operation in host and 320197ba5f4SPaul Zimmerman * device mode. The actual speed depends on the speed of 321197ba5f4SPaul Zimmerman * the attached device and the value of phy_type. 322197ba5f4SPaul Zimmerman * 0 - High Speed 323197ba5f4SPaul Zimmerman * (default when phy_type is UTMI+ or ULPI) 324197ba5f4SPaul Zimmerman * 1 - Full Speed 325197ba5f4SPaul Zimmerman * (default when phy_type is Full Speed) 326197ba5f4SPaul Zimmerman * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 327197ba5f4SPaul Zimmerman * 1 - Allow dynamic FIFO sizing (default, if available) 328197ba5f4SPaul Zimmerman * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 329c1d286cfSJohn Youn * are enabled for non-periodic IN endpoints in device 330c1d286cfSJohn Youn * mode. 331197ba5f4SPaul Zimmerman * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 332197ba5f4SPaul Zimmerman * dynamic FIFO sizing is enabled 333197ba5f4SPaul Zimmerman * 16 to 32768 334197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 335197ba5f4SPaul Zimmerman * the default. 336197ba5f4SPaul Zimmerman * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 337197ba5f4SPaul Zimmerman * in host mode when dynamic FIFO sizing is enabled 338197ba5f4SPaul Zimmerman * 16 to 32768 339197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 340197ba5f4SPaul Zimmerman * the default. 341197ba5f4SPaul Zimmerman * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 342197ba5f4SPaul Zimmerman * host mode when dynamic FIFO sizing is enabled 343197ba5f4SPaul Zimmerman * 16 to 32768 344197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 345197ba5f4SPaul Zimmerman * the default. 346197ba5f4SPaul Zimmerman * @max_transfer_size: The maximum transfer size supported, in bytes 347197ba5f4SPaul Zimmerman * 2047 to 65,535 348197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 349197ba5f4SPaul Zimmerman * the default. 350197ba5f4SPaul Zimmerman * @max_packet_count: The maximum number of packets in a transfer 351197ba5f4SPaul Zimmerman * 15 to 511 352197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 353197ba5f4SPaul Zimmerman * the default. 354197ba5f4SPaul Zimmerman * @host_channels: The number of host channel registers to use 355197ba5f4SPaul Zimmerman * 1 to 16 356197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 357197ba5f4SPaul Zimmerman * the default. 358197ba5f4SPaul Zimmerman * @phy_type: Specifies the type of PHY interface to use. By default, 359197ba5f4SPaul Zimmerman * the driver will automatically detect the phy_type. 360197ba5f4SPaul Zimmerman * 0 - Full Speed Phy 361197ba5f4SPaul Zimmerman * 1 - UTMI+ Phy 362197ba5f4SPaul Zimmerman * 2 - ULPI Phy 363197ba5f4SPaul Zimmerman * Defaults to best available option (2, 1, then 0) 364197ba5f4SPaul Zimmerman * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 365197ba5f4SPaul Zimmerman * is applicable for a phy_type of UTMI+ or ULPI. (For a 366197ba5f4SPaul Zimmerman * ULPI phy_type, this parameter indicates the data width 367197ba5f4SPaul Zimmerman * between the MAC and the ULPI Wrapper.) Also, this 368197ba5f4SPaul Zimmerman * parameter is applicable only if the OTG_HSPHY_WIDTH cC 369197ba5f4SPaul Zimmerman * parameter was set to "8 and 16 bits", meaning that the 370197ba5f4SPaul Zimmerman * core has been configured to work at either data path 371197ba5f4SPaul Zimmerman * width. 372197ba5f4SPaul Zimmerman * 8 or 16 (default 16 if available) 373197ba5f4SPaul Zimmerman * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 374197ba5f4SPaul Zimmerman * data rate. This parameter is only applicable if phy_type 375197ba5f4SPaul Zimmerman * is ULPI. 376197ba5f4SPaul Zimmerman * 0 - single data rate ULPI interface with 8 bit wide 377197ba5f4SPaul Zimmerman * data bus (default) 378197ba5f4SPaul Zimmerman * 1 - double data rate ULPI interface with 4 bit wide 379197ba5f4SPaul Zimmerman * data bus 380197ba5f4SPaul Zimmerman * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 381197ba5f4SPaul Zimmerman * external supply to drive the VBus 382197ba5f4SPaul Zimmerman * 0 - Internal supply (default) 383197ba5f4SPaul Zimmerman * 1 - External supply 384197ba5f4SPaul Zimmerman * @i2c_enable: Specifies whether to use the I2Cinterface for a full 385197ba5f4SPaul Zimmerman * speed PHY. This parameter is only applicable if phy_type 386197ba5f4SPaul Zimmerman * is FS. 387197ba5f4SPaul Zimmerman * 0 - No (default) 388197ba5f4SPaul Zimmerman * 1 - Yes 389197ba5f4SPaul Zimmerman * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 390197ba5f4SPaul Zimmerman * 0 - No (default) 391197ba5f4SPaul Zimmerman * 1 - Yes 392197ba5f4SPaul Zimmerman * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 393197ba5f4SPaul Zimmerman * when attached to a Full Speed or Low Speed device in 394197ba5f4SPaul Zimmerman * host mode. 395197ba5f4SPaul Zimmerman * 0 - Don't support low power mode (default) 396197ba5f4SPaul Zimmerman * 1 - Support low power mode 397197ba5f4SPaul Zimmerman * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 398197ba5f4SPaul Zimmerman * when connected to a Low Speed device in host 399197ba5f4SPaul Zimmerman * mode. This parameter is applicable only if 400197ba5f4SPaul Zimmerman * host_support_fs_ls_low_power is enabled. 401197ba5f4SPaul Zimmerman * 0 - 48 MHz 402197ba5f4SPaul Zimmerman * (default when phy_type is UTMI+ or ULPI) 403197ba5f4SPaul Zimmerman * 1 - 6 MHz 404197ba5f4SPaul Zimmerman * (default when phy_type is Full Speed) 405197ba5f4SPaul Zimmerman * @ts_dline: Enable Term Select Dline pulsing 406197ba5f4SPaul Zimmerman * 0 - No (default) 407197ba5f4SPaul Zimmerman * 1 - Yes 408197ba5f4SPaul Zimmerman * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 409197ba5f4SPaul Zimmerman * 0 - No (default for core < 2.92a) 410197ba5f4SPaul Zimmerman * 1 - Yes (default for core >= 2.92a) 411197ba5f4SPaul Zimmerman * @ahbcfg: This field allows the default value of the GAHBCFG 412197ba5f4SPaul Zimmerman * register to be overridden 413197ba5f4SPaul Zimmerman * -1 - GAHBCFG value will be set to 0x06 414197ba5f4SPaul Zimmerman * (INCR4, default) 415197ba5f4SPaul Zimmerman * all others - GAHBCFG value will be overridden with 416197ba5f4SPaul Zimmerman * this value 417197ba5f4SPaul Zimmerman * Not all bits can be controlled like this, the 418197ba5f4SPaul Zimmerman * bits defined by GAHBCFG_CTRL_MASK are controlled 419197ba5f4SPaul Zimmerman * by the driver and are ignored in this 420197ba5f4SPaul Zimmerman * configuration value. 421197ba5f4SPaul Zimmerman * @uframe_sched: True to enable the microframe scheduler 422a6d249d8SGregory Herrero * @external_id_pin_ctl: Specifies whether ID pin is handled externally. 423a6d249d8SGregory Herrero * Disable CONIDSTSCHNG controller interrupt in such 424a6d249d8SGregory Herrero * case. 425a6d249d8SGregory Herrero * 0 - No (default) 426a6d249d8SGregory Herrero * 1 - Yes 427285046aaSGregory Herrero * @hibernation: Specifies whether the controller support hibernation. 428285046aaSGregory Herrero * If hibernation is enabled, the controller will enter 429285046aaSGregory Herrero * hibernation in both peripheral and host mode when 430285046aaSGregory Herrero * needed. 431285046aaSGregory Herrero * 0 - No (default) 432285046aaSGregory Herrero * 1 - Yes 4339962b62fSJohn Youn * @g_dma: Enables gadget dma usage (default: autodetect). 434dec4b556SVahram Aharonyan * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect). 43505ee799fSJohn Youn * @g_rx_fifo_size: The periodic rx fifo size for the device, in 43605ee799fSJohn Youn * DWORDS from 16-32768 (default: 2048 if 43705ee799fSJohn Youn * possible, otherwise autodetect). 43805ee799fSJohn Youn * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in 43905ee799fSJohn Youn * DWORDS from 16-32768 (default: 1024 if 44005ee799fSJohn Youn * possible, otherwise autodetect). 44105ee799fSJohn Youn * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo 44205ee799fSJohn Youn * mode. Each value corresponds to one EP 44305ee799fSJohn Youn * starting from EP1 (max 15 values). Sizes are 44405ee799fSJohn Youn * in DWORDS with possible values from from 44505ee799fSJohn Youn * 16-32768 (default: 256, 256, 256, 256, 768, 44605ee799fSJohn Youn * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0). 447197ba5f4SPaul Zimmerman * 448197ba5f4SPaul Zimmerman * The following parameters may be specified when starting the module. These 449197ba5f4SPaul Zimmerman * parameters define how the DWC_otg controller should be configured. A 450197ba5f4SPaul Zimmerman * value of -1 (or any other out of range value) for any parameter means 451197ba5f4SPaul Zimmerman * to read the value from hardware (if possible) or use the builtin 452197ba5f4SPaul Zimmerman * default described above. 453197ba5f4SPaul Zimmerman */ 454197ba5f4SPaul Zimmerman struct dwc2_core_params { 455d21bcc3fSJohn Youn u8 otg_cap; 456c1d286cfSJohn Youn #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 457c1d286cfSJohn Youn #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 458c1d286cfSJohn Youn #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 459c1d286cfSJohn Youn 460d21bcc3fSJohn Youn u8 phy_type; 461c1d286cfSJohn Youn #define DWC2_PHY_TYPE_PARAM_FS 0 462c1d286cfSJohn Youn #define DWC2_PHY_TYPE_PARAM_UTMI 1 463c1d286cfSJohn Youn #define DWC2_PHY_TYPE_PARAM_ULPI 2 464c1d286cfSJohn Youn 46557b8e235SJohn Youn u8 speed; 46657b8e235SJohn Youn #define DWC2_SPEED_PARAM_HIGH 0 46757b8e235SJohn Youn #define DWC2_SPEED_PARAM_FULL 1 46857b8e235SJohn Youn #define DWC2_SPEED_PARAM_LOW 2 46957b8e235SJohn Youn 470d21bcc3fSJohn Youn u8 phy_utmi_width; 471d21bcc3fSJohn Youn bool phy_ulpi_ddr; 472d21bcc3fSJohn Youn bool phy_ulpi_ext_vbus; 47357b8e235SJohn Youn bool enable_dynamic_fifo; 47457b8e235SJohn Youn bool en_multiple_tx_fifo; 475d21bcc3fSJohn Youn bool i2c_enable; 476d21bcc3fSJohn Youn bool ulpi_fs_ls; 47757b8e235SJohn Youn bool ts_dline; 47857b8e235SJohn Youn bool reload_ctl; 47957b8e235SJohn Youn bool uframe_sched; 48057b8e235SJohn Youn bool external_id_pin_ctl; 48157b8e235SJohn Youn bool hibernation; 48257b8e235SJohn Youn u16 max_packet_count; 48357b8e235SJohn Youn u32 max_transfer_size; 48457b8e235SJohn Youn u32 ahbcfg; 48557b8e235SJohn Youn 48657b8e235SJohn Youn /* Host parameters */ 48757b8e235SJohn Youn bool host_dma; 48857b8e235SJohn Youn bool dma_desc_enable; 48957b8e235SJohn Youn bool dma_desc_fs_enable; 490d21bcc3fSJohn Youn bool host_support_fs_ls_low_power; 491d21bcc3fSJohn Youn bool host_ls_low_power_phy_clk; 492c1d286cfSJohn Youn 49357b8e235SJohn Youn u8 host_channels; 49457b8e235SJohn Youn u16 host_rx_fifo_size; 49557b8e235SJohn Youn u16 host_nperio_tx_fifo_size; 49657b8e235SJohn Youn u16 host_perio_tx_fifo_size; 4976b66ce51SJohn Youn 4986b66ce51SJohn Youn /* Gadget parameters */ 49905ee799fSJohn Youn bool g_dma; 500dec4b556SVahram Aharonyan bool g_dma_desc; 50100c704ccSLeo Yan u32 g_rx_fifo_size; 50200c704ccSLeo Yan u32 g_np_tx_fifo_size; 50305ee799fSJohn Youn u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; 504197ba5f4SPaul Zimmerman }; 505197ba5f4SPaul Zimmerman 506197ba5f4SPaul Zimmerman /** 507197ba5f4SPaul Zimmerman * struct dwc2_hw_params - Autodetected parameters. 508197ba5f4SPaul Zimmerman * 509197ba5f4SPaul Zimmerman * These parameters are the various parameters read from hardware 510197ba5f4SPaul Zimmerman * registers during initialization. They typically contain the best 511197ba5f4SPaul Zimmerman * supported or maximum value that can be configured in the 512197ba5f4SPaul Zimmerman * corresponding dwc2_core_params value. 513197ba5f4SPaul Zimmerman * 514197ba5f4SPaul Zimmerman * The values that are not in dwc2_core_params are documented below. 515197ba5f4SPaul Zimmerman * 516197ba5f4SPaul Zimmerman * @op_mode Mode of Operation 517197ba5f4SPaul Zimmerman * 0 - HNP- and SRP-Capable OTG (Host & Device) 518197ba5f4SPaul Zimmerman * 1 - SRP-Capable OTG (Host & Device) 519197ba5f4SPaul Zimmerman * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 520197ba5f4SPaul Zimmerman * 3 - SRP-Capable Device 521197ba5f4SPaul Zimmerman * 4 - Non-OTG Device 522197ba5f4SPaul Zimmerman * 5 - SRP-Capable Host 523197ba5f4SPaul Zimmerman * 6 - Non-OTG Host 524197ba5f4SPaul Zimmerman * @arch Architecture 525197ba5f4SPaul Zimmerman * 0 - Slave only 526197ba5f4SPaul Zimmerman * 1 - External DMA 527197ba5f4SPaul Zimmerman * 2 - Internal DMA 528197ba5f4SPaul Zimmerman * @power_optimized Are power optimizations enabled? 529197ba5f4SPaul Zimmerman * @num_dev_ep Number of device endpoints available 530197ba5f4SPaul Zimmerman * @num_dev_perio_in_ep Number of device periodic IN endpoints 531997f4f81SMickael Maison * available 532197ba5f4SPaul Zimmerman * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue 533197ba5f4SPaul Zimmerman * Depth 534197ba5f4SPaul Zimmerman * 0 to 30 535197ba5f4SPaul Zimmerman * @host_perio_tx_q_depth 536197ba5f4SPaul Zimmerman * Host Mode Periodic Request Queue Depth 537197ba5f4SPaul Zimmerman * 2, 4 or 8 538197ba5f4SPaul Zimmerman * @nperio_tx_q_depth 539197ba5f4SPaul Zimmerman * Non-Periodic Request Queue Depth 540197ba5f4SPaul Zimmerman * 2, 4 or 8 541197ba5f4SPaul Zimmerman * @hs_phy_type High-speed PHY interface type 542197ba5f4SPaul Zimmerman * 0 - High-speed interface not supported 543197ba5f4SPaul Zimmerman * 1 - UTMI+ 544197ba5f4SPaul Zimmerman * 2 - ULPI 545197ba5f4SPaul Zimmerman * 3 - UTMI+ and ULPI 546197ba5f4SPaul Zimmerman * @fs_phy_type Full-speed PHY interface type 547197ba5f4SPaul Zimmerman * 0 - Full speed interface not supported 548197ba5f4SPaul Zimmerman * 1 - Dedicated full speed interface 549197ba5f4SPaul Zimmerman * 2 - FS pins shared with UTMI+ pins 550197ba5f4SPaul Zimmerman * 3 - FS pins shared with ULPI pins 551197ba5f4SPaul Zimmerman * @total_fifo_size: Total internal RAM for FIFOs (bytes) 552197ba5f4SPaul Zimmerman * @utmi_phy_data_width UTMI+ PHY data width 553197ba5f4SPaul Zimmerman * 0 - 8 bits 554197ba5f4SPaul Zimmerman * 1 - 16 bits 555197ba5f4SPaul Zimmerman * 2 - 8 or 16 bits 556197ba5f4SPaul Zimmerman * @snpsid: Value from SNPSID register 55755e1040eSJohn Youn * @dev_ep_dirs: Direction of device endpoints (GHWCFG1) 558197ba5f4SPaul Zimmerman */ 559197ba5f4SPaul Zimmerman struct dwc2_hw_params { 560197ba5f4SPaul Zimmerman unsigned op_mode:3; 561197ba5f4SPaul Zimmerman unsigned arch:2; 562197ba5f4SPaul Zimmerman unsigned dma_desc_enable:1; 563197ba5f4SPaul Zimmerman unsigned enable_dynamic_fifo:1; 564197ba5f4SPaul Zimmerman unsigned en_multiple_tx_fifo:1; 565d1531319SJohn Youn unsigned rx_fifo_size:16; 566197ba5f4SPaul Zimmerman unsigned host_nperio_tx_fifo_size:16; 56755e1040eSJohn Youn unsigned dev_nperio_tx_fifo_size:16; 568197ba5f4SPaul Zimmerman unsigned host_perio_tx_fifo_size:16; 569197ba5f4SPaul Zimmerman unsigned nperio_tx_q_depth:3; 570197ba5f4SPaul Zimmerman unsigned host_perio_tx_q_depth:3; 571197ba5f4SPaul Zimmerman unsigned dev_token_q_depth:5; 572197ba5f4SPaul Zimmerman unsigned max_transfer_size:26; 573197ba5f4SPaul Zimmerman unsigned max_packet_count:11; 574197ba5f4SPaul Zimmerman unsigned host_channels:5; 575197ba5f4SPaul Zimmerman unsigned hs_phy_type:2; 576197ba5f4SPaul Zimmerman unsigned fs_phy_type:2; 577197ba5f4SPaul Zimmerman unsigned i2c_enable:1; 578197ba5f4SPaul Zimmerman unsigned num_dev_ep:4; 579197ba5f4SPaul Zimmerman unsigned num_dev_perio_in_ep:4; 580197ba5f4SPaul Zimmerman unsigned total_fifo_size:16; 581197ba5f4SPaul Zimmerman unsigned power_optimized:1; 582197ba5f4SPaul Zimmerman unsigned utmi_phy_data_width:2; 583197ba5f4SPaul Zimmerman u32 snpsid; 58455e1040eSJohn Youn u32 dev_ep_dirs; 585197ba5f4SPaul Zimmerman }; 586197ba5f4SPaul Zimmerman 5873f95001dSMian Yousaf Kaukab /* Size of control and EP0 buffers */ 5883f95001dSMian Yousaf Kaukab #define DWC2_CTRL_BUFF_SIZE 8 5893f95001dSMian Yousaf Kaukab 590197ba5f4SPaul Zimmerman /** 59138beaec6SJohn Youn * struct dwc2_gregs_backup - Holds global registers state before 59238beaec6SJohn Youn * entering partial power down 593d17ee77bSGregory Herrero * @gotgctl: Backup of GOTGCTL register 594d17ee77bSGregory Herrero * @gintmsk: Backup of GINTMSK register 595d17ee77bSGregory Herrero * @gahbcfg: Backup of GAHBCFG register 596d17ee77bSGregory Herrero * @gusbcfg: Backup of GUSBCFG register 597d17ee77bSGregory Herrero * @grxfsiz: Backup of GRXFSIZ register 598d17ee77bSGregory Herrero * @gnptxfsiz: Backup of GNPTXFSIZ register 599d17ee77bSGregory Herrero * @gi2cctl: Backup of GI2CCTL register 600d17ee77bSGregory Herrero * @hptxfsiz: Backup of HPTXFSIZ register 601d17ee77bSGregory Herrero * @gdfifocfg: Backup of GDFIFOCFG register 602d17ee77bSGregory Herrero * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 603d17ee77bSGregory Herrero * @gpwrdn: Backup of GPWRDN register 604d17ee77bSGregory Herrero */ 605d17ee77bSGregory Herrero struct dwc2_gregs_backup { 606d17ee77bSGregory Herrero u32 gotgctl; 607d17ee77bSGregory Herrero u32 gintmsk; 608d17ee77bSGregory Herrero u32 gahbcfg; 609d17ee77bSGregory Herrero u32 gusbcfg; 610d17ee77bSGregory Herrero u32 grxfsiz; 611d17ee77bSGregory Herrero u32 gnptxfsiz; 612d17ee77bSGregory Herrero u32 gi2cctl; 613d17ee77bSGregory Herrero u32 hptxfsiz; 614d17ee77bSGregory Herrero u32 pcgcctl; 615d17ee77bSGregory Herrero u32 gdfifocfg; 616d17ee77bSGregory Herrero u32 dtxfsiz[MAX_EPS_CHANNELS]; 617d17ee77bSGregory Herrero u32 gpwrdn; 618cc1e204cSMian Yousaf Kaukab bool valid; 619d17ee77bSGregory Herrero }; 620d17ee77bSGregory Herrero 621d17ee77bSGregory Herrero /** 62238beaec6SJohn Youn * struct dwc2_dregs_backup - Holds device registers state before 62338beaec6SJohn Youn * entering partial power down 624d17ee77bSGregory Herrero * @dcfg: Backup of DCFG register 625d17ee77bSGregory Herrero * @dctl: Backup of DCTL register 626d17ee77bSGregory Herrero * @daintmsk: Backup of DAINTMSK register 627d17ee77bSGregory Herrero * @diepmsk: Backup of DIEPMSK register 628d17ee77bSGregory Herrero * @doepmsk: Backup of DOEPMSK register 629d17ee77bSGregory Herrero * @diepctl: Backup of DIEPCTL register 630d17ee77bSGregory Herrero * @dieptsiz: Backup of DIEPTSIZ register 631d17ee77bSGregory Herrero * @diepdma: Backup of DIEPDMA register 632d17ee77bSGregory Herrero * @doepctl: Backup of DOEPCTL register 633d17ee77bSGregory Herrero * @doeptsiz: Backup of DOEPTSIZ register 634d17ee77bSGregory Herrero * @doepdma: Backup of DOEPDMA register 635d17ee77bSGregory Herrero */ 636d17ee77bSGregory Herrero struct dwc2_dregs_backup { 637d17ee77bSGregory Herrero u32 dcfg; 638d17ee77bSGregory Herrero u32 dctl; 639d17ee77bSGregory Herrero u32 daintmsk; 640d17ee77bSGregory Herrero u32 diepmsk; 641d17ee77bSGregory Herrero u32 doepmsk; 642d17ee77bSGregory Herrero u32 diepctl[MAX_EPS_CHANNELS]; 643d17ee77bSGregory Herrero u32 dieptsiz[MAX_EPS_CHANNELS]; 644d17ee77bSGregory Herrero u32 diepdma[MAX_EPS_CHANNELS]; 645d17ee77bSGregory Herrero u32 doepctl[MAX_EPS_CHANNELS]; 646d17ee77bSGregory Herrero u32 doeptsiz[MAX_EPS_CHANNELS]; 647d17ee77bSGregory Herrero u32 doepdma[MAX_EPS_CHANNELS]; 648cc1e204cSMian Yousaf Kaukab bool valid; 649d17ee77bSGregory Herrero }; 650d17ee77bSGregory Herrero 651d17ee77bSGregory Herrero /** 65238beaec6SJohn Youn * struct dwc2_hregs_backup - Holds host registers state before 65338beaec6SJohn Youn * entering partial power down 654d17ee77bSGregory Herrero * @hcfg: Backup of HCFG register 655d17ee77bSGregory Herrero * @haintmsk: Backup of HAINTMSK register 656d17ee77bSGregory Herrero * @hcintmsk: Backup of HCINTMSK register 657d17ee77bSGregory Herrero * @hptr0: Backup of HPTR0 register 658d17ee77bSGregory Herrero * @hfir: Backup of HFIR register 659d17ee77bSGregory Herrero */ 660d17ee77bSGregory Herrero struct dwc2_hregs_backup { 661d17ee77bSGregory Herrero u32 hcfg; 662d17ee77bSGregory Herrero u32 haintmsk; 663d17ee77bSGregory Herrero u32 hcintmsk[MAX_EPS_CHANNELS]; 664d17ee77bSGregory Herrero u32 hprt0; 665d17ee77bSGregory Herrero u32 hfir; 666cc1e204cSMian Yousaf Kaukab bool valid; 667d17ee77bSGregory Herrero }; 668d17ee77bSGregory Herrero 6699f9f09b0SDouglas Anderson /* 6709f9f09b0SDouglas Anderson * Constants related to high speed periodic scheduling 6719f9f09b0SDouglas Anderson * 6729f9f09b0SDouglas Anderson * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a 6739f9f09b0SDouglas Anderson * reservation point of view it's assumed that the schedule goes right back to 6749f9f09b0SDouglas Anderson * the beginning after the end of the schedule. 6759f9f09b0SDouglas Anderson * 6769f9f09b0SDouglas Anderson * What does that mean for scheduling things with a long interval? It means 6779f9f09b0SDouglas Anderson * we'll reserve time for them in every possible microframe that they could 6789f9f09b0SDouglas Anderson * ever be scheduled in. ...but we'll still only actually schedule them as 6799f9f09b0SDouglas Anderson * often as they were requested. 6809f9f09b0SDouglas Anderson * 6819f9f09b0SDouglas Anderson * We keep our schedule in a "bitmap" structure. This simplifies having 6829f9f09b0SDouglas Anderson * to keep track of and merge intervals: we just let the bitmap code do most 6839f9f09b0SDouglas Anderson * of the heavy lifting. In a way scheduling is much like memory allocation. 6849f9f09b0SDouglas Anderson * 6859f9f09b0SDouglas Anderson * We schedule 100us per uframe or 80% of 125us (the maximum amount you're 6869f9f09b0SDouglas Anderson * supposed to schedule for periodic transfers). That's according to spec. 6879f9f09b0SDouglas Anderson * 6889f9f09b0SDouglas Anderson * Note that though we only schedule 80% of each microframe, the bitmap that we 6899f9f09b0SDouglas Anderson * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of 6909f9f09b0SDouglas Anderson * space for each uFrame). 6919f9f09b0SDouglas Anderson * 6929f9f09b0SDouglas Anderson * Requirements: 6939f9f09b0SDouglas Anderson * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1) 6949f9f09b0SDouglas Anderson * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably 6959f9f09b0SDouglas Anderson * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might 6969f9f09b0SDouglas Anderson * be bugs). The 8 comes from the USB spec: number of microframes per frame. 6979f9f09b0SDouglas Anderson */ 6989f9f09b0SDouglas Anderson #define DWC2_US_PER_UFRAME 125 6999f9f09b0SDouglas Anderson #define DWC2_HS_PERIODIC_US_PER_UFRAME 100 7009f9f09b0SDouglas Anderson 7019f9f09b0SDouglas Anderson #define DWC2_HS_SCHEDULE_UFRAMES 8 7029f9f09b0SDouglas Anderson #define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \ 7039f9f09b0SDouglas Anderson DWC2_HS_PERIODIC_US_PER_UFRAME) 7049f9f09b0SDouglas Anderson 7059f9f09b0SDouglas Anderson /* 7069f9f09b0SDouglas Anderson * Constants related to low speed scheduling 7079f9f09b0SDouglas Anderson * 7089f9f09b0SDouglas Anderson * For high speed we schedule every 1us. For low speed that's a bit overkill, 7099f9f09b0SDouglas Anderson * so we make up a unit called a "slice" that's worth 25us. There are 40 7109f9f09b0SDouglas Anderson * slices in a full frame and we can schedule 36 of those (90%) for periodic 7119f9f09b0SDouglas Anderson * transfers. 7129f9f09b0SDouglas Anderson * 7139f9f09b0SDouglas Anderson * Our low speed schedule can be as short as 1 frame or could be longer. When 7149f9f09b0SDouglas Anderson * we only schedule 1 frame it means that we'll need to reserve a time every 7159f9f09b0SDouglas Anderson * frame even for things that only transfer very rarely, so something that runs 7169f9f09b0SDouglas Anderson * every 2048 frames will get time reserved in every frame. Our low speed 7179f9f09b0SDouglas Anderson * schedule can be longer and we'll be able to handle more overlap, but that 7189f9f09b0SDouglas Anderson * will come at increased memory cost and increased time to schedule. 7199f9f09b0SDouglas Anderson * 7209f9f09b0SDouglas Anderson * Note: one other advantage of a short low speed schedule is that if we mess 7219f9f09b0SDouglas Anderson * up and miss scheduling we can jump in and use any of the slots that we 7229f9f09b0SDouglas Anderson * happened to reserve. 7239f9f09b0SDouglas Anderson * 7249f9f09b0SDouglas Anderson * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for 7259f9f09b0SDouglas Anderson * the schedule. There will be one schedule per TT. 7269f9f09b0SDouglas Anderson * 7279f9f09b0SDouglas Anderson * Requirements: 7289f9f09b0SDouglas Anderson * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME. 7299f9f09b0SDouglas Anderson */ 7309f9f09b0SDouglas Anderson #define DWC2_US_PER_SLICE 25 7319f9f09b0SDouglas Anderson #define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE) 7329f9f09b0SDouglas Anderson 7339f9f09b0SDouglas Anderson #define DWC2_ROUND_US_TO_SLICE(us) \ 7349f9f09b0SDouglas Anderson (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \ 7359f9f09b0SDouglas Anderson DWC2_US_PER_SLICE) 7369f9f09b0SDouglas Anderson 7379f9f09b0SDouglas Anderson #define DWC2_LS_PERIODIC_US_PER_FRAME \ 7389f9f09b0SDouglas Anderson 900 7399f9f09b0SDouglas Anderson #define DWC2_LS_PERIODIC_SLICES_PER_FRAME \ 7409f9f09b0SDouglas Anderson (DWC2_LS_PERIODIC_US_PER_FRAME / \ 7419f9f09b0SDouglas Anderson DWC2_US_PER_SLICE) 7429f9f09b0SDouglas Anderson 7439f9f09b0SDouglas Anderson #define DWC2_LS_SCHEDULE_FRAMES 1 7449f9f09b0SDouglas Anderson #define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \ 7459f9f09b0SDouglas Anderson DWC2_LS_PERIODIC_SLICES_PER_FRAME) 7469f9f09b0SDouglas Anderson 747d17ee77bSGregory Herrero /** 748197ba5f4SPaul Zimmerman * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 749197ba5f4SPaul Zimmerman * and periodic schedules 750197ba5f4SPaul Zimmerman * 751941fcce4SDinh Nguyen * These are common for both host and peripheral modes: 752941fcce4SDinh Nguyen * 753197ba5f4SPaul Zimmerman * @dev: The struct device pointer 754197ba5f4SPaul Zimmerman * @regs: Pointer to controller regs 755197ba5f4SPaul Zimmerman * @hw_params: Parameters that were autodetected from the 756197ba5f4SPaul Zimmerman * hardware registers 757941fcce4SDinh Nguyen * @core_params: Parameters that define how the core should be configured 758197ba5f4SPaul Zimmerman * @op_state: The operational State, during transitions (a_host=> 759197ba5f4SPaul Zimmerman * a_peripheral and b_device=>b_host) this may not match 760197ba5f4SPaul Zimmerman * the core, but allows the software to determine 761197ba5f4SPaul Zimmerman * transitions 762c0155b9dSKever Yang * @dr_mode: Requested mode of operation, one of following: 763c0155b9dSKever Yang * - USB_DR_MODE_PERIPHERAL 764c0155b9dSKever Yang * - USB_DR_MODE_HOST 765c0155b9dSKever Yang * - USB_DR_MODE_OTG 76609a75e85SMarek Szyprowski * @hcd_enabled Host mode sub-driver initialization indicator. 76709a75e85SMarek Szyprowski * @gadget_enabled Peripheral mode sub-driver initialization indicator. 76809a75e85SMarek Szyprowski * @ll_hw_enabled Status of low-level hardware resources. 76909a75e85SMarek Szyprowski * @phy: The otg phy transceiver structure for phy control. 77038beaec6SJohn Youn * @uphy: The otg phy transceiver structure for old USB phy 77138beaec6SJohn Youn * control. 77238beaec6SJohn Youn * @plat: The platform specific configuration data. This can be 77338beaec6SJohn Youn * removed once all SoCs support usb transceiver. 77409a75e85SMarek Szyprowski * @supplies: Definition of USB power supplies 77509a75e85SMarek Szyprowski * @phyif: PHY interface width 776941fcce4SDinh Nguyen * @lock: Spinlock that protects all the driver data structures 777941fcce4SDinh Nguyen * @priv: Stores a pointer to the struct usb_hcd 778197ba5f4SPaul Zimmerman * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 779197ba5f4SPaul Zimmerman * transfer are in process of being queued 780197ba5f4SPaul Zimmerman * @srp_success: Stores status of SRP request in the case of a FS PHY 781197ba5f4SPaul Zimmerman * with an I2C interface 782197ba5f4SPaul Zimmerman * @wq_otg: Workqueue object used for handling of some interrupts 783197ba5f4SPaul Zimmerman * @wf_otg: Work object for handling Connector ID Status Change 784197ba5f4SPaul Zimmerman * interrupt 785197ba5f4SPaul Zimmerman * @wkp_timer: Timer object for handling Wakeup Detected interrupt 786197ba5f4SPaul Zimmerman * @lx_state: Lx state of connected device 787d17ee77bSGregory Herrero * @gregs_backup: Backup of global registers during suspend 788d17ee77bSGregory Herrero * @dregs_backup: Backup of device registers during suspend 789d17ee77bSGregory Herrero * @hregs_backup: Backup of host registers during suspend 790941fcce4SDinh Nguyen * 791941fcce4SDinh Nguyen * These are for host mode: 792941fcce4SDinh Nguyen * 793197ba5f4SPaul Zimmerman * @flags: Flags for handling root port state changes 794197ba5f4SPaul Zimmerman * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 795197ba5f4SPaul Zimmerman * Transfers associated with these QHs are not currently 796197ba5f4SPaul Zimmerman * assigned to a host channel. 797197ba5f4SPaul Zimmerman * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 798197ba5f4SPaul Zimmerman * Transfers associated with these QHs are currently 799197ba5f4SPaul Zimmerman * assigned to a host channel. 800197ba5f4SPaul Zimmerman * @non_periodic_qh_ptr: Pointer to next QH to process in the active 801197ba5f4SPaul Zimmerman * non-periodic schedule 802197ba5f4SPaul Zimmerman * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 803197ba5f4SPaul Zimmerman * list of QHs for periodic transfers that are _not_ 804197ba5f4SPaul Zimmerman * scheduled for the next frame. Each QH in the list has an 805197ba5f4SPaul Zimmerman * interval counter that determines when it needs to be 806197ba5f4SPaul Zimmerman * scheduled for execution. This scheduling mechanism 807197ba5f4SPaul Zimmerman * allows only a simple calculation for periodic bandwidth 808197ba5f4SPaul Zimmerman * used (i.e. must assume that all periodic transfers may 809197ba5f4SPaul Zimmerman * need to execute in the same frame). However, it greatly 810197ba5f4SPaul Zimmerman * simplifies scheduling and should be sufficient for the 811197ba5f4SPaul Zimmerman * vast majority of OTG hosts, which need to connect to a 812197ba5f4SPaul Zimmerman * small number of peripherals at one time. Items move from 813197ba5f4SPaul Zimmerman * this list to periodic_sched_ready when the QH interval 814197ba5f4SPaul Zimmerman * counter is 0 at SOF. 815197ba5f4SPaul Zimmerman * @periodic_sched_ready: List of periodic QHs that are ready for execution in 816197ba5f4SPaul Zimmerman * the next frame, but have not yet been assigned to host 817197ba5f4SPaul Zimmerman * channels. Items move from this list to 818197ba5f4SPaul Zimmerman * periodic_sched_assigned as host channels become 819197ba5f4SPaul Zimmerman * available during the current frame. 820197ba5f4SPaul Zimmerman * @periodic_sched_assigned: List of periodic QHs to be executed in the next 821197ba5f4SPaul Zimmerman * frame that are assigned to host channels. Items move 822197ba5f4SPaul Zimmerman * from this list to periodic_sched_queued as the 823197ba5f4SPaul Zimmerman * transactions for the QH are queued to the DWC_otg 824197ba5f4SPaul Zimmerman * controller. 825197ba5f4SPaul Zimmerman * @periodic_sched_queued: List of periodic QHs that have been queued for 826197ba5f4SPaul Zimmerman * execution. Items move from this list to either 827197ba5f4SPaul Zimmerman * periodic_sched_inactive or periodic_sched_ready when the 828197ba5f4SPaul Zimmerman * channel associated with the transfer is released. If the 829197ba5f4SPaul Zimmerman * interval for the QH is 1, the item moves to 830197ba5f4SPaul Zimmerman * periodic_sched_ready because it must be rescheduled for 831197ba5f4SPaul Zimmerman * the next frame. Otherwise, the item moves to 832197ba5f4SPaul Zimmerman * periodic_sched_inactive. 833c9c8ac01SDouglas Anderson * @split_order: List keeping track of channels doing splits, in order. 834197ba5f4SPaul Zimmerman * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 835197ba5f4SPaul Zimmerman * This value is in microseconds per (micro)frame. The 836197ba5f4SPaul Zimmerman * assumption is that all periodic transfers may occur in 837197ba5f4SPaul Zimmerman * the same (micro)frame. 8389f9f09b0SDouglas Anderson * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the 8399f9f09b0SDouglas Anderson * host is in high speed mode; low speed schedules are 8409f9f09b0SDouglas Anderson * stored elsewhere since we need one per TT. 841197ba5f4SPaul Zimmerman * @frame_number: Frame number read from the core at SOF. The value ranges 842197ba5f4SPaul Zimmerman * from 0 to HFNUM_MAX_FRNUM. 843197ba5f4SPaul Zimmerman * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 844197ba5f4SPaul Zimmerman * SOF enable/disable. 845197ba5f4SPaul Zimmerman * @free_hc_list: Free host channels in the controller. This is a list of 846197ba5f4SPaul Zimmerman * struct dwc2_host_chan items. 847197ba5f4SPaul Zimmerman * @periodic_channels: Number of host channels assigned to periodic transfers. 848197ba5f4SPaul Zimmerman * Currently assuming that there is a dedicated host 849197ba5f4SPaul Zimmerman * channel for each periodic transaction and at least one 850197ba5f4SPaul Zimmerman * host channel is available for non-periodic transactions. 851197ba5f4SPaul Zimmerman * @non_periodic_channels: Number of host channels assigned to non-periodic 852197ba5f4SPaul Zimmerman * transfers 853197ba5f4SPaul Zimmerman * @available_host_channels Number of host channels available for the microframe 854197ba5f4SPaul Zimmerman * scheduler to use 855197ba5f4SPaul Zimmerman * @hc_ptr_array: Array of pointers to the host channel descriptors. 856197ba5f4SPaul Zimmerman * Allows accessing a host channel descriptor given the 857197ba5f4SPaul Zimmerman * host channel number. This is useful in interrupt 858197ba5f4SPaul Zimmerman * handlers. 859197ba5f4SPaul Zimmerman * @status_buf: Buffer used for data received during the status phase of 860197ba5f4SPaul Zimmerman * a control transfer. 861197ba5f4SPaul Zimmerman * @status_buf_dma: DMA address for status_buf 862197ba5f4SPaul Zimmerman * @start_work: Delayed work for handling host A-cable connection 863197ba5f4SPaul Zimmerman * @reset_work: Delayed work for handling a port reset 864197ba5f4SPaul Zimmerman * @otg_port: OTG port number 865197ba5f4SPaul Zimmerman * @frame_list: Frame list 866197ba5f4SPaul Zimmerman * @frame_list_dma: Frame list DMA address 86795105a99SGregory Herrero * @frame_list_sz: Frame list size 8683b5fcc9aSGregory Herrero * @desc_gen_cache: Kmem cache for generic descriptors 8693b5fcc9aSGregory Herrero * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors 870941fcce4SDinh Nguyen * 871941fcce4SDinh Nguyen * These are for peripheral mode: 872941fcce4SDinh Nguyen * 873941fcce4SDinh Nguyen * @driver: USB gadget driver 874941fcce4SDinh Nguyen * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 875941fcce4SDinh Nguyen * @num_of_eps: Number of available EPs (excluding EP0) 876941fcce4SDinh Nguyen * @debug_root: Root directrory for debugfs. 877941fcce4SDinh Nguyen * @debug_file: Main status file for debugfs. 8789e14d0a5SGregory Herrero * @debug_testmode: Testmode status file for debugfs. 879941fcce4SDinh Nguyen * @debug_fifo: FIFO status file for debugfs. 880941fcce4SDinh Nguyen * @ep0_reply: Request used for ep0 reply. 881941fcce4SDinh Nguyen * @ep0_buff: Buffer for EP0 reply data, if needed. 882941fcce4SDinh Nguyen * @ctrl_buff: Buffer for EP0 control requests. 883941fcce4SDinh Nguyen * @ctrl_req: Request for EP0 control packets. 884fe0b94abSMian Yousaf Kaukab * @ep0_state: EP0 control transfers state 8859e14d0a5SGregory Herrero * @test_mode: USB test mode requested by the host 8860f6b80c0SVahram Aharonyan * @setup_desc_dma: EP0 setup stage desc chain DMA address 8870f6b80c0SVahram Aharonyan * @setup_desc: EP0 setup stage desc chain pointer 8880f6b80c0SVahram Aharonyan * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address 8890f6b80c0SVahram Aharonyan * @ctrl_in_desc: EP0 IN data phase desc chain pointer 8900f6b80c0SVahram Aharonyan * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address 8910f6b80c0SVahram Aharonyan * @ctrl_out_desc: EP0 OUT data phase desc chain pointer 892941fcce4SDinh Nguyen * @eps: The endpoints being supplied to the gadget framework 893197ba5f4SPaul Zimmerman */ 894197ba5f4SPaul Zimmerman struct dwc2_hsotg { 895197ba5f4SPaul Zimmerman struct device *dev; 896197ba5f4SPaul Zimmerman void __iomem *regs; 897197ba5f4SPaul Zimmerman /** Params detected from hardware */ 898197ba5f4SPaul Zimmerman struct dwc2_hw_params hw_params; 899197ba5f4SPaul Zimmerman /** Params to actually use */ 900bea8e86cSJohn Youn struct dwc2_core_params params; 901197ba5f4SPaul Zimmerman enum usb_otg_state op_state; 902c0155b9dSKever Yang enum usb_dr_mode dr_mode; 903e39af88fSMarek Szyprowski unsigned int hcd_enabled:1; 904e39af88fSMarek Szyprowski unsigned int gadget_enabled:1; 90509a75e85SMarek Szyprowski unsigned int ll_hw_enabled:1; 906197ba5f4SPaul Zimmerman 907941fcce4SDinh Nguyen struct phy *phy; 908941fcce4SDinh Nguyen struct usb_phy *uphy; 90909a75e85SMarek Szyprowski struct dwc2_hsotg_plat *plat; 910b98866c2SJohn Youn struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES]; 91109a75e85SMarek Szyprowski u32 phyif; 912941fcce4SDinh Nguyen 913941fcce4SDinh Nguyen spinlock_t lock; 914941fcce4SDinh Nguyen void *priv; 915941fcce4SDinh Nguyen int irq; 916941fcce4SDinh Nguyen struct clk *clk; 91783f8da56SDinh Nguyen struct reset_control *reset; 918941fcce4SDinh Nguyen 919197ba5f4SPaul Zimmerman unsigned int queuing_high_bandwidth:1; 920197ba5f4SPaul Zimmerman unsigned int srp_success:1; 921197ba5f4SPaul Zimmerman 922197ba5f4SPaul Zimmerman struct workqueue_struct *wq_otg; 923197ba5f4SPaul Zimmerman struct work_struct wf_otg; 924197ba5f4SPaul Zimmerman struct timer_list wkp_timer; 925197ba5f4SPaul Zimmerman enum dwc2_lx_state lx_state; 926cc1e204cSMian Yousaf Kaukab struct dwc2_gregs_backup gr_backup; 927cc1e204cSMian Yousaf Kaukab struct dwc2_dregs_backup dr_backup; 928cc1e204cSMian Yousaf Kaukab struct dwc2_hregs_backup hr_backup; 929197ba5f4SPaul Zimmerman 930941fcce4SDinh Nguyen struct dentry *debug_root; 931563cf017SMian Yousaf Kaukab struct debugfs_regset32 *regset; 932941fcce4SDinh Nguyen 933941fcce4SDinh Nguyen /* DWC OTG HW Release versions */ 934941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_71a 0x4f54271a 935941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_90a 0x4f54290a 936941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_92a 0x4f54292a 937941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_94a 0x4f54294a 938941fcce4SDinh Nguyen #define DWC2_CORE_REV_3_00a 0x4f54300a 939fef6bc37SJohn Youn #define DWC2_CORE_REV_3_10a 0x4f54310a 9401e6b98ebSVardan Mikayelyan #define DWC2_FS_IOT_REV_1_00a 0x5531100a 9411e6b98ebSVardan Mikayelyan #define DWC2_HS_IOT_REV_1_00a 0x5532100a 942941fcce4SDinh Nguyen 943941fcce4SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 944197ba5f4SPaul Zimmerman union dwc2_hcd_internal_flags { 945197ba5f4SPaul Zimmerman u32 d32; 946197ba5f4SPaul Zimmerman struct { 947197ba5f4SPaul Zimmerman unsigned port_connect_status_change:1; 948197ba5f4SPaul Zimmerman unsigned port_connect_status:1; 949197ba5f4SPaul Zimmerman unsigned port_reset_change:1; 950197ba5f4SPaul Zimmerman unsigned port_enable_change:1; 951197ba5f4SPaul Zimmerman unsigned port_suspend_change:1; 952197ba5f4SPaul Zimmerman unsigned port_over_current_change:1; 953197ba5f4SPaul Zimmerman unsigned port_l1_change:1; 954fd4850cfSCharles Manning unsigned reserved:25; 955197ba5f4SPaul Zimmerman } b; 956197ba5f4SPaul Zimmerman } flags; 957197ba5f4SPaul Zimmerman 958197ba5f4SPaul Zimmerman struct list_head non_periodic_sched_inactive; 959197ba5f4SPaul Zimmerman struct list_head non_periodic_sched_active; 960197ba5f4SPaul Zimmerman struct list_head *non_periodic_qh_ptr; 961197ba5f4SPaul Zimmerman struct list_head periodic_sched_inactive; 962197ba5f4SPaul Zimmerman struct list_head periodic_sched_ready; 963197ba5f4SPaul Zimmerman struct list_head periodic_sched_assigned; 964197ba5f4SPaul Zimmerman struct list_head periodic_sched_queued; 965c9c8ac01SDouglas Anderson struct list_head split_order; 966197ba5f4SPaul Zimmerman u16 periodic_usecs; 9679f9f09b0SDouglas Anderson unsigned long hs_periodic_bitmap[ 9689f9f09b0SDouglas Anderson DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)]; 969197ba5f4SPaul Zimmerman u16 frame_number; 970197ba5f4SPaul Zimmerman u16 periodic_qh_count; 971734643dfSGregory Herrero bool bus_suspended; 972fbb9e22bSMian Yousaf Kaukab bool new_connection; 973197ba5f4SPaul Zimmerman 974483bb254SDouglas Anderson u16 last_frame_num; 975483bb254SDouglas Anderson 976197ba5f4SPaul Zimmerman #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 977197ba5f4SPaul Zimmerman #define FRAME_NUM_ARRAY_SIZE 1000 978197ba5f4SPaul Zimmerman u16 *frame_num_array; 979197ba5f4SPaul Zimmerman u16 *last_frame_num_array; 980197ba5f4SPaul Zimmerman int frame_num_idx; 981197ba5f4SPaul Zimmerman int dumped_frame_num_array; 982197ba5f4SPaul Zimmerman #endif 983197ba5f4SPaul Zimmerman 984197ba5f4SPaul Zimmerman struct list_head free_hc_list; 985197ba5f4SPaul Zimmerman int periodic_channels; 986197ba5f4SPaul Zimmerman int non_periodic_channels; 987197ba5f4SPaul Zimmerman int available_host_channels; 988197ba5f4SPaul Zimmerman struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 989197ba5f4SPaul Zimmerman u8 *status_buf; 990197ba5f4SPaul Zimmerman dma_addr_t status_buf_dma; 991197ba5f4SPaul Zimmerman #define DWC2_HCD_STATUS_BUF_SIZE 64 992197ba5f4SPaul Zimmerman 993197ba5f4SPaul Zimmerman struct delayed_work start_work; 994197ba5f4SPaul Zimmerman struct delayed_work reset_work; 995197ba5f4SPaul Zimmerman u8 otg_port; 996197ba5f4SPaul Zimmerman u32 *frame_list; 997197ba5f4SPaul Zimmerman dma_addr_t frame_list_dma; 99895105a99SGregory Herrero u32 frame_list_sz; 9993b5fcc9aSGregory Herrero struct kmem_cache *desc_gen_cache; 10003b5fcc9aSGregory Herrero struct kmem_cache *desc_hsisoc_cache; 1001197ba5f4SPaul Zimmerman 1002197ba5f4SPaul Zimmerman #ifdef DEBUG 1003197ba5f4SPaul Zimmerman u32 frrem_samples; 1004197ba5f4SPaul Zimmerman u64 frrem_accum; 1005197ba5f4SPaul Zimmerman 1006197ba5f4SPaul Zimmerman u32 hfnum_7_samples_a; 1007197ba5f4SPaul Zimmerman u64 hfnum_7_frrem_accum_a; 1008197ba5f4SPaul Zimmerman u32 hfnum_0_samples_a; 1009197ba5f4SPaul Zimmerman u64 hfnum_0_frrem_accum_a; 1010197ba5f4SPaul Zimmerman u32 hfnum_other_samples_a; 1011197ba5f4SPaul Zimmerman u64 hfnum_other_frrem_accum_a; 1012197ba5f4SPaul Zimmerman 1013197ba5f4SPaul Zimmerman u32 hfnum_7_samples_b; 1014197ba5f4SPaul Zimmerman u64 hfnum_7_frrem_accum_b; 1015197ba5f4SPaul Zimmerman u32 hfnum_0_samples_b; 1016197ba5f4SPaul Zimmerman u64 hfnum_0_frrem_accum_b; 1017197ba5f4SPaul Zimmerman u32 hfnum_other_samples_b; 1018197ba5f4SPaul Zimmerman u64 hfnum_other_frrem_accum_b; 1019197ba5f4SPaul Zimmerman #endif 1020941fcce4SDinh Nguyen #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ 1021941fcce4SDinh Nguyen 1022b98866c2SJohn Youn #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1023b98866c2SJohn Youn IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1024941fcce4SDinh Nguyen /* Gadget structures */ 1025941fcce4SDinh Nguyen struct usb_gadget_driver *driver; 1026941fcce4SDinh Nguyen int fifo_mem; 1027941fcce4SDinh Nguyen unsigned int dedicated_fifos:1; 1028941fcce4SDinh Nguyen unsigned char num_of_eps; 1029941fcce4SDinh Nguyen u32 fifo_map; 1030941fcce4SDinh Nguyen 1031941fcce4SDinh Nguyen struct usb_request *ep0_reply; 1032941fcce4SDinh Nguyen struct usb_request *ctrl_req; 10333f95001dSMian Yousaf Kaukab void *ep0_buff; 10343f95001dSMian Yousaf Kaukab void *ctrl_buff; 1035fe0b94abSMian Yousaf Kaukab enum dwc2_ep0_state ep0_state; 10369e14d0a5SGregory Herrero u8 test_mode; 1037941fcce4SDinh Nguyen 10380f6b80c0SVahram Aharonyan dma_addr_t setup_desc_dma[2]; 10390f6b80c0SVahram Aharonyan struct dwc2_dma_desc *setup_desc[2]; 10400f6b80c0SVahram Aharonyan dma_addr_t ctrl_in_desc_dma; 10410f6b80c0SVahram Aharonyan struct dwc2_dma_desc *ctrl_in_desc; 10420f6b80c0SVahram Aharonyan dma_addr_t ctrl_out_desc_dma; 10430f6b80c0SVahram Aharonyan struct dwc2_dma_desc *ctrl_out_desc; 10440f6b80c0SVahram Aharonyan 1045941fcce4SDinh Nguyen struct usb_gadget gadget; 1046dc6e69e6SMarek Szyprowski unsigned int enabled:1; 10474ace06e8SMarek Szyprowski unsigned int connected:1; 10481f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS]; 10491f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS]; 1050941fcce4SDinh Nguyen #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 1051197ba5f4SPaul Zimmerman }; 1052197ba5f4SPaul Zimmerman 1053197ba5f4SPaul Zimmerman /* Reasons for halting a host channel */ 1054197ba5f4SPaul Zimmerman enum dwc2_halt_status { 1055197ba5f4SPaul Zimmerman DWC2_HC_XFER_NO_HALT_STATUS, 1056197ba5f4SPaul Zimmerman DWC2_HC_XFER_COMPLETE, 1057197ba5f4SPaul Zimmerman DWC2_HC_XFER_URB_COMPLETE, 1058197ba5f4SPaul Zimmerman DWC2_HC_XFER_ACK, 1059197ba5f4SPaul Zimmerman DWC2_HC_XFER_NAK, 1060197ba5f4SPaul Zimmerman DWC2_HC_XFER_NYET, 1061197ba5f4SPaul Zimmerman DWC2_HC_XFER_STALL, 1062197ba5f4SPaul Zimmerman DWC2_HC_XFER_XACT_ERR, 1063197ba5f4SPaul Zimmerman DWC2_HC_XFER_FRAME_OVERRUN, 1064197ba5f4SPaul Zimmerman DWC2_HC_XFER_BABBLE_ERR, 1065197ba5f4SPaul Zimmerman DWC2_HC_XFER_DATA_TOGGLE_ERR, 1066197ba5f4SPaul Zimmerman DWC2_HC_XFER_AHB_ERR, 1067197ba5f4SPaul Zimmerman DWC2_HC_XFER_PERIODIC_INCOMPLETE, 1068197ba5f4SPaul Zimmerman DWC2_HC_XFER_URB_DEQUEUE, 1069197ba5f4SPaul Zimmerman }; 1070197ba5f4SPaul Zimmerman 10711e6b98ebSVardan Mikayelyan /* Core version information */ 10721e6b98ebSVardan Mikayelyan static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg) 10731e6b98ebSVardan Mikayelyan { 10741e6b98ebSVardan Mikayelyan return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000; 10751e6b98ebSVardan Mikayelyan } 10761e6b98ebSVardan Mikayelyan 10771e6b98ebSVardan Mikayelyan static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg) 10781e6b98ebSVardan Mikayelyan { 10791e6b98ebSVardan Mikayelyan return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000; 10801e6b98ebSVardan Mikayelyan } 10811e6b98ebSVardan Mikayelyan 10821e6b98ebSVardan Mikayelyan static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg) 10831e6b98ebSVardan Mikayelyan { 10841e6b98ebSVardan Mikayelyan return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000; 10851e6b98ebSVardan Mikayelyan } 10861e6b98ebSVardan Mikayelyan 1087197ba5f4SPaul Zimmerman /* 1088197ba5f4SPaul Zimmerman * The following functions support initialization of the core driver component 1089197ba5f4SPaul Zimmerman * and the DWC_otg controller 1090197ba5f4SPaul Zimmerman */ 10916e6360b6SJohn Stultz int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait); 10929da51974SJohn Youn int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg); 10939da51974SJohn Youn int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg); 10949da51974SJohn Youn int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore); 1095197ba5f4SPaul Zimmerman 1096323230efSJohn Youn bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host); 1097323230efSJohn Youn void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg); 109809c96980SJohn Youn void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg); 109909c96980SJohn Youn 11009da51974SJohn Youn bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 1101197ba5f4SPaul Zimmerman 1102197ba5f4SPaul Zimmerman /* 1103197ba5f4SPaul Zimmerman * Common core Functions. 1104197ba5f4SPaul Zimmerman * The following functions support managing the DWC_otg controller in either 1105197ba5f4SPaul Zimmerman * device or host mode. 1106197ba5f4SPaul Zimmerman */ 11079da51974SJohn Youn void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 11089da51974SJohn Youn void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 11099da51974SJohn Youn void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 1110197ba5f4SPaul Zimmerman 11119da51974SJohn Youn void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 11129da51974SJohn Youn void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 1113197ba5f4SPaul Zimmerman 1114197ba5f4SPaul Zimmerman /* This function should be called on every hardware interrupt. */ 11159da51974SJohn Youn irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 1116197ba5f4SPaul Zimmerman 1117323230efSJohn Youn /* The device ID match table */ 1118323230efSJohn Youn extern const struct of_device_id dwc2_of_match_table[]; 1119323230efSJohn Youn 11209da51974SJohn Youn int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg); 11219da51974SJohn Youn int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg); 1122ecb176c6SMian Yousaf Kaukab 1123334bbd4eSJohn Youn /* Parameters */ 1124c1d286cfSJohn Youn int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); 1125334bbd4eSJohn Youn int dwc2_init_params(struct dwc2_hsotg *hsotg); 1126334bbd4eSJohn Youn 1127197ba5f4SPaul Zimmerman /* 11286bea9620SJohn Youn * The following functions check the controller's OTG operation mode 11296bea9620SJohn Youn * capability (GHWCFG2.OTG_MODE). 11306bea9620SJohn Youn * 11316bea9620SJohn Youn * These functions can be used before the internal hsotg->hw_params 11326bea9620SJohn Youn * are read in and cached so they always read directly from the 11336bea9620SJohn Youn * GHWCFG2 register. 11346bea9620SJohn Youn */ 11359da51974SJohn Youn unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg); 11366bea9620SJohn Youn bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg); 11376bea9620SJohn Youn bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg); 11386bea9620SJohn Youn bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg); 11396bea9620SJohn Youn 11406bea9620SJohn Youn /* 11411696d5abSJohn Youn * Returns the mode of operation, host or device 11421696d5abSJohn Youn */ 11431696d5abSJohn Youn static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) 11441696d5abSJohn Youn { 11451696d5abSJohn Youn return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0; 11461696d5abSJohn Youn } 11479da51974SJohn Youn 11481696d5abSJohn Youn static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) 11491696d5abSJohn Youn { 11501696d5abSJohn Youn return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0; 11511696d5abSJohn Youn } 11521696d5abSJohn Youn 11531696d5abSJohn Youn /* 1154197ba5f4SPaul Zimmerman * Dump core registers and SPRAM 1155197ba5f4SPaul Zimmerman */ 11569da51974SJohn Youn void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 11579da51974SJohn Youn void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 11589da51974SJohn Youn void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 1159197ba5f4SPaul Zimmerman 1160117777b2SDinh Nguyen /* Gadget defines */ 1161b98866c2SJohn Youn #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1162b98866c2SJohn Youn IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 11639da51974SJohn Youn int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg); 11649da51974SJohn Youn int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2); 11659da51974SJohn Youn int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2); 11669da51974SJohn Youn int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq); 11679da51974SJohn Youn void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1168643cc4deSGregory Herrero bool reset); 11699da51974SJohn Youn void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg); 11709da51974SJohn Youn void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2); 11719da51974SJohn Youn int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode); 1172f81f46e1SGregory Herrero #define dwc2_is_device_connected(hsotg) (hsotg->connected) 117358e52ff6SJohn Youn int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg); 117458e52ff6SJohn Youn int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg); 1175117777b2SDinh Nguyen #else 11761f91b4ccSFelipe Balbi static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2) 1177117777b2SDinh Nguyen { return 0; } 11781f91b4ccSFelipe Balbi static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2) 1179117777b2SDinh Nguyen { return 0; } 11801f91b4ccSFelipe Balbi static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2) 1181117777b2SDinh Nguyen { return 0; } 1182117777b2SDinh Nguyen static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) 1183117777b2SDinh Nguyen { return 0; } 11841f91b4ccSFelipe Balbi static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1185643cc4deSGregory Herrero bool reset) {} 11861f91b4ccSFelipe Balbi static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} 11871f91b4ccSFelipe Balbi static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} 11881f91b4ccSFelipe Balbi static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, 1189f91eea44SMian Yousaf Kaukab int testmode) 1190f91eea44SMian Yousaf Kaukab { return 0; } 1191f81f46e1SGregory Herrero #define dwc2_is_device_connected(hsotg) (0) 119258e52ff6SJohn Youn static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) 119358e52ff6SJohn Youn { return 0; } 119458e52ff6SJohn Youn static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg) 119558e52ff6SJohn Youn { return 0; } 1196117777b2SDinh Nguyen #endif 1197117777b2SDinh Nguyen 1198117777b2SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 11999da51974SJohn Youn int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 12009da51974SJohn Youn int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us); 12019da51974SJohn Youn void dwc2_hcd_connect(struct dwc2_hsotg *hsotg); 12029da51974SJohn Youn void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force); 12039da51974SJohn Youn void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 120458e52ff6SJohn Youn int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg); 120558e52ff6SJohn Youn int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg); 1206117777b2SDinh Nguyen #else 1207117777b2SDinh Nguyen static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1208117777b2SDinh Nguyen { return 0; } 1209fae4e826SDouglas Anderson static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, 1210fae4e826SDouglas Anderson int us) 1211fae4e826SDouglas Anderson { return 0; } 12126a659531SDouglas Anderson static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {} 12136a659531SDouglas Anderson static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {} 1214117777b2SDinh Nguyen static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} 1215117777b2SDinh Nguyen static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} 1216ecb176c6SMian Yousaf Kaukab static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) 1217117777b2SDinh Nguyen { return 0; } 121858e52ff6SJohn Youn static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 121958e52ff6SJohn Youn { return 0; } 122058e52ff6SJohn Youn static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 122158e52ff6SJohn Youn { return 0; } 122258e52ff6SJohn Youn 1223117777b2SDinh Nguyen #endif 1224117777b2SDinh Nguyen 1225197ba5f4SPaul Zimmerman #endif /* __DWC2_CORE_H__ */ 1226