15fd54aceSGreg Kroah-Hartman // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2197ba5f4SPaul Zimmerman /* 3197ba5f4SPaul Zimmerman * core.h - DesignWare HS OTG Controller common declarations 4197ba5f4SPaul Zimmerman * 5197ba5f4SPaul Zimmerman * Copyright (C) 2004-2013 Synopsys, Inc. 6197ba5f4SPaul Zimmerman * 7197ba5f4SPaul Zimmerman * Redistribution and use in source and binary forms, with or without 8197ba5f4SPaul Zimmerman * modification, are permitted provided that the following conditions 9197ba5f4SPaul Zimmerman * are met: 10197ba5f4SPaul Zimmerman * 1. Redistributions of source code must retain the above copyright 11197ba5f4SPaul Zimmerman * notice, this list of conditions, and the following disclaimer, 12197ba5f4SPaul Zimmerman * without modification. 13197ba5f4SPaul Zimmerman * 2. Redistributions in binary form must reproduce the above copyright 14197ba5f4SPaul Zimmerman * notice, this list of conditions and the following disclaimer in the 15197ba5f4SPaul Zimmerman * documentation and/or other materials provided with the distribution. 16197ba5f4SPaul Zimmerman * 3. The names of the above-listed copyright holders may not be used 17197ba5f4SPaul Zimmerman * to endorse or promote products derived from this software without 18197ba5f4SPaul Zimmerman * specific prior written permission. 19197ba5f4SPaul Zimmerman * 20197ba5f4SPaul Zimmerman * ALTERNATIVELY, this software may be distributed under the terms of the 21197ba5f4SPaul Zimmerman * GNU General Public License ("GPL") as published by the Free Software 22197ba5f4SPaul Zimmerman * Foundation; either version 2 of the License, or (at your option) any 23197ba5f4SPaul Zimmerman * later version. 24197ba5f4SPaul Zimmerman * 25197ba5f4SPaul Zimmerman * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 26197ba5f4SPaul Zimmerman * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 27197ba5f4SPaul Zimmerman * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28197ba5f4SPaul Zimmerman * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 29197ba5f4SPaul Zimmerman * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 30197ba5f4SPaul Zimmerman * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 31197ba5f4SPaul Zimmerman * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32197ba5f4SPaul Zimmerman * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 33197ba5f4SPaul Zimmerman * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 34197ba5f4SPaul Zimmerman * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 35197ba5f4SPaul Zimmerman * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36197ba5f4SPaul Zimmerman */ 37197ba5f4SPaul Zimmerman 38197ba5f4SPaul Zimmerman #ifndef __DWC2_CORE_H__ 39197ba5f4SPaul Zimmerman #define __DWC2_CORE_H__ 40197ba5f4SPaul Zimmerman 41f7c0b143SDinh Nguyen #include <linux/phy/phy.h> 42f7c0b143SDinh Nguyen #include <linux/regulator/consumer.h> 43f7c0b143SDinh Nguyen #include <linux/usb/gadget.h> 44f7c0b143SDinh Nguyen #include <linux/usb/otg.h> 45197ba5f4SPaul Zimmerman #include <linux/usb/phy.h> 46197ba5f4SPaul Zimmerman #include "hw.h" 47197ba5f4SPaul Zimmerman 4874fc4a75SDouglas Anderson /* 4974fc4a75SDouglas Anderson * Suggested defines for tracers: 5074fc4a75SDouglas Anderson * - no_printk: Disable tracing 5174fc4a75SDouglas Anderson * - pr_info: Print this info to the console 5274fc4a75SDouglas Anderson * - trace_printk: Print this info to trace buffer (good for verbose logging) 5374fc4a75SDouglas Anderson */ 5474fc4a75SDouglas Anderson 5574fc4a75SDouglas Anderson #define DWC2_TRACE_SCHEDULER no_printk 5674fc4a75SDouglas Anderson #define DWC2_TRACE_SCHEDULER_VB no_printk 5774fc4a75SDouglas Anderson 5874fc4a75SDouglas Anderson /* Detailed scheduler tracing, but won't overwhelm console */ 5974fc4a75SDouglas Anderson #define dwc2_sch_dbg(hsotg, fmt, ...) \ 6074fc4a75SDouglas Anderson DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \ 6174fc4a75SDouglas Anderson dev_name(hsotg->dev), ##__VA_ARGS__) 6274fc4a75SDouglas Anderson 6374fc4a75SDouglas Anderson /* Verbose scheduler tracing */ 6474fc4a75SDouglas Anderson #define dwc2_sch_vdbg(hsotg, fmt, ...) \ 6574fc4a75SDouglas Anderson DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \ 6674fc4a75SDouglas Anderson dev_name(hsotg->dev), ##__VA_ARGS__) 6774fc4a75SDouglas Anderson 6823e34392SArnd Bergmann #ifdef CONFIG_MIPS 6923e34392SArnd Bergmann /* 7023e34392SArnd Bergmann * There are some MIPS machines that can run in either big-endian 7123e34392SArnd Bergmann * or little-endian mode and that use the dwc2 register without 7223e34392SArnd Bergmann * a byteswap in both ways. 7323e34392SArnd Bergmann * Unlike other architectures, MIPS apparently does not require a 7423e34392SArnd Bergmann * barrier before the __raw_writel() to synchronize with DMA but does 7523e34392SArnd Bergmann * require the barrier after the __raw_writel() to serialize a set of 7623e34392SArnd Bergmann * writes. This set of operations was added specifically for MIPS and 7723e34392SArnd Bergmann * should only be used there. 7823e34392SArnd Bergmann */ 7995c8bc36SAntti Seppälä static inline u32 dwc2_readl(const void __iomem *addr) 80197ba5f4SPaul Zimmerman { 8195c8bc36SAntti Seppälä u32 value = __raw_readl(addr); 8295c8bc36SAntti Seppälä 8395c8bc36SAntti Seppälä /* In order to preserve endianness __raw_* operation is used. Therefore 8495c8bc36SAntti Seppälä * a barrier is needed to ensure IO access is not re-ordered across 8595c8bc36SAntti Seppälä * reads or writes 8695c8bc36SAntti Seppälä */ 8795c8bc36SAntti Seppälä mb(); 8895c8bc36SAntti Seppälä return value; 89197ba5f4SPaul Zimmerman } 90197ba5f4SPaul Zimmerman 9195c8bc36SAntti Seppälä static inline void dwc2_writel(u32 value, void __iomem *addr) 9295c8bc36SAntti Seppälä { 9395c8bc36SAntti Seppälä __raw_writel(value, addr); 9495c8bc36SAntti Seppälä 9595c8bc36SAntti Seppälä /* 9695c8bc36SAntti Seppälä * In order to preserve endianness __raw_* operation is used. Therefore 9795c8bc36SAntti Seppälä * a barrier is needed to ensure IO access is not re-ordered across 9895c8bc36SAntti Seppälä * reads or writes 9995c8bc36SAntti Seppälä */ 10095c8bc36SAntti Seppälä mb(); 10195c8bc36SAntti Seppälä #ifdef DWC2_LOG_WRITES 10295c8bc36SAntti Seppälä pr_info("INFO:: wrote %08x to %p\n", value, addr); 103197ba5f4SPaul Zimmerman #endif 10495c8bc36SAntti Seppälä } 10523e34392SArnd Bergmann #else 10623e34392SArnd Bergmann /* Normal architectures just use readl/write */ 10723e34392SArnd Bergmann static inline u32 dwc2_readl(const void __iomem *addr) 10823e34392SArnd Bergmann { 10923e34392SArnd Bergmann return readl(addr); 11023e34392SArnd Bergmann } 11123e34392SArnd Bergmann 11223e34392SArnd Bergmann static inline void dwc2_writel(u32 value, void __iomem *addr) 11323e34392SArnd Bergmann { 11423e34392SArnd Bergmann writel(value, addr); 11523e34392SArnd Bergmann 11623e34392SArnd Bergmann #ifdef DWC2_LOG_WRITES 11723e34392SArnd Bergmann pr_info("info:: wrote %08x to %p\n", value, addr); 11823e34392SArnd Bergmann #endif 11923e34392SArnd Bergmann } 12023e34392SArnd Bergmann #endif 121197ba5f4SPaul Zimmerman 122197ba5f4SPaul Zimmerman /* Maximum number of Endpoints/HostChannels */ 123197ba5f4SPaul Zimmerman #define MAX_EPS_CHANNELS 16 124197ba5f4SPaul Zimmerman 1251f91b4ccSFelipe Balbi /* dwc2-hsotg declarations */ 1261f91b4ccSFelipe Balbi static const char * const dwc2_hsotg_supply_names[] = { 127f7c0b143SDinh Nguyen "vusb_d", /* digital USB supply, 1.2V */ 128f7c0b143SDinh Nguyen "vusb_a", /* analog USB supply, 1.1V */ 129f7c0b143SDinh Nguyen }; 130f7c0b143SDinh Nguyen 131b98866c2SJohn Youn #define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names) 132b98866c2SJohn Youn 133f7c0b143SDinh Nguyen /* 134f7c0b143SDinh Nguyen * EP0_MPS_LIMIT 135f7c0b143SDinh Nguyen * 136f7c0b143SDinh Nguyen * Unfortunately there seems to be a limit of the amount of data that can 137f7c0b143SDinh Nguyen * be transferred by IN transactions on EP0. This is either 127 bytes or 3 138f7c0b143SDinh Nguyen * packets (which practically means 1 packet and 63 bytes of data) when the 139f7c0b143SDinh Nguyen * MPS is set to 64. 140f7c0b143SDinh Nguyen * 141f7c0b143SDinh Nguyen * This means if we are wanting to move >127 bytes of data, we need to 142f7c0b143SDinh Nguyen * split the transactions up, but just doing one packet at a time does 143f7c0b143SDinh Nguyen * not work (this may be an implicit DATA0 PID on first packet of the 144f7c0b143SDinh Nguyen * transaction) and doing 2 packets is outside the controller's limits. 145f7c0b143SDinh Nguyen * 146f7c0b143SDinh Nguyen * If we try to lower the MPS size for EP0, then no transfers work properly 147f7c0b143SDinh Nguyen * for EP0, and the system will fail basic enumeration. As no cause for this 148f7c0b143SDinh Nguyen * has currently been found, we cannot support any large IN transfers for 149f7c0b143SDinh Nguyen * EP0. 150f7c0b143SDinh Nguyen */ 151f7c0b143SDinh Nguyen #define EP0_MPS_LIMIT 64 152f7c0b143SDinh Nguyen 153941fcce4SDinh Nguyen struct dwc2_hsotg; 1541f91b4ccSFelipe Balbi struct dwc2_hsotg_req; 155f7c0b143SDinh Nguyen 156f7c0b143SDinh Nguyen /** 1571f91b4ccSFelipe Balbi * struct dwc2_hsotg_ep - driver endpoint definition. 158f7c0b143SDinh Nguyen * @ep: The gadget layer representation of the endpoint. 159f7c0b143SDinh Nguyen * @name: The driver generated name for the endpoint. 160f7c0b143SDinh Nguyen * @queue: Queue of requests for this endpoint. 161f7c0b143SDinh Nguyen * @parent: Reference back to the parent device structure. 162f7c0b143SDinh Nguyen * @req: The current request that the endpoint is processing. This is 163f7c0b143SDinh Nguyen * used to indicate an request has been loaded onto the endpoint 164f7c0b143SDinh Nguyen * and has yet to be completed (maybe due to data move, or simply 165f7c0b143SDinh Nguyen * awaiting an ack from the core all the data has been completed). 166f7c0b143SDinh Nguyen * @debugfs: File entry for debugfs file for this endpoint. 167f7c0b143SDinh Nguyen * @lock: State lock to protect contents of endpoint. 168f7c0b143SDinh Nguyen * @dir_in: Set to true if this endpoint is of the IN direction, which 169f7c0b143SDinh Nguyen * means that it is sending data to the Host. 170f7c0b143SDinh Nguyen * @index: The index for the endpoint registers. 171f7c0b143SDinh Nguyen * @mc: Multi Count - number of transactions per microframe 172142bd33fSVardan Mikayelyan * @interval - Interval for periodic endpoints, in frames or microframes. 173f7c0b143SDinh Nguyen * @name: The name array passed to the USB core. 174f7c0b143SDinh Nguyen * @halted: Set if the endpoint has been halted. 175f7c0b143SDinh Nguyen * @periodic: Set if this is a periodic ep, such as Interrupt 176f7c0b143SDinh Nguyen * @isochronous: Set if this is a isochronous ep 1778a20fa45SMian Yousaf Kaukab * @send_zlp: Set if we need to send a zero-length packet. 1785f54c54bSVahram Aharonyan * @desc_list_dma: The DMA address of descriptor chain currently in use. 1795f54c54bSVahram Aharonyan * @desc_list: Pointer to descriptor DMA chain head currently in use. 1805f54c54bSVahram Aharonyan * @desc_count: Count of entries within the DMA descriptor chain of EP. 181ab7d2192SVahram Aharonyan * @isoc_chain_num: Number of ISOC chain currently in use - either 0 or 1. 182ab7d2192SVahram Aharonyan * @next_desc: index of next free descriptor in the ISOC chain under SW control. 183f7c0b143SDinh Nguyen * @total_data: The total number of data bytes done. 184f7c0b143SDinh Nguyen * @fifo_size: The size of the FIFO (for periodic IN endpoints) 185f7c0b143SDinh Nguyen * @fifo_load: The amount of data loaded into the FIFO (periodic IN) 186f7c0b143SDinh Nguyen * @last_load: The offset of data for the last start of request. 187f7c0b143SDinh Nguyen * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN 18892d1635dSVardan Mikayelyan * @target_frame: Targeted frame num to setup next ISOC transfer 18992d1635dSVardan Mikayelyan * @frame_overrun: Indicates SOF number overrun in DSTS 190f7c0b143SDinh Nguyen * 191f7c0b143SDinh Nguyen * This is the driver's state for each registered enpoint, allowing it 192f7c0b143SDinh Nguyen * to keep track of transactions that need doing. Each endpoint has a 193f7c0b143SDinh Nguyen * lock to protect the state, to try and avoid using an overall lock 194f7c0b143SDinh Nguyen * for the host controller as much as possible. 195f7c0b143SDinh Nguyen * 196f7c0b143SDinh Nguyen * For periodic IN endpoints, we have fifo_size and fifo_load to try 197f7c0b143SDinh Nguyen * and keep track of the amount of data in the periodic FIFO for each 198f7c0b143SDinh Nguyen * of these as we don't have a status register that tells us how much 199f7c0b143SDinh Nguyen * is in each of them. (note, this may actually be useless information 200f7c0b143SDinh Nguyen * as in shared-fifo mode periodic in acts like a single-frame packet 201f7c0b143SDinh Nguyen * buffer than a fifo) 202f7c0b143SDinh Nguyen */ 2031f91b4ccSFelipe Balbi struct dwc2_hsotg_ep { 204f7c0b143SDinh Nguyen struct usb_ep ep; 205f7c0b143SDinh Nguyen struct list_head queue; 206941fcce4SDinh Nguyen struct dwc2_hsotg *parent; 2071f91b4ccSFelipe Balbi struct dwc2_hsotg_req *req; 208f7c0b143SDinh Nguyen struct dentry *debugfs; 209f7c0b143SDinh Nguyen 210f7c0b143SDinh Nguyen unsigned long total_data; 211f7c0b143SDinh Nguyen unsigned int size_loaded; 212f7c0b143SDinh Nguyen unsigned int last_load; 213f7c0b143SDinh Nguyen unsigned int fifo_load; 214f7c0b143SDinh Nguyen unsigned short fifo_size; 215b203d0a2SRobert Baldyga unsigned short fifo_index; 216f7c0b143SDinh Nguyen 217f7c0b143SDinh Nguyen unsigned char dir_in; 218f7c0b143SDinh Nguyen unsigned char index; 219f7c0b143SDinh Nguyen unsigned char mc; 22012814a3fSGrigor Tovmasyan u16 interval; 221f7c0b143SDinh Nguyen 222f7c0b143SDinh Nguyen unsigned int halted:1; 223f7c0b143SDinh Nguyen unsigned int periodic:1; 224f7c0b143SDinh Nguyen unsigned int isochronous:1; 2258a20fa45SMian Yousaf Kaukab unsigned int send_zlp:1; 22692d1635dSVardan Mikayelyan unsigned int target_frame; 22792d1635dSVardan Mikayelyan #define TARGET_FRAME_INITIAL 0xFFFFFFFF 22892d1635dSVardan Mikayelyan bool frame_overrun; 229f7c0b143SDinh Nguyen 2305f54c54bSVahram Aharonyan dma_addr_t desc_list_dma; 2315f54c54bSVahram Aharonyan struct dwc2_dma_desc *desc_list; 2325f54c54bSVahram Aharonyan u8 desc_count; 2335f54c54bSVahram Aharonyan 234ab7d2192SVahram Aharonyan unsigned char isoc_chain_num; 235ab7d2192SVahram Aharonyan unsigned int next_desc; 236ab7d2192SVahram Aharonyan 237f7c0b143SDinh Nguyen char name[10]; 238f7c0b143SDinh Nguyen }; 239f7c0b143SDinh Nguyen 240f7c0b143SDinh Nguyen /** 2411f91b4ccSFelipe Balbi * struct dwc2_hsotg_req - data transfer request 242f7c0b143SDinh Nguyen * @req: The USB gadget request 243f7c0b143SDinh Nguyen * @queue: The list of requests for the endpoint this is queued for. 2447d24c1b5SMian Yousaf Kaukab * @saved_req_buf: variable to save req.buf when bounce buffers are used. 245f7c0b143SDinh Nguyen */ 2461f91b4ccSFelipe Balbi struct dwc2_hsotg_req { 247f7c0b143SDinh Nguyen struct usb_request req; 248f7c0b143SDinh Nguyen struct list_head queue; 2497d24c1b5SMian Yousaf Kaukab void *saved_req_buf; 250f7c0b143SDinh Nguyen }; 251f7c0b143SDinh Nguyen 252b98866c2SJohn Youn #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 253b98866c2SJohn Youn IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 254f7c0b143SDinh Nguyen #define call_gadget(_hs, _entry) \ 255f7c0b143SDinh Nguyen do { \ 256f7c0b143SDinh Nguyen if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ 257f7c0b143SDinh Nguyen (_hs)->driver && (_hs)->driver->_entry) { \ 258f7c0b143SDinh Nguyen spin_unlock(&_hs->lock); \ 259f7c0b143SDinh Nguyen (_hs)->driver->_entry(&(_hs)->gadget); \ 260f7c0b143SDinh Nguyen spin_lock(&_hs->lock); \ 261f7c0b143SDinh Nguyen } \ 262f7c0b143SDinh Nguyen } while (0) 263941fcce4SDinh Nguyen #else 264941fcce4SDinh Nguyen #define call_gadget(_hs, _entry) do {} while (0) 265941fcce4SDinh Nguyen #endif 266f7c0b143SDinh Nguyen 267197ba5f4SPaul Zimmerman struct dwc2_hsotg; 268197ba5f4SPaul Zimmerman struct dwc2_host_chan; 269197ba5f4SPaul Zimmerman 270197ba5f4SPaul Zimmerman /* Device States */ 271197ba5f4SPaul Zimmerman enum dwc2_lx_state { 272197ba5f4SPaul Zimmerman DWC2_L0, /* On state */ 273197ba5f4SPaul Zimmerman DWC2_L1, /* LPM sleep state */ 274197ba5f4SPaul Zimmerman DWC2_L2, /* USB suspend state */ 275197ba5f4SPaul Zimmerman DWC2_L3, /* Off state */ 276197ba5f4SPaul Zimmerman }; 277197ba5f4SPaul Zimmerman 278fe0b94abSMian Yousaf Kaukab /* Gadget ep0 states */ 279fe0b94abSMian Yousaf Kaukab enum dwc2_ep0_state { 280fe0b94abSMian Yousaf Kaukab DWC2_EP0_SETUP, 281fe0b94abSMian Yousaf Kaukab DWC2_EP0_DATA_IN, 282fe0b94abSMian Yousaf Kaukab DWC2_EP0_DATA_OUT, 283fe0b94abSMian Yousaf Kaukab DWC2_EP0_STATUS_IN, 284fe0b94abSMian Yousaf Kaukab DWC2_EP0_STATUS_OUT, 285fe0b94abSMian Yousaf Kaukab }; 286fe0b94abSMian Yousaf Kaukab 287197ba5f4SPaul Zimmerman /** 288197ba5f4SPaul Zimmerman * struct dwc2_core_params - Parameters for configuring the core 289197ba5f4SPaul Zimmerman * 290197ba5f4SPaul Zimmerman * @otg_cap: Specifies the OTG capabilities. 291197ba5f4SPaul Zimmerman * 0 - HNP and SRP capable 292197ba5f4SPaul Zimmerman * 1 - SRP Only capable 293197ba5f4SPaul Zimmerman * 2 - No HNP/SRP capable (always available) 294197ba5f4SPaul Zimmerman * Defaults to best available option (0, 1, then 2) 295e7839f99SJohn Youn * @host_dma: Specifies whether to use slave or DMA mode for accessing 296197ba5f4SPaul Zimmerman * the data FIFOs. The driver will automatically detect the 297197ba5f4SPaul Zimmerman * value for this parameter if none is specified. 298197ba5f4SPaul Zimmerman * 0 - Slave (always available) 299197ba5f4SPaul Zimmerman * 1 - DMA (default, if available) 300197ba5f4SPaul Zimmerman * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 301197ba5f4SPaul Zimmerman * address DMA mode or descriptor DMA mode for accessing 302197ba5f4SPaul Zimmerman * the data FIFOs. The driver will automatically detect the 303197ba5f4SPaul Zimmerman * value for this if none is specified. 304197ba5f4SPaul Zimmerman * 0 - Address DMA 305197ba5f4SPaul Zimmerman * 1 - Descriptor DMA (default, if available) 306fbb9e22bSMian Yousaf Kaukab * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use 307fbb9e22bSMian Yousaf Kaukab * address DMA mode or descriptor DMA mode for accessing 308fbb9e22bSMian Yousaf Kaukab * the data FIFOs in Full Speed mode only. The driver 309fbb9e22bSMian Yousaf Kaukab * will automatically detect the value for this if none is 310fbb9e22bSMian Yousaf Kaukab * specified. 311fbb9e22bSMian Yousaf Kaukab * 0 - Address DMA 312fbb9e22bSMian Yousaf Kaukab * 1 - Descriptor DMA in FS (default, if available) 313197ba5f4SPaul Zimmerman * @speed: Specifies the maximum speed of operation in host and 314197ba5f4SPaul Zimmerman * device mode. The actual speed depends on the speed of 315197ba5f4SPaul Zimmerman * the attached device and the value of phy_type. 316197ba5f4SPaul Zimmerman * 0 - High Speed 317197ba5f4SPaul Zimmerman * (default when phy_type is UTMI+ or ULPI) 318197ba5f4SPaul Zimmerman * 1 - Full Speed 319197ba5f4SPaul Zimmerman * (default when phy_type is Full Speed) 320197ba5f4SPaul Zimmerman * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 321197ba5f4SPaul Zimmerman * 1 - Allow dynamic FIFO sizing (default, if available) 322197ba5f4SPaul Zimmerman * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 323c1d286cfSJohn Youn * are enabled for non-periodic IN endpoints in device 324c1d286cfSJohn Youn * mode. 325197ba5f4SPaul Zimmerman * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 326197ba5f4SPaul Zimmerman * dynamic FIFO sizing is enabled 327197ba5f4SPaul Zimmerman * 16 to 32768 328197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 329197ba5f4SPaul Zimmerman * the default. 330197ba5f4SPaul Zimmerman * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 331197ba5f4SPaul Zimmerman * in host mode when dynamic FIFO sizing is enabled 332197ba5f4SPaul Zimmerman * 16 to 32768 333197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 334197ba5f4SPaul Zimmerman * the default. 335197ba5f4SPaul Zimmerman * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 336197ba5f4SPaul Zimmerman * host mode when dynamic FIFO sizing is enabled 337197ba5f4SPaul Zimmerman * 16 to 32768 338197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 339197ba5f4SPaul Zimmerman * the default. 340197ba5f4SPaul Zimmerman * @max_transfer_size: The maximum transfer size supported, in bytes 341197ba5f4SPaul Zimmerman * 2047 to 65,535 342197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 343197ba5f4SPaul Zimmerman * the default. 344197ba5f4SPaul Zimmerman * @max_packet_count: The maximum number of packets in a transfer 345197ba5f4SPaul Zimmerman * 15 to 511 346197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 347197ba5f4SPaul Zimmerman * the default. 348197ba5f4SPaul Zimmerman * @host_channels: The number of host channel registers to use 349197ba5f4SPaul Zimmerman * 1 to 16 350197ba5f4SPaul Zimmerman * Actual maximum value is autodetected and also 351197ba5f4SPaul Zimmerman * the default. 352197ba5f4SPaul Zimmerman * @phy_type: Specifies the type of PHY interface to use. By default, 353197ba5f4SPaul Zimmerman * the driver will automatically detect the phy_type. 354197ba5f4SPaul Zimmerman * 0 - Full Speed Phy 355197ba5f4SPaul Zimmerman * 1 - UTMI+ Phy 356197ba5f4SPaul Zimmerman * 2 - ULPI Phy 357197ba5f4SPaul Zimmerman * Defaults to best available option (2, 1, then 0) 358197ba5f4SPaul Zimmerman * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 359197ba5f4SPaul Zimmerman * is applicable for a phy_type of UTMI+ or ULPI. (For a 360197ba5f4SPaul Zimmerman * ULPI phy_type, this parameter indicates the data width 361197ba5f4SPaul Zimmerman * between the MAC and the ULPI Wrapper.) Also, this 362197ba5f4SPaul Zimmerman * parameter is applicable only if the OTG_HSPHY_WIDTH cC 363197ba5f4SPaul Zimmerman * parameter was set to "8 and 16 bits", meaning that the 364197ba5f4SPaul Zimmerman * core has been configured to work at either data path 365197ba5f4SPaul Zimmerman * width. 366197ba5f4SPaul Zimmerman * 8 or 16 (default 16 if available) 367197ba5f4SPaul Zimmerman * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 368197ba5f4SPaul Zimmerman * data rate. This parameter is only applicable if phy_type 369197ba5f4SPaul Zimmerman * is ULPI. 370197ba5f4SPaul Zimmerman * 0 - single data rate ULPI interface with 8 bit wide 371197ba5f4SPaul Zimmerman * data bus (default) 372197ba5f4SPaul Zimmerman * 1 - double data rate ULPI interface with 4 bit wide 373197ba5f4SPaul Zimmerman * data bus 374197ba5f4SPaul Zimmerman * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 375197ba5f4SPaul Zimmerman * external supply to drive the VBus 376197ba5f4SPaul Zimmerman * 0 - Internal supply (default) 377197ba5f4SPaul Zimmerman * 1 - External supply 378197ba5f4SPaul Zimmerman * @i2c_enable: Specifies whether to use the I2Cinterface for a full 379197ba5f4SPaul Zimmerman * speed PHY. This parameter is only applicable if phy_type 380197ba5f4SPaul Zimmerman * is FS. 381197ba5f4SPaul Zimmerman * 0 - No (default) 382197ba5f4SPaul Zimmerman * 1 - Yes 383197ba5f4SPaul Zimmerman * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 384197ba5f4SPaul Zimmerman * 0 - No (default) 385197ba5f4SPaul Zimmerman * 1 - Yes 386197ba5f4SPaul Zimmerman * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 387197ba5f4SPaul Zimmerman * when attached to a Full Speed or Low Speed device in 388197ba5f4SPaul Zimmerman * host mode. 389197ba5f4SPaul Zimmerman * 0 - Don't support low power mode (default) 390197ba5f4SPaul Zimmerman * 1 - Support low power mode 391197ba5f4SPaul Zimmerman * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 392197ba5f4SPaul Zimmerman * when connected to a Low Speed device in host 393197ba5f4SPaul Zimmerman * mode. This parameter is applicable only if 394197ba5f4SPaul Zimmerman * host_support_fs_ls_low_power is enabled. 395197ba5f4SPaul Zimmerman * 0 - 48 MHz 396197ba5f4SPaul Zimmerman * (default when phy_type is UTMI+ or ULPI) 397197ba5f4SPaul Zimmerman * 1 - 6 MHz 398197ba5f4SPaul Zimmerman * (default when phy_type is Full Speed) 399b11633c4SDinh Nguyen * @oc_disable: Flag to disable overcurrent condition. 400b11633c4SDinh Nguyen * 0 - Allow overcurrent condition to get detected 401b11633c4SDinh Nguyen * 1 - Disable overcurrent condtion to get detected 402197ba5f4SPaul Zimmerman * @ts_dline: Enable Term Select Dline pulsing 403197ba5f4SPaul Zimmerman * 0 - No (default) 404197ba5f4SPaul Zimmerman * 1 - Yes 405197ba5f4SPaul Zimmerman * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 406197ba5f4SPaul Zimmerman * 0 - No (default for core < 2.92a) 407197ba5f4SPaul Zimmerman * 1 - Yes (default for core >= 2.92a) 408197ba5f4SPaul Zimmerman * @ahbcfg: This field allows the default value of the GAHBCFG 409197ba5f4SPaul Zimmerman * register to be overridden 410197ba5f4SPaul Zimmerman * -1 - GAHBCFG value will be set to 0x06 4111b52d2faSRazmik Karapetyan * (INCR, default) 412197ba5f4SPaul Zimmerman * all others - GAHBCFG value will be overridden with 413197ba5f4SPaul Zimmerman * this value 414197ba5f4SPaul Zimmerman * Not all bits can be controlled like this, the 415197ba5f4SPaul Zimmerman * bits defined by GAHBCFG_CTRL_MASK are controlled 416197ba5f4SPaul Zimmerman * by the driver and are ignored in this 417197ba5f4SPaul Zimmerman * configuration value. 418197ba5f4SPaul Zimmerman * @uframe_sched: True to enable the microframe scheduler 419a6d249d8SGregory Herrero * @external_id_pin_ctl: Specifies whether ID pin is handled externally. 420a6d249d8SGregory Herrero * Disable CONIDSTSCHNG controller interrupt in such 421a6d249d8SGregory Herrero * case. 422a6d249d8SGregory Herrero * 0 - No (default) 423a6d249d8SGregory Herrero * 1 - Yes 42441ba9b9bSVardan Mikayelyan * @power_down: Specifies whether the controller support power_down. 42541ba9b9bSVardan Mikayelyan * If power_down is enabled, the controller will enter 42641ba9b9bSVardan Mikayelyan * power_down in both peripheral and host mode when 427285046aaSGregory Herrero * needed. 428285046aaSGregory Herrero * 0 - No (default) 429631a2310SVardan Mikayelyan * 1 - Partial power down 430631a2310SVardan Mikayelyan * 2 - Hibernation 4316f80b6deSSevak Arakelyan * @lpm: Enable LPM support. 4326f80b6deSSevak Arakelyan * 0 - No 4336f80b6deSSevak Arakelyan * 1 - Yes 4346f80b6deSSevak Arakelyan * @lpm_clock_gating: Enable core PHY clock gating. 4356f80b6deSSevak Arakelyan * 0 - No 4366f80b6deSSevak Arakelyan * 1 - Yes 4376f80b6deSSevak Arakelyan * @besl: Enable LPM Errata support. 4386f80b6deSSevak Arakelyan * 0 - No 4396f80b6deSSevak Arakelyan * 1 - Yes 4406f80b6deSSevak Arakelyan * @hird_threshold_en: HIRD or HIRD Threshold enable. 4416f80b6deSSevak Arakelyan * 0 - No 4426f80b6deSSevak Arakelyan * 1 - Yes 4436f80b6deSSevak Arakelyan * @hird_threshold: Value of BESL or HIRD Threshold. 444e35b1350SBruno Herrera * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO 445e35b1350SBruno Herrera * register. 446e35b1350SBruno Herrera * 0 - Deactivate the transceiver (default) 447e35b1350SBruno Herrera * 1 - Activate the transceiver 4489962b62fSJohn Youn * @g_dma: Enables gadget dma usage (default: autodetect). 449dec4b556SVahram Aharonyan * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect). 45005ee799fSJohn Youn * @g_rx_fifo_size: The periodic rx fifo size for the device, in 45105ee799fSJohn Youn * DWORDS from 16-32768 (default: 2048 if 45205ee799fSJohn Youn * possible, otherwise autodetect). 45305ee799fSJohn Youn * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in 45405ee799fSJohn Youn * DWORDS from 16-32768 (default: 1024 if 45505ee799fSJohn Youn * possible, otherwise autodetect). 45605ee799fSJohn Youn * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo 45705ee799fSJohn Youn * mode. Each value corresponds to one EP 45805ee799fSJohn Youn * starting from EP1 (max 15 values). Sizes are 45905ee799fSJohn Youn * in DWORDS with possible values from from 46005ee799fSJohn Youn * 16-32768 (default: 256, 256, 256, 256, 768, 46105ee799fSJohn Youn * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0). 462ca8b0332SChen Yu * @change_speed_quirk: Change speed configuration to DWC2_SPEED_PARAM_FULL 463ca8b0332SChen Yu * while full&low speed device connect. And change speed 464ca8b0332SChen Yu * back to DWC2_SPEED_PARAM_HIGH while device is gone. 465ca8b0332SChen Yu * 0 - No (default) 466ca8b0332SChen Yu * 1 - Yes 467197ba5f4SPaul Zimmerman * 468197ba5f4SPaul Zimmerman * The following parameters may be specified when starting the module. These 469197ba5f4SPaul Zimmerman * parameters define how the DWC_otg controller should be configured. A 470197ba5f4SPaul Zimmerman * value of -1 (or any other out of range value) for any parameter means 471197ba5f4SPaul Zimmerman * to read the value from hardware (if possible) or use the builtin 472197ba5f4SPaul Zimmerman * default described above. 473197ba5f4SPaul Zimmerman */ 474197ba5f4SPaul Zimmerman struct dwc2_core_params { 475d21bcc3fSJohn Youn u8 otg_cap; 476c1d286cfSJohn Youn #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 477c1d286cfSJohn Youn #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 478c1d286cfSJohn Youn #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 479c1d286cfSJohn Youn 480d21bcc3fSJohn Youn u8 phy_type; 481c1d286cfSJohn Youn #define DWC2_PHY_TYPE_PARAM_FS 0 482c1d286cfSJohn Youn #define DWC2_PHY_TYPE_PARAM_UTMI 1 483c1d286cfSJohn Youn #define DWC2_PHY_TYPE_PARAM_ULPI 2 484c1d286cfSJohn Youn 48557b8e235SJohn Youn u8 speed; 48657b8e235SJohn Youn #define DWC2_SPEED_PARAM_HIGH 0 48757b8e235SJohn Youn #define DWC2_SPEED_PARAM_FULL 1 48857b8e235SJohn Youn #define DWC2_SPEED_PARAM_LOW 2 48957b8e235SJohn Youn 490d21bcc3fSJohn Youn u8 phy_utmi_width; 491d21bcc3fSJohn Youn bool phy_ulpi_ddr; 492d21bcc3fSJohn Youn bool phy_ulpi_ext_vbus; 49357b8e235SJohn Youn bool enable_dynamic_fifo; 49457b8e235SJohn Youn bool en_multiple_tx_fifo; 495d21bcc3fSJohn Youn bool i2c_enable; 49666e77a24SRazmik Karapetyan bool acg_enable; 497d21bcc3fSJohn Youn bool ulpi_fs_ls; 49857b8e235SJohn Youn bool ts_dline; 49957b8e235SJohn Youn bool reload_ctl; 50057b8e235SJohn Youn bool uframe_sched; 50157b8e235SJohn Youn bool external_id_pin_ctl; 502631a2310SVardan Mikayelyan 503631a2310SVardan Mikayelyan int power_down; 504631a2310SVardan Mikayelyan #define DWC2_POWER_DOWN_PARAM_NONE 0 505631a2310SVardan Mikayelyan #define DWC2_POWER_DOWN_PARAM_PARTIAL 1 506631a2310SVardan Mikayelyan #define DWC2_POWER_DOWN_PARAM_HIBERNATION 2 507631a2310SVardan Mikayelyan 5086f80b6deSSevak Arakelyan bool lpm; 5096f80b6deSSevak Arakelyan bool lpm_clock_gating; 5106f80b6deSSevak Arakelyan bool besl; 5116f80b6deSSevak Arakelyan bool hird_threshold_en; 5126f80b6deSSevak Arakelyan u8 hird_threshold; 513e35b1350SBruno Herrera bool activate_stm_fs_transceiver; 51457b8e235SJohn Youn u16 max_packet_count; 51557b8e235SJohn Youn u32 max_transfer_size; 51657b8e235SJohn Youn u32 ahbcfg; 51757b8e235SJohn Youn 51857b8e235SJohn Youn /* Host parameters */ 51957b8e235SJohn Youn bool host_dma; 52057b8e235SJohn Youn bool dma_desc_enable; 52157b8e235SJohn Youn bool dma_desc_fs_enable; 522d21bcc3fSJohn Youn bool host_support_fs_ls_low_power; 523d21bcc3fSJohn Youn bool host_ls_low_power_phy_clk; 524b11633c4SDinh Nguyen bool oc_disable; 525c1d286cfSJohn Youn 52657b8e235SJohn Youn u8 host_channels; 52757b8e235SJohn Youn u16 host_rx_fifo_size; 52857b8e235SJohn Youn u16 host_nperio_tx_fifo_size; 52957b8e235SJohn Youn u16 host_perio_tx_fifo_size; 5306b66ce51SJohn Youn 5316b66ce51SJohn Youn /* Gadget parameters */ 53205ee799fSJohn Youn bool g_dma; 533dec4b556SVahram Aharonyan bool g_dma_desc; 53400c704ccSLeo Yan u32 g_rx_fifo_size; 53500c704ccSLeo Yan u32 g_np_tx_fifo_size; 53605ee799fSJohn Youn u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; 537ca8b0332SChen Yu 538ca8b0332SChen Yu bool change_speed_quirk; 539197ba5f4SPaul Zimmerman }; 540197ba5f4SPaul Zimmerman 541197ba5f4SPaul Zimmerman /** 542197ba5f4SPaul Zimmerman * struct dwc2_hw_params - Autodetected parameters. 543197ba5f4SPaul Zimmerman * 544197ba5f4SPaul Zimmerman * These parameters are the various parameters read from hardware 545197ba5f4SPaul Zimmerman * registers during initialization. They typically contain the best 546197ba5f4SPaul Zimmerman * supported or maximum value that can be configured in the 547197ba5f4SPaul Zimmerman * corresponding dwc2_core_params value. 548197ba5f4SPaul Zimmerman * 549197ba5f4SPaul Zimmerman * The values that are not in dwc2_core_params are documented below. 550197ba5f4SPaul Zimmerman * 551197ba5f4SPaul Zimmerman * @op_mode Mode of Operation 552197ba5f4SPaul Zimmerman * 0 - HNP- and SRP-Capable OTG (Host & Device) 553197ba5f4SPaul Zimmerman * 1 - SRP-Capable OTG (Host & Device) 554197ba5f4SPaul Zimmerman * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 555197ba5f4SPaul Zimmerman * 3 - SRP-Capable Device 556197ba5f4SPaul Zimmerman * 4 - Non-OTG Device 557197ba5f4SPaul Zimmerman * 5 - SRP-Capable Host 558197ba5f4SPaul Zimmerman * 6 - Non-OTG Host 559197ba5f4SPaul Zimmerman * @arch Architecture 560197ba5f4SPaul Zimmerman * 0 - Slave only 561197ba5f4SPaul Zimmerman * 1 - External DMA 562197ba5f4SPaul Zimmerman * 2 - Internal DMA 563197ba5f4SPaul Zimmerman * @power_optimized Are power optimizations enabled? 564197ba5f4SPaul Zimmerman * @num_dev_ep Number of device endpoints available 5659273083aSMinas Harutyunyan * @num_dev_in_eps Number of device IN endpoints available 566197ba5f4SPaul Zimmerman * @num_dev_perio_in_ep Number of device periodic IN endpoints 567997f4f81SMickael Maison * available 568197ba5f4SPaul Zimmerman * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue 569197ba5f4SPaul Zimmerman * Depth 570197ba5f4SPaul Zimmerman * 0 to 30 571197ba5f4SPaul Zimmerman * @host_perio_tx_q_depth 572197ba5f4SPaul Zimmerman * Host Mode Periodic Request Queue Depth 573197ba5f4SPaul Zimmerman * 2, 4 or 8 574197ba5f4SPaul Zimmerman * @nperio_tx_q_depth 575197ba5f4SPaul Zimmerman * Non-Periodic Request Queue Depth 576197ba5f4SPaul Zimmerman * 2, 4 or 8 577197ba5f4SPaul Zimmerman * @hs_phy_type High-speed PHY interface type 578197ba5f4SPaul Zimmerman * 0 - High-speed interface not supported 579197ba5f4SPaul Zimmerman * 1 - UTMI+ 580197ba5f4SPaul Zimmerman * 2 - ULPI 581197ba5f4SPaul Zimmerman * 3 - UTMI+ and ULPI 582197ba5f4SPaul Zimmerman * @fs_phy_type Full-speed PHY interface type 583197ba5f4SPaul Zimmerman * 0 - Full speed interface not supported 584197ba5f4SPaul Zimmerman * 1 - Dedicated full speed interface 585197ba5f4SPaul Zimmerman * 2 - FS pins shared with UTMI+ pins 586197ba5f4SPaul Zimmerman * 3 - FS pins shared with ULPI pins 587197ba5f4SPaul Zimmerman * @total_fifo_size: Total internal RAM for FIFOs (bytes) 588631a2310SVardan Mikayelyan * @hibernation Is hibernation enabled? 589197ba5f4SPaul Zimmerman * @utmi_phy_data_width UTMI+ PHY data width 590197ba5f4SPaul Zimmerman * 0 - 8 bits 591197ba5f4SPaul Zimmerman * 1 - 16 bits 592197ba5f4SPaul Zimmerman * 2 - 8 or 16 bits 593197ba5f4SPaul Zimmerman * @snpsid: Value from SNPSID register 59455e1040eSJohn Youn * @dev_ep_dirs: Direction of device endpoints (GHWCFG1) 5959273083aSMinas Harutyunyan * @g_tx_fifo_size[] Power-on values of TxFIFO sizes 596197ba5f4SPaul Zimmerman */ 597197ba5f4SPaul Zimmerman struct dwc2_hw_params { 598197ba5f4SPaul Zimmerman unsigned op_mode:3; 599197ba5f4SPaul Zimmerman unsigned arch:2; 600197ba5f4SPaul Zimmerman unsigned dma_desc_enable:1; 601197ba5f4SPaul Zimmerman unsigned enable_dynamic_fifo:1; 602197ba5f4SPaul Zimmerman unsigned en_multiple_tx_fifo:1; 603d1531319SJohn Youn unsigned rx_fifo_size:16; 604197ba5f4SPaul Zimmerman unsigned host_nperio_tx_fifo_size:16; 60555e1040eSJohn Youn unsigned dev_nperio_tx_fifo_size:16; 606197ba5f4SPaul Zimmerman unsigned host_perio_tx_fifo_size:16; 607197ba5f4SPaul Zimmerman unsigned nperio_tx_q_depth:3; 608197ba5f4SPaul Zimmerman unsigned host_perio_tx_q_depth:3; 609197ba5f4SPaul Zimmerman unsigned dev_token_q_depth:5; 610197ba5f4SPaul Zimmerman unsigned max_transfer_size:26; 611197ba5f4SPaul Zimmerman unsigned max_packet_count:11; 612197ba5f4SPaul Zimmerman unsigned host_channels:5; 613197ba5f4SPaul Zimmerman unsigned hs_phy_type:2; 614197ba5f4SPaul Zimmerman unsigned fs_phy_type:2; 615197ba5f4SPaul Zimmerman unsigned i2c_enable:1; 61666e77a24SRazmik Karapetyan unsigned acg_enable:1; 617197ba5f4SPaul Zimmerman unsigned num_dev_ep:4; 6189273083aSMinas Harutyunyan unsigned num_dev_in_eps : 4; 619197ba5f4SPaul Zimmerman unsigned num_dev_perio_in_ep:4; 620197ba5f4SPaul Zimmerman unsigned total_fifo_size:16; 621197ba5f4SPaul Zimmerman unsigned power_optimized:1; 622631a2310SVardan Mikayelyan unsigned hibernation:1; 623197ba5f4SPaul Zimmerman unsigned utmi_phy_data_width:2; 6246f80b6deSSevak Arakelyan unsigned lpm_mode:1; 625197ba5f4SPaul Zimmerman u32 snpsid; 62655e1040eSJohn Youn u32 dev_ep_dirs; 6279273083aSMinas Harutyunyan u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; 628197ba5f4SPaul Zimmerman }; 629197ba5f4SPaul Zimmerman 6303f95001dSMian Yousaf Kaukab /* Size of control and EP0 buffers */ 6313f95001dSMian Yousaf Kaukab #define DWC2_CTRL_BUFF_SIZE 8 6323f95001dSMian Yousaf Kaukab 633197ba5f4SPaul Zimmerman /** 63438beaec6SJohn Youn * struct dwc2_gregs_backup - Holds global registers state before 63538beaec6SJohn Youn * entering partial power down 636d17ee77bSGregory Herrero * @gotgctl: Backup of GOTGCTL register 637d17ee77bSGregory Herrero * @gintmsk: Backup of GINTMSK register 638d17ee77bSGregory Herrero * @gahbcfg: Backup of GAHBCFG register 639d17ee77bSGregory Herrero * @gusbcfg: Backup of GUSBCFG register 640d17ee77bSGregory Herrero * @grxfsiz: Backup of GRXFSIZ register 641d17ee77bSGregory Herrero * @gnptxfsiz: Backup of GNPTXFSIZ register 642d17ee77bSGregory Herrero * @gi2cctl: Backup of GI2CCTL register 64366a36096SVardan Mikayelyan * @glpmcfg: Backup of GLPMCFG register 644d17ee77bSGregory Herrero * @gdfifocfg: Backup of GDFIFOCFG register 645d17ee77bSGregory Herrero * @gpwrdn: Backup of GPWRDN register 646d17ee77bSGregory Herrero */ 647d17ee77bSGregory Herrero struct dwc2_gregs_backup { 648d17ee77bSGregory Herrero u32 gotgctl; 649d17ee77bSGregory Herrero u32 gintmsk; 650d17ee77bSGregory Herrero u32 gahbcfg; 651d17ee77bSGregory Herrero u32 gusbcfg; 652d17ee77bSGregory Herrero u32 grxfsiz; 653d17ee77bSGregory Herrero u32 gnptxfsiz; 654d17ee77bSGregory Herrero u32 gi2cctl; 65566a36096SVardan Mikayelyan u32 glpmcfg; 656d17ee77bSGregory Herrero u32 pcgcctl; 657600a490eSRazmik Karapetyan u32 pcgcctl1; 658d17ee77bSGregory Herrero u32 gdfifocfg; 659d17ee77bSGregory Herrero u32 gpwrdn; 660cc1e204cSMian Yousaf Kaukab bool valid; 661d17ee77bSGregory Herrero }; 662d17ee77bSGregory Herrero 663d17ee77bSGregory Herrero /** 66438beaec6SJohn Youn * struct dwc2_dregs_backup - Holds device registers state before 66538beaec6SJohn Youn * entering partial power down 666d17ee77bSGregory Herrero * @dcfg: Backup of DCFG register 667d17ee77bSGregory Herrero * @dctl: Backup of DCTL register 668d17ee77bSGregory Herrero * @daintmsk: Backup of DAINTMSK register 669d17ee77bSGregory Herrero * @diepmsk: Backup of DIEPMSK register 670d17ee77bSGregory Herrero * @doepmsk: Backup of DOEPMSK register 671d17ee77bSGregory Herrero * @diepctl: Backup of DIEPCTL register 672d17ee77bSGregory Herrero * @dieptsiz: Backup of DIEPTSIZ register 673d17ee77bSGregory Herrero * @diepdma: Backup of DIEPDMA register 674d17ee77bSGregory Herrero * @doepctl: Backup of DOEPCTL register 675d17ee77bSGregory Herrero * @doeptsiz: Backup of DOEPTSIZ register 676d17ee77bSGregory Herrero * @doepdma: Backup of DOEPDMA register 677af7c2bd3SVardan Mikayelyan * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 678d17ee77bSGregory Herrero */ 679d17ee77bSGregory Herrero struct dwc2_dregs_backup { 680d17ee77bSGregory Herrero u32 dcfg; 681d17ee77bSGregory Herrero u32 dctl; 682d17ee77bSGregory Herrero u32 daintmsk; 683d17ee77bSGregory Herrero u32 diepmsk; 684d17ee77bSGregory Herrero u32 doepmsk; 685d17ee77bSGregory Herrero u32 diepctl[MAX_EPS_CHANNELS]; 686d17ee77bSGregory Herrero u32 dieptsiz[MAX_EPS_CHANNELS]; 687d17ee77bSGregory Herrero u32 diepdma[MAX_EPS_CHANNELS]; 688d17ee77bSGregory Herrero u32 doepctl[MAX_EPS_CHANNELS]; 689d17ee77bSGregory Herrero u32 doeptsiz[MAX_EPS_CHANNELS]; 690d17ee77bSGregory Herrero u32 doepdma[MAX_EPS_CHANNELS]; 691af7c2bd3SVardan Mikayelyan u32 dtxfsiz[MAX_EPS_CHANNELS]; 692cc1e204cSMian Yousaf Kaukab bool valid; 693d17ee77bSGregory Herrero }; 694d17ee77bSGregory Herrero 695d17ee77bSGregory Herrero /** 69638beaec6SJohn Youn * struct dwc2_hregs_backup - Holds host registers state before 69738beaec6SJohn Youn * entering partial power down 698d17ee77bSGregory Herrero * @hcfg: Backup of HCFG register 699d17ee77bSGregory Herrero * @haintmsk: Backup of HAINTMSK register 700d17ee77bSGregory Herrero * @hcintmsk: Backup of HCINTMSK register 701d17ee77bSGregory Herrero * @hptr0: Backup of HPTR0 register 702d17ee77bSGregory Herrero * @hfir: Backup of HFIR register 70366a36096SVardan Mikayelyan * @hptxfsiz: Backup of HPTXFSIZ register 704d17ee77bSGregory Herrero */ 705d17ee77bSGregory Herrero struct dwc2_hregs_backup { 706d17ee77bSGregory Herrero u32 hcfg; 707d17ee77bSGregory Herrero u32 haintmsk; 708d17ee77bSGregory Herrero u32 hcintmsk[MAX_EPS_CHANNELS]; 709d17ee77bSGregory Herrero u32 hprt0; 710d17ee77bSGregory Herrero u32 hfir; 71166a36096SVardan Mikayelyan u32 hptxfsiz; 712cc1e204cSMian Yousaf Kaukab bool valid; 713d17ee77bSGregory Herrero }; 714d17ee77bSGregory Herrero 7159f9f09b0SDouglas Anderson /* 7169f9f09b0SDouglas Anderson * Constants related to high speed periodic scheduling 7179f9f09b0SDouglas Anderson * 7189f9f09b0SDouglas Anderson * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a 7199f9f09b0SDouglas Anderson * reservation point of view it's assumed that the schedule goes right back to 7209f9f09b0SDouglas Anderson * the beginning after the end of the schedule. 7219f9f09b0SDouglas Anderson * 7229f9f09b0SDouglas Anderson * What does that mean for scheduling things with a long interval? It means 7239f9f09b0SDouglas Anderson * we'll reserve time for them in every possible microframe that they could 7249f9f09b0SDouglas Anderson * ever be scheduled in. ...but we'll still only actually schedule them as 7259f9f09b0SDouglas Anderson * often as they were requested. 7269f9f09b0SDouglas Anderson * 7279f9f09b0SDouglas Anderson * We keep our schedule in a "bitmap" structure. This simplifies having 7289f9f09b0SDouglas Anderson * to keep track of and merge intervals: we just let the bitmap code do most 7299f9f09b0SDouglas Anderson * of the heavy lifting. In a way scheduling is much like memory allocation. 7309f9f09b0SDouglas Anderson * 7319f9f09b0SDouglas Anderson * We schedule 100us per uframe or 80% of 125us (the maximum amount you're 7329f9f09b0SDouglas Anderson * supposed to schedule for periodic transfers). That's according to spec. 7339f9f09b0SDouglas Anderson * 7349f9f09b0SDouglas Anderson * Note that though we only schedule 80% of each microframe, the bitmap that we 7359f9f09b0SDouglas Anderson * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of 7369f9f09b0SDouglas Anderson * space for each uFrame). 7379f9f09b0SDouglas Anderson * 7389f9f09b0SDouglas Anderson * Requirements: 7399f9f09b0SDouglas Anderson * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1) 7409f9f09b0SDouglas Anderson * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably 7419f9f09b0SDouglas Anderson * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might 7429f9f09b0SDouglas Anderson * be bugs). The 8 comes from the USB spec: number of microframes per frame. 7439f9f09b0SDouglas Anderson */ 7449f9f09b0SDouglas Anderson #define DWC2_US_PER_UFRAME 125 7459f9f09b0SDouglas Anderson #define DWC2_HS_PERIODIC_US_PER_UFRAME 100 7469f9f09b0SDouglas Anderson 7479f9f09b0SDouglas Anderson #define DWC2_HS_SCHEDULE_UFRAMES 8 7489f9f09b0SDouglas Anderson #define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \ 7499f9f09b0SDouglas Anderson DWC2_HS_PERIODIC_US_PER_UFRAME) 7509f9f09b0SDouglas Anderson 7519f9f09b0SDouglas Anderson /* 7529f9f09b0SDouglas Anderson * Constants related to low speed scheduling 7539f9f09b0SDouglas Anderson * 7549f9f09b0SDouglas Anderson * For high speed we schedule every 1us. For low speed that's a bit overkill, 7559f9f09b0SDouglas Anderson * so we make up a unit called a "slice" that's worth 25us. There are 40 7569f9f09b0SDouglas Anderson * slices in a full frame and we can schedule 36 of those (90%) for periodic 7579f9f09b0SDouglas Anderson * transfers. 7589f9f09b0SDouglas Anderson * 7599f9f09b0SDouglas Anderson * Our low speed schedule can be as short as 1 frame or could be longer. When 7609f9f09b0SDouglas Anderson * we only schedule 1 frame it means that we'll need to reserve a time every 7619f9f09b0SDouglas Anderson * frame even for things that only transfer very rarely, so something that runs 7629f9f09b0SDouglas Anderson * every 2048 frames will get time reserved in every frame. Our low speed 7639f9f09b0SDouglas Anderson * schedule can be longer and we'll be able to handle more overlap, but that 7649f9f09b0SDouglas Anderson * will come at increased memory cost and increased time to schedule. 7659f9f09b0SDouglas Anderson * 7669f9f09b0SDouglas Anderson * Note: one other advantage of a short low speed schedule is that if we mess 7679f9f09b0SDouglas Anderson * up and miss scheduling we can jump in and use any of the slots that we 7689f9f09b0SDouglas Anderson * happened to reserve. 7699f9f09b0SDouglas Anderson * 7709f9f09b0SDouglas Anderson * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for 7719f9f09b0SDouglas Anderson * the schedule. There will be one schedule per TT. 7729f9f09b0SDouglas Anderson * 7739f9f09b0SDouglas Anderson * Requirements: 7749f9f09b0SDouglas Anderson * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME. 7759f9f09b0SDouglas Anderson */ 7769f9f09b0SDouglas Anderson #define DWC2_US_PER_SLICE 25 7779f9f09b0SDouglas Anderson #define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE) 7789f9f09b0SDouglas Anderson 7799f9f09b0SDouglas Anderson #define DWC2_ROUND_US_TO_SLICE(us) \ 7809f9f09b0SDouglas Anderson (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \ 7819f9f09b0SDouglas Anderson DWC2_US_PER_SLICE) 7829f9f09b0SDouglas Anderson 7839f9f09b0SDouglas Anderson #define DWC2_LS_PERIODIC_US_PER_FRAME \ 7849f9f09b0SDouglas Anderson 900 7859f9f09b0SDouglas Anderson #define DWC2_LS_PERIODIC_SLICES_PER_FRAME \ 7869f9f09b0SDouglas Anderson (DWC2_LS_PERIODIC_US_PER_FRAME / \ 7879f9f09b0SDouglas Anderson DWC2_US_PER_SLICE) 7889f9f09b0SDouglas Anderson 7899f9f09b0SDouglas Anderson #define DWC2_LS_SCHEDULE_FRAMES 1 7909f9f09b0SDouglas Anderson #define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \ 7919f9f09b0SDouglas Anderson DWC2_LS_PERIODIC_SLICES_PER_FRAME) 7929f9f09b0SDouglas Anderson 793d17ee77bSGregory Herrero /** 794197ba5f4SPaul Zimmerman * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 795197ba5f4SPaul Zimmerman * and periodic schedules 796197ba5f4SPaul Zimmerman * 797941fcce4SDinh Nguyen * These are common for both host and peripheral modes: 798941fcce4SDinh Nguyen * 799197ba5f4SPaul Zimmerman * @dev: The struct device pointer 800197ba5f4SPaul Zimmerman * @regs: Pointer to controller regs 801197ba5f4SPaul Zimmerman * @hw_params: Parameters that were autodetected from the 802197ba5f4SPaul Zimmerman * hardware registers 803941fcce4SDinh Nguyen * @core_params: Parameters that define how the core should be configured 804197ba5f4SPaul Zimmerman * @op_state: The operational State, during transitions (a_host=> 805197ba5f4SPaul Zimmerman * a_peripheral and b_device=>b_host) this may not match 806197ba5f4SPaul Zimmerman * the core, but allows the software to determine 807197ba5f4SPaul Zimmerman * transitions 808c0155b9dSKever Yang * @dr_mode: Requested mode of operation, one of following: 809c0155b9dSKever Yang * - USB_DR_MODE_PERIPHERAL 810c0155b9dSKever Yang * - USB_DR_MODE_HOST 811c0155b9dSKever Yang * - USB_DR_MODE_OTG 81209a75e85SMarek Szyprowski * @hcd_enabled Host mode sub-driver initialization indicator. 81309a75e85SMarek Szyprowski * @gadget_enabled Peripheral mode sub-driver initialization indicator. 81409a75e85SMarek Szyprowski * @ll_hw_enabled Status of low-level hardware resources. 81520fe4409SVardan Mikayelyan * @hibernated: True if core is hibernated 81609a75e85SMarek Szyprowski * @phy: The otg phy transceiver structure for phy control. 81738beaec6SJohn Youn * @uphy: The otg phy transceiver structure for old USB phy 81838beaec6SJohn Youn * control. 81938beaec6SJohn Youn * @plat: The platform specific configuration data. This can be 82038beaec6SJohn Youn * removed once all SoCs support usb transceiver. 82109a75e85SMarek Szyprowski * @supplies: Definition of USB power supplies 82209a75e85SMarek Szyprowski * @phyif: PHY interface width 823941fcce4SDinh Nguyen * @lock: Spinlock that protects all the driver data structures 824941fcce4SDinh Nguyen * @priv: Stores a pointer to the struct usb_hcd 825197ba5f4SPaul Zimmerman * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 826197ba5f4SPaul Zimmerman * transfer are in process of being queued 827197ba5f4SPaul Zimmerman * @srp_success: Stores status of SRP request in the case of a FS PHY 828197ba5f4SPaul Zimmerman * with an I2C interface 829197ba5f4SPaul Zimmerman * @wq_otg: Workqueue object used for handling of some interrupts 830197ba5f4SPaul Zimmerman * @wf_otg: Work object for handling Connector ID Status Change 831197ba5f4SPaul Zimmerman * interrupt 832197ba5f4SPaul Zimmerman * @wkp_timer: Timer object for handling Wakeup Detected interrupt 833197ba5f4SPaul Zimmerman * @lx_state: Lx state of connected device 834d17ee77bSGregory Herrero * @gregs_backup: Backup of global registers during suspend 835d17ee77bSGregory Herrero * @dregs_backup: Backup of device registers during suspend 836d17ee77bSGregory Herrero * @hregs_backup: Backup of host registers during suspend 837941fcce4SDinh Nguyen * 838941fcce4SDinh Nguyen * These are for host mode: 839941fcce4SDinh Nguyen * 840197ba5f4SPaul Zimmerman * @flags: Flags for handling root port state changes 841197ba5f4SPaul Zimmerman * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 842197ba5f4SPaul Zimmerman * Transfers associated with these QHs are not currently 843197ba5f4SPaul Zimmerman * assigned to a host channel. 844197ba5f4SPaul Zimmerman * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 845197ba5f4SPaul Zimmerman * Transfers associated with these QHs are currently 846197ba5f4SPaul Zimmerman * assigned to a host channel. 847197ba5f4SPaul Zimmerman * @non_periodic_qh_ptr: Pointer to next QH to process in the active 848197ba5f4SPaul Zimmerman * non-periodic schedule 849197ba5f4SPaul Zimmerman * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 850197ba5f4SPaul Zimmerman * list of QHs for periodic transfers that are _not_ 851197ba5f4SPaul Zimmerman * scheduled for the next frame. Each QH in the list has an 852197ba5f4SPaul Zimmerman * interval counter that determines when it needs to be 853197ba5f4SPaul Zimmerman * scheduled for execution. This scheduling mechanism 854197ba5f4SPaul Zimmerman * allows only a simple calculation for periodic bandwidth 855197ba5f4SPaul Zimmerman * used (i.e. must assume that all periodic transfers may 856197ba5f4SPaul Zimmerman * need to execute in the same frame). However, it greatly 857197ba5f4SPaul Zimmerman * simplifies scheduling and should be sufficient for the 858197ba5f4SPaul Zimmerman * vast majority of OTG hosts, which need to connect to a 859197ba5f4SPaul Zimmerman * small number of peripherals at one time. Items move from 860197ba5f4SPaul Zimmerman * this list to periodic_sched_ready when the QH interval 861197ba5f4SPaul Zimmerman * counter is 0 at SOF. 862197ba5f4SPaul Zimmerman * @periodic_sched_ready: List of periodic QHs that are ready for execution in 863197ba5f4SPaul Zimmerman * the next frame, but have not yet been assigned to host 864197ba5f4SPaul Zimmerman * channels. Items move from this list to 865197ba5f4SPaul Zimmerman * periodic_sched_assigned as host channels become 866197ba5f4SPaul Zimmerman * available during the current frame. 867197ba5f4SPaul Zimmerman * @periodic_sched_assigned: List of periodic QHs to be executed in the next 868197ba5f4SPaul Zimmerman * frame that are assigned to host channels. Items move 869197ba5f4SPaul Zimmerman * from this list to periodic_sched_queued as the 870197ba5f4SPaul Zimmerman * transactions for the QH are queued to the DWC_otg 871197ba5f4SPaul Zimmerman * controller. 872197ba5f4SPaul Zimmerman * @periodic_sched_queued: List of periodic QHs that have been queued for 873197ba5f4SPaul Zimmerman * execution. Items move from this list to either 874197ba5f4SPaul Zimmerman * periodic_sched_inactive or periodic_sched_ready when the 875197ba5f4SPaul Zimmerman * channel associated with the transfer is released. If the 876197ba5f4SPaul Zimmerman * interval for the QH is 1, the item moves to 877197ba5f4SPaul Zimmerman * periodic_sched_ready because it must be rescheduled for 878197ba5f4SPaul Zimmerman * the next frame. Otherwise, the item moves to 879197ba5f4SPaul Zimmerman * periodic_sched_inactive. 880c9c8ac01SDouglas Anderson * @split_order: List keeping track of channels doing splits, in order. 881197ba5f4SPaul Zimmerman * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 882197ba5f4SPaul Zimmerman * This value is in microseconds per (micro)frame. The 883197ba5f4SPaul Zimmerman * assumption is that all periodic transfers may occur in 884197ba5f4SPaul Zimmerman * the same (micro)frame. 8859f9f09b0SDouglas Anderson * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the 8869f9f09b0SDouglas Anderson * host is in high speed mode; low speed schedules are 8879f9f09b0SDouglas Anderson * stored elsewhere since we need one per TT. 888197ba5f4SPaul Zimmerman * @frame_number: Frame number read from the core at SOF. The value ranges 889197ba5f4SPaul Zimmerman * from 0 to HFNUM_MAX_FRNUM. 890197ba5f4SPaul Zimmerman * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 891197ba5f4SPaul Zimmerman * SOF enable/disable. 892197ba5f4SPaul Zimmerman * @free_hc_list: Free host channels in the controller. This is a list of 893197ba5f4SPaul Zimmerman * struct dwc2_host_chan items. 894197ba5f4SPaul Zimmerman * @periodic_channels: Number of host channels assigned to periodic transfers. 895197ba5f4SPaul Zimmerman * Currently assuming that there is a dedicated host 896197ba5f4SPaul Zimmerman * channel for each periodic transaction and at least one 897197ba5f4SPaul Zimmerman * host channel is available for non-periodic transactions. 898197ba5f4SPaul Zimmerman * @non_periodic_channels: Number of host channels assigned to non-periodic 899197ba5f4SPaul Zimmerman * transfers 900197ba5f4SPaul Zimmerman * @available_host_channels Number of host channels available for the microframe 901197ba5f4SPaul Zimmerman * scheduler to use 902197ba5f4SPaul Zimmerman * @hc_ptr_array: Array of pointers to the host channel descriptors. 903197ba5f4SPaul Zimmerman * Allows accessing a host channel descriptor given the 904197ba5f4SPaul Zimmerman * host channel number. This is useful in interrupt 905197ba5f4SPaul Zimmerman * handlers. 906197ba5f4SPaul Zimmerman * @status_buf: Buffer used for data received during the status phase of 907197ba5f4SPaul Zimmerman * a control transfer. 908197ba5f4SPaul Zimmerman * @status_buf_dma: DMA address for status_buf 909197ba5f4SPaul Zimmerman * @start_work: Delayed work for handling host A-cable connection 910197ba5f4SPaul Zimmerman * @reset_work: Delayed work for handling a port reset 911197ba5f4SPaul Zimmerman * @otg_port: OTG port number 912197ba5f4SPaul Zimmerman * @frame_list: Frame list 913197ba5f4SPaul Zimmerman * @frame_list_dma: Frame list DMA address 91495105a99SGregory Herrero * @frame_list_sz: Frame list size 9153b5fcc9aSGregory Herrero * @desc_gen_cache: Kmem cache for generic descriptors 9163b5fcc9aSGregory Herrero * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors 917941fcce4SDinh Nguyen * 918941fcce4SDinh Nguyen * These are for peripheral mode: 919941fcce4SDinh Nguyen * 920941fcce4SDinh Nguyen * @driver: USB gadget driver 921941fcce4SDinh Nguyen * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 922941fcce4SDinh Nguyen * @num_of_eps: Number of available EPs (excluding EP0) 923941fcce4SDinh Nguyen * @debug_root: Root directrory for debugfs. 924941fcce4SDinh Nguyen * @debug_file: Main status file for debugfs. 9259e14d0a5SGregory Herrero * @debug_testmode: Testmode status file for debugfs. 926941fcce4SDinh Nguyen * @debug_fifo: FIFO status file for debugfs. 927941fcce4SDinh Nguyen * @ep0_reply: Request used for ep0 reply. 928941fcce4SDinh Nguyen * @ep0_buff: Buffer for EP0 reply data, if needed. 929941fcce4SDinh Nguyen * @ctrl_buff: Buffer for EP0 control requests. 930941fcce4SDinh Nguyen * @ctrl_req: Request for EP0 control packets. 931fe0b94abSMian Yousaf Kaukab * @ep0_state: EP0 control transfers state 9329e14d0a5SGregory Herrero * @test_mode: USB test mode requested by the host 933fa389a6dSVardan Mikayelyan * @remote_wakeup_allowed: True if device is allowed to wake-up host by 934fa389a6dSVardan Mikayelyan * remote-wakeup signalling 9350f6b80c0SVahram Aharonyan * @setup_desc_dma: EP0 setup stage desc chain DMA address 9360f6b80c0SVahram Aharonyan * @setup_desc: EP0 setup stage desc chain pointer 9370f6b80c0SVahram Aharonyan * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address 9380f6b80c0SVahram Aharonyan * @ctrl_in_desc: EP0 IN data phase desc chain pointer 9390f6b80c0SVahram Aharonyan * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address 9400f6b80c0SVahram Aharonyan * @ctrl_out_desc: EP0 OUT data phase desc chain pointer 941941fcce4SDinh Nguyen * @eps: The endpoints being supplied to the gadget framework 942197ba5f4SPaul Zimmerman */ 943197ba5f4SPaul Zimmerman struct dwc2_hsotg { 944197ba5f4SPaul Zimmerman struct device *dev; 945197ba5f4SPaul Zimmerman void __iomem *regs; 946197ba5f4SPaul Zimmerman /** Params detected from hardware */ 947197ba5f4SPaul Zimmerman struct dwc2_hw_params hw_params; 948197ba5f4SPaul Zimmerman /** Params to actually use */ 949bea8e86cSJohn Youn struct dwc2_core_params params; 950197ba5f4SPaul Zimmerman enum usb_otg_state op_state; 951c0155b9dSKever Yang enum usb_dr_mode dr_mode; 952e39af88fSMarek Szyprowski unsigned int hcd_enabled:1; 953e39af88fSMarek Szyprowski unsigned int gadget_enabled:1; 95409a75e85SMarek Szyprowski unsigned int ll_hw_enabled:1; 95520fe4409SVardan Mikayelyan unsigned int hibernated:1; 956197ba5f4SPaul Zimmerman 957941fcce4SDinh Nguyen struct phy *phy; 958941fcce4SDinh Nguyen struct usb_phy *uphy; 95909a75e85SMarek Szyprowski struct dwc2_hsotg_plat *plat; 960b98866c2SJohn Youn struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES]; 96109a75e85SMarek Szyprowski u32 phyif; 962941fcce4SDinh Nguyen 963941fcce4SDinh Nguyen spinlock_t lock; 964941fcce4SDinh Nguyen void *priv; 965941fcce4SDinh Nguyen int irq; 966941fcce4SDinh Nguyen struct clk *clk; 96783f8da56SDinh Nguyen struct reset_control *reset; 968f2830ad4SDinh Nguyen struct reset_control *reset_ecc; 969941fcce4SDinh Nguyen 970197ba5f4SPaul Zimmerman unsigned int queuing_high_bandwidth:1; 971197ba5f4SPaul Zimmerman unsigned int srp_success:1; 972197ba5f4SPaul Zimmerman 973197ba5f4SPaul Zimmerman struct workqueue_struct *wq_otg; 974197ba5f4SPaul Zimmerman struct work_struct wf_otg; 975197ba5f4SPaul Zimmerman struct timer_list wkp_timer; 976197ba5f4SPaul Zimmerman enum dwc2_lx_state lx_state; 977cc1e204cSMian Yousaf Kaukab struct dwc2_gregs_backup gr_backup; 978cc1e204cSMian Yousaf Kaukab struct dwc2_dregs_backup dr_backup; 979cc1e204cSMian Yousaf Kaukab struct dwc2_hregs_backup hr_backup; 980197ba5f4SPaul Zimmerman 981941fcce4SDinh Nguyen struct dentry *debug_root; 982563cf017SMian Yousaf Kaukab struct debugfs_regset32 *regset; 983941fcce4SDinh Nguyen 984941fcce4SDinh Nguyen /* DWC OTG HW Release versions */ 985941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_71a 0x4f54271a 9866f80b6deSSevak Arakelyan #define DWC2_CORE_REV_2_80a 0x4f54280a 987941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_90a 0x4f54290a 988e1f411d1SSevak Arakelyan #define DWC2_CORE_REV_2_91a 0x4f54291a 989941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_92a 0x4f54292a 990941fcce4SDinh Nguyen #define DWC2_CORE_REV_2_94a 0x4f54294a 991941fcce4SDinh Nguyen #define DWC2_CORE_REV_3_00a 0x4f54300a 992fef6bc37SJohn Youn #define DWC2_CORE_REV_3_10a 0x4f54310a 9931e6b98ebSVardan Mikayelyan #define DWC2_FS_IOT_REV_1_00a 0x5531100a 9941e6b98ebSVardan Mikayelyan #define DWC2_HS_IOT_REV_1_00a 0x5532100a 995941fcce4SDinh Nguyen 996d14ccabaSGevorg Sahakyan /* DWC OTG HW Core ID */ 997d14ccabaSGevorg Sahakyan #define DWC2_OTG_ID 0x4f540000 998d14ccabaSGevorg Sahakyan #define DWC2_FS_IOT_ID 0x55310000 999d14ccabaSGevorg Sahakyan #define DWC2_HS_IOT_ID 0x55320000 1000d14ccabaSGevorg Sahakyan 1001941fcce4SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1002197ba5f4SPaul Zimmerman union dwc2_hcd_internal_flags { 1003197ba5f4SPaul Zimmerman u32 d32; 1004197ba5f4SPaul Zimmerman struct { 1005197ba5f4SPaul Zimmerman unsigned port_connect_status_change:1; 1006197ba5f4SPaul Zimmerman unsigned port_connect_status:1; 1007197ba5f4SPaul Zimmerman unsigned port_reset_change:1; 1008197ba5f4SPaul Zimmerman unsigned port_enable_change:1; 1009197ba5f4SPaul Zimmerman unsigned port_suspend_change:1; 1010197ba5f4SPaul Zimmerman unsigned port_over_current_change:1; 1011197ba5f4SPaul Zimmerman unsigned port_l1_change:1; 1012fd4850cfSCharles Manning unsigned reserved:25; 1013197ba5f4SPaul Zimmerman } b; 1014197ba5f4SPaul Zimmerman } flags; 1015197ba5f4SPaul Zimmerman 1016197ba5f4SPaul Zimmerman struct list_head non_periodic_sched_inactive; 101738d2b5fbSDouglas Anderson struct list_head non_periodic_sched_waiting; 1018197ba5f4SPaul Zimmerman struct list_head non_periodic_sched_active; 1019197ba5f4SPaul Zimmerman struct list_head *non_periodic_qh_ptr; 1020197ba5f4SPaul Zimmerman struct list_head periodic_sched_inactive; 1021197ba5f4SPaul Zimmerman struct list_head periodic_sched_ready; 1022197ba5f4SPaul Zimmerman struct list_head periodic_sched_assigned; 1023197ba5f4SPaul Zimmerman struct list_head periodic_sched_queued; 1024c9c8ac01SDouglas Anderson struct list_head split_order; 1025197ba5f4SPaul Zimmerman u16 periodic_usecs; 10269f9f09b0SDouglas Anderson unsigned long hs_periodic_bitmap[ 10279f9f09b0SDouglas Anderson DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)]; 1028197ba5f4SPaul Zimmerman u16 frame_number; 1029197ba5f4SPaul Zimmerman u16 periodic_qh_count; 1030734643dfSGregory Herrero bool bus_suspended; 1031fbb9e22bSMian Yousaf Kaukab bool new_connection; 1032197ba5f4SPaul Zimmerman 1033483bb254SDouglas Anderson u16 last_frame_num; 1034483bb254SDouglas Anderson 1035197ba5f4SPaul Zimmerman #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 1036197ba5f4SPaul Zimmerman #define FRAME_NUM_ARRAY_SIZE 1000 1037197ba5f4SPaul Zimmerman u16 *frame_num_array; 1038197ba5f4SPaul Zimmerman u16 *last_frame_num_array; 1039197ba5f4SPaul Zimmerman int frame_num_idx; 1040197ba5f4SPaul Zimmerman int dumped_frame_num_array; 1041197ba5f4SPaul Zimmerman #endif 1042197ba5f4SPaul Zimmerman 1043197ba5f4SPaul Zimmerman struct list_head free_hc_list; 1044197ba5f4SPaul Zimmerman int periodic_channels; 1045197ba5f4SPaul Zimmerman int non_periodic_channels; 1046197ba5f4SPaul Zimmerman int available_host_channels; 1047197ba5f4SPaul Zimmerman struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 1048197ba5f4SPaul Zimmerman u8 *status_buf; 1049197ba5f4SPaul Zimmerman dma_addr_t status_buf_dma; 1050197ba5f4SPaul Zimmerman #define DWC2_HCD_STATUS_BUF_SIZE 64 1051197ba5f4SPaul Zimmerman 1052197ba5f4SPaul Zimmerman struct delayed_work start_work; 1053197ba5f4SPaul Zimmerman struct delayed_work reset_work; 1054197ba5f4SPaul Zimmerman u8 otg_port; 1055197ba5f4SPaul Zimmerman u32 *frame_list; 1056197ba5f4SPaul Zimmerman dma_addr_t frame_list_dma; 105795105a99SGregory Herrero u32 frame_list_sz; 10583b5fcc9aSGregory Herrero struct kmem_cache *desc_gen_cache; 10593b5fcc9aSGregory Herrero struct kmem_cache *desc_hsisoc_cache; 1060197ba5f4SPaul Zimmerman 1061941fcce4SDinh Nguyen #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ 1062941fcce4SDinh Nguyen 1063b98866c2SJohn Youn #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1064b98866c2SJohn Youn IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1065941fcce4SDinh Nguyen /* Gadget structures */ 1066941fcce4SDinh Nguyen struct usb_gadget_driver *driver; 1067941fcce4SDinh Nguyen int fifo_mem; 1068941fcce4SDinh Nguyen unsigned int dedicated_fifos:1; 1069941fcce4SDinh Nguyen unsigned char num_of_eps; 1070941fcce4SDinh Nguyen u32 fifo_map; 1071941fcce4SDinh Nguyen 1072941fcce4SDinh Nguyen struct usb_request *ep0_reply; 1073941fcce4SDinh Nguyen struct usb_request *ctrl_req; 10743f95001dSMian Yousaf Kaukab void *ep0_buff; 10753f95001dSMian Yousaf Kaukab void *ctrl_buff; 1076fe0b94abSMian Yousaf Kaukab enum dwc2_ep0_state ep0_state; 10779e14d0a5SGregory Herrero u8 test_mode; 1078941fcce4SDinh Nguyen 10790f6b80c0SVahram Aharonyan dma_addr_t setup_desc_dma[2]; 10800f6b80c0SVahram Aharonyan struct dwc2_dma_desc *setup_desc[2]; 10810f6b80c0SVahram Aharonyan dma_addr_t ctrl_in_desc_dma; 10820f6b80c0SVahram Aharonyan struct dwc2_dma_desc *ctrl_in_desc; 10830f6b80c0SVahram Aharonyan dma_addr_t ctrl_out_desc_dma; 10840f6b80c0SVahram Aharonyan struct dwc2_dma_desc *ctrl_out_desc; 10850f6b80c0SVahram Aharonyan 1086941fcce4SDinh Nguyen struct usb_gadget gadget; 1087dc6e69e6SMarek Szyprowski unsigned int enabled:1; 10884ace06e8SMarek Szyprowski unsigned int connected:1; 1089fa389a6dSVardan Mikayelyan unsigned int remote_wakeup_allowed:1; 10901f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS]; 10911f91b4ccSFelipe Balbi struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS]; 1092941fcce4SDinh Nguyen #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 1093197ba5f4SPaul Zimmerman }; 1094197ba5f4SPaul Zimmerman 1095197ba5f4SPaul Zimmerman /* Reasons for halting a host channel */ 1096197ba5f4SPaul Zimmerman enum dwc2_halt_status { 1097197ba5f4SPaul Zimmerman DWC2_HC_XFER_NO_HALT_STATUS, 1098197ba5f4SPaul Zimmerman DWC2_HC_XFER_COMPLETE, 1099197ba5f4SPaul Zimmerman DWC2_HC_XFER_URB_COMPLETE, 1100197ba5f4SPaul Zimmerman DWC2_HC_XFER_ACK, 1101197ba5f4SPaul Zimmerman DWC2_HC_XFER_NAK, 1102197ba5f4SPaul Zimmerman DWC2_HC_XFER_NYET, 1103197ba5f4SPaul Zimmerman DWC2_HC_XFER_STALL, 1104197ba5f4SPaul Zimmerman DWC2_HC_XFER_XACT_ERR, 1105197ba5f4SPaul Zimmerman DWC2_HC_XFER_FRAME_OVERRUN, 1106197ba5f4SPaul Zimmerman DWC2_HC_XFER_BABBLE_ERR, 1107197ba5f4SPaul Zimmerman DWC2_HC_XFER_DATA_TOGGLE_ERR, 1108197ba5f4SPaul Zimmerman DWC2_HC_XFER_AHB_ERR, 1109197ba5f4SPaul Zimmerman DWC2_HC_XFER_PERIODIC_INCOMPLETE, 1110197ba5f4SPaul Zimmerman DWC2_HC_XFER_URB_DEQUEUE, 1111197ba5f4SPaul Zimmerman }; 1112197ba5f4SPaul Zimmerman 11131e6b98ebSVardan Mikayelyan /* Core version information */ 11141e6b98ebSVardan Mikayelyan static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg) 11151e6b98ebSVardan Mikayelyan { 11161e6b98ebSVardan Mikayelyan return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000; 11171e6b98ebSVardan Mikayelyan } 11181e6b98ebSVardan Mikayelyan 11191e6b98ebSVardan Mikayelyan static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg) 11201e6b98ebSVardan Mikayelyan { 11211e6b98ebSVardan Mikayelyan return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000; 11221e6b98ebSVardan Mikayelyan } 11231e6b98ebSVardan Mikayelyan 11241e6b98ebSVardan Mikayelyan static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg) 11251e6b98ebSVardan Mikayelyan { 11261e6b98ebSVardan Mikayelyan return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000; 11271e6b98ebSVardan Mikayelyan } 11281e6b98ebSVardan Mikayelyan 1129197ba5f4SPaul Zimmerman /* 1130197ba5f4SPaul Zimmerman * The following functions support initialization of the core driver component 1131197ba5f4SPaul Zimmerman * and the DWC_otg controller 1132197ba5f4SPaul Zimmerman */ 11336e6360b6SJohn Stultz int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait); 11349da51974SJohn Youn int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg); 113541ba9b9bSVardan Mikayelyan int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg); 113641ba9b9bSVardan Mikayelyan int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, bool restore); 1137624815ceSVardan Mikayelyan int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host); 1138624815ceSVardan Mikayelyan int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup, 1139624815ceSVardan Mikayelyan int reset, int is_host); 1140197ba5f4SPaul Zimmerman 1141323230efSJohn Youn bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host); 1142323230efSJohn Youn void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg); 114309c96980SJohn Youn void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg); 114409c96980SJohn Youn 11459da51974SJohn Youn bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 1146197ba5f4SPaul Zimmerman 1147197ba5f4SPaul Zimmerman /* 1148197ba5f4SPaul Zimmerman * Common core Functions. 1149197ba5f4SPaul Zimmerman * The following functions support managing the DWC_otg controller in either 1150197ba5f4SPaul Zimmerman * device or host mode. 1151197ba5f4SPaul Zimmerman */ 11529da51974SJohn Youn void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 11539da51974SJohn Youn void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 11549da51974SJohn Youn void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 1155197ba5f4SPaul Zimmerman 11569da51974SJohn Youn void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 11579da51974SJohn Youn void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 1158197ba5f4SPaul Zimmerman 115994d2666cSVardan Mikayelyan void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup, 116094d2666cSVardan Mikayelyan int is_host); 1161c5c403dcSVardan Mikayelyan int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg); 1162c5c403dcSVardan Mikayelyan int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg); 116394d2666cSVardan Mikayelyan 116466e77a24SRazmik Karapetyan void dwc2_enable_acg(struct dwc2_hsotg *hsotg); 116566e77a24SRazmik Karapetyan 1166197ba5f4SPaul Zimmerman /* This function should be called on every hardware interrupt. */ 11679da51974SJohn Youn irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 1168197ba5f4SPaul Zimmerman 1169323230efSJohn Youn /* The device ID match table */ 1170323230efSJohn Youn extern const struct of_device_id dwc2_of_match_table[]; 1171323230efSJohn Youn 11729da51974SJohn Youn int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg); 11739da51974SJohn Youn int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg); 1174ecb176c6SMian Yousaf Kaukab 117579d6b8c5SSevak Arakelyan /* Common polling functions */ 117679d6b8c5SSevak Arakelyan int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit, 117779d6b8c5SSevak Arakelyan u32 timeout); 117879d6b8c5SSevak Arakelyan int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit, 117979d6b8c5SSevak Arakelyan u32 timeout); 1180334bbd4eSJohn Youn /* Parameters */ 1181c1d286cfSJohn Youn int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); 1182334bbd4eSJohn Youn int dwc2_init_params(struct dwc2_hsotg *hsotg); 1183334bbd4eSJohn Youn 1184197ba5f4SPaul Zimmerman /* 11856bea9620SJohn Youn * The following functions check the controller's OTG operation mode 11866bea9620SJohn Youn * capability (GHWCFG2.OTG_MODE). 11876bea9620SJohn Youn * 11886bea9620SJohn Youn * These functions can be used before the internal hsotg->hw_params 11896bea9620SJohn Youn * are read in and cached so they always read directly from the 11906bea9620SJohn Youn * GHWCFG2 register. 11916bea9620SJohn Youn */ 11929da51974SJohn Youn unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg); 11936bea9620SJohn Youn bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg); 11946bea9620SJohn Youn bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg); 11956bea9620SJohn Youn bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg); 11966bea9620SJohn Youn 11976bea9620SJohn Youn /* 11981696d5abSJohn Youn * Returns the mode of operation, host or device 11991696d5abSJohn Youn */ 12001696d5abSJohn Youn static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) 12011696d5abSJohn Youn { 12021696d5abSJohn Youn return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0; 12031696d5abSJohn Youn } 12049da51974SJohn Youn 12051696d5abSJohn Youn static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) 12061696d5abSJohn Youn { 12071696d5abSJohn Youn return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0; 12081696d5abSJohn Youn } 12091696d5abSJohn Youn 12101696d5abSJohn Youn /* 1211197ba5f4SPaul Zimmerman * Dump core registers and SPRAM 1212197ba5f4SPaul Zimmerman */ 12139da51974SJohn Youn void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 12149da51974SJohn Youn void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 12159da51974SJohn Youn void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 1216197ba5f4SPaul Zimmerman 1217117777b2SDinh Nguyen /* Gadget defines */ 1218b98866c2SJohn Youn #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1219b98866c2SJohn Youn IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 12209da51974SJohn Youn int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg); 12219da51974SJohn Youn int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2); 12229da51974SJohn Youn int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2); 1223f3768997SVardan Mikayelyan int dwc2_gadget_init(struct dwc2_hsotg *hsotg); 12249da51974SJohn Youn void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1225643cc4deSGregory Herrero bool reset); 12269da51974SJohn Youn void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg); 12279da51974SJohn Youn void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2); 12289da51974SJohn Youn int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode); 1229f81f46e1SGregory Herrero #define dwc2_is_device_connected(hsotg) (hsotg->connected) 123058e52ff6SJohn Youn int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg); 12319a5d2816SVardan Mikayelyan int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup); 1232c5c403dcSVardan Mikayelyan int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg); 1233c5c403dcSVardan Mikayelyan int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, 1234c5c403dcSVardan Mikayelyan int rem_wakeup, int reset); 1235c138ecfaSSevak Arakelyan int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg); 1236c138ecfaSSevak Arakelyan int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg); 1237c138ecfaSSevak Arakelyan int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg); 123821b03405SSevak Arakelyan void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg); 1239117777b2SDinh Nguyen #else 12401f91b4ccSFelipe Balbi static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2) 1241117777b2SDinh Nguyen { return 0; } 12421f91b4ccSFelipe Balbi static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2) 1243117777b2SDinh Nguyen { return 0; } 12441f91b4ccSFelipe Balbi static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2) 1245117777b2SDinh Nguyen { return 0; } 1246f3768997SVardan Mikayelyan static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg) 1247117777b2SDinh Nguyen { return 0; } 12481f91b4ccSFelipe Balbi static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1249643cc4deSGregory Herrero bool reset) {} 12501f91b4ccSFelipe Balbi static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} 12511f91b4ccSFelipe Balbi static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} 12521f91b4ccSFelipe Balbi static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, 1253f91eea44SMian Yousaf Kaukab int testmode) 1254f91eea44SMian Yousaf Kaukab { return 0; } 1255f81f46e1SGregory Herrero #define dwc2_is_device_connected(hsotg) (0) 125658e52ff6SJohn Youn static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) 125758e52ff6SJohn Youn { return 0; } 12589a5d2816SVardan Mikayelyan static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, 12599a5d2816SVardan Mikayelyan int remote_wakeup) 126058e52ff6SJohn Youn { return 0; } 1261c5c403dcSVardan Mikayelyan static inline int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg) 1262c5c403dcSVardan Mikayelyan { return 0; } 1263c5c403dcSVardan Mikayelyan static inline int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, 1264c5c403dcSVardan Mikayelyan int rem_wakeup, int reset) 1265c5c403dcSVardan Mikayelyan { return 0; } 1266c138ecfaSSevak Arakelyan static inline int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg) 1267c138ecfaSSevak Arakelyan { return 0; } 1268c138ecfaSSevak Arakelyan static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) 1269c138ecfaSSevak Arakelyan { return 0; } 1270c138ecfaSSevak Arakelyan static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg) 1271c138ecfaSSevak Arakelyan { return 0; } 127221b03405SSevak Arakelyan static inline void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) {} 1273117777b2SDinh Nguyen #endif 1274117777b2SDinh Nguyen 1275117777b2SDinh Nguyen #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 12769da51974SJohn Youn int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 12779da51974SJohn Youn int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us); 12789da51974SJohn Youn void dwc2_hcd_connect(struct dwc2_hsotg *hsotg); 12799da51974SJohn Youn void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force); 12809da51974SJohn Youn void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 128158e52ff6SJohn Youn int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg); 128258e52ff6SJohn Youn int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg); 1283c5c403dcSVardan Mikayelyan int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg); 1284c5c403dcSVardan Mikayelyan int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, 1285c5c403dcSVardan Mikayelyan int rem_wakeup, int reset); 1286117777b2SDinh Nguyen #else 1287117777b2SDinh Nguyen static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1288117777b2SDinh Nguyen { return 0; } 1289fae4e826SDouglas Anderson static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, 1290fae4e826SDouglas Anderson int us) 1291fae4e826SDouglas Anderson { return 0; } 12926a659531SDouglas Anderson static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {} 12936a659531SDouglas Anderson static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {} 1294117777b2SDinh Nguyen static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} 1295117777b2SDinh Nguyen static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} 12964fe160d5SHeiner Kallweit static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg) 1297117777b2SDinh Nguyen { return 0; } 129858e52ff6SJohn Youn static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 129958e52ff6SJohn Youn { return 0; } 130058e52ff6SJohn Youn static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 130158e52ff6SJohn Youn { return 0; } 1302c5c403dcSVardan Mikayelyan static inline int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg) 1303c5c403dcSVardan Mikayelyan { return 0; } 1304c5c403dcSVardan Mikayelyan static inline int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, 1305c5c403dcSVardan Mikayelyan int rem_wakeup, int reset) 1306c5c403dcSVardan Mikayelyan { return 0; } 130758e52ff6SJohn Youn 1308117777b2SDinh Nguyen #endif 1309117777b2SDinh Nguyen 1310197ba5f4SPaul Zimmerman #endif /* __DWC2_CORE_H__ */ 1311