1 /* 2 * core.c - DesignWare HS OTG Controller common routines 3 * 4 * Copyright (C) 2004-2013 Synopsys, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The names of the above-listed copyright holders may not be used 16 * to endorse or promote products derived from this software without 17 * specific prior written permission. 18 * 19 * ALTERNATIVELY, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") as published by the Free Software 21 * Foundation; either version 2 of the License, or (at your option) any 22 * later version. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * The Core code provides basic services for accessing and managing the 39 * DWC_otg hardware. These services are used by both the Host Controller 40 * Driver and the Peripheral Controller Driver. 41 */ 42 #include <linux/kernel.h> 43 #include <linux/module.h> 44 #include <linux/moduleparam.h> 45 #include <linux/spinlock.h> 46 #include <linux/interrupt.h> 47 #include <linux/dma-mapping.h> 48 #include <linux/delay.h> 49 #include <linux/io.h> 50 #include <linux/slab.h> 51 #include <linux/usb.h> 52 53 #include <linux/usb/hcd.h> 54 #include <linux/usb/ch11.h> 55 56 #include "core.h" 57 #include "hcd.h" 58 59 /** 60 * dwc2_backup_global_registers() - Backup global controller registers. 61 * When suspending usb bus, registers needs to be backuped 62 * if controller power is disabled once suspended. 63 * 64 * @hsotg: Programming view of the DWC_otg controller 65 */ 66 static int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg) 67 { 68 struct dwc2_gregs_backup *gr; 69 int i; 70 71 /* Backup global regs */ 72 gr = &hsotg->gr_backup; 73 74 gr->gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 75 gr->gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 76 gr->gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 77 gr->gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 78 gr->grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); 79 gr->gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); 80 gr->hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ); 81 gr->gdfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG); 82 for (i = 0; i < MAX_EPS_CHANNELS; i++) 83 gr->dtxfsiz[i] = dwc2_readl(hsotg->regs + DPTXFSIZN(i)); 84 85 gr->valid = true; 86 return 0; 87 } 88 89 /** 90 * dwc2_restore_global_registers() - Restore controller global registers. 91 * When resuming usb bus, device registers needs to be restored 92 * if controller power were disabled. 93 * 94 * @hsotg: Programming view of the DWC_otg controller 95 */ 96 static int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg) 97 { 98 struct dwc2_gregs_backup *gr; 99 int i; 100 101 dev_dbg(hsotg->dev, "%s\n", __func__); 102 103 /* Restore global regs */ 104 gr = &hsotg->gr_backup; 105 if (!gr->valid) { 106 dev_err(hsotg->dev, "%s: no global registers to restore\n", 107 __func__); 108 return -EINVAL; 109 } 110 gr->valid = false; 111 112 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 113 dwc2_writel(gr->gotgctl, hsotg->regs + GOTGCTL); 114 dwc2_writel(gr->gintmsk, hsotg->regs + GINTMSK); 115 dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG); 116 dwc2_writel(gr->gahbcfg, hsotg->regs + GAHBCFG); 117 dwc2_writel(gr->grxfsiz, hsotg->regs + GRXFSIZ); 118 dwc2_writel(gr->gnptxfsiz, hsotg->regs + GNPTXFSIZ); 119 dwc2_writel(gr->hptxfsiz, hsotg->regs + HPTXFSIZ); 120 dwc2_writel(gr->gdfifocfg, hsotg->regs + GDFIFOCFG); 121 for (i = 0; i < MAX_EPS_CHANNELS; i++) 122 dwc2_writel(gr->dtxfsiz[i], hsotg->regs + DPTXFSIZN(i)); 123 124 return 0; 125 } 126 127 /** 128 * dwc2_exit_hibernation() - Exit controller from Partial Power Down. 129 * 130 * @hsotg: Programming view of the DWC_otg controller 131 * @restore: Controller registers need to be restored 132 */ 133 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore) 134 { 135 u32 pcgcctl; 136 int ret = 0; 137 138 if (!hsotg->core_params->hibernation) 139 return -ENOTSUPP; 140 141 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 142 pcgcctl &= ~PCGCTL_STOPPCLK; 143 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 144 145 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 146 pcgcctl &= ~PCGCTL_PWRCLMP; 147 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 148 149 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 150 pcgcctl &= ~PCGCTL_RSTPDWNMODULE; 151 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 152 153 udelay(100); 154 if (restore) { 155 ret = dwc2_restore_global_registers(hsotg); 156 if (ret) { 157 dev_err(hsotg->dev, "%s: failed to restore registers\n", 158 __func__); 159 return ret; 160 } 161 if (dwc2_is_host_mode(hsotg)) { 162 ret = dwc2_restore_host_registers(hsotg); 163 if (ret) { 164 dev_err(hsotg->dev, "%s: failed to restore host registers\n", 165 __func__); 166 return ret; 167 } 168 } else { 169 ret = dwc2_restore_device_registers(hsotg); 170 if (ret) { 171 dev_err(hsotg->dev, "%s: failed to restore device registers\n", 172 __func__); 173 return ret; 174 } 175 } 176 } 177 178 return ret; 179 } 180 181 /** 182 * dwc2_enter_hibernation() - Put controller in Partial Power Down. 183 * 184 * @hsotg: Programming view of the DWC_otg controller 185 */ 186 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg) 187 { 188 u32 pcgcctl; 189 int ret = 0; 190 191 if (!hsotg->core_params->hibernation) 192 return -ENOTSUPP; 193 194 /* Backup all registers */ 195 ret = dwc2_backup_global_registers(hsotg); 196 if (ret) { 197 dev_err(hsotg->dev, "%s: failed to backup global registers\n", 198 __func__); 199 return ret; 200 } 201 202 if (dwc2_is_host_mode(hsotg)) { 203 ret = dwc2_backup_host_registers(hsotg); 204 if (ret) { 205 dev_err(hsotg->dev, "%s: failed to backup host registers\n", 206 __func__); 207 return ret; 208 } 209 } else { 210 ret = dwc2_backup_device_registers(hsotg); 211 if (ret) { 212 dev_err(hsotg->dev, "%s: failed to backup device registers\n", 213 __func__); 214 return ret; 215 } 216 } 217 218 /* 219 * Clear any pending interrupts since dwc2 will not be able to 220 * clear them after entering hibernation. 221 */ 222 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 223 224 /* Put the controller in low power state */ 225 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 226 227 pcgcctl |= PCGCTL_PWRCLMP; 228 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 229 ndelay(20); 230 231 pcgcctl |= PCGCTL_RSTPDWNMODULE; 232 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 233 ndelay(20); 234 235 pcgcctl |= PCGCTL_STOPPCLK; 236 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 237 238 return ret; 239 } 240 241 /** 242 * dwc2_wait_for_mode() - Waits for the controller mode. 243 * @hsotg: Programming view of the DWC_otg controller. 244 * @host_mode: If true, waits for host mode, otherwise device mode. 245 */ 246 static void dwc2_wait_for_mode(struct dwc2_hsotg *hsotg, 247 bool host_mode) 248 { 249 ktime_t start; 250 ktime_t end; 251 unsigned int timeout = 110; 252 253 dev_vdbg(hsotg->dev, "Waiting for %s mode\n", 254 host_mode ? "host" : "device"); 255 256 start = ktime_get(); 257 258 while (1) { 259 s64 ms; 260 261 if (dwc2_is_host_mode(hsotg) == host_mode) { 262 dev_vdbg(hsotg->dev, "%s mode set\n", 263 host_mode ? "Host" : "Device"); 264 break; 265 } 266 267 end = ktime_get(); 268 ms = ktime_to_ms(ktime_sub(end, start)); 269 270 if (ms >= (s64)timeout) { 271 dev_warn(hsotg->dev, "%s: Couldn't set %s mode\n", 272 __func__, host_mode ? "host" : "device"); 273 break; 274 } 275 276 usleep_range(1000, 2000); 277 } 278 } 279 280 /** 281 * dwc2_iddig_filter_enabled() - Returns true if the IDDIG debounce 282 * filter is enabled. 283 */ 284 static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg) 285 { 286 u32 gsnpsid; 287 u32 ghwcfg4; 288 289 if (!dwc2_hw_is_otg(hsotg)) 290 return false; 291 292 /* Check if core configuration includes the IDDIG filter. */ 293 ghwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4); 294 if (!(ghwcfg4 & GHWCFG4_IDDIG_FILT_EN)) 295 return false; 296 297 /* 298 * Check if the IDDIG debounce filter is bypassed. Available 299 * in core version >= 3.10a. 300 */ 301 gsnpsid = dwc2_readl(hsotg->regs + GSNPSID); 302 if (gsnpsid >= DWC2_CORE_REV_3_10a) { 303 u32 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 304 305 if (gotgctl & GOTGCTL_DBNCE_FLTR_BYPASS) 306 return false; 307 } 308 309 return true; 310 } 311 312 /* 313 * Do core a soft reset of the core. Be careful with this because it 314 * resets all the internal state machines of the core. 315 */ 316 int dwc2_core_reset(struct dwc2_hsotg *hsotg) 317 { 318 u32 greset; 319 int count = 0; 320 bool wait_for_host_mode = false; 321 322 dev_vdbg(hsotg->dev, "%s()\n", __func__); 323 324 /* 325 * If the current mode is host, either due to the force mode 326 * bit being set (which persists after core reset) or the 327 * connector id pin, a core soft reset will temporarily reset 328 * the mode to device. A delay from the IDDIG debounce filter 329 * will occur before going back to host mode. 330 * 331 * Determine whether we will go back into host mode after a 332 * reset and account for this delay after the reset. 333 */ 334 if (dwc2_iddig_filter_enabled(hsotg)) { 335 u32 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 336 u32 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 337 338 if (!(gotgctl & GOTGCTL_CONID_B) || 339 (gusbcfg & GUSBCFG_FORCEHOSTMODE)) { 340 wait_for_host_mode = true; 341 } 342 } 343 344 /* Core Soft Reset */ 345 greset = dwc2_readl(hsotg->regs + GRSTCTL); 346 greset |= GRSTCTL_CSFTRST; 347 dwc2_writel(greset, hsotg->regs + GRSTCTL); 348 do { 349 udelay(1); 350 greset = dwc2_readl(hsotg->regs + GRSTCTL); 351 if (++count > 50) { 352 dev_warn(hsotg->dev, 353 "%s() HANG! Soft Reset GRSTCTL=%0x\n", 354 __func__, greset); 355 return -EBUSY; 356 } 357 } while (greset & GRSTCTL_CSFTRST); 358 359 /* Wait for AHB master IDLE state */ 360 count = 0; 361 do { 362 udelay(1); 363 greset = dwc2_readl(hsotg->regs + GRSTCTL); 364 if (++count > 50) { 365 dev_warn(hsotg->dev, 366 "%s() HANG! AHB Idle GRSTCTL=%0x\n", 367 __func__, greset); 368 return -EBUSY; 369 } 370 } while (!(greset & GRSTCTL_AHBIDLE)); 371 372 if (wait_for_host_mode) 373 dwc2_wait_for_mode(hsotg, true); 374 375 return 0; 376 } 377 378 /* 379 * Force the mode of the controller. 380 * 381 * Forcing the mode is needed for two cases: 382 * 383 * 1) If the dr_mode is set to either HOST or PERIPHERAL we force the 384 * controller to stay in a particular mode regardless of ID pin 385 * changes. We do this usually after a core reset. 386 * 387 * 2) During probe we want to read reset values of the hw 388 * configuration registers that are only available in either host or 389 * device mode. We may need to force the mode if the current mode does 390 * not allow us to access the register in the mode that we want. 391 * 392 * In either case it only makes sense to force the mode if the 393 * controller hardware is OTG capable. 394 * 395 * Checks are done in this function to determine whether doing a force 396 * would be valid or not. 397 * 398 * If a force is done, it requires a IDDIG debounce filter delay if 399 * the filter is configured and enabled. We poll the current mode of 400 * the controller to account for this delay. 401 */ 402 static bool dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host) 403 { 404 u32 gusbcfg; 405 u32 set; 406 u32 clear; 407 408 dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device"); 409 410 /* 411 * Force mode has no effect if the hardware is not OTG. 412 */ 413 if (!dwc2_hw_is_otg(hsotg)) 414 return false; 415 416 /* 417 * If dr_mode is either peripheral or host only, there is no 418 * need to ever force the mode to the opposite mode. 419 */ 420 if (WARN_ON(host && hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)) 421 return false; 422 423 if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST)) 424 return false; 425 426 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 427 428 set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE; 429 clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE; 430 431 gusbcfg &= ~clear; 432 gusbcfg |= set; 433 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); 434 435 dwc2_wait_for_mode(hsotg, host); 436 return true; 437 } 438 439 /** 440 * dwc2_clear_force_mode() - Clears the force mode bits. 441 * 442 * After clearing the bits, wait up to 100 ms to account for any 443 * potential IDDIG filter delay. We can't know if we expect this delay 444 * or not because the value of the connector ID status is affected by 445 * the force mode. We only need to call this once during probe if 446 * dr_mode == OTG. 447 */ 448 static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg) 449 { 450 u32 gusbcfg; 451 452 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 453 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE; 454 gusbcfg &= ~GUSBCFG_FORCEDEVMODE; 455 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); 456 457 if (dwc2_iddig_filter_enabled(hsotg)) 458 usleep_range(100000, 110000); 459 } 460 461 /* 462 * Sets or clears force mode based on the dr_mode parameter. 463 */ 464 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg) 465 { 466 bool ret; 467 468 switch (hsotg->dr_mode) { 469 case USB_DR_MODE_HOST: 470 ret = dwc2_force_mode(hsotg, true); 471 /* 472 * NOTE: This is required for some rockchip soc based 473 * platforms on their host-only dwc2. 474 */ 475 if (!ret) 476 msleep(50); 477 478 break; 479 case USB_DR_MODE_PERIPHERAL: 480 dwc2_force_mode(hsotg, false); 481 break; 482 case USB_DR_MODE_OTG: 483 dwc2_clear_force_mode(hsotg); 484 break; 485 default: 486 dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n", 487 __func__, hsotg->dr_mode); 488 break; 489 } 490 } 491 492 /* 493 * Do core a soft reset of the core. Be careful with this because it 494 * resets all the internal state machines of the core. 495 * 496 * Additionally this will apply force mode as per the hsotg->dr_mode 497 * parameter. 498 */ 499 int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg) 500 { 501 int retval; 502 503 retval = dwc2_core_reset(hsotg); 504 if (retval) 505 return retval; 506 507 dwc2_force_dr_mode(hsotg); 508 return 0; 509 } 510 511 /** 512 * dwc2_dump_host_registers() - Prints the host registers 513 * 514 * @hsotg: Programming view of DWC_otg controller 515 * 516 * NOTE: This function will be removed once the peripheral controller code 517 * is integrated and the driver is stable 518 */ 519 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg) 520 { 521 #ifdef DEBUG 522 u32 __iomem *addr; 523 int i; 524 525 dev_dbg(hsotg->dev, "Host Global Registers\n"); 526 addr = hsotg->regs + HCFG; 527 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n", 528 (unsigned long)addr, dwc2_readl(addr)); 529 addr = hsotg->regs + HFIR; 530 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n", 531 (unsigned long)addr, dwc2_readl(addr)); 532 addr = hsotg->regs + HFNUM; 533 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n", 534 (unsigned long)addr, dwc2_readl(addr)); 535 addr = hsotg->regs + HPTXSTS; 536 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n", 537 (unsigned long)addr, dwc2_readl(addr)); 538 addr = hsotg->regs + HAINT; 539 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n", 540 (unsigned long)addr, dwc2_readl(addr)); 541 addr = hsotg->regs + HAINTMSK; 542 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n", 543 (unsigned long)addr, dwc2_readl(addr)); 544 if (hsotg->core_params->dma_desc_enable > 0) { 545 addr = hsotg->regs + HFLBADDR; 546 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n", 547 (unsigned long)addr, dwc2_readl(addr)); 548 } 549 550 addr = hsotg->regs + HPRT0; 551 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n", 552 (unsigned long)addr, dwc2_readl(addr)); 553 554 for (i = 0; i < hsotg->core_params->host_channels; i++) { 555 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i); 556 addr = hsotg->regs + HCCHAR(i); 557 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n", 558 (unsigned long)addr, dwc2_readl(addr)); 559 addr = hsotg->regs + HCSPLT(i); 560 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n", 561 (unsigned long)addr, dwc2_readl(addr)); 562 addr = hsotg->regs + HCINT(i); 563 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n", 564 (unsigned long)addr, dwc2_readl(addr)); 565 addr = hsotg->regs + HCINTMSK(i); 566 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n", 567 (unsigned long)addr, dwc2_readl(addr)); 568 addr = hsotg->regs + HCTSIZ(i); 569 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n", 570 (unsigned long)addr, dwc2_readl(addr)); 571 addr = hsotg->regs + HCDMA(i); 572 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n", 573 (unsigned long)addr, dwc2_readl(addr)); 574 if (hsotg->core_params->dma_desc_enable > 0) { 575 addr = hsotg->regs + HCDMAB(i); 576 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n", 577 (unsigned long)addr, dwc2_readl(addr)); 578 } 579 } 580 #endif 581 } 582 583 /** 584 * dwc2_dump_global_registers() - Prints the core global registers 585 * 586 * @hsotg: Programming view of DWC_otg controller 587 * 588 * NOTE: This function will be removed once the peripheral controller code 589 * is integrated and the driver is stable 590 */ 591 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg) 592 { 593 #ifdef DEBUG 594 u32 __iomem *addr; 595 596 dev_dbg(hsotg->dev, "Core Global Registers\n"); 597 addr = hsotg->regs + GOTGCTL; 598 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n", 599 (unsigned long)addr, dwc2_readl(addr)); 600 addr = hsotg->regs + GOTGINT; 601 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n", 602 (unsigned long)addr, dwc2_readl(addr)); 603 addr = hsotg->regs + GAHBCFG; 604 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n", 605 (unsigned long)addr, dwc2_readl(addr)); 606 addr = hsotg->regs + GUSBCFG; 607 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n", 608 (unsigned long)addr, dwc2_readl(addr)); 609 addr = hsotg->regs + GRSTCTL; 610 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n", 611 (unsigned long)addr, dwc2_readl(addr)); 612 addr = hsotg->regs + GINTSTS; 613 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n", 614 (unsigned long)addr, dwc2_readl(addr)); 615 addr = hsotg->regs + GINTMSK; 616 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n", 617 (unsigned long)addr, dwc2_readl(addr)); 618 addr = hsotg->regs + GRXSTSR; 619 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n", 620 (unsigned long)addr, dwc2_readl(addr)); 621 addr = hsotg->regs + GRXFSIZ; 622 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n", 623 (unsigned long)addr, dwc2_readl(addr)); 624 addr = hsotg->regs + GNPTXFSIZ; 625 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n", 626 (unsigned long)addr, dwc2_readl(addr)); 627 addr = hsotg->regs + GNPTXSTS; 628 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n", 629 (unsigned long)addr, dwc2_readl(addr)); 630 addr = hsotg->regs + GI2CCTL; 631 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n", 632 (unsigned long)addr, dwc2_readl(addr)); 633 addr = hsotg->regs + GPVNDCTL; 634 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n", 635 (unsigned long)addr, dwc2_readl(addr)); 636 addr = hsotg->regs + GGPIO; 637 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n", 638 (unsigned long)addr, dwc2_readl(addr)); 639 addr = hsotg->regs + GUID; 640 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n", 641 (unsigned long)addr, dwc2_readl(addr)); 642 addr = hsotg->regs + GSNPSID; 643 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n", 644 (unsigned long)addr, dwc2_readl(addr)); 645 addr = hsotg->regs + GHWCFG1; 646 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n", 647 (unsigned long)addr, dwc2_readl(addr)); 648 addr = hsotg->regs + GHWCFG2; 649 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n", 650 (unsigned long)addr, dwc2_readl(addr)); 651 addr = hsotg->regs + GHWCFG3; 652 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n", 653 (unsigned long)addr, dwc2_readl(addr)); 654 addr = hsotg->regs + GHWCFG4; 655 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n", 656 (unsigned long)addr, dwc2_readl(addr)); 657 addr = hsotg->regs + GLPMCFG; 658 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n", 659 (unsigned long)addr, dwc2_readl(addr)); 660 addr = hsotg->regs + GPWRDN; 661 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n", 662 (unsigned long)addr, dwc2_readl(addr)); 663 addr = hsotg->regs + GDFIFOCFG; 664 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n", 665 (unsigned long)addr, dwc2_readl(addr)); 666 addr = hsotg->regs + HPTXFSIZ; 667 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n", 668 (unsigned long)addr, dwc2_readl(addr)); 669 670 addr = hsotg->regs + PCGCTL; 671 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n", 672 (unsigned long)addr, dwc2_readl(addr)); 673 #endif 674 } 675 676 /** 677 * dwc2_flush_tx_fifo() - Flushes a Tx FIFO 678 * 679 * @hsotg: Programming view of DWC_otg controller 680 * @num: Tx FIFO to flush 681 */ 682 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num) 683 { 684 u32 greset; 685 int count = 0; 686 687 dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num); 688 689 greset = GRSTCTL_TXFFLSH; 690 greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK; 691 dwc2_writel(greset, hsotg->regs + GRSTCTL); 692 693 do { 694 greset = dwc2_readl(hsotg->regs + GRSTCTL); 695 if (++count > 10000) { 696 dev_warn(hsotg->dev, 697 "%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n", 698 __func__, greset, 699 dwc2_readl(hsotg->regs + GNPTXSTS)); 700 break; 701 } 702 udelay(1); 703 } while (greset & GRSTCTL_TXFFLSH); 704 705 /* Wait for at least 3 PHY Clocks */ 706 udelay(1); 707 } 708 709 /** 710 * dwc2_flush_rx_fifo() - Flushes the Rx FIFO 711 * 712 * @hsotg: Programming view of DWC_otg controller 713 */ 714 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg) 715 { 716 u32 greset; 717 int count = 0; 718 719 dev_vdbg(hsotg->dev, "%s()\n", __func__); 720 721 greset = GRSTCTL_RXFFLSH; 722 dwc2_writel(greset, hsotg->regs + GRSTCTL); 723 724 do { 725 greset = dwc2_readl(hsotg->regs + GRSTCTL); 726 if (++count > 10000) { 727 dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n", 728 __func__, greset); 729 break; 730 } 731 udelay(1); 732 } while (greset & GRSTCTL_RXFFLSH); 733 734 /* Wait for at least 3 PHY Clocks */ 735 udelay(1); 736 } 737 738 #define DWC2_OUT_OF_BOUNDS(a, b, c) ((a) < (b) || (a) > (c)) 739 740 /* Parameter access functions */ 741 void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val) 742 { 743 int valid = 1; 744 745 switch (val) { 746 case DWC2_CAP_PARAM_HNP_SRP_CAPABLE: 747 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) 748 valid = 0; 749 break; 750 case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE: 751 switch (hsotg->hw_params.op_mode) { 752 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 753 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 754 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 755 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 756 break; 757 default: 758 valid = 0; 759 break; 760 } 761 break; 762 case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE: 763 /* always valid */ 764 break; 765 default: 766 valid = 0; 767 break; 768 } 769 770 if (!valid) { 771 if (val >= 0) 772 dev_err(hsotg->dev, 773 "%d invalid for otg_cap parameter. Check HW configuration.\n", 774 val); 775 switch (hsotg->hw_params.op_mode) { 776 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 777 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE; 778 break; 779 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 780 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 781 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 782 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE; 783 break; 784 default: 785 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 786 break; 787 } 788 dev_dbg(hsotg->dev, "Setting otg_cap to %d\n", val); 789 } 790 791 hsotg->core_params->otg_cap = val; 792 } 793 794 void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val) 795 { 796 int valid = 1; 797 798 if (val > 0 && hsotg->hw_params.arch == GHWCFG2_SLAVE_ONLY_ARCH) 799 valid = 0; 800 if (val < 0) 801 valid = 0; 802 803 if (!valid) { 804 if (val >= 0) 805 dev_err(hsotg->dev, 806 "%d invalid for dma_enable parameter. Check HW configuration.\n", 807 val); 808 val = hsotg->hw_params.arch != GHWCFG2_SLAVE_ONLY_ARCH; 809 dev_dbg(hsotg->dev, "Setting dma_enable to %d\n", val); 810 } 811 812 hsotg->core_params->dma_enable = val; 813 } 814 815 void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val) 816 { 817 int valid = 1; 818 819 if (val > 0 && (hsotg->core_params->dma_enable <= 0 || 820 !hsotg->hw_params.dma_desc_enable)) 821 valid = 0; 822 if (val < 0) 823 valid = 0; 824 825 if (!valid) { 826 if (val >= 0) 827 dev_err(hsotg->dev, 828 "%d invalid for dma_desc_enable parameter. Check HW configuration.\n", 829 val); 830 val = (hsotg->core_params->dma_enable > 0 && 831 hsotg->hw_params.dma_desc_enable); 832 dev_dbg(hsotg->dev, "Setting dma_desc_enable to %d\n", val); 833 } 834 835 hsotg->core_params->dma_desc_enable = val; 836 } 837 838 void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg, int val) 839 { 840 int valid = 1; 841 842 if (val > 0 && (hsotg->core_params->dma_enable <= 0 || 843 !hsotg->hw_params.dma_desc_enable)) 844 valid = 0; 845 if (val < 0) 846 valid = 0; 847 848 if (!valid) { 849 if (val >= 0) 850 dev_err(hsotg->dev, 851 "%d invalid for dma_desc_fs_enable parameter. Check HW configuration.\n", 852 val); 853 val = (hsotg->core_params->dma_enable > 0 && 854 hsotg->hw_params.dma_desc_enable); 855 } 856 857 hsotg->core_params->dma_desc_fs_enable = val; 858 dev_dbg(hsotg->dev, "Setting dma_desc_fs_enable to %d\n", val); 859 } 860 861 void dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg, 862 int val) 863 { 864 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 865 if (val >= 0) { 866 dev_err(hsotg->dev, 867 "Wrong value for host_support_fs_low_power\n"); 868 dev_err(hsotg->dev, 869 "host_support_fs_low_power must be 0 or 1\n"); 870 } 871 val = 0; 872 dev_dbg(hsotg->dev, 873 "Setting host_support_fs_low_power to %d\n", val); 874 } 875 876 hsotg->core_params->host_support_fs_ls_low_power = val; 877 } 878 879 void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, int val) 880 { 881 int valid = 1; 882 883 if (val > 0 && !hsotg->hw_params.enable_dynamic_fifo) 884 valid = 0; 885 if (val < 0) 886 valid = 0; 887 888 if (!valid) { 889 if (val >= 0) 890 dev_err(hsotg->dev, 891 "%d invalid for enable_dynamic_fifo parameter. Check HW configuration.\n", 892 val); 893 val = hsotg->hw_params.enable_dynamic_fifo; 894 dev_dbg(hsotg->dev, "Setting enable_dynamic_fifo to %d\n", val); 895 } 896 897 hsotg->core_params->enable_dynamic_fifo = val; 898 } 899 900 void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val) 901 { 902 int valid = 1; 903 904 if (val < 16 || val > hsotg->hw_params.host_rx_fifo_size) 905 valid = 0; 906 907 if (!valid) { 908 if (val >= 0) 909 dev_err(hsotg->dev, 910 "%d invalid for host_rx_fifo_size. Check HW configuration.\n", 911 val); 912 val = hsotg->hw_params.host_rx_fifo_size; 913 dev_dbg(hsotg->dev, "Setting host_rx_fifo_size to %d\n", val); 914 } 915 916 hsotg->core_params->host_rx_fifo_size = val; 917 } 918 919 void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val) 920 { 921 int valid = 1; 922 923 if (val < 16 || val > hsotg->hw_params.host_nperio_tx_fifo_size) 924 valid = 0; 925 926 if (!valid) { 927 if (val >= 0) 928 dev_err(hsotg->dev, 929 "%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n", 930 val); 931 val = hsotg->hw_params.host_nperio_tx_fifo_size; 932 dev_dbg(hsotg->dev, "Setting host_nperio_tx_fifo_size to %d\n", 933 val); 934 } 935 936 hsotg->core_params->host_nperio_tx_fifo_size = val; 937 } 938 939 void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val) 940 { 941 int valid = 1; 942 943 if (val < 16 || val > hsotg->hw_params.host_perio_tx_fifo_size) 944 valid = 0; 945 946 if (!valid) { 947 if (val >= 0) 948 dev_err(hsotg->dev, 949 "%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n", 950 val); 951 val = hsotg->hw_params.host_perio_tx_fifo_size; 952 dev_dbg(hsotg->dev, "Setting host_perio_tx_fifo_size to %d\n", 953 val); 954 } 955 956 hsotg->core_params->host_perio_tx_fifo_size = val; 957 } 958 959 void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val) 960 { 961 int valid = 1; 962 963 if (val < 2047 || val > hsotg->hw_params.max_transfer_size) 964 valid = 0; 965 966 if (!valid) { 967 if (val >= 0) 968 dev_err(hsotg->dev, 969 "%d invalid for max_transfer_size. Check HW configuration.\n", 970 val); 971 val = hsotg->hw_params.max_transfer_size; 972 dev_dbg(hsotg->dev, "Setting max_transfer_size to %d\n", val); 973 } 974 975 hsotg->core_params->max_transfer_size = val; 976 } 977 978 void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val) 979 { 980 int valid = 1; 981 982 if (val < 15 || val > hsotg->hw_params.max_packet_count) 983 valid = 0; 984 985 if (!valid) { 986 if (val >= 0) 987 dev_err(hsotg->dev, 988 "%d invalid for max_packet_count. Check HW configuration.\n", 989 val); 990 val = hsotg->hw_params.max_packet_count; 991 dev_dbg(hsotg->dev, "Setting max_packet_count to %d\n", val); 992 } 993 994 hsotg->core_params->max_packet_count = val; 995 } 996 997 void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val) 998 { 999 int valid = 1; 1000 1001 if (val < 1 || val > hsotg->hw_params.host_channels) 1002 valid = 0; 1003 1004 if (!valid) { 1005 if (val >= 0) 1006 dev_err(hsotg->dev, 1007 "%d invalid for host_channels. Check HW configuration.\n", 1008 val); 1009 val = hsotg->hw_params.host_channels; 1010 dev_dbg(hsotg->dev, "Setting host_channels to %d\n", val); 1011 } 1012 1013 hsotg->core_params->host_channels = val; 1014 } 1015 1016 void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val) 1017 { 1018 int valid = 0; 1019 u32 hs_phy_type, fs_phy_type; 1020 1021 if (DWC2_OUT_OF_BOUNDS(val, DWC2_PHY_TYPE_PARAM_FS, 1022 DWC2_PHY_TYPE_PARAM_ULPI)) { 1023 if (val >= 0) { 1024 dev_err(hsotg->dev, "Wrong value for phy_type\n"); 1025 dev_err(hsotg->dev, "phy_type must be 0, 1 or 2\n"); 1026 } 1027 1028 valid = 0; 1029 } 1030 1031 hs_phy_type = hsotg->hw_params.hs_phy_type; 1032 fs_phy_type = hsotg->hw_params.fs_phy_type; 1033 if (val == DWC2_PHY_TYPE_PARAM_UTMI && 1034 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || 1035 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 1036 valid = 1; 1037 else if (val == DWC2_PHY_TYPE_PARAM_ULPI && 1038 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI || 1039 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 1040 valid = 1; 1041 else if (val == DWC2_PHY_TYPE_PARAM_FS && 1042 fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 1043 valid = 1; 1044 1045 if (!valid) { 1046 if (val >= 0) 1047 dev_err(hsotg->dev, 1048 "%d invalid for phy_type. Check HW configuration.\n", 1049 val); 1050 val = DWC2_PHY_TYPE_PARAM_FS; 1051 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) { 1052 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || 1053 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI) 1054 val = DWC2_PHY_TYPE_PARAM_UTMI; 1055 else 1056 val = DWC2_PHY_TYPE_PARAM_ULPI; 1057 } 1058 dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val); 1059 } 1060 1061 hsotg->core_params->phy_type = val; 1062 } 1063 1064 static int dwc2_get_param_phy_type(struct dwc2_hsotg *hsotg) 1065 { 1066 return hsotg->core_params->phy_type; 1067 } 1068 1069 void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val) 1070 { 1071 int valid = 1; 1072 1073 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 1074 if (val >= 0) { 1075 dev_err(hsotg->dev, "Wrong value for speed parameter\n"); 1076 dev_err(hsotg->dev, "max_speed parameter must be 0 or 1\n"); 1077 } 1078 valid = 0; 1079 } 1080 1081 if (val == DWC2_SPEED_PARAM_HIGH && 1082 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS) 1083 valid = 0; 1084 1085 if (!valid) { 1086 if (val >= 0) 1087 dev_err(hsotg->dev, 1088 "%d invalid for speed parameter. Check HW configuration.\n", 1089 val); 1090 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS ? 1091 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH; 1092 dev_dbg(hsotg->dev, "Setting speed to %d\n", val); 1093 } 1094 1095 hsotg->core_params->speed = val; 1096 } 1097 1098 void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, int val) 1099 { 1100 int valid = 1; 1101 1102 if (DWC2_OUT_OF_BOUNDS(val, DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ, 1103 DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)) { 1104 if (val >= 0) { 1105 dev_err(hsotg->dev, 1106 "Wrong value for host_ls_low_power_phy_clk parameter\n"); 1107 dev_err(hsotg->dev, 1108 "host_ls_low_power_phy_clk must be 0 or 1\n"); 1109 } 1110 valid = 0; 1111 } 1112 1113 if (val == DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ && 1114 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS) 1115 valid = 0; 1116 1117 if (!valid) { 1118 if (val >= 0) 1119 dev_err(hsotg->dev, 1120 "%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n", 1121 val); 1122 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS 1123 ? DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1124 : DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ; 1125 dev_dbg(hsotg->dev, "Setting host_ls_low_power_phy_clk to %d\n", 1126 val); 1127 } 1128 1129 hsotg->core_params->host_ls_low_power_phy_clk = val; 1130 } 1131 1132 void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val) 1133 { 1134 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 1135 if (val >= 0) { 1136 dev_err(hsotg->dev, "Wrong value for phy_ulpi_ddr\n"); 1137 dev_err(hsotg->dev, "phy_upli_ddr must be 0 or 1\n"); 1138 } 1139 val = 0; 1140 dev_dbg(hsotg->dev, "Setting phy_upli_ddr to %d\n", val); 1141 } 1142 1143 hsotg->core_params->phy_ulpi_ddr = val; 1144 } 1145 1146 void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val) 1147 { 1148 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 1149 if (val >= 0) { 1150 dev_err(hsotg->dev, 1151 "Wrong value for phy_ulpi_ext_vbus\n"); 1152 dev_err(hsotg->dev, 1153 "phy_ulpi_ext_vbus must be 0 or 1\n"); 1154 } 1155 val = 0; 1156 dev_dbg(hsotg->dev, "Setting phy_ulpi_ext_vbus to %d\n", val); 1157 } 1158 1159 hsotg->core_params->phy_ulpi_ext_vbus = val; 1160 } 1161 1162 void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val) 1163 { 1164 int valid = 0; 1165 1166 switch (hsotg->hw_params.utmi_phy_data_width) { 1167 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8: 1168 valid = (val == 8); 1169 break; 1170 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16: 1171 valid = (val == 16); 1172 break; 1173 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16: 1174 valid = (val == 8 || val == 16); 1175 break; 1176 } 1177 1178 if (!valid) { 1179 if (val >= 0) { 1180 dev_err(hsotg->dev, 1181 "%d invalid for phy_utmi_width. Check HW configuration.\n", 1182 val); 1183 } 1184 val = (hsotg->hw_params.utmi_phy_data_width == 1185 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16; 1186 dev_dbg(hsotg->dev, "Setting phy_utmi_width to %d\n", val); 1187 } 1188 1189 hsotg->core_params->phy_utmi_width = val; 1190 } 1191 1192 void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val) 1193 { 1194 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 1195 if (val >= 0) { 1196 dev_err(hsotg->dev, "Wrong value for ulpi_fs_ls\n"); 1197 dev_err(hsotg->dev, "ulpi_fs_ls must be 0 or 1\n"); 1198 } 1199 val = 0; 1200 dev_dbg(hsotg->dev, "Setting ulpi_fs_ls to %d\n", val); 1201 } 1202 1203 hsotg->core_params->ulpi_fs_ls = val; 1204 } 1205 1206 void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val) 1207 { 1208 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 1209 if (val >= 0) { 1210 dev_err(hsotg->dev, "Wrong value for ts_dline\n"); 1211 dev_err(hsotg->dev, "ts_dline must be 0 or 1\n"); 1212 } 1213 val = 0; 1214 dev_dbg(hsotg->dev, "Setting ts_dline to %d\n", val); 1215 } 1216 1217 hsotg->core_params->ts_dline = val; 1218 } 1219 1220 void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val) 1221 { 1222 int valid = 1; 1223 1224 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 1225 if (val >= 0) { 1226 dev_err(hsotg->dev, "Wrong value for i2c_enable\n"); 1227 dev_err(hsotg->dev, "i2c_enable must be 0 or 1\n"); 1228 } 1229 1230 valid = 0; 1231 } 1232 1233 if (val == 1 && !(hsotg->hw_params.i2c_enable)) 1234 valid = 0; 1235 1236 if (!valid) { 1237 if (val >= 0) 1238 dev_err(hsotg->dev, 1239 "%d invalid for i2c_enable. Check HW configuration.\n", 1240 val); 1241 val = hsotg->hw_params.i2c_enable; 1242 dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val); 1243 } 1244 1245 hsotg->core_params->i2c_enable = val; 1246 } 1247 1248 void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, int val) 1249 { 1250 int valid = 1; 1251 1252 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 1253 if (val >= 0) { 1254 dev_err(hsotg->dev, 1255 "Wrong value for en_multiple_tx_fifo,\n"); 1256 dev_err(hsotg->dev, 1257 "en_multiple_tx_fifo must be 0 or 1\n"); 1258 } 1259 valid = 0; 1260 } 1261 1262 if (val == 1 && !hsotg->hw_params.en_multiple_tx_fifo) 1263 valid = 0; 1264 1265 if (!valid) { 1266 if (val >= 0) 1267 dev_err(hsotg->dev, 1268 "%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n", 1269 val); 1270 val = hsotg->hw_params.en_multiple_tx_fifo; 1271 dev_dbg(hsotg->dev, "Setting en_multiple_tx_fifo to %d\n", val); 1272 } 1273 1274 hsotg->core_params->en_multiple_tx_fifo = val; 1275 } 1276 1277 void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val) 1278 { 1279 int valid = 1; 1280 1281 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 1282 if (val >= 0) { 1283 dev_err(hsotg->dev, 1284 "'%d' invalid for parameter reload_ctl\n", val); 1285 dev_err(hsotg->dev, "reload_ctl must be 0 or 1\n"); 1286 } 1287 valid = 0; 1288 } 1289 1290 if (val == 1 && hsotg->hw_params.snpsid < DWC2_CORE_REV_2_92a) 1291 valid = 0; 1292 1293 if (!valid) { 1294 if (val >= 0) 1295 dev_err(hsotg->dev, 1296 "%d invalid for parameter reload_ctl. Check HW configuration.\n", 1297 val); 1298 val = hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_92a; 1299 dev_dbg(hsotg->dev, "Setting reload_ctl to %d\n", val); 1300 } 1301 1302 hsotg->core_params->reload_ctl = val; 1303 } 1304 1305 void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val) 1306 { 1307 if (val != -1) 1308 hsotg->core_params->ahbcfg = val; 1309 else 1310 hsotg->core_params->ahbcfg = GAHBCFG_HBSTLEN_INCR4 << 1311 GAHBCFG_HBSTLEN_SHIFT; 1312 } 1313 1314 void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val) 1315 { 1316 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 1317 if (val >= 0) { 1318 dev_err(hsotg->dev, 1319 "'%d' invalid for parameter otg_ver\n", val); 1320 dev_err(hsotg->dev, 1321 "otg_ver must be 0 (for OTG 1.3 support) or 1 (for OTG 2.0 support)\n"); 1322 } 1323 val = 0; 1324 dev_dbg(hsotg->dev, "Setting otg_ver to %d\n", val); 1325 } 1326 1327 hsotg->core_params->otg_ver = val; 1328 } 1329 1330 static void dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val) 1331 { 1332 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 1333 if (val >= 0) { 1334 dev_err(hsotg->dev, 1335 "'%d' invalid for parameter uframe_sched\n", 1336 val); 1337 dev_err(hsotg->dev, "uframe_sched must be 0 or 1\n"); 1338 } 1339 val = 1; 1340 dev_dbg(hsotg->dev, "Setting uframe_sched to %d\n", val); 1341 } 1342 1343 hsotg->core_params->uframe_sched = val; 1344 } 1345 1346 static void dwc2_set_param_external_id_pin_ctl(struct dwc2_hsotg *hsotg, 1347 int val) 1348 { 1349 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 1350 if (val >= 0) { 1351 dev_err(hsotg->dev, 1352 "'%d' invalid for parameter external_id_pin_ctl\n", 1353 val); 1354 dev_err(hsotg->dev, "external_id_pin_ctl must be 0 or 1\n"); 1355 } 1356 val = 0; 1357 dev_dbg(hsotg->dev, "Setting external_id_pin_ctl to %d\n", val); 1358 } 1359 1360 hsotg->core_params->external_id_pin_ctl = val; 1361 } 1362 1363 static void dwc2_set_param_hibernation(struct dwc2_hsotg *hsotg, 1364 int val) 1365 { 1366 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 1367 if (val >= 0) { 1368 dev_err(hsotg->dev, 1369 "'%d' invalid for parameter hibernation\n", 1370 val); 1371 dev_err(hsotg->dev, "hibernation must be 0 or 1\n"); 1372 } 1373 val = 0; 1374 dev_dbg(hsotg->dev, "Setting hibernation to %d\n", val); 1375 } 1376 1377 hsotg->core_params->hibernation = val; 1378 } 1379 1380 /* 1381 * This function is called during module intialization to pass module parameters 1382 * for the DWC_otg core. 1383 */ 1384 void dwc2_set_parameters(struct dwc2_hsotg *hsotg, 1385 const struct dwc2_core_params *params) 1386 { 1387 dev_dbg(hsotg->dev, "%s()\n", __func__); 1388 1389 dwc2_set_param_otg_cap(hsotg, params->otg_cap); 1390 dwc2_set_param_dma_enable(hsotg, params->dma_enable); 1391 dwc2_set_param_dma_desc_enable(hsotg, params->dma_desc_enable); 1392 dwc2_set_param_dma_desc_fs_enable(hsotg, params->dma_desc_fs_enable); 1393 dwc2_set_param_host_support_fs_ls_low_power(hsotg, 1394 params->host_support_fs_ls_low_power); 1395 dwc2_set_param_enable_dynamic_fifo(hsotg, 1396 params->enable_dynamic_fifo); 1397 dwc2_set_param_host_rx_fifo_size(hsotg, 1398 params->host_rx_fifo_size); 1399 dwc2_set_param_host_nperio_tx_fifo_size(hsotg, 1400 params->host_nperio_tx_fifo_size); 1401 dwc2_set_param_host_perio_tx_fifo_size(hsotg, 1402 params->host_perio_tx_fifo_size); 1403 dwc2_set_param_max_transfer_size(hsotg, 1404 params->max_transfer_size); 1405 dwc2_set_param_max_packet_count(hsotg, 1406 params->max_packet_count); 1407 dwc2_set_param_host_channels(hsotg, params->host_channels); 1408 dwc2_set_param_phy_type(hsotg, params->phy_type); 1409 dwc2_set_param_speed(hsotg, params->speed); 1410 dwc2_set_param_host_ls_low_power_phy_clk(hsotg, 1411 params->host_ls_low_power_phy_clk); 1412 dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr); 1413 dwc2_set_param_phy_ulpi_ext_vbus(hsotg, 1414 params->phy_ulpi_ext_vbus); 1415 dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width); 1416 dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls); 1417 dwc2_set_param_ts_dline(hsotg, params->ts_dline); 1418 dwc2_set_param_i2c_enable(hsotg, params->i2c_enable); 1419 dwc2_set_param_en_multiple_tx_fifo(hsotg, 1420 params->en_multiple_tx_fifo); 1421 dwc2_set_param_reload_ctl(hsotg, params->reload_ctl); 1422 dwc2_set_param_ahbcfg(hsotg, params->ahbcfg); 1423 dwc2_set_param_otg_ver(hsotg, params->otg_ver); 1424 dwc2_set_param_uframe_sched(hsotg, params->uframe_sched); 1425 dwc2_set_param_external_id_pin_ctl(hsotg, params->external_id_pin_ctl); 1426 dwc2_set_param_hibernation(hsotg, params->hibernation); 1427 } 1428 1429 /* 1430 * Forces either host or device mode if the controller is not 1431 * currently in that mode. 1432 * 1433 * Returns true if the mode was forced. 1434 */ 1435 static bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host) 1436 { 1437 if (host && dwc2_is_host_mode(hsotg)) 1438 return false; 1439 else if (!host && dwc2_is_device_mode(hsotg)) 1440 return false; 1441 1442 return dwc2_force_mode(hsotg, host); 1443 } 1444 1445 /* 1446 * Gets host hardware parameters. Forces host mode if not currently in 1447 * host mode. Should be called immediately after a core soft reset in 1448 * order to get the reset values. 1449 */ 1450 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg) 1451 { 1452 struct dwc2_hw_params *hw = &hsotg->hw_params; 1453 u32 gnptxfsiz; 1454 u32 hptxfsiz; 1455 bool forced; 1456 1457 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) 1458 return; 1459 1460 forced = dwc2_force_mode_if_needed(hsotg, true); 1461 1462 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); 1463 hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ); 1464 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz); 1465 dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz); 1466 1467 if (forced) 1468 dwc2_clear_force_mode(hsotg); 1469 1470 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 1471 FIFOSIZE_DEPTH_SHIFT; 1472 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> 1473 FIFOSIZE_DEPTH_SHIFT; 1474 } 1475 1476 /* 1477 * Gets device hardware parameters. Forces device mode if not 1478 * currently in device mode. Should be called immediately after a core 1479 * soft reset in order to get the reset values. 1480 */ 1481 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg) 1482 { 1483 struct dwc2_hw_params *hw = &hsotg->hw_params; 1484 bool forced; 1485 u32 gnptxfsiz; 1486 1487 if (hsotg->dr_mode == USB_DR_MODE_HOST) 1488 return; 1489 1490 forced = dwc2_force_mode_if_needed(hsotg, false); 1491 1492 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); 1493 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz); 1494 1495 if (forced) 1496 dwc2_clear_force_mode(hsotg); 1497 1498 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 1499 FIFOSIZE_DEPTH_SHIFT; 1500 } 1501 1502 /** 1503 * During device initialization, read various hardware configuration 1504 * registers and interpret the contents. 1505 */ 1506 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) 1507 { 1508 struct dwc2_hw_params *hw = &hsotg->hw_params; 1509 unsigned width; 1510 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4; 1511 u32 grxfsiz; 1512 1513 /* 1514 * Attempt to ensure this device is really a DWC_otg Controller. 1515 * Read and verify the GSNPSID register contents. The value should be 1516 * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3", 1517 * as in "OTG version 2.xx" or "OTG version 3.xx". 1518 */ 1519 hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID); 1520 if ((hw->snpsid & 0xfffff000) != 0x4f542000 && 1521 (hw->snpsid & 0xfffff000) != 0x4f543000) { 1522 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n", 1523 hw->snpsid); 1524 return -ENODEV; 1525 } 1526 1527 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n", 1528 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf, 1529 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid); 1530 1531 hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1); 1532 hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2); 1533 hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3); 1534 hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4); 1535 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); 1536 1537 dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1); 1538 dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2); 1539 dev_dbg(hsotg->dev, "hwcfg3=%08x\n", hwcfg3); 1540 dev_dbg(hsotg->dev, "hwcfg4=%08x\n", hwcfg4); 1541 dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz); 1542 1543 /* 1544 * Host specific hardware parameters. Reading these parameters 1545 * requires the controller to be in host mode. The mode will 1546 * be forced, if necessary, to read these values. 1547 */ 1548 dwc2_get_host_hwparams(hsotg); 1549 dwc2_get_dev_hwparams(hsotg); 1550 1551 /* hwcfg1 */ 1552 hw->dev_ep_dirs = hwcfg1; 1553 1554 /* hwcfg2 */ 1555 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> 1556 GHWCFG2_OP_MODE_SHIFT; 1557 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> 1558 GHWCFG2_ARCHITECTURE_SHIFT; 1559 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); 1560 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> 1561 GHWCFG2_NUM_HOST_CHAN_SHIFT); 1562 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> 1563 GHWCFG2_HS_PHY_TYPE_SHIFT; 1564 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> 1565 GHWCFG2_FS_PHY_TYPE_SHIFT; 1566 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> 1567 GHWCFG2_NUM_DEV_EP_SHIFT; 1568 hw->nperio_tx_q_depth = 1569 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >> 1570 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1; 1571 hw->host_perio_tx_q_depth = 1572 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >> 1573 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1; 1574 hw->dev_token_q_depth = 1575 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >> 1576 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT; 1577 1578 /* hwcfg3 */ 1579 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >> 1580 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT; 1581 hw->max_transfer_size = (1 << (width + 11)) - 1; 1582 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >> 1583 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT; 1584 hw->max_packet_count = (1 << (width + 4)) - 1; 1585 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); 1586 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> 1587 GHWCFG3_DFIFO_DEPTH_SHIFT; 1588 1589 /* hwcfg4 */ 1590 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); 1591 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> 1592 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT; 1593 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); 1594 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); 1595 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> 1596 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT; 1597 1598 /* fifo sizes */ 1599 hw->host_rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> 1600 GRXFSIZ_DEPTH_SHIFT; 1601 1602 dev_dbg(hsotg->dev, "Detected values from hardware:\n"); 1603 dev_dbg(hsotg->dev, " op_mode=%d\n", 1604 hw->op_mode); 1605 dev_dbg(hsotg->dev, " arch=%d\n", 1606 hw->arch); 1607 dev_dbg(hsotg->dev, " dma_desc_enable=%d\n", 1608 hw->dma_desc_enable); 1609 dev_dbg(hsotg->dev, " power_optimized=%d\n", 1610 hw->power_optimized); 1611 dev_dbg(hsotg->dev, " i2c_enable=%d\n", 1612 hw->i2c_enable); 1613 dev_dbg(hsotg->dev, " hs_phy_type=%d\n", 1614 hw->hs_phy_type); 1615 dev_dbg(hsotg->dev, " fs_phy_type=%d\n", 1616 hw->fs_phy_type); 1617 dev_dbg(hsotg->dev, " utmi_phy_data_width=%d\n", 1618 hw->utmi_phy_data_width); 1619 dev_dbg(hsotg->dev, " num_dev_ep=%d\n", 1620 hw->num_dev_ep); 1621 dev_dbg(hsotg->dev, " num_dev_perio_in_ep=%d\n", 1622 hw->num_dev_perio_in_ep); 1623 dev_dbg(hsotg->dev, " host_channels=%d\n", 1624 hw->host_channels); 1625 dev_dbg(hsotg->dev, " max_transfer_size=%d\n", 1626 hw->max_transfer_size); 1627 dev_dbg(hsotg->dev, " max_packet_count=%d\n", 1628 hw->max_packet_count); 1629 dev_dbg(hsotg->dev, " nperio_tx_q_depth=0x%0x\n", 1630 hw->nperio_tx_q_depth); 1631 dev_dbg(hsotg->dev, " host_perio_tx_q_depth=0x%0x\n", 1632 hw->host_perio_tx_q_depth); 1633 dev_dbg(hsotg->dev, " dev_token_q_depth=0x%0x\n", 1634 hw->dev_token_q_depth); 1635 dev_dbg(hsotg->dev, " enable_dynamic_fifo=%d\n", 1636 hw->enable_dynamic_fifo); 1637 dev_dbg(hsotg->dev, " en_multiple_tx_fifo=%d\n", 1638 hw->en_multiple_tx_fifo); 1639 dev_dbg(hsotg->dev, " total_fifo_size=%d\n", 1640 hw->total_fifo_size); 1641 dev_dbg(hsotg->dev, " host_rx_fifo_size=%d\n", 1642 hw->host_rx_fifo_size); 1643 dev_dbg(hsotg->dev, " host_nperio_tx_fifo_size=%d\n", 1644 hw->host_nperio_tx_fifo_size); 1645 dev_dbg(hsotg->dev, " host_perio_tx_fifo_size=%d\n", 1646 hw->host_perio_tx_fifo_size); 1647 dev_dbg(hsotg->dev, "\n"); 1648 1649 return 0; 1650 } 1651 1652 /* 1653 * Sets all parameters to the given value. 1654 * 1655 * Assumes that the dwc2_core_params struct contains only integers. 1656 */ 1657 void dwc2_set_all_params(struct dwc2_core_params *params, int value) 1658 { 1659 int *p = (int *)params; 1660 size_t size = sizeof(*params) / sizeof(*p); 1661 int i; 1662 1663 for (i = 0; i < size; i++) 1664 p[i] = value; 1665 } 1666 1667 1668 u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg) 1669 { 1670 return hsotg->core_params->otg_ver == 1 ? 0x0200 : 0x0103; 1671 } 1672 1673 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg) 1674 { 1675 if (dwc2_readl(hsotg->regs + GSNPSID) == 0xffffffff) 1676 return false; 1677 else 1678 return true; 1679 } 1680 1681 /** 1682 * dwc2_enable_global_interrupts() - Enables the controller's Global 1683 * Interrupt in the AHB Config register 1684 * 1685 * @hsotg: Programming view of DWC_otg controller 1686 */ 1687 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg) 1688 { 1689 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 1690 1691 ahbcfg |= GAHBCFG_GLBL_INTR_EN; 1692 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 1693 } 1694 1695 /** 1696 * dwc2_disable_global_interrupts() - Disables the controller's Global 1697 * Interrupt in the AHB Config register 1698 * 1699 * @hsotg: Programming view of DWC_otg controller 1700 */ 1701 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg) 1702 { 1703 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 1704 1705 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 1706 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 1707 } 1708 1709 /* Returns the controller's GHWCFG2.OTG_MODE. */ 1710 unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg) 1711 { 1712 u32 ghwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2); 1713 1714 return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >> 1715 GHWCFG2_OP_MODE_SHIFT; 1716 } 1717 1718 /* Returns true if the controller is capable of DRD. */ 1719 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg) 1720 { 1721 unsigned op_mode = dwc2_op_mode(hsotg); 1722 1723 return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) || 1724 (op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) || 1725 (op_mode == GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE); 1726 } 1727 1728 /* Returns true if the controller is host-only. */ 1729 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg) 1730 { 1731 unsigned op_mode = dwc2_op_mode(hsotg); 1732 1733 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) || 1734 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST); 1735 } 1736 1737 /* Returns true if the controller is device-only. */ 1738 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg) 1739 { 1740 unsigned op_mode = dwc2_op_mode(hsotg); 1741 1742 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) || 1743 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE); 1744 } 1745 1746 MODULE_DESCRIPTION("DESIGNWARE HS OTG Core"); 1747 MODULE_AUTHOR("Synopsys, Inc."); 1748 MODULE_LICENSE("Dual BSD/GPL"); 1749