1 /* 2 * core.c - DesignWare HS OTG Controller common routines 3 * 4 * Copyright (C) 2004-2013 Synopsys, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The names of the above-listed copyright holders may not be used 16 * to endorse or promote products derived from this software without 17 * specific prior written permission. 18 * 19 * ALTERNATIVELY, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") as published by the Free Software 21 * Foundation; either version 2 of the License, or (at your option) any 22 * later version. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * The Core code provides basic services for accessing and managing the 39 * DWC_otg hardware. These services are used by both the Host Controller 40 * Driver and the Peripheral Controller Driver. 41 */ 42 #include <linux/kernel.h> 43 #include <linux/module.h> 44 #include <linux/moduleparam.h> 45 #include <linux/spinlock.h> 46 #include <linux/interrupt.h> 47 #include <linux/dma-mapping.h> 48 #include <linux/delay.h> 49 #include <linux/io.h> 50 #include <linux/slab.h> 51 #include <linux/usb.h> 52 53 #include <linux/usb/hcd.h> 54 #include <linux/usb/ch11.h> 55 56 #include "core.h" 57 #include "hcd.h" 58 59 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 60 /** 61 * dwc2_backup_host_registers() - Backup controller host registers. 62 * When suspending usb bus, registers needs to be backuped 63 * if controller power is disabled once suspended. 64 * 65 * @hsotg: Programming view of the DWC_otg controller 66 */ 67 static int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 68 { 69 struct dwc2_hregs_backup *hr; 70 int i; 71 72 dev_dbg(hsotg->dev, "%s\n", __func__); 73 74 /* Backup Host regs */ 75 hr = &hsotg->hr_backup; 76 hr->hcfg = dwc2_readl(hsotg->regs + HCFG); 77 hr->haintmsk = dwc2_readl(hsotg->regs + HAINTMSK); 78 for (i = 0; i < hsotg->core_params->host_channels; ++i) 79 hr->hcintmsk[i] = dwc2_readl(hsotg->regs + HCINTMSK(i)); 80 81 hr->hprt0 = dwc2_read_hprt0(hsotg); 82 hr->hfir = dwc2_readl(hsotg->regs + HFIR); 83 hr->valid = true; 84 85 return 0; 86 } 87 88 /** 89 * dwc2_restore_host_registers() - Restore controller host registers. 90 * When resuming usb bus, device registers needs to be restored 91 * if controller power were disabled. 92 * 93 * @hsotg: Programming view of the DWC_otg controller 94 */ 95 static int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 96 { 97 struct dwc2_hregs_backup *hr; 98 int i; 99 100 dev_dbg(hsotg->dev, "%s\n", __func__); 101 102 /* Restore host regs */ 103 hr = &hsotg->hr_backup; 104 if (!hr->valid) { 105 dev_err(hsotg->dev, "%s: no host registers to restore\n", 106 __func__); 107 return -EINVAL; 108 } 109 hr->valid = false; 110 111 dwc2_writel(hr->hcfg, hsotg->regs + HCFG); 112 dwc2_writel(hr->haintmsk, hsotg->regs + HAINTMSK); 113 114 for (i = 0; i < hsotg->core_params->host_channels; ++i) 115 dwc2_writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i)); 116 117 dwc2_writel(hr->hprt0, hsotg->regs + HPRT0); 118 dwc2_writel(hr->hfir, hsotg->regs + HFIR); 119 hsotg->frame_number = 0; 120 121 return 0; 122 } 123 #else 124 static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 125 { return 0; } 126 127 static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 128 { return 0; } 129 #endif 130 131 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 132 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 133 /** 134 * dwc2_backup_device_registers() - Backup controller device registers. 135 * When suspending usb bus, registers needs to be backuped 136 * if controller power is disabled once suspended. 137 * 138 * @hsotg: Programming view of the DWC_otg controller 139 */ 140 static int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) 141 { 142 struct dwc2_dregs_backup *dr; 143 int i; 144 145 dev_dbg(hsotg->dev, "%s\n", __func__); 146 147 /* Backup dev regs */ 148 dr = &hsotg->dr_backup; 149 150 dr->dcfg = dwc2_readl(hsotg->regs + DCFG); 151 dr->dctl = dwc2_readl(hsotg->regs + DCTL); 152 dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); 153 dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK); 154 dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK); 155 156 for (i = 0; i < hsotg->num_of_eps; i++) { 157 /* Backup IN EPs */ 158 dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i)); 159 160 /* Ensure DATA PID is correctly configured */ 161 if (dr->diepctl[i] & DXEPCTL_DPID) 162 dr->diepctl[i] |= DXEPCTL_SETD1PID; 163 else 164 dr->diepctl[i] |= DXEPCTL_SETD0PID; 165 166 dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i)); 167 dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i)); 168 169 /* Backup OUT EPs */ 170 dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i)); 171 172 /* Ensure DATA PID is correctly configured */ 173 if (dr->doepctl[i] & DXEPCTL_DPID) 174 dr->doepctl[i] |= DXEPCTL_SETD1PID; 175 else 176 dr->doepctl[i] |= DXEPCTL_SETD0PID; 177 178 dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i)); 179 dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i)); 180 } 181 dr->valid = true; 182 return 0; 183 } 184 185 /** 186 * dwc2_restore_device_registers() - Restore controller device registers. 187 * When resuming usb bus, device registers needs to be restored 188 * if controller power were disabled. 189 * 190 * @hsotg: Programming view of the DWC_otg controller 191 */ 192 static int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg) 193 { 194 struct dwc2_dregs_backup *dr; 195 u32 dctl; 196 int i; 197 198 dev_dbg(hsotg->dev, "%s\n", __func__); 199 200 /* Restore dev regs */ 201 dr = &hsotg->dr_backup; 202 if (!dr->valid) { 203 dev_err(hsotg->dev, "%s: no device registers to restore\n", 204 __func__); 205 return -EINVAL; 206 } 207 dr->valid = false; 208 209 dwc2_writel(dr->dcfg, hsotg->regs + DCFG); 210 dwc2_writel(dr->dctl, hsotg->regs + DCTL); 211 dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK); 212 dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK); 213 dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK); 214 215 for (i = 0; i < hsotg->num_of_eps; i++) { 216 /* Restore IN EPs */ 217 dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i)); 218 dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i)); 219 dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i)); 220 221 /* Restore OUT EPs */ 222 dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i)); 223 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i)); 224 dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i)); 225 } 226 227 /* Set the Power-On Programming done bit */ 228 dctl = dwc2_readl(hsotg->regs + DCTL); 229 dctl |= DCTL_PWRONPRGDONE; 230 dwc2_writel(dctl, hsotg->regs + DCTL); 231 232 return 0; 233 } 234 #else 235 static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) 236 { return 0; } 237 238 static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg) 239 { return 0; } 240 #endif 241 242 /** 243 * dwc2_backup_global_registers() - Backup global controller registers. 244 * When suspending usb bus, registers needs to be backuped 245 * if controller power is disabled once suspended. 246 * 247 * @hsotg: Programming view of the DWC_otg controller 248 */ 249 static int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg) 250 { 251 struct dwc2_gregs_backup *gr; 252 int i; 253 254 /* Backup global regs */ 255 gr = &hsotg->gr_backup; 256 257 gr->gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 258 gr->gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 259 gr->gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 260 gr->gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 261 gr->grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); 262 gr->gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); 263 gr->hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ); 264 gr->gdfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG); 265 for (i = 0; i < MAX_EPS_CHANNELS; i++) 266 gr->dtxfsiz[i] = dwc2_readl(hsotg->regs + DPTXFSIZN(i)); 267 268 gr->valid = true; 269 return 0; 270 } 271 272 /** 273 * dwc2_restore_global_registers() - Restore controller global registers. 274 * When resuming usb bus, device registers needs to be restored 275 * if controller power were disabled. 276 * 277 * @hsotg: Programming view of the DWC_otg controller 278 */ 279 static int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg) 280 { 281 struct dwc2_gregs_backup *gr; 282 int i; 283 284 dev_dbg(hsotg->dev, "%s\n", __func__); 285 286 /* Restore global regs */ 287 gr = &hsotg->gr_backup; 288 if (!gr->valid) { 289 dev_err(hsotg->dev, "%s: no global registers to restore\n", 290 __func__); 291 return -EINVAL; 292 } 293 gr->valid = false; 294 295 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 296 dwc2_writel(gr->gotgctl, hsotg->regs + GOTGCTL); 297 dwc2_writel(gr->gintmsk, hsotg->regs + GINTMSK); 298 dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG); 299 dwc2_writel(gr->gahbcfg, hsotg->regs + GAHBCFG); 300 dwc2_writel(gr->grxfsiz, hsotg->regs + GRXFSIZ); 301 dwc2_writel(gr->gnptxfsiz, hsotg->regs + GNPTXFSIZ); 302 dwc2_writel(gr->hptxfsiz, hsotg->regs + HPTXFSIZ); 303 dwc2_writel(gr->gdfifocfg, hsotg->regs + GDFIFOCFG); 304 for (i = 0; i < MAX_EPS_CHANNELS; i++) 305 dwc2_writel(gr->dtxfsiz[i], hsotg->regs + DPTXFSIZN(i)); 306 307 return 0; 308 } 309 310 /** 311 * dwc2_exit_hibernation() - Exit controller from Partial Power Down. 312 * 313 * @hsotg: Programming view of the DWC_otg controller 314 * @restore: Controller registers need to be restored 315 */ 316 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore) 317 { 318 u32 pcgcctl; 319 int ret = 0; 320 321 if (!hsotg->core_params->hibernation) 322 return -ENOTSUPP; 323 324 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 325 pcgcctl &= ~PCGCTL_STOPPCLK; 326 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 327 328 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 329 pcgcctl &= ~PCGCTL_PWRCLMP; 330 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 331 332 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 333 pcgcctl &= ~PCGCTL_RSTPDWNMODULE; 334 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 335 336 udelay(100); 337 if (restore) { 338 ret = dwc2_restore_global_registers(hsotg); 339 if (ret) { 340 dev_err(hsotg->dev, "%s: failed to restore registers\n", 341 __func__); 342 return ret; 343 } 344 if (dwc2_is_host_mode(hsotg)) { 345 ret = dwc2_restore_host_registers(hsotg); 346 if (ret) { 347 dev_err(hsotg->dev, "%s: failed to restore host registers\n", 348 __func__); 349 return ret; 350 } 351 } else { 352 ret = dwc2_restore_device_registers(hsotg); 353 if (ret) { 354 dev_err(hsotg->dev, "%s: failed to restore device registers\n", 355 __func__); 356 return ret; 357 } 358 } 359 } 360 361 return ret; 362 } 363 364 /** 365 * dwc2_enter_hibernation() - Put controller in Partial Power Down. 366 * 367 * @hsotg: Programming view of the DWC_otg controller 368 */ 369 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg) 370 { 371 u32 pcgcctl; 372 int ret = 0; 373 374 if (!hsotg->core_params->hibernation) 375 return -ENOTSUPP; 376 377 /* Backup all registers */ 378 ret = dwc2_backup_global_registers(hsotg); 379 if (ret) { 380 dev_err(hsotg->dev, "%s: failed to backup global registers\n", 381 __func__); 382 return ret; 383 } 384 385 if (dwc2_is_host_mode(hsotg)) { 386 ret = dwc2_backup_host_registers(hsotg); 387 if (ret) { 388 dev_err(hsotg->dev, "%s: failed to backup host registers\n", 389 __func__); 390 return ret; 391 } 392 } else { 393 ret = dwc2_backup_device_registers(hsotg); 394 if (ret) { 395 dev_err(hsotg->dev, "%s: failed to backup device registers\n", 396 __func__); 397 return ret; 398 } 399 } 400 401 /* 402 * Clear any pending interrupts since dwc2 will not be able to 403 * clear them after entering hibernation. 404 */ 405 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 406 407 /* Put the controller in low power state */ 408 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 409 410 pcgcctl |= PCGCTL_PWRCLMP; 411 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 412 ndelay(20); 413 414 pcgcctl |= PCGCTL_RSTPDWNMODULE; 415 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 416 ndelay(20); 417 418 pcgcctl |= PCGCTL_STOPPCLK; 419 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 420 421 return ret; 422 } 423 424 /** 425 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts, 426 * used in both device and host modes 427 * 428 * @hsotg: Programming view of the DWC_otg controller 429 */ 430 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg) 431 { 432 u32 intmsk; 433 434 /* Clear any pending OTG Interrupts */ 435 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); 436 437 /* Clear any pending interrupts */ 438 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 439 440 /* Enable the interrupts in the GINTMSK */ 441 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT; 442 443 if (hsotg->core_params->dma_enable <= 0) 444 intmsk |= GINTSTS_RXFLVL; 445 if (hsotg->core_params->external_id_pin_ctl <= 0) 446 intmsk |= GINTSTS_CONIDSTSCHNG; 447 448 intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP | 449 GINTSTS_SESSREQINT; 450 451 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 452 } 453 454 /* 455 * Initializes the FSLSPClkSel field of the HCFG register depending on the 456 * PHY type 457 */ 458 static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg) 459 { 460 u32 hcfg, val; 461 462 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && 463 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && 464 hsotg->core_params->ulpi_fs_ls > 0) || 465 hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) { 466 /* Full speed PHY */ 467 val = HCFG_FSLSPCLKSEL_48_MHZ; 468 } else { 469 /* High speed PHY running at full speed or high speed */ 470 val = HCFG_FSLSPCLKSEL_30_60_MHZ; 471 } 472 473 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); 474 hcfg = dwc2_readl(hsotg->regs + HCFG); 475 hcfg &= ~HCFG_FSLSPCLKSEL_MASK; 476 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT; 477 dwc2_writel(hcfg, hsotg->regs + HCFG); 478 } 479 480 /* 481 * Do core a soft reset of the core. Be careful with this because it 482 * resets all the internal state machines of the core. 483 */ 484 int dwc2_core_reset(struct dwc2_hsotg *hsotg) 485 { 486 u32 greset; 487 int count = 0; 488 489 dev_vdbg(hsotg->dev, "%s()\n", __func__); 490 491 /* Core Soft Reset */ 492 greset = dwc2_readl(hsotg->regs + GRSTCTL); 493 greset |= GRSTCTL_CSFTRST; 494 dwc2_writel(greset, hsotg->regs + GRSTCTL); 495 do { 496 udelay(1); 497 greset = dwc2_readl(hsotg->regs + GRSTCTL); 498 if (++count > 50) { 499 dev_warn(hsotg->dev, 500 "%s() HANG! Soft Reset GRSTCTL=%0x\n", 501 __func__, greset); 502 return -EBUSY; 503 } 504 } while (greset & GRSTCTL_CSFTRST); 505 506 /* Wait for AHB master IDLE state */ 507 count = 0; 508 do { 509 udelay(1); 510 greset = dwc2_readl(hsotg->regs + GRSTCTL); 511 if (++count > 50) { 512 dev_warn(hsotg->dev, 513 "%s() HANG! AHB Idle GRSTCTL=%0x\n", 514 __func__, greset); 515 return -EBUSY; 516 } 517 } while (!(greset & GRSTCTL_AHBIDLE)); 518 519 return 0; 520 } 521 522 /* 523 * Force the mode of the controller. 524 * 525 * Forcing the mode is needed for two cases: 526 * 527 * 1) If the dr_mode is set to either HOST or PERIPHERAL we force the 528 * controller to stay in a particular mode regardless of ID pin 529 * changes. We do this usually after a core reset. 530 * 531 * 2) During probe we want to read reset values of the hw 532 * configuration registers that are only available in either host or 533 * device mode. We may need to force the mode if the current mode does 534 * not allow us to access the register in the mode that we want. 535 * 536 * In either case it only makes sense to force the mode if the 537 * controller hardware is OTG capable. 538 * 539 * Checks are done in this function to determine whether doing a force 540 * would be valid or not. 541 * 542 * If a force is done, it requires a 25ms delay to take effect. 543 * 544 * Returns true if the mode was forced. 545 */ 546 static bool dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host) 547 { 548 u32 gusbcfg; 549 u32 set; 550 u32 clear; 551 552 dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device"); 553 554 /* 555 * Force mode has no effect if the hardware is not OTG. 556 */ 557 if (!dwc2_hw_is_otg(hsotg)) 558 return false; 559 560 /* 561 * If dr_mode is either peripheral or host only, there is no 562 * need to ever force the mode to the opposite mode. 563 */ 564 if (WARN_ON(host && hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)) 565 return false; 566 567 if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST)) 568 return false; 569 570 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 571 572 set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE; 573 clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE; 574 575 gusbcfg &= ~clear; 576 gusbcfg |= set; 577 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); 578 579 msleep(25); 580 return true; 581 } 582 583 /* 584 * Clears the force mode bits. 585 */ 586 static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg) 587 { 588 u32 gusbcfg; 589 590 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 591 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE; 592 gusbcfg &= ~GUSBCFG_FORCEDEVMODE; 593 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); 594 595 /* 596 * NOTE: This long sleep is _very_ important, otherwise the core will 597 * not stay in host mode after a connector ID change! 598 */ 599 msleep(25); 600 } 601 602 /* 603 * Sets or clears force mode based on the dr_mode parameter. 604 */ 605 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg) 606 { 607 switch (hsotg->dr_mode) { 608 case USB_DR_MODE_HOST: 609 dwc2_force_mode(hsotg, true); 610 break; 611 case USB_DR_MODE_PERIPHERAL: 612 dwc2_force_mode(hsotg, false); 613 break; 614 case USB_DR_MODE_OTG: 615 dwc2_clear_force_mode(hsotg); 616 break; 617 default: 618 dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n", 619 __func__, hsotg->dr_mode); 620 break; 621 } 622 } 623 624 /* 625 * Do core a soft reset of the core. Be careful with this because it 626 * resets all the internal state machines of the core. 627 * 628 * Additionally this will apply force mode as per the hsotg->dr_mode 629 * parameter. 630 */ 631 int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg) 632 { 633 int retval; 634 635 retval = dwc2_core_reset(hsotg); 636 if (retval) 637 return retval; 638 639 dwc2_force_dr_mode(hsotg); 640 return 0; 641 } 642 643 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 644 { 645 u32 usbcfg, i2cctl; 646 int retval = 0; 647 648 /* 649 * core_init() is now called on every switch so only call the 650 * following for the first time through 651 */ 652 if (select_phy) { 653 dev_dbg(hsotg->dev, "FS PHY selected\n"); 654 655 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 656 if (!(usbcfg & GUSBCFG_PHYSEL)) { 657 usbcfg |= GUSBCFG_PHYSEL; 658 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 659 660 /* Reset after a PHY select */ 661 retval = dwc2_core_reset_and_force_dr_mode(hsotg); 662 663 if (retval) { 664 dev_err(hsotg->dev, 665 "%s: Reset failed, aborting", __func__); 666 return retval; 667 } 668 } 669 } 670 671 /* 672 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also 673 * do this on HNP Dev/Host mode switches (done in dev_init and 674 * host_init). 675 */ 676 if (dwc2_is_host_mode(hsotg)) 677 dwc2_init_fs_ls_pclk_sel(hsotg); 678 679 if (hsotg->core_params->i2c_enable > 0) { 680 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n"); 681 682 /* Program GUSBCFG.OtgUtmiFsSel to I2C */ 683 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 684 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL; 685 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 686 687 /* Program GI2CCTL.I2CEn */ 688 i2cctl = dwc2_readl(hsotg->regs + GI2CCTL); 689 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK; 690 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT; 691 i2cctl &= ~GI2CCTL_I2CEN; 692 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL); 693 i2cctl |= GI2CCTL_I2CEN; 694 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL); 695 } 696 697 return retval; 698 } 699 700 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 701 { 702 u32 usbcfg, usbcfg_old; 703 int retval = 0; 704 705 if (!select_phy) 706 return 0; 707 708 usbcfg = usbcfg_old = dwc2_readl(hsotg->regs + GUSBCFG); 709 710 /* 711 * HS PHY parameters. These parameters are preserved during soft reset 712 * so only program the first time. Do a soft reset immediately after 713 * setting phyif. 714 */ 715 switch (hsotg->core_params->phy_type) { 716 case DWC2_PHY_TYPE_PARAM_ULPI: 717 /* ULPI interface */ 718 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n"); 719 usbcfg |= GUSBCFG_ULPI_UTMI_SEL; 720 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL); 721 if (hsotg->core_params->phy_ulpi_ddr > 0) 722 usbcfg |= GUSBCFG_DDRSEL; 723 break; 724 case DWC2_PHY_TYPE_PARAM_UTMI: 725 /* UTMI+ interface */ 726 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n"); 727 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16); 728 if (hsotg->core_params->phy_utmi_width == 16) 729 usbcfg |= GUSBCFG_PHYIF16; 730 break; 731 default: 732 dev_err(hsotg->dev, "FS PHY selected at HS!\n"); 733 break; 734 } 735 736 if (usbcfg != usbcfg_old) { 737 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 738 739 /* Reset after setting the PHY parameters */ 740 retval = dwc2_core_reset_and_force_dr_mode(hsotg); 741 if (retval) { 742 dev_err(hsotg->dev, 743 "%s: Reset failed, aborting", __func__); 744 return retval; 745 } 746 } 747 748 return retval; 749 } 750 751 static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 752 { 753 u32 usbcfg; 754 int retval = 0; 755 756 if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL && 757 hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) { 758 /* If FS mode with FS PHY */ 759 retval = dwc2_fs_phy_init(hsotg, select_phy); 760 if (retval) 761 return retval; 762 } else { 763 /* High speed PHY */ 764 retval = dwc2_hs_phy_init(hsotg, select_phy); 765 if (retval) 766 return retval; 767 } 768 769 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && 770 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && 771 hsotg->core_params->ulpi_fs_ls > 0) { 772 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n"); 773 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 774 usbcfg |= GUSBCFG_ULPI_FS_LS; 775 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M; 776 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 777 } else { 778 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 779 usbcfg &= ~GUSBCFG_ULPI_FS_LS; 780 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M; 781 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 782 } 783 784 return retval; 785 } 786 787 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) 788 { 789 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 790 791 switch (hsotg->hw_params.arch) { 792 case GHWCFG2_EXT_DMA_ARCH: 793 dev_err(hsotg->dev, "External DMA Mode not supported\n"); 794 return -EINVAL; 795 796 case GHWCFG2_INT_DMA_ARCH: 797 dev_dbg(hsotg->dev, "Internal DMA Mode\n"); 798 if (hsotg->core_params->ahbcfg != -1) { 799 ahbcfg &= GAHBCFG_CTRL_MASK; 800 ahbcfg |= hsotg->core_params->ahbcfg & 801 ~GAHBCFG_CTRL_MASK; 802 } 803 break; 804 805 case GHWCFG2_SLAVE_ONLY_ARCH: 806 default: 807 dev_dbg(hsotg->dev, "Slave Only Mode\n"); 808 break; 809 } 810 811 dev_dbg(hsotg->dev, "dma_enable:%d dma_desc_enable:%d\n", 812 hsotg->core_params->dma_enable, 813 hsotg->core_params->dma_desc_enable); 814 815 if (hsotg->core_params->dma_enable > 0) { 816 if (hsotg->core_params->dma_desc_enable > 0) 817 dev_dbg(hsotg->dev, "Using Descriptor DMA mode\n"); 818 else 819 dev_dbg(hsotg->dev, "Using Buffer DMA mode\n"); 820 } else { 821 dev_dbg(hsotg->dev, "Using Slave mode\n"); 822 hsotg->core_params->dma_desc_enable = 0; 823 } 824 825 if (hsotg->core_params->dma_enable > 0) 826 ahbcfg |= GAHBCFG_DMA_EN; 827 828 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 829 830 return 0; 831 } 832 833 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg) 834 { 835 u32 usbcfg; 836 837 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 838 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP); 839 840 switch (hsotg->hw_params.op_mode) { 841 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 842 if (hsotg->core_params->otg_cap == 843 DWC2_CAP_PARAM_HNP_SRP_CAPABLE) 844 usbcfg |= GUSBCFG_HNPCAP; 845 if (hsotg->core_params->otg_cap != 846 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE) 847 usbcfg |= GUSBCFG_SRPCAP; 848 break; 849 850 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 851 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 852 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 853 if (hsotg->core_params->otg_cap != 854 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE) 855 usbcfg |= GUSBCFG_SRPCAP; 856 break; 857 858 case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE: 859 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE: 860 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST: 861 default: 862 break; 863 } 864 865 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 866 } 867 868 /** 869 * dwc2_core_init() - Initializes the DWC_otg controller registers and 870 * prepares the core for device mode or host mode operation 871 * 872 * @hsotg: Programming view of the DWC_otg controller 873 * @initial_setup: If true then this is the first init for this instance. 874 */ 875 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) 876 { 877 u32 usbcfg, otgctl; 878 int retval; 879 880 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 881 882 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 883 884 /* Set ULPI External VBUS bit if needed */ 885 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV; 886 if (hsotg->core_params->phy_ulpi_ext_vbus == 887 DWC2_PHY_ULPI_EXTERNAL_VBUS) 888 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV; 889 890 /* Set external TS Dline pulsing bit if needed */ 891 usbcfg &= ~GUSBCFG_TERMSELDLPULSE; 892 if (hsotg->core_params->ts_dline > 0) 893 usbcfg |= GUSBCFG_TERMSELDLPULSE; 894 895 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 896 897 /* 898 * Reset the Controller 899 * 900 * We only need to reset the controller if this is a re-init. 901 * For the first init we know for sure that earlier code reset us (it 902 * needed to in order to properly detect various parameters). 903 */ 904 if (!initial_setup) { 905 retval = dwc2_core_reset_and_force_dr_mode(hsotg); 906 if (retval) { 907 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n", 908 __func__); 909 return retval; 910 } 911 } 912 913 /* 914 * This needs to happen in FS mode before any other programming occurs 915 */ 916 retval = dwc2_phy_init(hsotg, initial_setup); 917 if (retval) 918 return retval; 919 920 /* Program the GAHBCFG Register */ 921 retval = dwc2_gahbcfg_init(hsotg); 922 if (retval) 923 return retval; 924 925 /* Program the GUSBCFG register */ 926 dwc2_gusbcfg_init(hsotg); 927 928 /* Program the GOTGCTL register */ 929 otgctl = dwc2_readl(hsotg->regs + GOTGCTL); 930 otgctl &= ~GOTGCTL_OTGVER; 931 if (hsotg->core_params->otg_ver > 0) 932 otgctl |= GOTGCTL_OTGVER; 933 dwc2_writel(otgctl, hsotg->regs + GOTGCTL); 934 dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->core_params->otg_ver); 935 936 /* Clear the SRP success bit for FS-I2c */ 937 hsotg->srp_success = 0; 938 939 /* Enable common interrupts */ 940 dwc2_enable_common_interrupts(hsotg); 941 942 /* 943 * Do device or host initialization based on mode during PCD and 944 * HCD initialization 945 */ 946 if (dwc2_is_host_mode(hsotg)) { 947 dev_dbg(hsotg->dev, "Host Mode\n"); 948 hsotg->op_state = OTG_STATE_A_HOST; 949 } else { 950 dev_dbg(hsotg->dev, "Device Mode\n"); 951 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 952 } 953 954 return 0; 955 } 956 957 /** 958 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts 959 * 960 * @hsotg: Programming view of DWC_otg controller 961 */ 962 void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg) 963 { 964 u32 intmsk; 965 966 dev_dbg(hsotg->dev, "%s()\n", __func__); 967 968 /* Disable all interrupts */ 969 dwc2_writel(0, hsotg->regs + GINTMSK); 970 dwc2_writel(0, hsotg->regs + HAINTMSK); 971 972 /* Enable the common interrupts */ 973 dwc2_enable_common_interrupts(hsotg); 974 975 /* Enable host mode interrupts without disturbing common interrupts */ 976 intmsk = dwc2_readl(hsotg->regs + GINTMSK); 977 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT; 978 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 979 } 980 981 /** 982 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts 983 * 984 * @hsotg: Programming view of DWC_otg controller 985 */ 986 void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg) 987 { 988 u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK); 989 990 /* Disable host mode interrupts without disturbing common interrupts */ 991 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT | 992 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT); 993 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 994 } 995 996 /* 997 * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size 998 * For system that have a total fifo depth that is smaller than the default 999 * RX + TX fifo size. 1000 * 1001 * @hsotg: Programming view of DWC_otg controller 1002 */ 1003 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg) 1004 { 1005 struct dwc2_core_params *params = hsotg->core_params; 1006 struct dwc2_hw_params *hw = &hsotg->hw_params; 1007 u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size; 1008 1009 total_fifo_size = hw->total_fifo_size; 1010 rxfsiz = params->host_rx_fifo_size; 1011 nptxfsiz = params->host_nperio_tx_fifo_size; 1012 ptxfsiz = params->host_perio_tx_fifo_size; 1013 1014 /* 1015 * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth 1016 * allocation with support for high bandwidth endpoints. Synopsys 1017 * defines MPS(Max Packet size) for a periodic EP=1024, and for 1018 * non-periodic as 512. 1019 */ 1020 if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) { 1021 /* 1022 * For Buffer DMA mode/Scatter Gather DMA mode 1023 * 2 * ((Largest Packet size / 4) + 1 + 1) + n 1024 * with n = number of host channel. 1025 * 2 * ((1024/4) + 2) = 516 1026 */ 1027 rxfsiz = 516 + hw->host_channels; 1028 1029 /* 1030 * min non-periodic tx fifo depth 1031 * 2 * (largest non-periodic USB packet used / 4) 1032 * 2 * (512/4) = 256 1033 */ 1034 nptxfsiz = 256; 1035 1036 /* 1037 * min periodic tx fifo depth 1038 * (largest packet size*MC)/4 1039 * (1024 * 3)/4 = 768 1040 */ 1041 ptxfsiz = 768; 1042 1043 params->host_rx_fifo_size = rxfsiz; 1044 params->host_nperio_tx_fifo_size = nptxfsiz; 1045 params->host_perio_tx_fifo_size = ptxfsiz; 1046 } 1047 1048 /* 1049 * If the summation of RX, NPTX and PTX fifo sizes is still 1050 * bigger than the total_fifo_size, then we have a problem. 1051 * 1052 * We won't be able to allocate as many endpoints. Right now, 1053 * we're just printing an error message, but ideally this FIFO 1054 * allocation algorithm would be improved in the future. 1055 * 1056 * FIXME improve this FIFO allocation algorithm. 1057 */ 1058 if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz))) 1059 dev_err(hsotg->dev, "invalid fifo sizes\n"); 1060 } 1061 1062 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg) 1063 { 1064 struct dwc2_core_params *params = hsotg->core_params; 1065 u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz; 1066 1067 if (!params->enable_dynamic_fifo) 1068 return; 1069 1070 dwc2_calculate_dynamic_fifo(hsotg); 1071 1072 /* Rx FIFO */ 1073 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); 1074 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz); 1075 grxfsiz &= ~GRXFSIZ_DEPTH_MASK; 1076 grxfsiz |= params->host_rx_fifo_size << 1077 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK; 1078 dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ); 1079 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", 1080 dwc2_readl(hsotg->regs + GRXFSIZ)); 1081 1082 /* Non-periodic Tx FIFO */ 1083 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n", 1084 dwc2_readl(hsotg->regs + GNPTXFSIZ)); 1085 nptxfsiz = params->host_nperio_tx_fifo_size << 1086 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; 1087 nptxfsiz |= params->host_rx_fifo_size << 1088 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; 1089 dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ); 1090 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n", 1091 dwc2_readl(hsotg->regs + GNPTXFSIZ)); 1092 1093 /* Periodic Tx FIFO */ 1094 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n", 1095 dwc2_readl(hsotg->regs + HPTXFSIZ)); 1096 hptxfsiz = params->host_perio_tx_fifo_size << 1097 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; 1098 hptxfsiz |= (params->host_rx_fifo_size + 1099 params->host_nperio_tx_fifo_size) << 1100 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; 1101 dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ); 1102 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n", 1103 dwc2_readl(hsotg->regs + HPTXFSIZ)); 1104 1105 if (hsotg->core_params->en_multiple_tx_fifo > 0 && 1106 hsotg->hw_params.snpsid <= DWC2_CORE_REV_2_94a) { 1107 /* 1108 * Global DFIFOCFG calculation for Host mode - 1109 * include RxFIFO, NPTXFIFO and HPTXFIFO 1110 */ 1111 dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG); 1112 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK; 1113 dfifocfg |= (params->host_rx_fifo_size + 1114 params->host_nperio_tx_fifo_size + 1115 params->host_perio_tx_fifo_size) << 1116 GDFIFOCFG_EPINFOBASE_SHIFT & 1117 GDFIFOCFG_EPINFOBASE_MASK; 1118 dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG); 1119 } 1120 } 1121 1122 /** 1123 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for 1124 * Host mode 1125 * 1126 * @hsotg: Programming view of DWC_otg controller 1127 * 1128 * This function flushes the Tx and Rx FIFOs and flushes any entries in the 1129 * request queues. Host channels are reset to ensure that they are ready for 1130 * performing transfers. 1131 */ 1132 void dwc2_core_host_init(struct dwc2_hsotg *hsotg) 1133 { 1134 u32 hcfg, hfir, otgctl; 1135 1136 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 1137 1138 /* Restart the Phy Clock */ 1139 dwc2_writel(0, hsotg->regs + PCGCTL); 1140 1141 /* Initialize Host Configuration Register */ 1142 dwc2_init_fs_ls_pclk_sel(hsotg); 1143 if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL) { 1144 hcfg = dwc2_readl(hsotg->regs + HCFG); 1145 hcfg |= HCFG_FSLSSUPP; 1146 dwc2_writel(hcfg, hsotg->regs + HCFG); 1147 } 1148 1149 /* 1150 * This bit allows dynamic reloading of the HFIR register during 1151 * runtime. This bit needs to be programmed during initial configuration 1152 * and its value must not be changed during runtime. 1153 */ 1154 if (hsotg->core_params->reload_ctl > 0) { 1155 hfir = dwc2_readl(hsotg->regs + HFIR); 1156 hfir |= HFIR_RLDCTRL; 1157 dwc2_writel(hfir, hsotg->regs + HFIR); 1158 } 1159 1160 if (hsotg->core_params->dma_desc_enable > 0) { 1161 u32 op_mode = hsotg->hw_params.op_mode; 1162 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a || 1163 !hsotg->hw_params.dma_desc_enable || 1164 op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE || 1165 op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE || 1166 op_mode == GHWCFG2_OP_MODE_UNDEFINED) { 1167 dev_err(hsotg->dev, 1168 "Hardware does not support descriptor DMA mode -\n"); 1169 dev_err(hsotg->dev, 1170 "falling back to buffer DMA mode.\n"); 1171 hsotg->core_params->dma_desc_enable = 0; 1172 } else { 1173 hcfg = dwc2_readl(hsotg->regs + HCFG); 1174 hcfg |= HCFG_DESCDMA; 1175 dwc2_writel(hcfg, hsotg->regs + HCFG); 1176 } 1177 } 1178 1179 /* Configure data FIFO sizes */ 1180 dwc2_config_fifos(hsotg); 1181 1182 /* TODO - check this */ 1183 /* Clear Host Set HNP Enable in the OTG Control Register */ 1184 otgctl = dwc2_readl(hsotg->regs + GOTGCTL); 1185 otgctl &= ~GOTGCTL_HSTSETHNPEN; 1186 dwc2_writel(otgctl, hsotg->regs + GOTGCTL); 1187 1188 /* Make sure the FIFOs are flushed */ 1189 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */); 1190 dwc2_flush_rx_fifo(hsotg); 1191 1192 /* Clear Host Set HNP Enable in the OTG Control Register */ 1193 otgctl = dwc2_readl(hsotg->regs + GOTGCTL); 1194 otgctl &= ~GOTGCTL_HSTSETHNPEN; 1195 dwc2_writel(otgctl, hsotg->regs + GOTGCTL); 1196 1197 if (hsotg->core_params->dma_desc_enable <= 0) { 1198 int num_channels, i; 1199 u32 hcchar; 1200 1201 /* Flush out any leftover queued requests */ 1202 num_channels = hsotg->core_params->host_channels; 1203 for (i = 0; i < num_channels; i++) { 1204 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 1205 hcchar &= ~HCCHAR_CHENA; 1206 hcchar |= HCCHAR_CHDIS; 1207 hcchar &= ~HCCHAR_EPDIR; 1208 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 1209 } 1210 1211 /* Halt all channels to put them into a known state */ 1212 for (i = 0; i < num_channels; i++) { 1213 int count = 0; 1214 1215 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 1216 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS; 1217 hcchar &= ~HCCHAR_EPDIR; 1218 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 1219 dev_dbg(hsotg->dev, "%s: Halt channel %d\n", 1220 __func__, i); 1221 do { 1222 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 1223 if (++count > 1000) { 1224 dev_err(hsotg->dev, 1225 "Unable to clear enable on channel %d\n", 1226 i); 1227 break; 1228 } 1229 udelay(1); 1230 } while (hcchar & HCCHAR_CHENA); 1231 } 1232 } 1233 1234 /* Turn on the vbus power */ 1235 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state); 1236 if (hsotg->op_state == OTG_STATE_A_HOST) { 1237 u32 hprt0 = dwc2_read_hprt0(hsotg); 1238 1239 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n", 1240 !!(hprt0 & HPRT0_PWR)); 1241 if (!(hprt0 & HPRT0_PWR)) { 1242 hprt0 |= HPRT0_PWR; 1243 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1244 } 1245 } 1246 1247 dwc2_enable_host_interrupts(hsotg); 1248 } 1249 1250 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg, 1251 struct dwc2_host_chan *chan) 1252 { 1253 u32 hcintmsk = HCINTMSK_CHHLTD; 1254 1255 switch (chan->ep_type) { 1256 case USB_ENDPOINT_XFER_CONTROL: 1257 case USB_ENDPOINT_XFER_BULK: 1258 dev_vdbg(hsotg->dev, "control/bulk\n"); 1259 hcintmsk |= HCINTMSK_XFERCOMPL; 1260 hcintmsk |= HCINTMSK_STALL; 1261 hcintmsk |= HCINTMSK_XACTERR; 1262 hcintmsk |= HCINTMSK_DATATGLERR; 1263 if (chan->ep_is_in) { 1264 hcintmsk |= HCINTMSK_BBLERR; 1265 } else { 1266 hcintmsk |= HCINTMSK_NAK; 1267 hcintmsk |= HCINTMSK_NYET; 1268 if (chan->do_ping) 1269 hcintmsk |= HCINTMSK_ACK; 1270 } 1271 1272 if (chan->do_split) { 1273 hcintmsk |= HCINTMSK_NAK; 1274 if (chan->complete_split) 1275 hcintmsk |= HCINTMSK_NYET; 1276 else 1277 hcintmsk |= HCINTMSK_ACK; 1278 } 1279 1280 if (chan->error_state) 1281 hcintmsk |= HCINTMSK_ACK; 1282 break; 1283 1284 case USB_ENDPOINT_XFER_INT: 1285 if (dbg_perio()) 1286 dev_vdbg(hsotg->dev, "intr\n"); 1287 hcintmsk |= HCINTMSK_XFERCOMPL; 1288 hcintmsk |= HCINTMSK_NAK; 1289 hcintmsk |= HCINTMSK_STALL; 1290 hcintmsk |= HCINTMSK_XACTERR; 1291 hcintmsk |= HCINTMSK_DATATGLERR; 1292 hcintmsk |= HCINTMSK_FRMOVRUN; 1293 1294 if (chan->ep_is_in) 1295 hcintmsk |= HCINTMSK_BBLERR; 1296 if (chan->error_state) 1297 hcintmsk |= HCINTMSK_ACK; 1298 if (chan->do_split) { 1299 if (chan->complete_split) 1300 hcintmsk |= HCINTMSK_NYET; 1301 else 1302 hcintmsk |= HCINTMSK_ACK; 1303 } 1304 break; 1305 1306 case USB_ENDPOINT_XFER_ISOC: 1307 if (dbg_perio()) 1308 dev_vdbg(hsotg->dev, "isoc\n"); 1309 hcintmsk |= HCINTMSK_XFERCOMPL; 1310 hcintmsk |= HCINTMSK_FRMOVRUN; 1311 hcintmsk |= HCINTMSK_ACK; 1312 1313 if (chan->ep_is_in) { 1314 hcintmsk |= HCINTMSK_XACTERR; 1315 hcintmsk |= HCINTMSK_BBLERR; 1316 } 1317 break; 1318 default: 1319 dev_err(hsotg->dev, "## Unknown EP type ##\n"); 1320 break; 1321 } 1322 1323 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); 1324 if (dbg_hc(chan)) 1325 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); 1326 } 1327 1328 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg, 1329 struct dwc2_host_chan *chan) 1330 { 1331 u32 hcintmsk = HCINTMSK_CHHLTD; 1332 1333 /* 1334 * For Descriptor DMA mode core halts the channel on AHB error. 1335 * Interrupt is not required. 1336 */ 1337 if (hsotg->core_params->dma_desc_enable <= 0) { 1338 if (dbg_hc(chan)) 1339 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); 1340 hcintmsk |= HCINTMSK_AHBERR; 1341 } else { 1342 if (dbg_hc(chan)) 1343 dev_vdbg(hsotg->dev, "desc DMA enabled\n"); 1344 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1345 hcintmsk |= HCINTMSK_XFERCOMPL; 1346 } 1347 1348 if (chan->error_state && !chan->do_split && 1349 chan->ep_type != USB_ENDPOINT_XFER_ISOC) { 1350 if (dbg_hc(chan)) 1351 dev_vdbg(hsotg->dev, "setting ACK\n"); 1352 hcintmsk |= HCINTMSK_ACK; 1353 if (chan->ep_is_in) { 1354 hcintmsk |= HCINTMSK_DATATGLERR; 1355 if (chan->ep_type != USB_ENDPOINT_XFER_INT) 1356 hcintmsk |= HCINTMSK_NAK; 1357 } 1358 } 1359 1360 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); 1361 if (dbg_hc(chan)) 1362 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); 1363 } 1364 1365 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg, 1366 struct dwc2_host_chan *chan) 1367 { 1368 u32 intmsk; 1369 1370 if (hsotg->core_params->dma_enable > 0) { 1371 if (dbg_hc(chan)) 1372 dev_vdbg(hsotg->dev, "DMA enabled\n"); 1373 dwc2_hc_enable_dma_ints(hsotg, chan); 1374 } else { 1375 if (dbg_hc(chan)) 1376 dev_vdbg(hsotg->dev, "DMA disabled\n"); 1377 dwc2_hc_enable_slave_ints(hsotg, chan); 1378 } 1379 1380 /* Enable the top level host channel interrupt */ 1381 intmsk = dwc2_readl(hsotg->regs + HAINTMSK); 1382 intmsk |= 1 << chan->hc_num; 1383 dwc2_writel(intmsk, hsotg->regs + HAINTMSK); 1384 if (dbg_hc(chan)) 1385 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk); 1386 1387 /* Make sure host channel interrupts are enabled */ 1388 intmsk = dwc2_readl(hsotg->regs + GINTMSK); 1389 intmsk |= GINTSTS_HCHINT; 1390 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 1391 if (dbg_hc(chan)) 1392 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk); 1393 } 1394 1395 /** 1396 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from 1397 * a specific endpoint 1398 * 1399 * @hsotg: Programming view of DWC_otg controller 1400 * @chan: Information needed to initialize the host channel 1401 * 1402 * The HCCHARn register is set up with the characteristics specified in chan. 1403 * Host channel interrupts that may need to be serviced while this transfer is 1404 * in progress are enabled. 1405 */ 1406 void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 1407 { 1408 u8 hc_num = chan->hc_num; 1409 u32 hcintmsk; 1410 u32 hcchar; 1411 u32 hcsplt = 0; 1412 1413 if (dbg_hc(chan)) 1414 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1415 1416 /* Clear old interrupt conditions for this host channel */ 1417 hcintmsk = 0xffffffff; 1418 hcintmsk &= ~HCINTMSK_RESERVED14_31; 1419 dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num)); 1420 1421 /* Enable channel interrupts required for this transfer */ 1422 dwc2_hc_enable_ints(hsotg, chan); 1423 1424 /* 1425 * Program the HCCHARn register with the endpoint characteristics for 1426 * the current transfer 1427 */ 1428 hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK; 1429 hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK; 1430 if (chan->ep_is_in) 1431 hcchar |= HCCHAR_EPDIR; 1432 if (chan->speed == USB_SPEED_LOW) 1433 hcchar |= HCCHAR_LSPDDEV; 1434 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK; 1435 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK; 1436 dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num)); 1437 if (dbg_hc(chan)) { 1438 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n", 1439 hc_num, hcchar); 1440 1441 dev_vdbg(hsotg->dev, "%s: Channel %d\n", 1442 __func__, hc_num); 1443 dev_vdbg(hsotg->dev, " Dev Addr: %d\n", 1444 chan->dev_addr); 1445 dev_vdbg(hsotg->dev, " Ep Num: %d\n", 1446 chan->ep_num); 1447 dev_vdbg(hsotg->dev, " Is In: %d\n", 1448 chan->ep_is_in); 1449 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n", 1450 chan->speed == USB_SPEED_LOW); 1451 dev_vdbg(hsotg->dev, " Ep Type: %d\n", 1452 chan->ep_type); 1453 dev_vdbg(hsotg->dev, " Max Pkt: %d\n", 1454 chan->max_packet); 1455 } 1456 1457 /* Program the HCSPLT register for SPLITs */ 1458 if (chan->do_split) { 1459 if (dbg_hc(chan)) 1460 dev_vdbg(hsotg->dev, 1461 "Programming HC %d with split --> %s\n", 1462 hc_num, 1463 chan->complete_split ? "CSPLIT" : "SSPLIT"); 1464 if (chan->complete_split) 1465 hcsplt |= HCSPLT_COMPSPLT; 1466 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT & 1467 HCSPLT_XACTPOS_MASK; 1468 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT & 1469 HCSPLT_HUBADDR_MASK; 1470 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT & 1471 HCSPLT_PRTADDR_MASK; 1472 if (dbg_hc(chan)) { 1473 dev_vdbg(hsotg->dev, " comp split %d\n", 1474 chan->complete_split); 1475 dev_vdbg(hsotg->dev, " xact pos %d\n", 1476 chan->xact_pos); 1477 dev_vdbg(hsotg->dev, " hub addr %d\n", 1478 chan->hub_addr); 1479 dev_vdbg(hsotg->dev, " hub port %d\n", 1480 chan->hub_port); 1481 dev_vdbg(hsotg->dev, " is_in %d\n", 1482 chan->ep_is_in); 1483 dev_vdbg(hsotg->dev, " Max Pkt %d\n", 1484 chan->max_packet); 1485 dev_vdbg(hsotg->dev, " xferlen %d\n", 1486 chan->xfer_len); 1487 } 1488 } 1489 1490 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num)); 1491 } 1492 1493 /** 1494 * dwc2_hc_halt() - Attempts to halt a host channel 1495 * 1496 * @hsotg: Controller register interface 1497 * @chan: Host channel to halt 1498 * @halt_status: Reason for halting the channel 1499 * 1500 * This function should only be called in Slave mode or to abort a transfer in 1501 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the 1502 * controller halts the channel when the transfer is complete or a condition 1503 * occurs that requires application intervention. 1504 * 1505 * In slave mode, checks for a free request queue entry, then sets the Channel 1506 * Enable and Channel Disable bits of the Host Channel Characteristics 1507 * register of the specified channel to intiate the halt. If there is no free 1508 * request queue entry, sets only the Channel Disable bit of the HCCHARn 1509 * register to flush requests for this channel. In the latter case, sets a 1510 * flag to indicate that the host channel needs to be halted when a request 1511 * queue slot is open. 1512 * 1513 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the 1514 * HCCHARn register. The controller ensures there is space in the request 1515 * queue before submitting the halt request. 1516 * 1517 * Some time may elapse before the core flushes any posted requests for this 1518 * host channel and halts. The Channel Halted interrupt handler completes the 1519 * deactivation of the host channel. 1520 */ 1521 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 1522 enum dwc2_halt_status halt_status) 1523 { 1524 u32 nptxsts, hptxsts, hcchar; 1525 1526 if (dbg_hc(chan)) 1527 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1528 if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS) 1529 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status); 1530 1531 if (halt_status == DWC2_HC_XFER_URB_DEQUEUE || 1532 halt_status == DWC2_HC_XFER_AHB_ERR) { 1533 /* 1534 * Disable all channel interrupts except Ch Halted. The QTD 1535 * and QH state associated with this transfer has been cleared 1536 * (in the case of URB_DEQUEUE), so the channel needs to be 1537 * shut down carefully to prevent crashes. 1538 */ 1539 u32 hcintmsk = HCINTMSK_CHHLTD; 1540 1541 dev_vdbg(hsotg->dev, "dequeue/error\n"); 1542 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); 1543 1544 /* 1545 * Make sure no other interrupts besides halt are currently 1546 * pending. Handling another interrupt could cause a crash due 1547 * to the QTD and QH state. 1548 */ 1549 dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num)); 1550 1551 /* 1552 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR 1553 * even if the channel was already halted for some other 1554 * reason 1555 */ 1556 chan->halt_status = halt_status; 1557 1558 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1559 if (!(hcchar & HCCHAR_CHENA)) { 1560 /* 1561 * The channel is either already halted or it hasn't 1562 * started yet. In DMA mode, the transfer may halt if 1563 * it finishes normally or a condition occurs that 1564 * requires driver intervention. Don't want to halt 1565 * the channel again. In either Slave or DMA mode, 1566 * it's possible that the transfer has been assigned 1567 * to a channel, but not started yet when an URB is 1568 * dequeued. Don't want to halt a channel that hasn't 1569 * started yet. 1570 */ 1571 return; 1572 } 1573 } 1574 if (chan->halt_pending) { 1575 /* 1576 * A halt has already been issued for this channel. This might 1577 * happen when a transfer is aborted by a higher level in 1578 * the stack. 1579 */ 1580 dev_vdbg(hsotg->dev, 1581 "*** %s: Channel %d, chan->halt_pending already set ***\n", 1582 __func__, chan->hc_num); 1583 return; 1584 } 1585 1586 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1587 1588 /* No need to set the bit in DDMA for disabling the channel */ 1589 /* TODO check it everywhere channel is disabled */ 1590 if (hsotg->core_params->dma_desc_enable <= 0) { 1591 if (dbg_hc(chan)) 1592 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); 1593 hcchar |= HCCHAR_CHENA; 1594 } else { 1595 if (dbg_hc(chan)) 1596 dev_dbg(hsotg->dev, "desc DMA enabled\n"); 1597 } 1598 hcchar |= HCCHAR_CHDIS; 1599 1600 if (hsotg->core_params->dma_enable <= 0) { 1601 if (dbg_hc(chan)) 1602 dev_vdbg(hsotg->dev, "DMA not enabled\n"); 1603 hcchar |= HCCHAR_CHENA; 1604 1605 /* Check for space in the request queue to issue the halt */ 1606 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || 1607 chan->ep_type == USB_ENDPOINT_XFER_BULK) { 1608 dev_vdbg(hsotg->dev, "control/bulk\n"); 1609 nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); 1610 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) { 1611 dev_vdbg(hsotg->dev, "Disabling channel\n"); 1612 hcchar &= ~HCCHAR_CHENA; 1613 } 1614 } else { 1615 if (dbg_perio()) 1616 dev_vdbg(hsotg->dev, "isoc/intr\n"); 1617 hptxsts = dwc2_readl(hsotg->regs + HPTXSTS); 1618 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 || 1619 hsotg->queuing_high_bandwidth) { 1620 if (dbg_perio()) 1621 dev_vdbg(hsotg->dev, "Disabling channel\n"); 1622 hcchar &= ~HCCHAR_CHENA; 1623 } 1624 } 1625 } else { 1626 if (dbg_hc(chan)) 1627 dev_vdbg(hsotg->dev, "DMA enabled\n"); 1628 } 1629 1630 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1631 chan->halt_status = halt_status; 1632 1633 if (hcchar & HCCHAR_CHENA) { 1634 if (dbg_hc(chan)) 1635 dev_vdbg(hsotg->dev, "Channel enabled\n"); 1636 chan->halt_pending = 1; 1637 chan->halt_on_queue = 0; 1638 } else { 1639 if (dbg_hc(chan)) 1640 dev_vdbg(hsotg->dev, "Channel disabled\n"); 1641 chan->halt_on_queue = 1; 1642 } 1643 1644 if (dbg_hc(chan)) { 1645 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1646 chan->hc_num); 1647 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n", 1648 hcchar); 1649 dev_vdbg(hsotg->dev, " halt_pending: %d\n", 1650 chan->halt_pending); 1651 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n", 1652 chan->halt_on_queue); 1653 dev_vdbg(hsotg->dev, " halt_status: %d\n", 1654 chan->halt_status); 1655 } 1656 } 1657 1658 /** 1659 * dwc2_hc_cleanup() - Clears the transfer state for a host channel 1660 * 1661 * @hsotg: Programming view of DWC_otg controller 1662 * @chan: Identifies the host channel to clean up 1663 * 1664 * This function is normally called after a transfer is done and the host 1665 * channel is being released 1666 */ 1667 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 1668 { 1669 u32 hcintmsk; 1670 1671 chan->xfer_started = 0; 1672 1673 /* 1674 * Clear channel interrupt enables and any unhandled channel interrupt 1675 * conditions 1676 */ 1677 dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num)); 1678 hcintmsk = 0xffffffff; 1679 hcintmsk &= ~HCINTMSK_RESERVED14_31; 1680 dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num)); 1681 } 1682 1683 /** 1684 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in 1685 * which frame a periodic transfer should occur 1686 * 1687 * @hsotg: Programming view of DWC_otg controller 1688 * @chan: Identifies the host channel to set up and its properties 1689 * @hcchar: Current value of the HCCHAR register for the specified host channel 1690 * 1691 * This function has no effect on non-periodic transfers 1692 */ 1693 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg, 1694 struct dwc2_host_chan *chan, u32 *hcchar) 1695 { 1696 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1697 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1698 /* 1 if _next_ frame is odd, 0 if it's even */ 1699 if (!(dwc2_hcd_get_frame_number(hsotg) & 0x1)) 1700 *hcchar |= HCCHAR_ODDFRM; 1701 } 1702 } 1703 1704 static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan) 1705 { 1706 /* Set up the initial PID for the transfer */ 1707 if (chan->speed == USB_SPEED_HIGH) { 1708 if (chan->ep_is_in) { 1709 if (chan->multi_count == 1) 1710 chan->data_pid_start = DWC2_HC_PID_DATA0; 1711 else if (chan->multi_count == 2) 1712 chan->data_pid_start = DWC2_HC_PID_DATA1; 1713 else 1714 chan->data_pid_start = DWC2_HC_PID_DATA2; 1715 } else { 1716 if (chan->multi_count == 1) 1717 chan->data_pid_start = DWC2_HC_PID_DATA0; 1718 else 1719 chan->data_pid_start = DWC2_HC_PID_MDATA; 1720 } 1721 } else { 1722 chan->data_pid_start = DWC2_HC_PID_DATA0; 1723 } 1724 } 1725 1726 /** 1727 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with 1728 * the Host Channel 1729 * 1730 * @hsotg: Programming view of DWC_otg controller 1731 * @chan: Information needed to initialize the host channel 1732 * 1733 * This function should only be called in Slave mode. For a channel associated 1734 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel 1735 * associated with a periodic EP, the periodic Tx FIFO is written. 1736 * 1737 * Upon return the xfer_buf and xfer_count fields in chan are incremented by 1738 * the number of bytes written to the Tx FIFO. 1739 */ 1740 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg, 1741 struct dwc2_host_chan *chan) 1742 { 1743 u32 i; 1744 u32 remaining_count; 1745 u32 byte_count; 1746 u32 dword_count; 1747 u32 __iomem *data_fifo; 1748 u32 *data_buf = (u32 *)chan->xfer_buf; 1749 1750 if (dbg_hc(chan)) 1751 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1752 1753 data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num)); 1754 1755 remaining_count = chan->xfer_len - chan->xfer_count; 1756 if (remaining_count > chan->max_packet) 1757 byte_count = chan->max_packet; 1758 else 1759 byte_count = remaining_count; 1760 1761 dword_count = (byte_count + 3) / 4; 1762 1763 if (((unsigned long)data_buf & 0x3) == 0) { 1764 /* xfer_buf is DWORD aligned */ 1765 for (i = 0; i < dword_count; i++, data_buf++) 1766 dwc2_writel(*data_buf, data_fifo); 1767 } else { 1768 /* xfer_buf is not DWORD aligned */ 1769 for (i = 0; i < dword_count; i++, data_buf++) { 1770 u32 data = data_buf[0] | data_buf[1] << 8 | 1771 data_buf[2] << 16 | data_buf[3] << 24; 1772 dwc2_writel(data, data_fifo); 1773 } 1774 } 1775 1776 chan->xfer_count += byte_count; 1777 chan->xfer_buf += byte_count; 1778 } 1779 1780 /** 1781 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host 1782 * channel and starts the transfer 1783 * 1784 * @hsotg: Programming view of DWC_otg controller 1785 * @chan: Information needed to initialize the host channel. The xfer_len value 1786 * may be reduced to accommodate the max widths of the XferSize and 1787 * PktCnt fields in the HCTSIZn register. The multi_count value may be 1788 * changed to reflect the final xfer_len value. 1789 * 1790 * This function may be called in either Slave mode or DMA mode. In Slave mode, 1791 * the caller must ensure that there is sufficient space in the request queue 1792 * and Tx Data FIFO. 1793 * 1794 * For an OUT transfer in Slave mode, it loads a data packet into the 1795 * appropriate FIFO. If necessary, additional data packets are loaded in the 1796 * Host ISR. 1797 * 1798 * For an IN transfer in Slave mode, a data packet is requested. The data 1799 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary, 1800 * additional data packets are requested in the Host ISR. 1801 * 1802 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ 1803 * register along with a packet count of 1 and the channel is enabled. This 1804 * causes a single PING transaction to occur. Other fields in HCTSIZ are 1805 * simply set to 0 since no data transfer occurs in this case. 1806 * 1807 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with 1808 * all the information required to perform the subsequent data transfer. In 1809 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the 1810 * controller performs the entire PING protocol, then starts the data 1811 * transfer. 1812 */ 1813 void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 1814 struct dwc2_host_chan *chan) 1815 { 1816 u32 max_hc_xfer_size = hsotg->core_params->max_transfer_size; 1817 u16 max_hc_pkt_count = hsotg->core_params->max_packet_count; 1818 u32 hcchar; 1819 u32 hctsiz = 0; 1820 u16 num_packets; 1821 u32 ec_mc; 1822 1823 if (dbg_hc(chan)) 1824 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1825 1826 if (chan->do_ping) { 1827 if (hsotg->core_params->dma_enable <= 0) { 1828 if (dbg_hc(chan)) 1829 dev_vdbg(hsotg->dev, "ping, no DMA\n"); 1830 dwc2_hc_do_ping(hsotg, chan); 1831 chan->xfer_started = 1; 1832 return; 1833 } else { 1834 if (dbg_hc(chan)) 1835 dev_vdbg(hsotg->dev, "ping, DMA\n"); 1836 hctsiz |= TSIZ_DOPNG; 1837 } 1838 } 1839 1840 if (chan->do_split) { 1841 if (dbg_hc(chan)) 1842 dev_vdbg(hsotg->dev, "split\n"); 1843 num_packets = 1; 1844 1845 if (chan->complete_split && !chan->ep_is_in) 1846 /* 1847 * For CSPLIT OUT Transfer, set the size to 0 so the 1848 * core doesn't expect any data written to the FIFO 1849 */ 1850 chan->xfer_len = 0; 1851 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet) 1852 chan->xfer_len = chan->max_packet; 1853 else if (!chan->ep_is_in && chan->xfer_len > 188) 1854 chan->xfer_len = 188; 1855 1856 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & 1857 TSIZ_XFERSIZE_MASK; 1858 1859 /* For split set ec_mc for immediate retries */ 1860 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1861 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1862 ec_mc = 3; 1863 else 1864 ec_mc = 1; 1865 } else { 1866 if (dbg_hc(chan)) 1867 dev_vdbg(hsotg->dev, "no split\n"); 1868 /* 1869 * Ensure that the transfer length and packet count will fit 1870 * in the widths allocated for them in the HCTSIZn register 1871 */ 1872 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1873 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1874 /* 1875 * Make sure the transfer size is no larger than one 1876 * (micro)frame's worth of data. (A check was done 1877 * when the periodic transfer was accepted to ensure 1878 * that a (micro)frame's worth of data can be 1879 * programmed into a channel.) 1880 */ 1881 u32 max_periodic_len = 1882 chan->multi_count * chan->max_packet; 1883 1884 if (chan->xfer_len > max_periodic_len) 1885 chan->xfer_len = max_periodic_len; 1886 } else if (chan->xfer_len > max_hc_xfer_size) { 1887 /* 1888 * Make sure that xfer_len is a multiple of max packet 1889 * size 1890 */ 1891 chan->xfer_len = 1892 max_hc_xfer_size - chan->max_packet + 1; 1893 } 1894 1895 if (chan->xfer_len > 0) { 1896 num_packets = (chan->xfer_len + chan->max_packet - 1) / 1897 chan->max_packet; 1898 if (num_packets > max_hc_pkt_count) { 1899 num_packets = max_hc_pkt_count; 1900 chan->xfer_len = num_packets * chan->max_packet; 1901 } 1902 } else { 1903 /* Need 1 packet for transfer length of 0 */ 1904 num_packets = 1; 1905 } 1906 1907 if (chan->ep_is_in) 1908 /* 1909 * Always program an integral # of max packets for IN 1910 * transfers 1911 */ 1912 chan->xfer_len = num_packets * chan->max_packet; 1913 1914 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1915 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1916 /* 1917 * Make sure that the multi_count field matches the 1918 * actual transfer length 1919 */ 1920 chan->multi_count = num_packets; 1921 1922 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1923 dwc2_set_pid_isoc(chan); 1924 1925 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & 1926 TSIZ_XFERSIZE_MASK; 1927 1928 /* The ec_mc gets the multi_count for non-split */ 1929 ec_mc = chan->multi_count; 1930 } 1931 1932 chan->start_pkt_count = num_packets; 1933 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK; 1934 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & 1935 TSIZ_SC_MC_PID_MASK; 1936 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); 1937 if (dbg_hc(chan)) { 1938 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n", 1939 hctsiz, chan->hc_num); 1940 1941 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1942 chan->hc_num); 1943 dev_vdbg(hsotg->dev, " Xfer Size: %d\n", 1944 (hctsiz & TSIZ_XFERSIZE_MASK) >> 1945 TSIZ_XFERSIZE_SHIFT); 1946 dev_vdbg(hsotg->dev, " Num Pkts: %d\n", 1947 (hctsiz & TSIZ_PKTCNT_MASK) >> 1948 TSIZ_PKTCNT_SHIFT); 1949 dev_vdbg(hsotg->dev, " Start PID: %d\n", 1950 (hctsiz & TSIZ_SC_MC_PID_MASK) >> 1951 TSIZ_SC_MC_PID_SHIFT); 1952 } 1953 1954 if (hsotg->core_params->dma_enable > 0) { 1955 dma_addr_t dma_addr; 1956 1957 if (chan->align_buf) { 1958 if (dbg_hc(chan)) 1959 dev_vdbg(hsotg->dev, "align_buf\n"); 1960 dma_addr = chan->align_buf; 1961 } else { 1962 dma_addr = chan->xfer_dma; 1963 } 1964 dwc2_writel((u32)dma_addr, hsotg->regs + HCDMA(chan->hc_num)); 1965 if (dbg_hc(chan)) 1966 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n", 1967 (unsigned long)dma_addr, chan->hc_num); 1968 } 1969 1970 /* Start the split */ 1971 if (chan->do_split) { 1972 u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); 1973 1974 hcsplt |= HCSPLT_SPLTENA; 1975 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num)); 1976 } 1977 1978 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1979 hcchar &= ~HCCHAR_MULTICNT_MASK; 1980 hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK; 1981 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); 1982 1983 if (hcchar & HCCHAR_CHDIS) 1984 dev_warn(hsotg->dev, 1985 "%s: chdis set, channel %d, hcchar 0x%08x\n", 1986 __func__, chan->hc_num, hcchar); 1987 1988 /* Set host channel enable after all other setup is complete */ 1989 hcchar |= HCCHAR_CHENA; 1990 hcchar &= ~HCCHAR_CHDIS; 1991 1992 if (dbg_hc(chan)) 1993 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", 1994 (hcchar & HCCHAR_MULTICNT_MASK) >> 1995 HCCHAR_MULTICNT_SHIFT); 1996 1997 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1998 if (dbg_hc(chan)) 1999 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, 2000 chan->hc_num); 2001 2002 chan->xfer_started = 1; 2003 chan->requests++; 2004 2005 if (hsotg->core_params->dma_enable <= 0 && 2006 !chan->ep_is_in && chan->xfer_len > 0) 2007 /* Load OUT packet into the appropriate Tx FIFO */ 2008 dwc2_hc_write_packet(hsotg, chan); 2009 } 2010 2011 /** 2012 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a 2013 * host channel and starts the transfer in Descriptor DMA mode 2014 * 2015 * @hsotg: Programming view of DWC_otg controller 2016 * @chan: Information needed to initialize the host channel 2017 * 2018 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set. 2019 * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field 2020 * with micro-frame bitmap. 2021 * 2022 * Initializes HCDMA register with descriptor list address and CTD value then 2023 * starts the transfer via enabling the channel. 2024 */ 2025 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 2026 struct dwc2_host_chan *chan) 2027 { 2028 u32 hcchar; 2029 u32 hctsiz = 0; 2030 2031 if (chan->do_ping) 2032 hctsiz |= TSIZ_DOPNG; 2033 2034 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 2035 dwc2_set_pid_isoc(chan); 2036 2037 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */ 2038 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & 2039 TSIZ_SC_MC_PID_MASK; 2040 2041 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */ 2042 hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK; 2043 2044 /* Non-zero only for high-speed interrupt endpoints */ 2045 hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK; 2046 2047 if (dbg_hc(chan)) { 2048 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 2049 chan->hc_num); 2050 dev_vdbg(hsotg->dev, " Start PID: %d\n", 2051 chan->data_pid_start); 2052 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1); 2053 } 2054 2055 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); 2056 2057 dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr, 2058 chan->desc_list_sz, DMA_TO_DEVICE); 2059 2060 dwc2_writel(chan->desc_list_addr, hsotg->regs + HCDMA(chan->hc_num)); 2061 2062 if (dbg_hc(chan)) 2063 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n", 2064 &chan->desc_list_addr, chan->hc_num); 2065 2066 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 2067 hcchar &= ~HCCHAR_MULTICNT_MASK; 2068 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT & 2069 HCCHAR_MULTICNT_MASK; 2070 2071 if (hcchar & HCCHAR_CHDIS) 2072 dev_warn(hsotg->dev, 2073 "%s: chdis set, channel %d, hcchar 0x%08x\n", 2074 __func__, chan->hc_num, hcchar); 2075 2076 /* Set host channel enable after all other setup is complete */ 2077 hcchar |= HCCHAR_CHENA; 2078 hcchar &= ~HCCHAR_CHDIS; 2079 2080 if (dbg_hc(chan)) 2081 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", 2082 (hcchar & HCCHAR_MULTICNT_MASK) >> 2083 HCCHAR_MULTICNT_SHIFT); 2084 2085 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 2086 if (dbg_hc(chan)) 2087 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, 2088 chan->hc_num); 2089 2090 chan->xfer_started = 1; 2091 chan->requests++; 2092 } 2093 2094 /** 2095 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by 2096 * a previous call to dwc2_hc_start_transfer() 2097 * 2098 * @hsotg: Programming view of DWC_otg controller 2099 * @chan: Information needed to initialize the host channel 2100 * 2101 * The caller must ensure there is sufficient space in the request queue and Tx 2102 * Data FIFO. This function should only be called in Slave mode. In DMA mode, 2103 * the controller acts autonomously to complete transfers programmed to a host 2104 * channel. 2105 * 2106 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO 2107 * if there is any data remaining to be queued. For an IN transfer, another 2108 * data packet is always requested. For the SETUP phase of a control transfer, 2109 * this function does nothing. 2110 * 2111 * Return: 1 if a new request is queued, 0 if no more requests are required 2112 * for this transfer 2113 */ 2114 int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 2115 struct dwc2_host_chan *chan) 2116 { 2117 if (dbg_hc(chan)) 2118 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 2119 chan->hc_num); 2120 2121 if (chan->do_split) 2122 /* SPLITs always queue just once per channel */ 2123 return 0; 2124 2125 if (chan->data_pid_start == DWC2_HC_PID_SETUP) 2126 /* SETUPs are queued only once since they can't be NAK'd */ 2127 return 0; 2128 2129 if (chan->ep_is_in) { 2130 /* 2131 * Always queue another request for other IN transfers. If 2132 * back-to-back INs are issued and NAKs are received for both, 2133 * the driver may still be processing the first NAK when the 2134 * second NAK is received. When the interrupt handler clears 2135 * the NAK interrupt for the first NAK, the second NAK will 2136 * not be seen. So we can't depend on the NAK interrupt 2137 * handler to requeue a NAK'd request. Instead, IN requests 2138 * are issued each time this function is called. When the 2139 * transfer completes, the extra requests for the channel will 2140 * be flushed. 2141 */ 2142 u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 2143 2144 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); 2145 hcchar |= HCCHAR_CHENA; 2146 hcchar &= ~HCCHAR_CHDIS; 2147 if (dbg_hc(chan)) 2148 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n", 2149 hcchar); 2150 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 2151 chan->requests++; 2152 return 1; 2153 } 2154 2155 /* OUT transfers */ 2156 2157 if (chan->xfer_count < chan->xfer_len) { 2158 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 2159 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 2160 u32 hcchar = dwc2_readl(hsotg->regs + 2161 HCCHAR(chan->hc_num)); 2162 2163 dwc2_hc_set_even_odd_frame(hsotg, chan, 2164 &hcchar); 2165 } 2166 2167 /* Load OUT packet into the appropriate Tx FIFO */ 2168 dwc2_hc_write_packet(hsotg, chan); 2169 chan->requests++; 2170 return 1; 2171 } 2172 2173 return 0; 2174 } 2175 2176 /** 2177 * dwc2_hc_do_ping() - Starts a PING transfer 2178 * 2179 * @hsotg: Programming view of DWC_otg controller 2180 * @chan: Information needed to initialize the host channel 2181 * 2182 * This function should only be called in Slave mode. The Do Ping bit is set in 2183 * the HCTSIZ register, then the channel is enabled. 2184 */ 2185 void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 2186 { 2187 u32 hcchar; 2188 u32 hctsiz; 2189 2190 if (dbg_hc(chan)) 2191 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 2192 chan->hc_num); 2193 2194 2195 hctsiz = TSIZ_DOPNG; 2196 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT; 2197 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); 2198 2199 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 2200 hcchar |= HCCHAR_CHENA; 2201 hcchar &= ~HCCHAR_CHDIS; 2202 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 2203 } 2204 2205 /** 2206 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for 2207 * the HFIR register according to PHY type and speed 2208 * 2209 * @hsotg: Programming view of DWC_otg controller 2210 * 2211 * NOTE: The caller can modify the value of the HFIR register only after the 2212 * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort) 2213 * has been set 2214 */ 2215 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg) 2216 { 2217 u32 usbcfg; 2218 u32 hprt0; 2219 int clock = 60; /* default value */ 2220 2221 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 2222 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 2223 2224 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) && 2225 !(usbcfg & GUSBCFG_PHYIF16)) 2226 clock = 60; 2227 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type == 2228 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI) 2229 clock = 48; 2230 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 2231 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) 2232 clock = 30; 2233 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 2234 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16)) 2235 clock = 60; 2236 if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 2237 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) 2238 clock = 48; 2239 if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) && 2240 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI) 2241 clock = 48; 2242 if ((usbcfg & GUSBCFG_PHYSEL) && 2243 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 2244 clock = 48; 2245 2246 if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED) 2247 /* High speed case */ 2248 return 125 * clock; 2249 else 2250 /* FS/LS case */ 2251 return 1000 * clock; 2252 } 2253 2254 /** 2255 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination 2256 * buffer 2257 * 2258 * @core_if: Programming view of DWC_otg controller 2259 * @dest: Destination buffer for the packet 2260 * @bytes: Number of bytes to copy to the destination 2261 */ 2262 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes) 2263 { 2264 u32 __iomem *fifo = hsotg->regs + HCFIFO(0); 2265 u32 *data_buf = (u32 *)dest; 2266 int word_count = (bytes + 3) / 4; 2267 int i; 2268 2269 /* 2270 * Todo: Account for the case where dest is not dword aligned. This 2271 * requires reading data from the FIFO into a u32 temp buffer, then 2272 * moving it into the data buffer. 2273 */ 2274 2275 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes); 2276 2277 for (i = 0; i < word_count; i++, data_buf++) 2278 *data_buf = dwc2_readl(fifo); 2279 } 2280 2281 /** 2282 * dwc2_dump_host_registers() - Prints the host registers 2283 * 2284 * @hsotg: Programming view of DWC_otg controller 2285 * 2286 * NOTE: This function will be removed once the peripheral controller code 2287 * is integrated and the driver is stable 2288 */ 2289 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg) 2290 { 2291 #ifdef DEBUG 2292 u32 __iomem *addr; 2293 int i; 2294 2295 dev_dbg(hsotg->dev, "Host Global Registers\n"); 2296 addr = hsotg->regs + HCFG; 2297 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n", 2298 (unsigned long)addr, dwc2_readl(addr)); 2299 addr = hsotg->regs + HFIR; 2300 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n", 2301 (unsigned long)addr, dwc2_readl(addr)); 2302 addr = hsotg->regs + HFNUM; 2303 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n", 2304 (unsigned long)addr, dwc2_readl(addr)); 2305 addr = hsotg->regs + HPTXSTS; 2306 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n", 2307 (unsigned long)addr, dwc2_readl(addr)); 2308 addr = hsotg->regs + HAINT; 2309 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n", 2310 (unsigned long)addr, dwc2_readl(addr)); 2311 addr = hsotg->regs + HAINTMSK; 2312 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n", 2313 (unsigned long)addr, dwc2_readl(addr)); 2314 if (hsotg->core_params->dma_desc_enable > 0) { 2315 addr = hsotg->regs + HFLBADDR; 2316 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n", 2317 (unsigned long)addr, dwc2_readl(addr)); 2318 } 2319 2320 addr = hsotg->regs + HPRT0; 2321 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n", 2322 (unsigned long)addr, dwc2_readl(addr)); 2323 2324 for (i = 0; i < hsotg->core_params->host_channels; i++) { 2325 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i); 2326 addr = hsotg->regs + HCCHAR(i); 2327 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n", 2328 (unsigned long)addr, dwc2_readl(addr)); 2329 addr = hsotg->regs + HCSPLT(i); 2330 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n", 2331 (unsigned long)addr, dwc2_readl(addr)); 2332 addr = hsotg->regs + HCINT(i); 2333 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n", 2334 (unsigned long)addr, dwc2_readl(addr)); 2335 addr = hsotg->regs + HCINTMSK(i); 2336 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n", 2337 (unsigned long)addr, dwc2_readl(addr)); 2338 addr = hsotg->regs + HCTSIZ(i); 2339 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n", 2340 (unsigned long)addr, dwc2_readl(addr)); 2341 addr = hsotg->regs + HCDMA(i); 2342 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n", 2343 (unsigned long)addr, dwc2_readl(addr)); 2344 if (hsotg->core_params->dma_desc_enable > 0) { 2345 addr = hsotg->regs + HCDMAB(i); 2346 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n", 2347 (unsigned long)addr, dwc2_readl(addr)); 2348 } 2349 } 2350 #endif 2351 } 2352 2353 /** 2354 * dwc2_dump_global_registers() - Prints the core global registers 2355 * 2356 * @hsotg: Programming view of DWC_otg controller 2357 * 2358 * NOTE: This function will be removed once the peripheral controller code 2359 * is integrated and the driver is stable 2360 */ 2361 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg) 2362 { 2363 #ifdef DEBUG 2364 u32 __iomem *addr; 2365 2366 dev_dbg(hsotg->dev, "Core Global Registers\n"); 2367 addr = hsotg->regs + GOTGCTL; 2368 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n", 2369 (unsigned long)addr, dwc2_readl(addr)); 2370 addr = hsotg->regs + GOTGINT; 2371 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n", 2372 (unsigned long)addr, dwc2_readl(addr)); 2373 addr = hsotg->regs + GAHBCFG; 2374 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n", 2375 (unsigned long)addr, dwc2_readl(addr)); 2376 addr = hsotg->regs + GUSBCFG; 2377 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n", 2378 (unsigned long)addr, dwc2_readl(addr)); 2379 addr = hsotg->regs + GRSTCTL; 2380 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n", 2381 (unsigned long)addr, dwc2_readl(addr)); 2382 addr = hsotg->regs + GINTSTS; 2383 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n", 2384 (unsigned long)addr, dwc2_readl(addr)); 2385 addr = hsotg->regs + GINTMSK; 2386 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n", 2387 (unsigned long)addr, dwc2_readl(addr)); 2388 addr = hsotg->regs + GRXSTSR; 2389 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n", 2390 (unsigned long)addr, dwc2_readl(addr)); 2391 addr = hsotg->regs + GRXFSIZ; 2392 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n", 2393 (unsigned long)addr, dwc2_readl(addr)); 2394 addr = hsotg->regs + GNPTXFSIZ; 2395 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n", 2396 (unsigned long)addr, dwc2_readl(addr)); 2397 addr = hsotg->regs + GNPTXSTS; 2398 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n", 2399 (unsigned long)addr, dwc2_readl(addr)); 2400 addr = hsotg->regs + GI2CCTL; 2401 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n", 2402 (unsigned long)addr, dwc2_readl(addr)); 2403 addr = hsotg->regs + GPVNDCTL; 2404 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n", 2405 (unsigned long)addr, dwc2_readl(addr)); 2406 addr = hsotg->regs + GGPIO; 2407 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n", 2408 (unsigned long)addr, dwc2_readl(addr)); 2409 addr = hsotg->regs + GUID; 2410 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n", 2411 (unsigned long)addr, dwc2_readl(addr)); 2412 addr = hsotg->regs + GSNPSID; 2413 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n", 2414 (unsigned long)addr, dwc2_readl(addr)); 2415 addr = hsotg->regs + GHWCFG1; 2416 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n", 2417 (unsigned long)addr, dwc2_readl(addr)); 2418 addr = hsotg->regs + GHWCFG2; 2419 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n", 2420 (unsigned long)addr, dwc2_readl(addr)); 2421 addr = hsotg->regs + GHWCFG3; 2422 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n", 2423 (unsigned long)addr, dwc2_readl(addr)); 2424 addr = hsotg->regs + GHWCFG4; 2425 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n", 2426 (unsigned long)addr, dwc2_readl(addr)); 2427 addr = hsotg->regs + GLPMCFG; 2428 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n", 2429 (unsigned long)addr, dwc2_readl(addr)); 2430 addr = hsotg->regs + GPWRDN; 2431 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n", 2432 (unsigned long)addr, dwc2_readl(addr)); 2433 addr = hsotg->regs + GDFIFOCFG; 2434 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n", 2435 (unsigned long)addr, dwc2_readl(addr)); 2436 addr = hsotg->regs + HPTXFSIZ; 2437 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n", 2438 (unsigned long)addr, dwc2_readl(addr)); 2439 2440 addr = hsotg->regs + PCGCTL; 2441 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n", 2442 (unsigned long)addr, dwc2_readl(addr)); 2443 #endif 2444 } 2445 2446 /** 2447 * dwc2_flush_tx_fifo() - Flushes a Tx FIFO 2448 * 2449 * @hsotg: Programming view of DWC_otg controller 2450 * @num: Tx FIFO to flush 2451 */ 2452 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num) 2453 { 2454 u32 greset; 2455 int count = 0; 2456 2457 dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num); 2458 2459 greset = GRSTCTL_TXFFLSH; 2460 greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK; 2461 dwc2_writel(greset, hsotg->regs + GRSTCTL); 2462 2463 do { 2464 greset = dwc2_readl(hsotg->regs + GRSTCTL); 2465 if (++count > 10000) { 2466 dev_warn(hsotg->dev, 2467 "%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n", 2468 __func__, greset, 2469 dwc2_readl(hsotg->regs + GNPTXSTS)); 2470 break; 2471 } 2472 udelay(1); 2473 } while (greset & GRSTCTL_TXFFLSH); 2474 2475 /* Wait for at least 3 PHY Clocks */ 2476 udelay(1); 2477 } 2478 2479 /** 2480 * dwc2_flush_rx_fifo() - Flushes the Rx FIFO 2481 * 2482 * @hsotg: Programming view of DWC_otg controller 2483 */ 2484 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg) 2485 { 2486 u32 greset; 2487 int count = 0; 2488 2489 dev_vdbg(hsotg->dev, "%s()\n", __func__); 2490 2491 greset = GRSTCTL_RXFFLSH; 2492 dwc2_writel(greset, hsotg->regs + GRSTCTL); 2493 2494 do { 2495 greset = dwc2_readl(hsotg->regs + GRSTCTL); 2496 if (++count > 10000) { 2497 dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n", 2498 __func__, greset); 2499 break; 2500 } 2501 udelay(1); 2502 } while (greset & GRSTCTL_RXFFLSH); 2503 2504 /* Wait for at least 3 PHY Clocks */ 2505 udelay(1); 2506 } 2507 2508 #define DWC2_OUT_OF_BOUNDS(a, b, c) ((a) < (b) || (a) > (c)) 2509 2510 /* Parameter access functions */ 2511 void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val) 2512 { 2513 int valid = 1; 2514 2515 switch (val) { 2516 case DWC2_CAP_PARAM_HNP_SRP_CAPABLE: 2517 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) 2518 valid = 0; 2519 break; 2520 case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE: 2521 switch (hsotg->hw_params.op_mode) { 2522 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 2523 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 2524 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 2525 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 2526 break; 2527 default: 2528 valid = 0; 2529 break; 2530 } 2531 break; 2532 case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE: 2533 /* always valid */ 2534 break; 2535 default: 2536 valid = 0; 2537 break; 2538 } 2539 2540 if (!valid) { 2541 if (val >= 0) 2542 dev_err(hsotg->dev, 2543 "%d invalid for otg_cap parameter. Check HW configuration.\n", 2544 val); 2545 switch (hsotg->hw_params.op_mode) { 2546 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 2547 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE; 2548 break; 2549 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 2550 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 2551 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 2552 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE; 2553 break; 2554 default: 2555 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 2556 break; 2557 } 2558 dev_dbg(hsotg->dev, "Setting otg_cap to %d\n", val); 2559 } 2560 2561 hsotg->core_params->otg_cap = val; 2562 } 2563 2564 void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val) 2565 { 2566 int valid = 1; 2567 2568 if (val > 0 && hsotg->hw_params.arch == GHWCFG2_SLAVE_ONLY_ARCH) 2569 valid = 0; 2570 if (val < 0) 2571 valid = 0; 2572 2573 if (!valid) { 2574 if (val >= 0) 2575 dev_err(hsotg->dev, 2576 "%d invalid for dma_enable parameter. Check HW configuration.\n", 2577 val); 2578 val = hsotg->hw_params.arch != GHWCFG2_SLAVE_ONLY_ARCH; 2579 dev_dbg(hsotg->dev, "Setting dma_enable to %d\n", val); 2580 } 2581 2582 hsotg->core_params->dma_enable = val; 2583 } 2584 2585 void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val) 2586 { 2587 int valid = 1; 2588 2589 if (val > 0 && (hsotg->core_params->dma_enable <= 0 || 2590 !hsotg->hw_params.dma_desc_enable)) 2591 valid = 0; 2592 if (val < 0) 2593 valid = 0; 2594 2595 if (!valid) { 2596 if (val >= 0) 2597 dev_err(hsotg->dev, 2598 "%d invalid for dma_desc_enable parameter. Check HW configuration.\n", 2599 val); 2600 val = (hsotg->core_params->dma_enable > 0 && 2601 hsotg->hw_params.dma_desc_enable); 2602 dev_dbg(hsotg->dev, "Setting dma_desc_enable to %d\n", val); 2603 } 2604 2605 hsotg->core_params->dma_desc_enable = val; 2606 } 2607 2608 void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg, int val) 2609 { 2610 int valid = 1; 2611 2612 if (val > 0 && (hsotg->core_params->dma_enable <= 0 || 2613 !hsotg->hw_params.dma_desc_enable)) 2614 valid = 0; 2615 if (val < 0) 2616 valid = 0; 2617 2618 if (!valid) { 2619 if (val >= 0) 2620 dev_err(hsotg->dev, 2621 "%d invalid for dma_desc_fs_enable parameter. Check HW configuration.\n", 2622 val); 2623 val = (hsotg->core_params->dma_enable > 0 && 2624 hsotg->hw_params.dma_desc_enable); 2625 } 2626 2627 hsotg->core_params->dma_desc_fs_enable = val; 2628 dev_dbg(hsotg->dev, "Setting dma_desc_fs_enable to %d\n", val); 2629 } 2630 2631 void dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg, 2632 int val) 2633 { 2634 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 2635 if (val >= 0) { 2636 dev_err(hsotg->dev, 2637 "Wrong value for host_support_fs_low_power\n"); 2638 dev_err(hsotg->dev, 2639 "host_support_fs_low_power must be 0 or 1\n"); 2640 } 2641 val = 0; 2642 dev_dbg(hsotg->dev, 2643 "Setting host_support_fs_low_power to %d\n", val); 2644 } 2645 2646 hsotg->core_params->host_support_fs_ls_low_power = val; 2647 } 2648 2649 void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, int val) 2650 { 2651 int valid = 1; 2652 2653 if (val > 0 && !hsotg->hw_params.enable_dynamic_fifo) 2654 valid = 0; 2655 if (val < 0) 2656 valid = 0; 2657 2658 if (!valid) { 2659 if (val >= 0) 2660 dev_err(hsotg->dev, 2661 "%d invalid for enable_dynamic_fifo parameter. Check HW configuration.\n", 2662 val); 2663 val = hsotg->hw_params.enable_dynamic_fifo; 2664 dev_dbg(hsotg->dev, "Setting enable_dynamic_fifo to %d\n", val); 2665 } 2666 2667 hsotg->core_params->enable_dynamic_fifo = val; 2668 } 2669 2670 void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val) 2671 { 2672 int valid = 1; 2673 2674 if (val < 16 || val > hsotg->hw_params.host_rx_fifo_size) 2675 valid = 0; 2676 2677 if (!valid) { 2678 if (val >= 0) 2679 dev_err(hsotg->dev, 2680 "%d invalid for host_rx_fifo_size. Check HW configuration.\n", 2681 val); 2682 val = hsotg->hw_params.host_rx_fifo_size; 2683 dev_dbg(hsotg->dev, "Setting host_rx_fifo_size to %d\n", val); 2684 } 2685 2686 hsotg->core_params->host_rx_fifo_size = val; 2687 } 2688 2689 void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val) 2690 { 2691 int valid = 1; 2692 2693 if (val < 16 || val > hsotg->hw_params.host_nperio_tx_fifo_size) 2694 valid = 0; 2695 2696 if (!valid) { 2697 if (val >= 0) 2698 dev_err(hsotg->dev, 2699 "%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n", 2700 val); 2701 val = hsotg->hw_params.host_nperio_tx_fifo_size; 2702 dev_dbg(hsotg->dev, "Setting host_nperio_tx_fifo_size to %d\n", 2703 val); 2704 } 2705 2706 hsotg->core_params->host_nperio_tx_fifo_size = val; 2707 } 2708 2709 void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val) 2710 { 2711 int valid = 1; 2712 2713 if (val < 16 || val > hsotg->hw_params.host_perio_tx_fifo_size) 2714 valid = 0; 2715 2716 if (!valid) { 2717 if (val >= 0) 2718 dev_err(hsotg->dev, 2719 "%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n", 2720 val); 2721 val = hsotg->hw_params.host_perio_tx_fifo_size; 2722 dev_dbg(hsotg->dev, "Setting host_perio_tx_fifo_size to %d\n", 2723 val); 2724 } 2725 2726 hsotg->core_params->host_perio_tx_fifo_size = val; 2727 } 2728 2729 void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val) 2730 { 2731 int valid = 1; 2732 2733 if (val < 2047 || val > hsotg->hw_params.max_transfer_size) 2734 valid = 0; 2735 2736 if (!valid) { 2737 if (val >= 0) 2738 dev_err(hsotg->dev, 2739 "%d invalid for max_transfer_size. Check HW configuration.\n", 2740 val); 2741 val = hsotg->hw_params.max_transfer_size; 2742 dev_dbg(hsotg->dev, "Setting max_transfer_size to %d\n", val); 2743 } 2744 2745 hsotg->core_params->max_transfer_size = val; 2746 } 2747 2748 void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val) 2749 { 2750 int valid = 1; 2751 2752 if (val < 15 || val > hsotg->hw_params.max_packet_count) 2753 valid = 0; 2754 2755 if (!valid) { 2756 if (val >= 0) 2757 dev_err(hsotg->dev, 2758 "%d invalid for max_packet_count. Check HW configuration.\n", 2759 val); 2760 val = hsotg->hw_params.max_packet_count; 2761 dev_dbg(hsotg->dev, "Setting max_packet_count to %d\n", val); 2762 } 2763 2764 hsotg->core_params->max_packet_count = val; 2765 } 2766 2767 void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val) 2768 { 2769 int valid = 1; 2770 2771 if (val < 1 || val > hsotg->hw_params.host_channels) 2772 valid = 0; 2773 2774 if (!valid) { 2775 if (val >= 0) 2776 dev_err(hsotg->dev, 2777 "%d invalid for host_channels. Check HW configuration.\n", 2778 val); 2779 val = hsotg->hw_params.host_channels; 2780 dev_dbg(hsotg->dev, "Setting host_channels to %d\n", val); 2781 } 2782 2783 hsotg->core_params->host_channels = val; 2784 } 2785 2786 void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val) 2787 { 2788 int valid = 0; 2789 u32 hs_phy_type, fs_phy_type; 2790 2791 if (DWC2_OUT_OF_BOUNDS(val, DWC2_PHY_TYPE_PARAM_FS, 2792 DWC2_PHY_TYPE_PARAM_ULPI)) { 2793 if (val >= 0) { 2794 dev_err(hsotg->dev, "Wrong value for phy_type\n"); 2795 dev_err(hsotg->dev, "phy_type must be 0, 1 or 2\n"); 2796 } 2797 2798 valid = 0; 2799 } 2800 2801 hs_phy_type = hsotg->hw_params.hs_phy_type; 2802 fs_phy_type = hsotg->hw_params.fs_phy_type; 2803 if (val == DWC2_PHY_TYPE_PARAM_UTMI && 2804 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || 2805 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 2806 valid = 1; 2807 else if (val == DWC2_PHY_TYPE_PARAM_ULPI && 2808 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI || 2809 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 2810 valid = 1; 2811 else if (val == DWC2_PHY_TYPE_PARAM_FS && 2812 fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 2813 valid = 1; 2814 2815 if (!valid) { 2816 if (val >= 0) 2817 dev_err(hsotg->dev, 2818 "%d invalid for phy_type. Check HW configuration.\n", 2819 val); 2820 val = DWC2_PHY_TYPE_PARAM_FS; 2821 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) { 2822 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || 2823 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI) 2824 val = DWC2_PHY_TYPE_PARAM_UTMI; 2825 else 2826 val = DWC2_PHY_TYPE_PARAM_ULPI; 2827 } 2828 dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val); 2829 } 2830 2831 hsotg->core_params->phy_type = val; 2832 } 2833 2834 static int dwc2_get_param_phy_type(struct dwc2_hsotg *hsotg) 2835 { 2836 return hsotg->core_params->phy_type; 2837 } 2838 2839 void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val) 2840 { 2841 int valid = 1; 2842 2843 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 2844 if (val >= 0) { 2845 dev_err(hsotg->dev, "Wrong value for speed parameter\n"); 2846 dev_err(hsotg->dev, "max_speed parameter must be 0 or 1\n"); 2847 } 2848 valid = 0; 2849 } 2850 2851 if (val == DWC2_SPEED_PARAM_HIGH && 2852 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS) 2853 valid = 0; 2854 2855 if (!valid) { 2856 if (val >= 0) 2857 dev_err(hsotg->dev, 2858 "%d invalid for speed parameter. Check HW configuration.\n", 2859 val); 2860 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS ? 2861 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH; 2862 dev_dbg(hsotg->dev, "Setting speed to %d\n", val); 2863 } 2864 2865 hsotg->core_params->speed = val; 2866 } 2867 2868 void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, int val) 2869 { 2870 int valid = 1; 2871 2872 if (DWC2_OUT_OF_BOUNDS(val, DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ, 2873 DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)) { 2874 if (val >= 0) { 2875 dev_err(hsotg->dev, 2876 "Wrong value for host_ls_low_power_phy_clk parameter\n"); 2877 dev_err(hsotg->dev, 2878 "host_ls_low_power_phy_clk must be 0 or 1\n"); 2879 } 2880 valid = 0; 2881 } 2882 2883 if (val == DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ && 2884 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS) 2885 valid = 0; 2886 2887 if (!valid) { 2888 if (val >= 0) 2889 dev_err(hsotg->dev, 2890 "%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n", 2891 val); 2892 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS 2893 ? DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 2894 : DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ; 2895 dev_dbg(hsotg->dev, "Setting host_ls_low_power_phy_clk to %d\n", 2896 val); 2897 } 2898 2899 hsotg->core_params->host_ls_low_power_phy_clk = val; 2900 } 2901 2902 void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val) 2903 { 2904 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 2905 if (val >= 0) { 2906 dev_err(hsotg->dev, "Wrong value for phy_ulpi_ddr\n"); 2907 dev_err(hsotg->dev, "phy_upli_ddr must be 0 or 1\n"); 2908 } 2909 val = 0; 2910 dev_dbg(hsotg->dev, "Setting phy_upli_ddr to %d\n", val); 2911 } 2912 2913 hsotg->core_params->phy_ulpi_ddr = val; 2914 } 2915 2916 void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val) 2917 { 2918 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 2919 if (val >= 0) { 2920 dev_err(hsotg->dev, 2921 "Wrong value for phy_ulpi_ext_vbus\n"); 2922 dev_err(hsotg->dev, 2923 "phy_ulpi_ext_vbus must be 0 or 1\n"); 2924 } 2925 val = 0; 2926 dev_dbg(hsotg->dev, "Setting phy_ulpi_ext_vbus to %d\n", val); 2927 } 2928 2929 hsotg->core_params->phy_ulpi_ext_vbus = val; 2930 } 2931 2932 void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val) 2933 { 2934 int valid = 0; 2935 2936 switch (hsotg->hw_params.utmi_phy_data_width) { 2937 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8: 2938 valid = (val == 8); 2939 break; 2940 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16: 2941 valid = (val == 16); 2942 break; 2943 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16: 2944 valid = (val == 8 || val == 16); 2945 break; 2946 } 2947 2948 if (!valid) { 2949 if (val >= 0) { 2950 dev_err(hsotg->dev, 2951 "%d invalid for phy_utmi_width. Check HW configuration.\n", 2952 val); 2953 } 2954 val = (hsotg->hw_params.utmi_phy_data_width == 2955 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16; 2956 dev_dbg(hsotg->dev, "Setting phy_utmi_width to %d\n", val); 2957 } 2958 2959 hsotg->core_params->phy_utmi_width = val; 2960 } 2961 2962 void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val) 2963 { 2964 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 2965 if (val >= 0) { 2966 dev_err(hsotg->dev, "Wrong value for ulpi_fs_ls\n"); 2967 dev_err(hsotg->dev, "ulpi_fs_ls must be 0 or 1\n"); 2968 } 2969 val = 0; 2970 dev_dbg(hsotg->dev, "Setting ulpi_fs_ls to %d\n", val); 2971 } 2972 2973 hsotg->core_params->ulpi_fs_ls = val; 2974 } 2975 2976 void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val) 2977 { 2978 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 2979 if (val >= 0) { 2980 dev_err(hsotg->dev, "Wrong value for ts_dline\n"); 2981 dev_err(hsotg->dev, "ts_dline must be 0 or 1\n"); 2982 } 2983 val = 0; 2984 dev_dbg(hsotg->dev, "Setting ts_dline to %d\n", val); 2985 } 2986 2987 hsotg->core_params->ts_dline = val; 2988 } 2989 2990 void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val) 2991 { 2992 int valid = 1; 2993 2994 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 2995 if (val >= 0) { 2996 dev_err(hsotg->dev, "Wrong value for i2c_enable\n"); 2997 dev_err(hsotg->dev, "i2c_enable must be 0 or 1\n"); 2998 } 2999 3000 valid = 0; 3001 } 3002 3003 if (val == 1 && !(hsotg->hw_params.i2c_enable)) 3004 valid = 0; 3005 3006 if (!valid) { 3007 if (val >= 0) 3008 dev_err(hsotg->dev, 3009 "%d invalid for i2c_enable. Check HW configuration.\n", 3010 val); 3011 val = hsotg->hw_params.i2c_enable; 3012 dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val); 3013 } 3014 3015 hsotg->core_params->i2c_enable = val; 3016 } 3017 3018 void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, int val) 3019 { 3020 int valid = 1; 3021 3022 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 3023 if (val >= 0) { 3024 dev_err(hsotg->dev, 3025 "Wrong value for en_multiple_tx_fifo,\n"); 3026 dev_err(hsotg->dev, 3027 "en_multiple_tx_fifo must be 0 or 1\n"); 3028 } 3029 valid = 0; 3030 } 3031 3032 if (val == 1 && !hsotg->hw_params.en_multiple_tx_fifo) 3033 valid = 0; 3034 3035 if (!valid) { 3036 if (val >= 0) 3037 dev_err(hsotg->dev, 3038 "%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n", 3039 val); 3040 val = hsotg->hw_params.en_multiple_tx_fifo; 3041 dev_dbg(hsotg->dev, "Setting en_multiple_tx_fifo to %d\n", val); 3042 } 3043 3044 hsotg->core_params->en_multiple_tx_fifo = val; 3045 } 3046 3047 void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val) 3048 { 3049 int valid = 1; 3050 3051 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 3052 if (val >= 0) { 3053 dev_err(hsotg->dev, 3054 "'%d' invalid for parameter reload_ctl\n", val); 3055 dev_err(hsotg->dev, "reload_ctl must be 0 or 1\n"); 3056 } 3057 valid = 0; 3058 } 3059 3060 if (val == 1 && hsotg->hw_params.snpsid < DWC2_CORE_REV_2_92a) 3061 valid = 0; 3062 3063 if (!valid) { 3064 if (val >= 0) 3065 dev_err(hsotg->dev, 3066 "%d invalid for parameter reload_ctl. Check HW configuration.\n", 3067 val); 3068 val = hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_92a; 3069 dev_dbg(hsotg->dev, "Setting reload_ctl to %d\n", val); 3070 } 3071 3072 hsotg->core_params->reload_ctl = val; 3073 } 3074 3075 void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val) 3076 { 3077 if (val != -1) 3078 hsotg->core_params->ahbcfg = val; 3079 else 3080 hsotg->core_params->ahbcfg = GAHBCFG_HBSTLEN_INCR4 << 3081 GAHBCFG_HBSTLEN_SHIFT; 3082 } 3083 3084 void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val) 3085 { 3086 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 3087 if (val >= 0) { 3088 dev_err(hsotg->dev, 3089 "'%d' invalid for parameter otg_ver\n", val); 3090 dev_err(hsotg->dev, 3091 "otg_ver must be 0 (for OTG 1.3 support) or 1 (for OTG 2.0 support)\n"); 3092 } 3093 val = 0; 3094 dev_dbg(hsotg->dev, "Setting otg_ver to %d\n", val); 3095 } 3096 3097 hsotg->core_params->otg_ver = val; 3098 } 3099 3100 static void dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val) 3101 { 3102 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 3103 if (val >= 0) { 3104 dev_err(hsotg->dev, 3105 "'%d' invalid for parameter uframe_sched\n", 3106 val); 3107 dev_err(hsotg->dev, "uframe_sched must be 0 or 1\n"); 3108 } 3109 val = 1; 3110 dev_dbg(hsotg->dev, "Setting uframe_sched to %d\n", val); 3111 } 3112 3113 hsotg->core_params->uframe_sched = val; 3114 } 3115 3116 static void dwc2_set_param_external_id_pin_ctl(struct dwc2_hsotg *hsotg, 3117 int val) 3118 { 3119 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 3120 if (val >= 0) { 3121 dev_err(hsotg->dev, 3122 "'%d' invalid for parameter external_id_pin_ctl\n", 3123 val); 3124 dev_err(hsotg->dev, "external_id_pin_ctl must be 0 or 1\n"); 3125 } 3126 val = 0; 3127 dev_dbg(hsotg->dev, "Setting external_id_pin_ctl to %d\n", val); 3128 } 3129 3130 hsotg->core_params->external_id_pin_ctl = val; 3131 } 3132 3133 static void dwc2_set_param_hibernation(struct dwc2_hsotg *hsotg, 3134 int val) 3135 { 3136 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 3137 if (val >= 0) { 3138 dev_err(hsotg->dev, 3139 "'%d' invalid for parameter hibernation\n", 3140 val); 3141 dev_err(hsotg->dev, "hibernation must be 0 or 1\n"); 3142 } 3143 val = 0; 3144 dev_dbg(hsotg->dev, "Setting hibernation to %d\n", val); 3145 } 3146 3147 hsotg->core_params->hibernation = val; 3148 } 3149 3150 /* 3151 * This function is called during module intialization to pass module parameters 3152 * for the DWC_otg core. 3153 */ 3154 void dwc2_set_parameters(struct dwc2_hsotg *hsotg, 3155 const struct dwc2_core_params *params) 3156 { 3157 dev_dbg(hsotg->dev, "%s()\n", __func__); 3158 3159 dwc2_set_param_otg_cap(hsotg, params->otg_cap); 3160 dwc2_set_param_dma_enable(hsotg, params->dma_enable); 3161 dwc2_set_param_dma_desc_enable(hsotg, params->dma_desc_enable); 3162 dwc2_set_param_dma_desc_fs_enable(hsotg, params->dma_desc_fs_enable); 3163 dwc2_set_param_host_support_fs_ls_low_power(hsotg, 3164 params->host_support_fs_ls_low_power); 3165 dwc2_set_param_enable_dynamic_fifo(hsotg, 3166 params->enable_dynamic_fifo); 3167 dwc2_set_param_host_rx_fifo_size(hsotg, 3168 params->host_rx_fifo_size); 3169 dwc2_set_param_host_nperio_tx_fifo_size(hsotg, 3170 params->host_nperio_tx_fifo_size); 3171 dwc2_set_param_host_perio_tx_fifo_size(hsotg, 3172 params->host_perio_tx_fifo_size); 3173 dwc2_set_param_max_transfer_size(hsotg, 3174 params->max_transfer_size); 3175 dwc2_set_param_max_packet_count(hsotg, 3176 params->max_packet_count); 3177 dwc2_set_param_host_channels(hsotg, params->host_channels); 3178 dwc2_set_param_phy_type(hsotg, params->phy_type); 3179 dwc2_set_param_speed(hsotg, params->speed); 3180 dwc2_set_param_host_ls_low_power_phy_clk(hsotg, 3181 params->host_ls_low_power_phy_clk); 3182 dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr); 3183 dwc2_set_param_phy_ulpi_ext_vbus(hsotg, 3184 params->phy_ulpi_ext_vbus); 3185 dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width); 3186 dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls); 3187 dwc2_set_param_ts_dline(hsotg, params->ts_dline); 3188 dwc2_set_param_i2c_enable(hsotg, params->i2c_enable); 3189 dwc2_set_param_en_multiple_tx_fifo(hsotg, 3190 params->en_multiple_tx_fifo); 3191 dwc2_set_param_reload_ctl(hsotg, params->reload_ctl); 3192 dwc2_set_param_ahbcfg(hsotg, params->ahbcfg); 3193 dwc2_set_param_otg_ver(hsotg, params->otg_ver); 3194 dwc2_set_param_uframe_sched(hsotg, params->uframe_sched); 3195 dwc2_set_param_external_id_pin_ctl(hsotg, params->external_id_pin_ctl); 3196 dwc2_set_param_hibernation(hsotg, params->hibernation); 3197 } 3198 3199 /* 3200 * Forces either host or device mode if the controller is not 3201 * currently in that mode. 3202 * 3203 * Returns true if the mode was forced. 3204 */ 3205 static bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host) 3206 { 3207 if (host && dwc2_is_host_mode(hsotg)) 3208 return false; 3209 else if (!host && dwc2_is_device_mode(hsotg)) 3210 return false; 3211 3212 return dwc2_force_mode(hsotg, host); 3213 } 3214 3215 /* 3216 * Gets host hardware parameters. Forces host mode if not currently in 3217 * host mode. Should be called immediately after a core soft reset in 3218 * order to get the reset values. 3219 */ 3220 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg) 3221 { 3222 struct dwc2_hw_params *hw = &hsotg->hw_params; 3223 u32 gnptxfsiz; 3224 u32 hptxfsiz; 3225 bool forced; 3226 3227 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) 3228 return; 3229 3230 forced = dwc2_force_mode_if_needed(hsotg, true); 3231 3232 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); 3233 hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ); 3234 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz); 3235 dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz); 3236 3237 if (forced) 3238 dwc2_clear_force_mode(hsotg); 3239 3240 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 3241 FIFOSIZE_DEPTH_SHIFT; 3242 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> 3243 FIFOSIZE_DEPTH_SHIFT; 3244 } 3245 3246 /* 3247 * Gets device hardware parameters. Forces device mode if not 3248 * currently in device mode. Should be called immediately after a core 3249 * soft reset in order to get the reset values. 3250 */ 3251 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg) 3252 { 3253 struct dwc2_hw_params *hw = &hsotg->hw_params; 3254 bool forced; 3255 u32 gnptxfsiz; 3256 3257 if (hsotg->dr_mode == USB_DR_MODE_HOST) 3258 return; 3259 3260 forced = dwc2_force_mode_if_needed(hsotg, false); 3261 3262 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); 3263 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz); 3264 3265 if (forced) 3266 dwc2_clear_force_mode(hsotg); 3267 3268 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 3269 FIFOSIZE_DEPTH_SHIFT; 3270 } 3271 3272 /** 3273 * During device initialization, read various hardware configuration 3274 * registers and interpret the contents. 3275 */ 3276 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) 3277 { 3278 struct dwc2_hw_params *hw = &hsotg->hw_params; 3279 unsigned width; 3280 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4; 3281 u32 grxfsiz; 3282 3283 /* 3284 * Attempt to ensure this device is really a DWC_otg Controller. 3285 * Read and verify the GSNPSID register contents. The value should be 3286 * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3", 3287 * as in "OTG version 2.xx" or "OTG version 3.xx". 3288 */ 3289 hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID); 3290 if ((hw->snpsid & 0xfffff000) != 0x4f542000 && 3291 (hw->snpsid & 0xfffff000) != 0x4f543000) { 3292 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n", 3293 hw->snpsid); 3294 return -ENODEV; 3295 } 3296 3297 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n", 3298 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf, 3299 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid); 3300 3301 hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1); 3302 hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2); 3303 hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3); 3304 hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4); 3305 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); 3306 3307 dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1); 3308 dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2); 3309 dev_dbg(hsotg->dev, "hwcfg3=%08x\n", hwcfg3); 3310 dev_dbg(hsotg->dev, "hwcfg4=%08x\n", hwcfg4); 3311 dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz); 3312 3313 /* 3314 * Host specific hardware parameters. Reading these parameters 3315 * requires the controller to be in host mode. The mode will 3316 * be forced, if necessary, to read these values. 3317 */ 3318 dwc2_get_host_hwparams(hsotg); 3319 dwc2_get_dev_hwparams(hsotg); 3320 3321 /* hwcfg1 */ 3322 hw->dev_ep_dirs = hwcfg1; 3323 3324 /* hwcfg2 */ 3325 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> 3326 GHWCFG2_OP_MODE_SHIFT; 3327 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> 3328 GHWCFG2_ARCHITECTURE_SHIFT; 3329 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); 3330 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> 3331 GHWCFG2_NUM_HOST_CHAN_SHIFT); 3332 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> 3333 GHWCFG2_HS_PHY_TYPE_SHIFT; 3334 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> 3335 GHWCFG2_FS_PHY_TYPE_SHIFT; 3336 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> 3337 GHWCFG2_NUM_DEV_EP_SHIFT; 3338 hw->nperio_tx_q_depth = 3339 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >> 3340 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1; 3341 hw->host_perio_tx_q_depth = 3342 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >> 3343 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1; 3344 hw->dev_token_q_depth = 3345 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >> 3346 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT; 3347 3348 /* hwcfg3 */ 3349 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >> 3350 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT; 3351 hw->max_transfer_size = (1 << (width + 11)) - 1; 3352 /* 3353 * Clip max_transfer_size to 65535. dwc2_hc_setup_align_buf() allocates 3354 * coherent buffers with this size, and if it's too large we can 3355 * exhaust the coherent DMA pool. 3356 */ 3357 if (hw->max_transfer_size > 65535) 3358 hw->max_transfer_size = 65535; 3359 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >> 3360 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT; 3361 hw->max_packet_count = (1 << (width + 4)) - 1; 3362 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); 3363 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> 3364 GHWCFG3_DFIFO_DEPTH_SHIFT; 3365 3366 /* hwcfg4 */ 3367 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); 3368 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> 3369 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT; 3370 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); 3371 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); 3372 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> 3373 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT; 3374 3375 /* fifo sizes */ 3376 hw->host_rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> 3377 GRXFSIZ_DEPTH_SHIFT; 3378 3379 dev_dbg(hsotg->dev, "Detected values from hardware:\n"); 3380 dev_dbg(hsotg->dev, " op_mode=%d\n", 3381 hw->op_mode); 3382 dev_dbg(hsotg->dev, " arch=%d\n", 3383 hw->arch); 3384 dev_dbg(hsotg->dev, " dma_desc_enable=%d\n", 3385 hw->dma_desc_enable); 3386 dev_dbg(hsotg->dev, " power_optimized=%d\n", 3387 hw->power_optimized); 3388 dev_dbg(hsotg->dev, " i2c_enable=%d\n", 3389 hw->i2c_enable); 3390 dev_dbg(hsotg->dev, " hs_phy_type=%d\n", 3391 hw->hs_phy_type); 3392 dev_dbg(hsotg->dev, " fs_phy_type=%d\n", 3393 hw->fs_phy_type); 3394 dev_dbg(hsotg->dev, " utmi_phy_data_width=%d\n", 3395 hw->utmi_phy_data_width); 3396 dev_dbg(hsotg->dev, " num_dev_ep=%d\n", 3397 hw->num_dev_ep); 3398 dev_dbg(hsotg->dev, " num_dev_perio_in_ep=%d\n", 3399 hw->num_dev_perio_in_ep); 3400 dev_dbg(hsotg->dev, " host_channels=%d\n", 3401 hw->host_channels); 3402 dev_dbg(hsotg->dev, " max_transfer_size=%d\n", 3403 hw->max_transfer_size); 3404 dev_dbg(hsotg->dev, " max_packet_count=%d\n", 3405 hw->max_packet_count); 3406 dev_dbg(hsotg->dev, " nperio_tx_q_depth=0x%0x\n", 3407 hw->nperio_tx_q_depth); 3408 dev_dbg(hsotg->dev, " host_perio_tx_q_depth=0x%0x\n", 3409 hw->host_perio_tx_q_depth); 3410 dev_dbg(hsotg->dev, " dev_token_q_depth=0x%0x\n", 3411 hw->dev_token_q_depth); 3412 dev_dbg(hsotg->dev, " enable_dynamic_fifo=%d\n", 3413 hw->enable_dynamic_fifo); 3414 dev_dbg(hsotg->dev, " en_multiple_tx_fifo=%d\n", 3415 hw->en_multiple_tx_fifo); 3416 dev_dbg(hsotg->dev, " total_fifo_size=%d\n", 3417 hw->total_fifo_size); 3418 dev_dbg(hsotg->dev, " host_rx_fifo_size=%d\n", 3419 hw->host_rx_fifo_size); 3420 dev_dbg(hsotg->dev, " host_nperio_tx_fifo_size=%d\n", 3421 hw->host_nperio_tx_fifo_size); 3422 dev_dbg(hsotg->dev, " host_perio_tx_fifo_size=%d\n", 3423 hw->host_perio_tx_fifo_size); 3424 dev_dbg(hsotg->dev, "\n"); 3425 3426 return 0; 3427 } 3428 3429 /* 3430 * Sets all parameters to the given value. 3431 * 3432 * Assumes that the dwc2_core_params struct contains only integers. 3433 */ 3434 void dwc2_set_all_params(struct dwc2_core_params *params, int value) 3435 { 3436 int *p = (int *)params; 3437 size_t size = sizeof(*params) / sizeof(*p); 3438 int i; 3439 3440 for (i = 0; i < size; i++) 3441 p[i] = value; 3442 } 3443 3444 3445 u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg) 3446 { 3447 return hsotg->core_params->otg_ver == 1 ? 0x0200 : 0x0103; 3448 } 3449 3450 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg) 3451 { 3452 if (dwc2_readl(hsotg->regs + GSNPSID) == 0xffffffff) 3453 return false; 3454 else 3455 return true; 3456 } 3457 3458 /** 3459 * dwc2_enable_global_interrupts() - Enables the controller's Global 3460 * Interrupt in the AHB Config register 3461 * 3462 * @hsotg: Programming view of DWC_otg controller 3463 */ 3464 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg) 3465 { 3466 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 3467 3468 ahbcfg |= GAHBCFG_GLBL_INTR_EN; 3469 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 3470 } 3471 3472 /** 3473 * dwc2_disable_global_interrupts() - Disables the controller's Global 3474 * Interrupt in the AHB Config register 3475 * 3476 * @hsotg: Programming view of DWC_otg controller 3477 */ 3478 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg) 3479 { 3480 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 3481 3482 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 3483 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 3484 } 3485 3486 /* Returns the controller's GHWCFG2.OTG_MODE. */ 3487 unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg) 3488 { 3489 u32 ghwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2); 3490 3491 return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >> 3492 GHWCFG2_OP_MODE_SHIFT; 3493 } 3494 3495 /* Returns true if the controller is capable of DRD. */ 3496 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg) 3497 { 3498 unsigned op_mode = dwc2_op_mode(hsotg); 3499 3500 return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) || 3501 (op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) || 3502 (op_mode == GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE); 3503 } 3504 3505 /* Returns true if the controller is host-only. */ 3506 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg) 3507 { 3508 unsigned op_mode = dwc2_op_mode(hsotg); 3509 3510 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) || 3511 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST); 3512 } 3513 3514 /* Returns true if the controller is device-only. */ 3515 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg) 3516 { 3517 unsigned op_mode = dwc2_op_mode(hsotg); 3518 3519 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) || 3520 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE); 3521 } 3522 3523 MODULE_DESCRIPTION("DESIGNWARE HS OTG Core"); 3524 MODULE_AUTHOR("Synopsys, Inc."); 3525 MODULE_LICENSE("Dual BSD/GPL"); 3526