1 /* 2 * core.c - DesignWare HS OTG Controller common routines 3 * 4 * Copyright (C) 2004-2013 Synopsys, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The names of the above-listed copyright holders may not be used 16 * to endorse or promote products derived from this software without 17 * specific prior written permission. 18 * 19 * ALTERNATIVELY, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") as published by the Free Software 21 * Foundation; either version 2 of the License, or (at your option) any 22 * later version. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * The Core code provides basic services for accessing and managing the 39 * DWC_otg hardware. These services are used by both the Host Controller 40 * Driver and the Peripheral Controller Driver. 41 */ 42 #include <linux/kernel.h> 43 #include <linux/module.h> 44 #include <linux/moduleparam.h> 45 #include <linux/spinlock.h> 46 #include <linux/interrupt.h> 47 #include <linux/dma-mapping.h> 48 #include <linux/delay.h> 49 #include <linux/io.h> 50 #include <linux/slab.h> 51 #include <linux/usb.h> 52 53 #include <linux/usb/hcd.h> 54 #include <linux/usb/ch11.h> 55 56 #include "core.h" 57 #include "hcd.h" 58 59 /** 60 * dwc2_backup_global_registers() - Backup global controller registers. 61 * When suspending usb bus, registers needs to be backuped 62 * if controller power is disabled once suspended. 63 * 64 * @hsotg: Programming view of the DWC_otg controller 65 */ 66 static int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg) 67 { 68 struct dwc2_gregs_backup *gr; 69 int i; 70 71 /* Backup global regs */ 72 gr = &hsotg->gr_backup; 73 74 gr->gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 75 gr->gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 76 gr->gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 77 gr->gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 78 gr->grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); 79 gr->gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); 80 gr->hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ); 81 gr->gdfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG); 82 for (i = 0; i < MAX_EPS_CHANNELS; i++) 83 gr->dtxfsiz[i] = dwc2_readl(hsotg->regs + DPTXFSIZN(i)); 84 85 gr->valid = true; 86 return 0; 87 } 88 89 /** 90 * dwc2_restore_global_registers() - Restore controller global registers. 91 * When resuming usb bus, device registers needs to be restored 92 * if controller power were disabled. 93 * 94 * @hsotg: Programming view of the DWC_otg controller 95 */ 96 static int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg) 97 { 98 struct dwc2_gregs_backup *gr; 99 int i; 100 101 dev_dbg(hsotg->dev, "%s\n", __func__); 102 103 /* Restore global regs */ 104 gr = &hsotg->gr_backup; 105 if (!gr->valid) { 106 dev_err(hsotg->dev, "%s: no global registers to restore\n", 107 __func__); 108 return -EINVAL; 109 } 110 gr->valid = false; 111 112 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 113 dwc2_writel(gr->gotgctl, hsotg->regs + GOTGCTL); 114 dwc2_writel(gr->gintmsk, hsotg->regs + GINTMSK); 115 dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG); 116 dwc2_writel(gr->gahbcfg, hsotg->regs + GAHBCFG); 117 dwc2_writel(gr->grxfsiz, hsotg->regs + GRXFSIZ); 118 dwc2_writel(gr->gnptxfsiz, hsotg->regs + GNPTXFSIZ); 119 dwc2_writel(gr->hptxfsiz, hsotg->regs + HPTXFSIZ); 120 dwc2_writel(gr->gdfifocfg, hsotg->regs + GDFIFOCFG); 121 for (i = 0; i < MAX_EPS_CHANNELS; i++) 122 dwc2_writel(gr->dtxfsiz[i], hsotg->regs + DPTXFSIZN(i)); 123 124 return 0; 125 } 126 127 /** 128 * dwc2_exit_hibernation() - Exit controller from Partial Power Down. 129 * 130 * @hsotg: Programming view of the DWC_otg controller 131 * @restore: Controller registers need to be restored 132 */ 133 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore) 134 { 135 u32 pcgcctl; 136 int ret = 0; 137 138 if (!hsotg->core_params->hibernation) 139 return -ENOTSUPP; 140 141 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 142 pcgcctl &= ~PCGCTL_STOPPCLK; 143 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 144 145 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 146 pcgcctl &= ~PCGCTL_PWRCLMP; 147 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 148 149 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 150 pcgcctl &= ~PCGCTL_RSTPDWNMODULE; 151 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 152 153 udelay(100); 154 if (restore) { 155 ret = dwc2_restore_global_registers(hsotg); 156 if (ret) { 157 dev_err(hsotg->dev, "%s: failed to restore registers\n", 158 __func__); 159 return ret; 160 } 161 if (dwc2_is_host_mode(hsotg)) { 162 ret = dwc2_restore_host_registers(hsotg); 163 if (ret) { 164 dev_err(hsotg->dev, "%s: failed to restore host registers\n", 165 __func__); 166 return ret; 167 } 168 } else { 169 ret = dwc2_restore_device_registers(hsotg); 170 if (ret) { 171 dev_err(hsotg->dev, "%s: failed to restore device registers\n", 172 __func__); 173 return ret; 174 } 175 } 176 } 177 178 return ret; 179 } 180 181 /** 182 * dwc2_enter_hibernation() - Put controller in Partial Power Down. 183 * 184 * @hsotg: Programming view of the DWC_otg controller 185 */ 186 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg) 187 { 188 u32 pcgcctl; 189 int ret = 0; 190 191 if (!hsotg->core_params->hibernation) 192 return -ENOTSUPP; 193 194 /* Backup all registers */ 195 ret = dwc2_backup_global_registers(hsotg); 196 if (ret) { 197 dev_err(hsotg->dev, "%s: failed to backup global registers\n", 198 __func__); 199 return ret; 200 } 201 202 if (dwc2_is_host_mode(hsotg)) { 203 ret = dwc2_backup_host_registers(hsotg); 204 if (ret) { 205 dev_err(hsotg->dev, "%s: failed to backup host registers\n", 206 __func__); 207 return ret; 208 } 209 } else { 210 ret = dwc2_backup_device_registers(hsotg); 211 if (ret) { 212 dev_err(hsotg->dev, "%s: failed to backup device registers\n", 213 __func__); 214 return ret; 215 } 216 } 217 218 /* 219 * Clear any pending interrupts since dwc2 will not be able to 220 * clear them after entering hibernation. 221 */ 222 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 223 224 /* Put the controller in low power state */ 225 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 226 227 pcgcctl |= PCGCTL_PWRCLMP; 228 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 229 ndelay(20); 230 231 pcgcctl |= PCGCTL_RSTPDWNMODULE; 232 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 233 ndelay(20); 234 235 pcgcctl |= PCGCTL_STOPPCLK; 236 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 237 238 return ret; 239 } 240 241 /** 242 * dwc2_wait_for_mode() - Waits for the controller mode. 243 * @hsotg: Programming view of the DWC_otg controller. 244 * @host_mode: If true, waits for host mode, otherwise device mode. 245 */ 246 static void dwc2_wait_for_mode(struct dwc2_hsotg *hsotg, 247 bool host_mode) 248 { 249 ktime_t start; 250 ktime_t end; 251 unsigned int timeout = 110; 252 253 dev_vdbg(hsotg->dev, "Waiting for %s mode\n", 254 host_mode ? "host" : "device"); 255 256 start = ktime_get(); 257 258 while (1) { 259 s64 ms; 260 261 if (dwc2_is_host_mode(hsotg) == host_mode) { 262 dev_vdbg(hsotg->dev, "%s mode set\n", 263 host_mode ? "Host" : "Device"); 264 break; 265 } 266 267 end = ktime_get(); 268 ms = ktime_to_ms(ktime_sub(end, start)); 269 270 if (ms >= (s64)timeout) { 271 dev_warn(hsotg->dev, "%s: Couldn't set %s mode\n", 272 __func__, host_mode ? "host" : "device"); 273 break; 274 } 275 276 usleep_range(1000, 2000); 277 } 278 } 279 280 /** 281 * dwc2_iddig_filter_enabled() - Returns true if the IDDIG debounce 282 * filter is enabled. 283 */ 284 static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg) 285 { 286 u32 gsnpsid; 287 u32 ghwcfg4; 288 289 if (!dwc2_hw_is_otg(hsotg)) 290 return false; 291 292 /* Check if core configuration includes the IDDIG filter. */ 293 ghwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4); 294 if (!(ghwcfg4 & GHWCFG4_IDDIG_FILT_EN)) 295 return false; 296 297 /* 298 * Check if the IDDIG debounce filter is bypassed. Available 299 * in core version >= 3.10a. 300 */ 301 gsnpsid = dwc2_readl(hsotg->regs + GSNPSID); 302 if (gsnpsid >= DWC2_CORE_REV_3_10a) { 303 u32 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 304 305 if (gotgctl & GOTGCTL_DBNCE_FLTR_BYPASS) 306 return false; 307 } 308 309 return true; 310 } 311 312 /* 313 * Do core a soft reset of the core. Be careful with this because it 314 * resets all the internal state machines of the core. 315 */ 316 int dwc2_core_reset(struct dwc2_hsotg *hsotg) 317 { 318 u32 greset; 319 int count = 0; 320 bool wait_for_host_mode = false; 321 322 dev_vdbg(hsotg->dev, "%s()\n", __func__); 323 324 /* 325 * If the current mode is host, either due to the force mode 326 * bit being set (which persists after core reset) or the 327 * connector id pin, a core soft reset will temporarily reset 328 * the mode to device. A delay from the IDDIG debounce filter 329 * will occur before going back to host mode. 330 * 331 * Determine whether we will go back into host mode after a 332 * reset and account for this delay after the reset. 333 */ 334 if (dwc2_iddig_filter_enabled(hsotg)) { 335 u32 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 336 u32 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 337 338 if (!(gotgctl & GOTGCTL_CONID_B) || 339 (gusbcfg & GUSBCFG_FORCEHOSTMODE)) { 340 wait_for_host_mode = true; 341 } 342 } 343 344 /* Core Soft Reset */ 345 greset = dwc2_readl(hsotg->regs + GRSTCTL); 346 greset |= GRSTCTL_CSFTRST; 347 dwc2_writel(greset, hsotg->regs + GRSTCTL); 348 do { 349 udelay(1); 350 greset = dwc2_readl(hsotg->regs + GRSTCTL); 351 if (++count > 50) { 352 dev_warn(hsotg->dev, 353 "%s() HANG! Soft Reset GRSTCTL=%0x\n", 354 __func__, greset); 355 return -EBUSY; 356 } 357 } while (greset & GRSTCTL_CSFTRST); 358 359 /* Wait for AHB master IDLE state */ 360 count = 0; 361 do { 362 udelay(1); 363 greset = dwc2_readl(hsotg->regs + GRSTCTL); 364 if (++count > 50) { 365 dev_warn(hsotg->dev, 366 "%s() HANG! AHB Idle GRSTCTL=%0x\n", 367 __func__, greset); 368 return -EBUSY; 369 } 370 } while (!(greset & GRSTCTL_AHBIDLE)); 371 372 if (wait_for_host_mode) 373 dwc2_wait_for_mode(hsotg, true); 374 375 return 0; 376 } 377 378 /* 379 * Force the mode of the controller. 380 * 381 * Forcing the mode is needed for two cases: 382 * 383 * 1) If the dr_mode is set to either HOST or PERIPHERAL we force the 384 * controller to stay in a particular mode regardless of ID pin 385 * changes. We do this usually after a core reset. 386 * 387 * 2) During probe we want to read reset values of the hw 388 * configuration registers that are only available in either host or 389 * device mode. We may need to force the mode if the current mode does 390 * not allow us to access the register in the mode that we want. 391 * 392 * In either case it only makes sense to force the mode if the 393 * controller hardware is OTG capable. 394 * 395 * Checks are done in this function to determine whether doing a force 396 * would be valid or not. 397 * 398 * If a force is done, it requires a IDDIG debounce filter delay if 399 * the filter is configured and enabled. We poll the current mode of 400 * the controller to account for this delay. 401 */ 402 static bool dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host) 403 { 404 u32 gusbcfg; 405 u32 set; 406 u32 clear; 407 408 dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device"); 409 410 /* 411 * Force mode has no effect if the hardware is not OTG. 412 */ 413 if (!dwc2_hw_is_otg(hsotg)) 414 return false; 415 416 /* 417 * If dr_mode is either peripheral or host only, there is no 418 * need to ever force the mode to the opposite mode. 419 */ 420 if (WARN_ON(host && hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)) 421 return false; 422 423 if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST)) 424 return false; 425 426 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 427 428 set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE; 429 clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE; 430 431 gusbcfg &= ~clear; 432 gusbcfg |= set; 433 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); 434 435 dwc2_wait_for_mode(hsotg, host); 436 return true; 437 } 438 439 /** 440 * dwc2_clear_force_mode() - Clears the force mode bits. 441 * 442 * After clearing the bits, wait up to 100 ms to account for any 443 * potential IDDIG filter delay. We can't know if we expect this delay 444 * or not because the value of the connector ID status is affected by 445 * the force mode. We only need to call this once during probe if 446 * dr_mode == OTG. 447 */ 448 static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg) 449 { 450 u32 gusbcfg; 451 452 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 453 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE; 454 gusbcfg &= ~GUSBCFG_FORCEDEVMODE; 455 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); 456 457 if (dwc2_iddig_filter_enabled(hsotg)) 458 usleep_range(100000, 110000); 459 } 460 461 /* 462 * Sets or clears force mode based on the dr_mode parameter. 463 */ 464 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg) 465 { 466 switch (hsotg->dr_mode) { 467 case USB_DR_MODE_HOST: 468 dwc2_force_mode(hsotg, true); 469 break; 470 case USB_DR_MODE_PERIPHERAL: 471 dwc2_force_mode(hsotg, false); 472 break; 473 case USB_DR_MODE_OTG: 474 dwc2_clear_force_mode(hsotg); 475 break; 476 default: 477 dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n", 478 __func__, hsotg->dr_mode); 479 break; 480 } 481 } 482 483 /* 484 * Do core a soft reset of the core. Be careful with this because it 485 * resets all the internal state machines of the core. 486 * 487 * Additionally this will apply force mode as per the hsotg->dr_mode 488 * parameter. 489 */ 490 int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg) 491 { 492 int retval; 493 494 retval = dwc2_core_reset(hsotg); 495 if (retval) 496 return retval; 497 498 dwc2_force_dr_mode(hsotg); 499 return 0; 500 } 501 502 /** 503 * dwc2_dump_host_registers() - Prints the host registers 504 * 505 * @hsotg: Programming view of DWC_otg controller 506 * 507 * NOTE: This function will be removed once the peripheral controller code 508 * is integrated and the driver is stable 509 */ 510 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg) 511 { 512 #ifdef DEBUG 513 u32 __iomem *addr; 514 int i; 515 516 dev_dbg(hsotg->dev, "Host Global Registers\n"); 517 addr = hsotg->regs + HCFG; 518 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n", 519 (unsigned long)addr, dwc2_readl(addr)); 520 addr = hsotg->regs + HFIR; 521 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n", 522 (unsigned long)addr, dwc2_readl(addr)); 523 addr = hsotg->regs + HFNUM; 524 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n", 525 (unsigned long)addr, dwc2_readl(addr)); 526 addr = hsotg->regs + HPTXSTS; 527 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n", 528 (unsigned long)addr, dwc2_readl(addr)); 529 addr = hsotg->regs + HAINT; 530 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n", 531 (unsigned long)addr, dwc2_readl(addr)); 532 addr = hsotg->regs + HAINTMSK; 533 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n", 534 (unsigned long)addr, dwc2_readl(addr)); 535 if (hsotg->core_params->dma_desc_enable > 0) { 536 addr = hsotg->regs + HFLBADDR; 537 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n", 538 (unsigned long)addr, dwc2_readl(addr)); 539 } 540 541 addr = hsotg->regs + HPRT0; 542 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n", 543 (unsigned long)addr, dwc2_readl(addr)); 544 545 for (i = 0; i < hsotg->core_params->host_channels; i++) { 546 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i); 547 addr = hsotg->regs + HCCHAR(i); 548 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n", 549 (unsigned long)addr, dwc2_readl(addr)); 550 addr = hsotg->regs + HCSPLT(i); 551 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n", 552 (unsigned long)addr, dwc2_readl(addr)); 553 addr = hsotg->regs + HCINT(i); 554 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n", 555 (unsigned long)addr, dwc2_readl(addr)); 556 addr = hsotg->regs + HCINTMSK(i); 557 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n", 558 (unsigned long)addr, dwc2_readl(addr)); 559 addr = hsotg->regs + HCTSIZ(i); 560 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n", 561 (unsigned long)addr, dwc2_readl(addr)); 562 addr = hsotg->regs + HCDMA(i); 563 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n", 564 (unsigned long)addr, dwc2_readl(addr)); 565 if (hsotg->core_params->dma_desc_enable > 0) { 566 addr = hsotg->regs + HCDMAB(i); 567 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n", 568 (unsigned long)addr, dwc2_readl(addr)); 569 } 570 } 571 #endif 572 } 573 574 /** 575 * dwc2_dump_global_registers() - Prints the core global registers 576 * 577 * @hsotg: Programming view of DWC_otg controller 578 * 579 * NOTE: This function will be removed once the peripheral controller code 580 * is integrated and the driver is stable 581 */ 582 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg) 583 { 584 #ifdef DEBUG 585 u32 __iomem *addr; 586 587 dev_dbg(hsotg->dev, "Core Global Registers\n"); 588 addr = hsotg->regs + GOTGCTL; 589 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n", 590 (unsigned long)addr, dwc2_readl(addr)); 591 addr = hsotg->regs + GOTGINT; 592 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n", 593 (unsigned long)addr, dwc2_readl(addr)); 594 addr = hsotg->regs + GAHBCFG; 595 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n", 596 (unsigned long)addr, dwc2_readl(addr)); 597 addr = hsotg->regs + GUSBCFG; 598 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n", 599 (unsigned long)addr, dwc2_readl(addr)); 600 addr = hsotg->regs + GRSTCTL; 601 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n", 602 (unsigned long)addr, dwc2_readl(addr)); 603 addr = hsotg->regs + GINTSTS; 604 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n", 605 (unsigned long)addr, dwc2_readl(addr)); 606 addr = hsotg->regs + GINTMSK; 607 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n", 608 (unsigned long)addr, dwc2_readl(addr)); 609 addr = hsotg->regs + GRXSTSR; 610 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n", 611 (unsigned long)addr, dwc2_readl(addr)); 612 addr = hsotg->regs + GRXFSIZ; 613 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n", 614 (unsigned long)addr, dwc2_readl(addr)); 615 addr = hsotg->regs + GNPTXFSIZ; 616 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n", 617 (unsigned long)addr, dwc2_readl(addr)); 618 addr = hsotg->regs + GNPTXSTS; 619 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n", 620 (unsigned long)addr, dwc2_readl(addr)); 621 addr = hsotg->regs + GI2CCTL; 622 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n", 623 (unsigned long)addr, dwc2_readl(addr)); 624 addr = hsotg->regs + GPVNDCTL; 625 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n", 626 (unsigned long)addr, dwc2_readl(addr)); 627 addr = hsotg->regs + GGPIO; 628 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n", 629 (unsigned long)addr, dwc2_readl(addr)); 630 addr = hsotg->regs + GUID; 631 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n", 632 (unsigned long)addr, dwc2_readl(addr)); 633 addr = hsotg->regs + GSNPSID; 634 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n", 635 (unsigned long)addr, dwc2_readl(addr)); 636 addr = hsotg->regs + GHWCFG1; 637 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n", 638 (unsigned long)addr, dwc2_readl(addr)); 639 addr = hsotg->regs + GHWCFG2; 640 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n", 641 (unsigned long)addr, dwc2_readl(addr)); 642 addr = hsotg->regs + GHWCFG3; 643 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n", 644 (unsigned long)addr, dwc2_readl(addr)); 645 addr = hsotg->regs + GHWCFG4; 646 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n", 647 (unsigned long)addr, dwc2_readl(addr)); 648 addr = hsotg->regs + GLPMCFG; 649 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n", 650 (unsigned long)addr, dwc2_readl(addr)); 651 addr = hsotg->regs + GPWRDN; 652 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n", 653 (unsigned long)addr, dwc2_readl(addr)); 654 addr = hsotg->regs + GDFIFOCFG; 655 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n", 656 (unsigned long)addr, dwc2_readl(addr)); 657 addr = hsotg->regs + HPTXFSIZ; 658 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n", 659 (unsigned long)addr, dwc2_readl(addr)); 660 661 addr = hsotg->regs + PCGCTL; 662 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n", 663 (unsigned long)addr, dwc2_readl(addr)); 664 #endif 665 } 666 667 /** 668 * dwc2_flush_tx_fifo() - Flushes a Tx FIFO 669 * 670 * @hsotg: Programming view of DWC_otg controller 671 * @num: Tx FIFO to flush 672 */ 673 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num) 674 { 675 u32 greset; 676 int count = 0; 677 678 dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num); 679 680 greset = GRSTCTL_TXFFLSH; 681 greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK; 682 dwc2_writel(greset, hsotg->regs + GRSTCTL); 683 684 do { 685 greset = dwc2_readl(hsotg->regs + GRSTCTL); 686 if (++count > 10000) { 687 dev_warn(hsotg->dev, 688 "%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n", 689 __func__, greset, 690 dwc2_readl(hsotg->regs + GNPTXSTS)); 691 break; 692 } 693 udelay(1); 694 } while (greset & GRSTCTL_TXFFLSH); 695 696 /* Wait for at least 3 PHY Clocks */ 697 udelay(1); 698 } 699 700 /** 701 * dwc2_flush_rx_fifo() - Flushes the Rx FIFO 702 * 703 * @hsotg: Programming view of DWC_otg controller 704 */ 705 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg) 706 { 707 u32 greset; 708 int count = 0; 709 710 dev_vdbg(hsotg->dev, "%s()\n", __func__); 711 712 greset = GRSTCTL_RXFFLSH; 713 dwc2_writel(greset, hsotg->regs + GRSTCTL); 714 715 do { 716 greset = dwc2_readl(hsotg->regs + GRSTCTL); 717 if (++count > 10000) { 718 dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n", 719 __func__, greset); 720 break; 721 } 722 udelay(1); 723 } while (greset & GRSTCTL_RXFFLSH); 724 725 /* Wait for at least 3 PHY Clocks */ 726 udelay(1); 727 } 728 729 #define DWC2_OUT_OF_BOUNDS(a, b, c) ((a) < (b) || (a) > (c)) 730 731 /* Parameter access functions */ 732 void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val) 733 { 734 int valid = 1; 735 736 switch (val) { 737 case DWC2_CAP_PARAM_HNP_SRP_CAPABLE: 738 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) 739 valid = 0; 740 break; 741 case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE: 742 switch (hsotg->hw_params.op_mode) { 743 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 744 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 745 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 746 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 747 break; 748 default: 749 valid = 0; 750 break; 751 } 752 break; 753 case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE: 754 /* always valid */ 755 break; 756 default: 757 valid = 0; 758 break; 759 } 760 761 if (!valid) { 762 if (val >= 0) 763 dev_err(hsotg->dev, 764 "%d invalid for otg_cap parameter. Check HW configuration.\n", 765 val); 766 switch (hsotg->hw_params.op_mode) { 767 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 768 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE; 769 break; 770 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 771 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 772 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 773 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE; 774 break; 775 default: 776 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 777 break; 778 } 779 dev_dbg(hsotg->dev, "Setting otg_cap to %d\n", val); 780 } 781 782 hsotg->core_params->otg_cap = val; 783 } 784 785 void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val) 786 { 787 int valid = 1; 788 789 if (val > 0 && hsotg->hw_params.arch == GHWCFG2_SLAVE_ONLY_ARCH) 790 valid = 0; 791 if (val < 0) 792 valid = 0; 793 794 if (!valid) { 795 if (val >= 0) 796 dev_err(hsotg->dev, 797 "%d invalid for dma_enable parameter. Check HW configuration.\n", 798 val); 799 val = hsotg->hw_params.arch != GHWCFG2_SLAVE_ONLY_ARCH; 800 dev_dbg(hsotg->dev, "Setting dma_enable to %d\n", val); 801 } 802 803 hsotg->core_params->dma_enable = val; 804 } 805 806 void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val) 807 { 808 int valid = 1; 809 810 if (val > 0 && (hsotg->core_params->dma_enable <= 0 || 811 !hsotg->hw_params.dma_desc_enable)) 812 valid = 0; 813 if (val < 0) 814 valid = 0; 815 816 if (!valid) { 817 if (val >= 0) 818 dev_err(hsotg->dev, 819 "%d invalid for dma_desc_enable parameter. Check HW configuration.\n", 820 val); 821 val = (hsotg->core_params->dma_enable > 0 && 822 hsotg->hw_params.dma_desc_enable); 823 dev_dbg(hsotg->dev, "Setting dma_desc_enable to %d\n", val); 824 } 825 826 hsotg->core_params->dma_desc_enable = val; 827 } 828 829 void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg, int val) 830 { 831 int valid = 1; 832 833 if (val > 0 && (hsotg->core_params->dma_enable <= 0 || 834 !hsotg->hw_params.dma_desc_enable)) 835 valid = 0; 836 if (val < 0) 837 valid = 0; 838 839 if (!valid) { 840 if (val >= 0) 841 dev_err(hsotg->dev, 842 "%d invalid for dma_desc_fs_enable parameter. Check HW configuration.\n", 843 val); 844 val = (hsotg->core_params->dma_enable > 0 && 845 hsotg->hw_params.dma_desc_enable); 846 } 847 848 hsotg->core_params->dma_desc_fs_enable = val; 849 dev_dbg(hsotg->dev, "Setting dma_desc_fs_enable to %d\n", val); 850 } 851 852 void dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg, 853 int val) 854 { 855 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 856 if (val >= 0) { 857 dev_err(hsotg->dev, 858 "Wrong value for host_support_fs_low_power\n"); 859 dev_err(hsotg->dev, 860 "host_support_fs_low_power must be 0 or 1\n"); 861 } 862 val = 0; 863 dev_dbg(hsotg->dev, 864 "Setting host_support_fs_low_power to %d\n", val); 865 } 866 867 hsotg->core_params->host_support_fs_ls_low_power = val; 868 } 869 870 void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, int val) 871 { 872 int valid = 1; 873 874 if (val > 0 && !hsotg->hw_params.enable_dynamic_fifo) 875 valid = 0; 876 if (val < 0) 877 valid = 0; 878 879 if (!valid) { 880 if (val >= 0) 881 dev_err(hsotg->dev, 882 "%d invalid for enable_dynamic_fifo parameter. Check HW configuration.\n", 883 val); 884 val = hsotg->hw_params.enable_dynamic_fifo; 885 dev_dbg(hsotg->dev, "Setting enable_dynamic_fifo to %d\n", val); 886 } 887 888 hsotg->core_params->enable_dynamic_fifo = val; 889 } 890 891 void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val) 892 { 893 int valid = 1; 894 895 if (val < 16 || val > hsotg->hw_params.host_rx_fifo_size) 896 valid = 0; 897 898 if (!valid) { 899 if (val >= 0) 900 dev_err(hsotg->dev, 901 "%d invalid for host_rx_fifo_size. Check HW configuration.\n", 902 val); 903 val = hsotg->hw_params.host_rx_fifo_size; 904 dev_dbg(hsotg->dev, "Setting host_rx_fifo_size to %d\n", val); 905 } 906 907 hsotg->core_params->host_rx_fifo_size = val; 908 } 909 910 void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val) 911 { 912 int valid = 1; 913 914 if (val < 16 || val > hsotg->hw_params.host_nperio_tx_fifo_size) 915 valid = 0; 916 917 if (!valid) { 918 if (val >= 0) 919 dev_err(hsotg->dev, 920 "%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n", 921 val); 922 val = hsotg->hw_params.host_nperio_tx_fifo_size; 923 dev_dbg(hsotg->dev, "Setting host_nperio_tx_fifo_size to %d\n", 924 val); 925 } 926 927 hsotg->core_params->host_nperio_tx_fifo_size = val; 928 } 929 930 void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val) 931 { 932 int valid = 1; 933 934 if (val < 16 || val > hsotg->hw_params.host_perio_tx_fifo_size) 935 valid = 0; 936 937 if (!valid) { 938 if (val >= 0) 939 dev_err(hsotg->dev, 940 "%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n", 941 val); 942 val = hsotg->hw_params.host_perio_tx_fifo_size; 943 dev_dbg(hsotg->dev, "Setting host_perio_tx_fifo_size to %d\n", 944 val); 945 } 946 947 hsotg->core_params->host_perio_tx_fifo_size = val; 948 } 949 950 void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val) 951 { 952 int valid = 1; 953 954 if (val < 2047 || val > hsotg->hw_params.max_transfer_size) 955 valid = 0; 956 957 if (!valid) { 958 if (val >= 0) 959 dev_err(hsotg->dev, 960 "%d invalid for max_transfer_size. Check HW configuration.\n", 961 val); 962 val = hsotg->hw_params.max_transfer_size; 963 dev_dbg(hsotg->dev, "Setting max_transfer_size to %d\n", val); 964 } 965 966 hsotg->core_params->max_transfer_size = val; 967 } 968 969 void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val) 970 { 971 int valid = 1; 972 973 if (val < 15 || val > hsotg->hw_params.max_packet_count) 974 valid = 0; 975 976 if (!valid) { 977 if (val >= 0) 978 dev_err(hsotg->dev, 979 "%d invalid for max_packet_count. Check HW configuration.\n", 980 val); 981 val = hsotg->hw_params.max_packet_count; 982 dev_dbg(hsotg->dev, "Setting max_packet_count to %d\n", val); 983 } 984 985 hsotg->core_params->max_packet_count = val; 986 } 987 988 void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val) 989 { 990 int valid = 1; 991 992 if (val < 1 || val > hsotg->hw_params.host_channels) 993 valid = 0; 994 995 if (!valid) { 996 if (val >= 0) 997 dev_err(hsotg->dev, 998 "%d invalid for host_channels. Check HW configuration.\n", 999 val); 1000 val = hsotg->hw_params.host_channels; 1001 dev_dbg(hsotg->dev, "Setting host_channels to %d\n", val); 1002 } 1003 1004 hsotg->core_params->host_channels = val; 1005 } 1006 1007 void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val) 1008 { 1009 int valid = 0; 1010 u32 hs_phy_type, fs_phy_type; 1011 1012 if (DWC2_OUT_OF_BOUNDS(val, DWC2_PHY_TYPE_PARAM_FS, 1013 DWC2_PHY_TYPE_PARAM_ULPI)) { 1014 if (val >= 0) { 1015 dev_err(hsotg->dev, "Wrong value for phy_type\n"); 1016 dev_err(hsotg->dev, "phy_type must be 0, 1 or 2\n"); 1017 } 1018 1019 valid = 0; 1020 } 1021 1022 hs_phy_type = hsotg->hw_params.hs_phy_type; 1023 fs_phy_type = hsotg->hw_params.fs_phy_type; 1024 if (val == DWC2_PHY_TYPE_PARAM_UTMI && 1025 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || 1026 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 1027 valid = 1; 1028 else if (val == DWC2_PHY_TYPE_PARAM_ULPI && 1029 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI || 1030 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 1031 valid = 1; 1032 else if (val == DWC2_PHY_TYPE_PARAM_FS && 1033 fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 1034 valid = 1; 1035 1036 if (!valid) { 1037 if (val >= 0) 1038 dev_err(hsotg->dev, 1039 "%d invalid for phy_type. Check HW configuration.\n", 1040 val); 1041 val = DWC2_PHY_TYPE_PARAM_FS; 1042 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) { 1043 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || 1044 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI) 1045 val = DWC2_PHY_TYPE_PARAM_UTMI; 1046 else 1047 val = DWC2_PHY_TYPE_PARAM_ULPI; 1048 } 1049 dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val); 1050 } 1051 1052 hsotg->core_params->phy_type = val; 1053 } 1054 1055 static int dwc2_get_param_phy_type(struct dwc2_hsotg *hsotg) 1056 { 1057 return hsotg->core_params->phy_type; 1058 } 1059 1060 void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val) 1061 { 1062 int valid = 1; 1063 1064 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 1065 if (val >= 0) { 1066 dev_err(hsotg->dev, "Wrong value for speed parameter\n"); 1067 dev_err(hsotg->dev, "max_speed parameter must be 0 or 1\n"); 1068 } 1069 valid = 0; 1070 } 1071 1072 if (val == DWC2_SPEED_PARAM_HIGH && 1073 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS) 1074 valid = 0; 1075 1076 if (!valid) { 1077 if (val >= 0) 1078 dev_err(hsotg->dev, 1079 "%d invalid for speed parameter. Check HW configuration.\n", 1080 val); 1081 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS ? 1082 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH; 1083 dev_dbg(hsotg->dev, "Setting speed to %d\n", val); 1084 } 1085 1086 hsotg->core_params->speed = val; 1087 } 1088 1089 void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, int val) 1090 { 1091 int valid = 1; 1092 1093 if (DWC2_OUT_OF_BOUNDS(val, DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ, 1094 DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)) { 1095 if (val >= 0) { 1096 dev_err(hsotg->dev, 1097 "Wrong value for host_ls_low_power_phy_clk parameter\n"); 1098 dev_err(hsotg->dev, 1099 "host_ls_low_power_phy_clk must be 0 or 1\n"); 1100 } 1101 valid = 0; 1102 } 1103 1104 if (val == DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ && 1105 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS) 1106 valid = 0; 1107 1108 if (!valid) { 1109 if (val >= 0) 1110 dev_err(hsotg->dev, 1111 "%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n", 1112 val); 1113 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS 1114 ? DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1115 : DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ; 1116 dev_dbg(hsotg->dev, "Setting host_ls_low_power_phy_clk to %d\n", 1117 val); 1118 } 1119 1120 hsotg->core_params->host_ls_low_power_phy_clk = val; 1121 } 1122 1123 void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val) 1124 { 1125 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 1126 if (val >= 0) { 1127 dev_err(hsotg->dev, "Wrong value for phy_ulpi_ddr\n"); 1128 dev_err(hsotg->dev, "phy_upli_ddr must be 0 or 1\n"); 1129 } 1130 val = 0; 1131 dev_dbg(hsotg->dev, "Setting phy_upli_ddr to %d\n", val); 1132 } 1133 1134 hsotg->core_params->phy_ulpi_ddr = val; 1135 } 1136 1137 void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val) 1138 { 1139 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 1140 if (val >= 0) { 1141 dev_err(hsotg->dev, 1142 "Wrong value for phy_ulpi_ext_vbus\n"); 1143 dev_err(hsotg->dev, 1144 "phy_ulpi_ext_vbus must be 0 or 1\n"); 1145 } 1146 val = 0; 1147 dev_dbg(hsotg->dev, "Setting phy_ulpi_ext_vbus to %d\n", val); 1148 } 1149 1150 hsotg->core_params->phy_ulpi_ext_vbus = val; 1151 } 1152 1153 void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val) 1154 { 1155 int valid = 0; 1156 1157 switch (hsotg->hw_params.utmi_phy_data_width) { 1158 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8: 1159 valid = (val == 8); 1160 break; 1161 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16: 1162 valid = (val == 16); 1163 break; 1164 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16: 1165 valid = (val == 8 || val == 16); 1166 break; 1167 } 1168 1169 if (!valid) { 1170 if (val >= 0) { 1171 dev_err(hsotg->dev, 1172 "%d invalid for phy_utmi_width. Check HW configuration.\n", 1173 val); 1174 } 1175 val = (hsotg->hw_params.utmi_phy_data_width == 1176 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16; 1177 dev_dbg(hsotg->dev, "Setting phy_utmi_width to %d\n", val); 1178 } 1179 1180 hsotg->core_params->phy_utmi_width = val; 1181 } 1182 1183 void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val) 1184 { 1185 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 1186 if (val >= 0) { 1187 dev_err(hsotg->dev, "Wrong value for ulpi_fs_ls\n"); 1188 dev_err(hsotg->dev, "ulpi_fs_ls must be 0 or 1\n"); 1189 } 1190 val = 0; 1191 dev_dbg(hsotg->dev, "Setting ulpi_fs_ls to %d\n", val); 1192 } 1193 1194 hsotg->core_params->ulpi_fs_ls = val; 1195 } 1196 1197 void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val) 1198 { 1199 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 1200 if (val >= 0) { 1201 dev_err(hsotg->dev, "Wrong value for ts_dline\n"); 1202 dev_err(hsotg->dev, "ts_dline must be 0 or 1\n"); 1203 } 1204 val = 0; 1205 dev_dbg(hsotg->dev, "Setting ts_dline to %d\n", val); 1206 } 1207 1208 hsotg->core_params->ts_dline = val; 1209 } 1210 1211 void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val) 1212 { 1213 int valid = 1; 1214 1215 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 1216 if (val >= 0) { 1217 dev_err(hsotg->dev, "Wrong value for i2c_enable\n"); 1218 dev_err(hsotg->dev, "i2c_enable must be 0 or 1\n"); 1219 } 1220 1221 valid = 0; 1222 } 1223 1224 if (val == 1 && !(hsotg->hw_params.i2c_enable)) 1225 valid = 0; 1226 1227 if (!valid) { 1228 if (val >= 0) 1229 dev_err(hsotg->dev, 1230 "%d invalid for i2c_enable. Check HW configuration.\n", 1231 val); 1232 val = hsotg->hw_params.i2c_enable; 1233 dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val); 1234 } 1235 1236 hsotg->core_params->i2c_enable = val; 1237 } 1238 1239 void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, int val) 1240 { 1241 int valid = 1; 1242 1243 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 1244 if (val >= 0) { 1245 dev_err(hsotg->dev, 1246 "Wrong value for en_multiple_tx_fifo,\n"); 1247 dev_err(hsotg->dev, 1248 "en_multiple_tx_fifo must be 0 or 1\n"); 1249 } 1250 valid = 0; 1251 } 1252 1253 if (val == 1 && !hsotg->hw_params.en_multiple_tx_fifo) 1254 valid = 0; 1255 1256 if (!valid) { 1257 if (val >= 0) 1258 dev_err(hsotg->dev, 1259 "%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n", 1260 val); 1261 val = hsotg->hw_params.en_multiple_tx_fifo; 1262 dev_dbg(hsotg->dev, "Setting en_multiple_tx_fifo to %d\n", val); 1263 } 1264 1265 hsotg->core_params->en_multiple_tx_fifo = val; 1266 } 1267 1268 void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val) 1269 { 1270 int valid = 1; 1271 1272 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 1273 if (val >= 0) { 1274 dev_err(hsotg->dev, 1275 "'%d' invalid for parameter reload_ctl\n", val); 1276 dev_err(hsotg->dev, "reload_ctl must be 0 or 1\n"); 1277 } 1278 valid = 0; 1279 } 1280 1281 if (val == 1 && hsotg->hw_params.snpsid < DWC2_CORE_REV_2_92a) 1282 valid = 0; 1283 1284 if (!valid) { 1285 if (val >= 0) 1286 dev_err(hsotg->dev, 1287 "%d invalid for parameter reload_ctl. Check HW configuration.\n", 1288 val); 1289 val = hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_92a; 1290 dev_dbg(hsotg->dev, "Setting reload_ctl to %d\n", val); 1291 } 1292 1293 hsotg->core_params->reload_ctl = val; 1294 } 1295 1296 void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val) 1297 { 1298 if (val != -1) 1299 hsotg->core_params->ahbcfg = val; 1300 else 1301 hsotg->core_params->ahbcfg = GAHBCFG_HBSTLEN_INCR4 << 1302 GAHBCFG_HBSTLEN_SHIFT; 1303 } 1304 1305 void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val) 1306 { 1307 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 1308 if (val >= 0) { 1309 dev_err(hsotg->dev, 1310 "'%d' invalid for parameter otg_ver\n", val); 1311 dev_err(hsotg->dev, 1312 "otg_ver must be 0 (for OTG 1.3 support) or 1 (for OTG 2.0 support)\n"); 1313 } 1314 val = 0; 1315 dev_dbg(hsotg->dev, "Setting otg_ver to %d\n", val); 1316 } 1317 1318 hsotg->core_params->otg_ver = val; 1319 } 1320 1321 static void dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val) 1322 { 1323 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 1324 if (val >= 0) { 1325 dev_err(hsotg->dev, 1326 "'%d' invalid for parameter uframe_sched\n", 1327 val); 1328 dev_err(hsotg->dev, "uframe_sched must be 0 or 1\n"); 1329 } 1330 val = 1; 1331 dev_dbg(hsotg->dev, "Setting uframe_sched to %d\n", val); 1332 } 1333 1334 hsotg->core_params->uframe_sched = val; 1335 } 1336 1337 static void dwc2_set_param_external_id_pin_ctl(struct dwc2_hsotg *hsotg, 1338 int val) 1339 { 1340 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 1341 if (val >= 0) { 1342 dev_err(hsotg->dev, 1343 "'%d' invalid for parameter external_id_pin_ctl\n", 1344 val); 1345 dev_err(hsotg->dev, "external_id_pin_ctl must be 0 or 1\n"); 1346 } 1347 val = 0; 1348 dev_dbg(hsotg->dev, "Setting external_id_pin_ctl to %d\n", val); 1349 } 1350 1351 hsotg->core_params->external_id_pin_ctl = val; 1352 } 1353 1354 static void dwc2_set_param_hibernation(struct dwc2_hsotg *hsotg, 1355 int val) 1356 { 1357 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 1358 if (val >= 0) { 1359 dev_err(hsotg->dev, 1360 "'%d' invalid for parameter hibernation\n", 1361 val); 1362 dev_err(hsotg->dev, "hibernation must be 0 or 1\n"); 1363 } 1364 val = 0; 1365 dev_dbg(hsotg->dev, "Setting hibernation to %d\n", val); 1366 } 1367 1368 hsotg->core_params->hibernation = val; 1369 } 1370 1371 /* 1372 * This function is called during module intialization to pass module parameters 1373 * for the DWC_otg core. 1374 */ 1375 void dwc2_set_parameters(struct dwc2_hsotg *hsotg, 1376 const struct dwc2_core_params *params) 1377 { 1378 dev_dbg(hsotg->dev, "%s()\n", __func__); 1379 1380 dwc2_set_param_otg_cap(hsotg, params->otg_cap); 1381 dwc2_set_param_dma_enable(hsotg, params->dma_enable); 1382 dwc2_set_param_dma_desc_enable(hsotg, params->dma_desc_enable); 1383 dwc2_set_param_dma_desc_fs_enable(hsotg, params->dma_desc_fs_enable); 1384 dwc2_set_param_host_support_fs_ls_low_power(hsotg, 1385 params->host_support_fs_ls_low_power); 1386 dwc2_set_param_enable_dynamic_fifo(hsotg, 1387 params->enable_dynamic_fifo); 1388 dwc2_set_param_host_rx_fifo_size(hsotg, 1389 params->host_rx_fifo_size); 1390 dwc2_set_param_host_nperio_tx_fifo_size(hsotg, 1391 params->host_nperio_tx_fifo_size); 1392 dwc2_set_param_host_perio_tx_fifo_size(hsotg, 1393 params->host_perio_tx_fifo_size); 1394 dwc2_set_param_max_transfer_size(hsotg, 1395 params->max_transfer_size); 1396 dwc2_set_param_max_packet_count(hsotg, 1397 params->max_packet_count); 1398 dwc2_set_param_host_channels(hsotg, params->host_channels); 1399 dwc2_set_param_phy_type(hsotg, params->phy_type); 1400 dwc2_set_param_speed(hsotg, params->speed); 1401 dwc2_set_param_host_ls_low_power_phy_clk(hsotg, 1402 params->host_ls_low_power_phy_clk); 1403 dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr); 1404 dwc2_set_param_phy_ulpi_ext_vbus(hsotg, 1405 params->phy_ulpi_ext_vbus); 1406 dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width); 1407 dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls); 1408 dwc2_set_param_ts_dline(hsotg, params->ts_dline); 1409 dwc2_set_param_i2c_enable(hsotg, params->i2c_enable); 1410 dwc2_set_param_en_multiple_tx_fifo(hsotg, 1411 params->en_multiple_tx_fifo); 1412 dwc2_set_param_reload_ctl(hsotg, params->reload_ctl); 1413 dwc2_set_param_ahbcfg(hsotg, params->ahbcfg); 1414 dwc2_set_param_otg_ver(hsotg, params->otg_ver); 1415 dwc2_set_param_uframe_sched(hsotg, params->uframe_sched); 1416 dwc2_set_param_external_id_pin_ctl(hsotg, params->external_id_pin_ctl); 1417 dwc2_set_param_hibernation(hsotg, params->hibernation); 1418 } 1419 1420 /* 1421 * Forces either host or device mode if the controller is not 1422 * currently in that mode. 1423 * 1424 * Returns true if the mode was forced. 1425 */ 1426 static bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host) 1427 { 1428 if (host && dwc2_is_host_mode(hsotg)) 1429 return false; 1430 else if (!host && dwc2_is_device_mode(hsotg)) 1431 return false; 1432 1433 return dwc2_force_mode(hsotg, host); 1434 } 1435 1436 /* 1437 * Gets host hardware parameters. Forces host mode if not currently in 1438 * host mode. Should be called immediately after a core soft reset in 1439 * order to get the reset values. 1440 */ 1441 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg) 1442 { 1443 struct dwc2_hw_params *hw = &hsotg->hw_params; 1444 u32 gnptxfsiz; 1445 u32 hptxfsiz; 1446 bool forced; 1447 1448 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) 1449 return; 1450 1451 forced = dwc2_force_mode_if_needed(hsotg, true); 1452 1453 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); 1454 hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ); 1455 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz); 1456 dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz); 1457 1458 if (forced) 1459 dwc2_clear_force_mode(hsotg); 1460 1461 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 1462 FIFOSIZE_DEPTH_SHIFT; 1463 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> 1464 FIFOSIZE_DEPTH_SHIFT; 1465 } 1466 1467 /* 1468 * Gets device hardware parameters. Forces device mode if not 1469 * currently in device mode. Should be called immediately after a core 1470 * soft reset in order to get the reset values. 1471 */ 1472 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg) 1473 { 1474 struct dwc2_hw_params *hw = &hsotg->hw_params; 1475 bool forced; 1476 u32 gnptxfsiz; 1477 1478 if (hsotg->dr_mode == USB_DR_MODE_HOST) 1479 return; 1480 1481 forced = dwc2_force_mode_if_needed(hsotg, false); 1482 1483 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); 1484 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz); 1485 1486 if (forced) 1487 dwc2_clear_force_mode(hsotg); 1488 1489 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 1490 FIFOSIZE_DEPTH_SHIFT; 1491 } 1492 1493 /** 1494 * During device initialization, read various hardware configuration 1495 * registers and interpret the contents. 1496 */ 1497 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) 1498 { 1499 struct dwc2_hw_params *hw = &hsotg->hw_params; 1500 unsigned width; 1501 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4; 1502 u32 grxfsiz; 1503 1504 /* 1505 * Attempt to ensure this device is really a DWC_otg Controller. 1506 * Read and verify the GSNPSID register contents. The value should be 1507 * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3", 1508 * as in "OTG version 2.xx" or "OTG version 3.xx". 1509 */ 1510 hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID); 1511 if ((hw->snpsid & 0xfffff000) != 0x4f542000 && 1512 (hw->snpsid & 0xfffff000) != 0x4f543000) { 1513 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n", 1514 hw->snpsid); 1515 return -ENODEV; 1516 } 1517 1518 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n", 1519 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf, 1520 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid); 1521 1522 hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1); 1523 hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2); 1524 hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3); 1525 hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4); 1526 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); 1527 1528 dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1); 1529 dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2); 1530 dev_dbg(hsotg->dev, "hwcfg3=%08x\n", hwcfg3); 1531 dev_dbg(hsotg->dev, "hwcfg4=%08x\n", hwcfg4); 1532 dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz); 1533 1534 /* 1535 * Host specific hardware parameters. Reading these parameters 1536 * requires the controller to be in host mode. The mode will 1537 * be forced, if necessary, to read these values. 1538 */ 1539 dwc2_get_host_hwparams(hsotg); 1540 dwc2_get_dev_hwparams(hsotg); 1541 1542 /* hwcfg1 */ 1543 hw->dev_ep_dirs = hwcfg1; 1544 1545 /* hwcfg2 */ 1546 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> 1547 GHWCFG2_OP_MODE_SHIFT; 1548 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> 1549 GHWCFG2_ARCHITECTURE_SHIFT; 1550 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); 1551 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> 1552 GHWCFG2_NUM_HOST_CHAN_SHIFT); 1553 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> 1554 GHWCFG2_HS_PHY_TYPE_SHIFT; 1555 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> 1556 GHWCFG2_FS_PHY_TYPE_SHIFT; 1557 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> 1558 GHWCFG2_NUM_DEV_EP_SHIFT; 1559 hw->nperio_tx_q_depth = 1560 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >> 1561 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1; 1562 hw->host_perio_tx_q_depth = 1563 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >> 1564 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1; 1565 hw->dev_token_q_depth = 1566 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >> 1567 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT; 1568 1569 /* hwcfg3 */ 1570 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >> 1571 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT; 1572 hw->max_transfer_size = (1 << (width + 11)) - 1; 1573 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >> 1574 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT; 1575 hw->max_packet_count = (1 << (width + 4)) - 1; 1576 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); 1577 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> 1578 GHWCFG3_DFIFO_DEPTH_SHIFT; 1579 1580 /* hwcfg4 */ 1581 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); 1582 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> 1583 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT; 1584 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); 1585 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); 1586 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> 1587 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT; 1588 1589 /* fifo sizes */ 1590 hw->host_rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> 1591 GRXFSIZ_DEPTH_SHIFT; 1592 1593 dev_dbg(hsotg->dev, "Detected values from hardware:\n"); 1594 dev_dbg(hsotg->dev, " op_mode=%d\n", 1595 hw->op_mode); 1596 dev_dbg(hsotg->dev, " arch=%d\n", 1597 hw->arch); 1598 dev_dbg(hsotg->dev, " dma_desc_enable=%d\n", 1599 hw->dma_desc_enable); 1600 dev_dbg(hsotg->dev, " power_optimized=%d\n", 1601 hw->power_optimized); 1602 dev_dbg(hsotg->dev, " i2c_enable=%d\n", 1603 hw->i2c_enable); 1604 dev_dbg(hsotg->dev, " hs_phy_type=%d\n", 1605 hw->hs_phy_type); 1606 dev_dbg(hsotg->dev, " fs_phy_type=%d\n", 1607 hw->fs_phy_type); 1608 dev_dbg(hsotg->dev, " utmi_phy_data_width=%d\n", 1609 hw->utmi_phy_data_width); 1610 dev_dbg(hsotg->dev, " num_dev_ep=%d\n", 1611 hw->num_dev_ep); 1612 dev_dbg(hsotg->dev, " num_dev_perio_in_ep=%d\n", 1613 hw->num_dev_perio_in_ep); 1614 dev_dbg(hsotg->dev, " host_channels=%d\n", 1615 hw->host_channels); 1616 dev_dbg(hsotg->dev, " max_transfer_size=%d\n", 1617 hw->max_transfer_size); 1618 dev_dbg(hsotg->dev, " max_packet_count=%d\n", 1619 hw->max_packet_count); 1620 dev_dbg(hsotg->dev, " nperio_tx_q_depth=0x%0x\n", 1621 hw->nperio_tx_q_depth); 1622 dev_dbg(hsotg->dev, " host_perio_tx_q_depth=0x%0x\n", 1623 hw->host_perio_tx_q_depth); 1624 dev_dbg(hsotg->dev, " dev_token_q_depth=0x%0x\n", 1625 hw->dev_token_q_depth); 1626 dev_dbg(hsotg->dev, " enable_dynamic_fifo=%d\n", 1627 hw->enable_dynamic_fifo); 1628 dev_dbg(hsotg->dev, " en_multiple_tx_fifo=%d\n", 1629 hw->en_multiple_tx_fifo); 1630 dev_dbg(hsotg->dev, " total_fifo_size=%d\n", 1631 hw->total_fifo_size); 1632 dev_dbg(hsotg->dev, " host_rx_fifo_size=%d\n", 1633 hw->host_rx_fifo_size); 1634 dev_dbg(hsotg->dev, " host_nperio_tx_fifo_size=%d\n", 1635 hw->host_nperio_tx_fifo_size); 1636 dev_dbg(hsotg->dev, " host_perio_tx_fifo_size=%d\n", 1637 hw->host_perio_tx_fifo_size); 1638 dev_dbg(hsotg->dev, "\n"); 1639 1640 return 0; 1641 } 1642 1643 /* 1644 * Sets all parameters to the given value. 1645 * 1646 * Assumes that the dwc2_core_params struct contains only integers. 1647 */ 1648 void dwc2_set_all_params(struct dwc2_core_params *params, int value) 1649 { 1650 int *p = (int *)params; 1651 size_t size = sizeof(*params) / sizeof(*p); 1652 int i; 1653 1654 for (i = 0; i < size; i++) 1655 p[i] = value; 1656 } 1657 1658 1659 u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg) 1660 { 1661 return hsotg->core_params->otg_ver == 1 ? 0x0200 : 0x0103; 1662 } 1663 1664 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg) 1665 { 1666 if (dwc2_readl(hsotg->regs + GSNPSID) == 0xffffffff) 1667 return false; 1668 else 1669 return true; 1670 } 1671 1672 /** 1673 * dwc2_enable_global_interrupts() - Enables the controller's Global 1674 * Interrupt in the AHB Config register 1675 * 1676 * @hsotg: Programming view of DWC_otg controller 1677 */ 1678 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg) 1679 { 1680 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 1681 1682 ahbcfg |= GAHBCFG_GLBL_INTR_EN; 1683 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 1684 } 1685 1686 /** 1687 * dwc2_disable_global_interrupts() - Disables the controller's Global 1688 * Interrupt in the AHB Config register 1689 * 1690 * @hsotg: Programming view of DWC_otg controller 1691 */ 1692 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg) 1693 { 1694 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 1695 1696 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 1697 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 1698 } 1699 1700 /* Returns the controller's GHWCFG2.OTG_MODE. */ 1701 unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg) 1702 { 1703 u32 ghwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2); 1704 1705 return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >> 1706 GHWCFG2_OP_MODE_SHIFT; 1707 } 1708 1709 /* Returns true if the controller is capable of DRD. */ 1710 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg) 1711 { 1712 unsigned op_mode = dwc2_op_mode(hsotg); 1713 1714 return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) || 1715 (op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) || 1716 (op_mode == GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE); 1717 } 1718 1719 /* Returns true if the controller is host-only. */ 1720 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg) 1721 { 1722 unsigned op_mode = dwc2_op_mode(hsotg); 1723 1724 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) || 1725 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST); 1726 } 1727 1728 /* Returns true if the controller is device-only. */ 1729 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg) 1730 { 1731 unsigned op_mode = dwc2_op_mode(hsotg); 1732 1733 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) || 1734 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE); 1735 } 1736 1737 MODULE_DESCRIPTION("DESIGNWARE HS OTG Core"); 1738 MODULE_AUTHOR("Synopsys, Inc."); 1739 MODULE_LICENSE("Dual BSD/GPL"); 1740