1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* 3 * core.c - DesignWare HS OTG Controller common routines 4 * 5 * Copyright (C) 2004-2013 Synopsys, Inc. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The names of the above-listed copyright holders may not be used 17 * to endorse or promote products derived from this software without 18 * specific prior written permission. 19 * 20 * ALTERNATIVELY, this software may be distributed under the terms of the 21 * GNU General Public License ("GPL") as published by the Free Software 22 * Foundation; either version 2 of the License, or (at your option) any 23 * later version. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * The Core code provides basic services for accessing and managing the 40 * DWC_otg hardware. These services are used by both the Host Controller 41 * Driver and the Peripheral Controller Driver. 42 */ 43 #include <linux/kernel.h> 44 #include <linux/module.h> 45 #include <linux/moduleparam.h> 46 #include <linux/spinlock.h> 47 #include <linux/interrupt.h> 48 #include <linux/dma-mapping.h> 49 #include <linux/delay.h> 50 #include <linux/io.h> 51 #include <linux/slab.h> 52 #include <linux/usb.h> 53 54 #include <linux/usb/hcd.h> 55 #include <linux/usb/ch11.h> 56 57 #include "core.h" 58 #include "hcd.h" 59 60 /** 61 * dwc2_backup_global_registers() - Backup global controller registers. 62 * When suspending usb bus, registers needs to be backuped 63 * if controller power is disabled once suspended. 64 * 65 * @hsotg: Programming view of the DWC_otg controller 66 */ 67 int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg) 68 { 69 struct dwc2_gregs_backup *gr; 70 71 dev_dbg(hsotg->dev, "%s\n", __func__); 72 73 /* Backup global regs */ 74 gr = &hsotg->gr_backup; 75 76 gr->gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 77 gr->gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 78 gr->gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 79 gr->gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 80 gr->grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); 81 gr->gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); 82 gr->gdfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG); 83 gr->pcgcctl1 = dwc2_readl(hsotg->regs + PCGCCTL1); 84 gr->glpmcfg = dwc2_readl(hsotg->regs + GLPMCFG); 85 gr->gi2cctl = dwc2_readl(hsotg->regs + GI2CCTL); 86 gr->pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 87 88 gr->valid = true; 89 return 0; 90 } 91 92 /** 93 * dwc2_restore_global_registers() - Restore controller global registers. 94 * When resuming usb bus, device registers needs to be restored 95 * if controller power were disabled. 96 * 97 * @hsotg: Programming view of the DWC_otg controller 98 */ 99 int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg) 100 { 101 struct dwc2_gregs_backup *gr; 102 103 dev_dbg(hsotg->dev, "%s\n", __func__); 104 105 /* Restore global regs */ 106 gr = &hsotg->gr_backup; 107 if (!gr->valid) { 108 dev_err(hsotg->dev, "%s: no global registers to restore\n", 109 __func__); 110 return -EINVAL; 111 } 112 gr->valid = false; 113 114 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 115 dwc2_writel(gr->gotgctl, hsotg->regs + GOTGCTL); 116 dwc2_writel(gr->gintmsk, hsotg->regs + GINTMSK); 117 dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG); 118 dwc2_writel(gr->gahbcfg, hsotg->regs + GAHBCFG); 119 dwc2_writel(gr->grxfsiz, hsotg->regs + GRXFSIZ); 120 dwc2_writel(gr->gnptxfsiz, hsotg->regs + GNPTXFSIZ); 121 dwc2_writel(gr->gdfifocfg, hsotg->regs + GDFIFOCFG); 122 dwc2_writel(gr->pcgcctl1, hsotg->regs + PCGCCTL1); 123 dwc2_writel(gr->glpmcfg, hsotg->regs + GLPMCFG); 124 dwc2_writel(gr->pcgcctl, hsotg->regs + PCGCTL); 125 dwc2_writel(gr->gi2cctl, hsotg->regs + GI2CCTL); 126 127 return 0; 128 } 129 130 /** 131 * dwc2_exit_partial_power_down() - Exit controller from Partial Power Down. 132 * 133 * @hsotg: Programming view of the DWC_otg controller 134 * @restore: Controller registers need to be restored 135 */ 136 int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, bool restore) 137 { 138 u32 pcgcctl; 139 int ret = 0; 140 141 if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL) 142 return -ENOTSUPP; 143 144 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 145 pcgcctl &= ~PCGCTL_STOPPCLK; 146 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 147 148 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 149 pcgcctl &= ~PCGCTL_PWRCLMP; 150 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 151 152 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 153 pcgcctl &= ~PCGCTL_RSTPDWNMODULE; 154 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 155 156 udelay(100); 157 if (restore) { 158 ret = dwc2_restore_global_registers(hsotg); 159 if (ret) { 160 dev_err(hsotg->dev, "%s: failed to restore registers\n", 161 __func__); 162 return ret; 163 } 164 if (dwc2_is_host_mode(hsotg)) { 165 ret = dwc2_restore_host_registers(hsotg); 166 if (ret) { 167 dev_err(hsotg->dev, "%s: failed to restore host registers\n", 168 __func__); 169 return ret; 170 } 171 } else { 172 ret = dwc2_restore_device_registers(hsotg, 0); 173 if (ret) { 174 dev_err(hsotg->dev, "%s: failed to restore device registers\n", 175 __func__); 176 return ret; 177 } 178 } 179 } 180 181 return ret; 182 } 183 184 /** 185 * dwc2_enter_partial_power_down() - Put controller in Partial Power Down. 186 * 187 * @hsotg: Programming view of the DWC_otg controller 188 */ 189 int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg) 190 { 191 u32 pcgcctl; 192 int ret = 0; 193 194 if (!hsotg->params.power_down) 195 return -ENOTSUPP; 196 197 /* Backup all registers */ 198 ret = dwc2_backup_global_registers(hsotg); 199 if (ret) { 200 dev_err(hsotg->dev, "%s: failed to backup global registers\n", 201 __func__); 202 return ret; 203 } 204 205 if (dwc2_is_host_mode(hsotg)) { 206 ret = dwc2_backup_host_registers(hsotg); 207 if (ret) { 208 dev_err(hsotg->dev, "%s: failed to backup host registers\n", 209 __func__); 210 return ret; 211 } 212 } else { 213 ret = dwc2_backup_device_registers(hsotg); 214 if (ret) { 215 dev_err(hsotg->dev, "%s: failed to backup device registers\n", 216 __func__); 217 return ret; 218 } 219 } 220 221 /* 222 * Clear any pending interrupts since dwc2 will not be able to 223 * clear them after entering partial_power_down. 224 */ 225 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 226 227 /* Put the controller in low power state */ 228 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); 229 230 pcgcctl |= PCGCTL_PWRCLMP; 231 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 232 ndelay(20); 233 234 pcgcctl |= PCGCTL_RSTPDWNMODULE; 235 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 236 ndelay(20); 237 238 pcgcctl |= PCGCTL_STOPPCLK; 239 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 240 241 return ret; 242 } 243 244 /** 245 * dwc2_restore_essential_regs() - Restore essiential regs of core. 246 * 247 * @hsotg: Programming view of the DWC_otg controller 248 * @rmode: Restore mode, enabled in case of remote-wakeup. 249 * @is_host: Host or device mode. 250 */ 251 static void dwc2_restore_essential_regs(struct dwc2_hsotg *hsotg, int rmode, 252 int is_host) 253 { 254 u32 pcgcctl; 255 struct dwc2_gregs_backup *gr; 256 struct dwc2_dregs_backup *dr; 257 struct dwc2_hregs_backup *hr; 258 259 gr = &hsotg->gr_backup; 260 dr = &hsotg->dr_backup; 261 hr = &hsotg->hr_backup; 262 263 dev_dbg(hsotg->dev, "%s: restoring essential regs\n", __func__); 264 265 /* Load restore values for [31:14] bits */ 266 pcgcctl = (gr->pcgcctl & 0xffffc000); 267 /* If High Speed */ 268 if (is_host) { 269 if (!(pcgcctl & PCGCTL_P2HD_PRT_SPD_MASK)) 270 pcgcctl |= BIT(17); 271 } else { 272 if (!(pcgcctl & PCGCTL_P2HD_DEV_ENUM_SPD_MASK)) 273 pcgcctl |= BIT(17); 274 } 275 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 276 277 /* Umnask global Interrupt in GAHBCFG and restore it */ 278 dwc2_writel(gr->gahbcfg | GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG); 279 280 /* Clear all pending interupts */ 281 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 282 283 /* Unmask restore done interrupt */ 284 dwc2_writel(GINTSTS_RESTOREDONE, hsotg->regs + GINTMSK); 285 286 /* Restore GUSBCFG and HCFG/DCFG */ 287 dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG); 288 289 if (is_host) { 290 dwc2_writel(hr->hcfg, hsotg->regs + HCFG); 291 if (rmode) 292 pcgcctl |= PCGCTL_RESTOREMODE; 293 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 294 udelay(10); 295 296 pcgcctl |= PCGCTL_ESS_REG_RESTORED; 297 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 298 udelay(10); 299 } else { 300 dwc2_writel(dr->dcfg, hsotg->regs + DCFG); 301 if (!rmode) 302 pcgcctl |= PCGCTL_RESTOREMODE | PCGCTL_RSTPDWNMODULE; 303 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 304 udelay(10); 305 306 pcgcctl |= PCGCTL_ESS_REG_RESTORED; 307 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); 308 udelay(10); 309 } 310 } 311 312 /** 313 * dwc2_hib_restore_common() - Common part of restore routine. 314 * 315 * @hsotg: Programming view of the DWC_otg controller 316 * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup. 317 * @is_host: Host or device mode. 318 */ 319 void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup, 320 int is_host) 321 { 322 u32 gpwrdn; 323 324 /* Switch-on voltage to the core */ 325 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 326 gpwrdn &= ~GPWRDN_PWRDNSWTCH; 327 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 328 udelay(10); 329 330 /* Reset core */ 331 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 332 gpwrdn &= ~GPWRDN_PWRDNRSTN; 333 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 334 udelay(10); 335 336 /* Enable restore from PMU */ 337 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 338 gpwrdn |= GPWRDN_RESTORE; 339 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 340 udelay(10); 341 342 /* Disable Power Down Clamp */ 343 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 344 gpwrdn &= ~GPWRDN_PWRDNCLMP; 345 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 346 udelay(50); 347 348 if (!is_host && rem_wakeup) 349 udelay(70); 350 351 /* Deassert reset core */ 352 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 353 gpwrdn |= GPWRDN_PWRDNRSTN; 354 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 355 udelay(10); 356 357 /* Disable PMU interrupt */ 358 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); 359 gpwrdn &= ~GPWRDN_PMUINTSEL; 360 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); 361 udelay(10); 362 363 /* Set Restore Essential Regs bit in PCGCCTL register */ 364 dwc2_restore_essential_regs(hsotg, rem_wakeup, is_host); 365 366 /* 367 * Wait For Restore_done Interrupt. This mechanism of polling the 368 * interrupt is introduced to avoid any possible race conditions 369 */ 370 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, GINTSTS_RESTOREDONE, 371 20000)) { 372 dev_dbg(hsotg->dev, 373 "%s: Restore Done wan't generated here\n", 374 __func__); 375 } else { 376 dev_dbg(hsotg->dev, "restore done generated here\n"); 377 } 378 } 379 380 /** 381 * dwc2_wait_for_mode() - Waits for the controller mode. 382 * @hsotg: Programming view of the DWC_otg controller. 383 * @host_mode: If true, waits for host mode, otherwise device mode. 384 */ 385 static void dwc2_wait_for_mode(struct dwc2_hsotg *hsotg, 386 bool host_mode) 387 { 388 ktime_t start; 389 ktime_t end; 390 unsigned int timeout = 110; 391 392 dev_vdbg(hsotg->dev, "Waiting for %s mode\n", 393 host_mode ? "host" : "device"); 394 395 start = ktime_get(); 396 397 while (1) { 398 s64 ms; 399 400 if (dwc2_is_host_mode(hsotg) == host_mode) { 401 dev_vdbg(hsotg->dev, "%s mode set\n", 402 host_mode ? "Host" : "Device"); 403 break; 404 } 405 406 end = ktime_get(); 407 ms = ktime_to_ms(ktime_sub(end, start)); 408 409 if (ms >= (s64)timeout) { 410 dev_warn(hsotg->dev, "%s: Couldn't set %s mode\n", 411 __func__, host_mode ? "host" : "device"); 412 break; 413 } 414 415 usleep_range(1000, 2000); 416 } 417 } 418 419 /** 420 * dwc2_iddig_filter_enabled() - Returns true if the IDDIG debounce 421 * filter is enabled. 422 */ 423 static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg) 424 { 425 u32 gsnpsid; 426 u32 ghwcfg4; 427 428 if (!dwc2_hw_is_otg(hsotg)) 429 return false; 430 431 /* Check if core configuration includes the IDDIG filter. */ 432 ghwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4); 433 if (!(ghwcfg4 & GHWCFG4_IDDIG_FILT_EN)) 434 return false; 435 436 /* 437 * Check if the IDDIG debounce filter is bypassed. Available 438 * in core version >= 3.10a. 439 */ 440 gsnpsid = dwc2_readl(hsotg->regs + GSNPSID); 441 if (gsnpsid >= DWC2_CORE_REV_3_10a) { 442 u32 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 443 444 if (gotgctl & GOTGCTL_DBNCE_FLTR_BYPASS) 445 return false; 446 } 447 448 return true; 449 } 450 451 /* 452 * dwc2_enter_hibernation() - Common function to enter hibernation. 453 * 454 * @hsotg: Programming view of the DWC_otg controller 455 * @is_host: True if core is in host mode. 456 * 457 * Return: 0 if successful, negative error code otherwise 458 */ 459 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host) 460 { 461 if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_HIBERNATION) 462 return -ENOTSUPP; 463 464 if (is_host) 465 return dwc2_host_enter_hibernation(hsotg); 466 else 467 return dwc2_gadget_enter_hibernation(hsotg); 468 } 469 470 /* 471 * dwc2_exit_hibernation() - Common function to exit from hibernation. 472 * 473 * @hsotg: Programming view of the DWC_otg controller 474 * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup. 475 * @reset: Enabled in case of restore with reset. 476 * @is_host: True if core is in host mode. 477 * 478 * Return: 0 if successful, negative error code otherwise 479 */ 480 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup, 481 int reset, int is_host) 482 { 483 if (is_host) 484 return dwc2_host_exit_hibernation(hsotg, rem_wakeup, reset); 485 else 486 return dwc2_gadget_exit_hibernation(hsotg, rem_wakeup, reset); 487 } 488 489 /* 490 * Do core a soft reset of the core. Be careful with this because it 491 * resets all the internal state machines of the core. 492 */ 493 int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait) 494 { 495 u32 greset; 496 bool wait_for_host_mode = false; 497 498 dev_vdbg(hsotg->dev, "%s()\n", __func__); 499 500 /* 501 * If the current mode is host, either due to the force mode 502 * bit being set (which persists after core reset) or the 503 * connector id pin, a core soft reset will temporarily reset 504 * the mode to device. A delay from the IDDIG debounce filter 505 * will occur before going back to host mode. 506 * 507 * Determine whether we will go back into host mode after a 508 * reset and account for this delay after the reset. 509 */ 510 if (dwc2_iddig_filter_enabled(hsotg)) { 511 u32 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 512 u32 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 513 514 if (!(gotgctl & GOTGCTL_CONID_B) || 515 (gusbcfg & GUSBCFG_FORCEHOSTMODE)) { 516 wait_for_host_mode = true; 517 } 518 } 519 520 /* Core Soft Reset */ 521 greset = dwc2_readl(hsotg->regs + GRSTCTL); 522 greset |= GRSTCTL_CSFTRST; 523 dwc2_writel(greset, hsotg->regs + GRSTCTL); 524 525 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_CSFTRST, 50)) { 526 dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL GRSTCTL_CSFTRST\n", 527 __func__); 528 return -EBUSY; 529 } 530 531 /* Wait for AHB master IDLE state */ 532 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 50)) { 533 dev_warn(hsotg->dev, "%s: HANG! AHB Idle timeout GRSTCTL GRSTCTL_AHBIDLE\n", 534 __func__); 535 return -EBUSY; 536 } 537 538 if (wait_for_host_mode && !skip_wait) 539 dwc2_wait_for_mode(hsotg, true); 540 541 return 0; 542 } 543 544 /** 545 * dwc2_force_mode() - Force the mode of the controller. 546 * 547 * Forcing the mode is needed for two cases: 548 * 549 * 1) If the dr_mode is set to either HOST or PERIPHERAL we force the 550 * controller to stay in a particular mode regardless of ID pin 551 * changes. We do this once during probe. 552 * 553 * 2) During probe we want to read reset values of the hw 554 * configuration registers that are only available in either host or 555 * device mode. We may need to force the mode if the current mode does 556 * not allow us to access the register in the mode that we want. 557 * 558 * In either case it only makes sense to force the mode if the 559 * controller hardware is OTG capable. 560 * 561 * Checks are done in this function to determine whether doing a force 562 * would be valid or not. 563 * 564 * If a force is done, it requires a IDDIG debounce filter delay if 565 * the filter is configured and enabled. We poll the current mode of 566 * the controller to account for this delay. 567 */ 568 void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host) 569 { 570 u32 gusbcfg; 571 u32 set; 572 u32 clear; 573 574 dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device"); 575 576 /* 577 * Force mode has no effect if the hardware is not OTG. 578 */ 579 if (!dwc2_hw_is_otg(hsotg)) 580 return; 581 582 /* 583 * If dr_mode is either peripheral or host only, there is no 584 * need to ever force the mode to the opposite mode. 585 */ 586 if (WARN_ON(host && hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)) 587 return; 588 589 if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST)) 590 return; 591 592 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 593 594 set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE; 595 clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE; 596 597 gusbcfg &= ~clear; 598 gusbcfg |= set; 599 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); 600 601 dwc2_wait_for_mode(hsotg, host); 602 return; 603 } 604 605 /** 606 * dwc2_clear_force_mode() - Clears the force mode bits. 607 * 608 * After clearing the bits, wait up to 100 ms to account for any 609 * potential IDDIG filter delay. We can't know if we expect this delay 610 * or not because the value of the connector ID status is affected by 611 * the force mode. We only need to call this once during probe if 612 * dr_mode == OTG. 613 */ 614 static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg) 615 { 616 u32 gusbcfg; 617 618 if (!dwc2_hw_is_otg(hsotg)) 619 return; 620 621 dev_dbg(hsotg->dev, "Clearing force mode bits\n"); 622 623 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 624 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE; 625 gusbcfg &= ~GUSBCFG_FORCEDEVMODE; 626 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); 627 628 if (dwc2_iddig_filter_enabled(hsotg)) 629 msleep(100); 630 } 631 632 /* 633 * Sets or clears force mode based on the dr_mode parameter. 634 */ 635 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg) 636 { 637 switch (hsotg->dr_mode) { 638 case USB_DR_MODE_HOST: 639 /* 640 * NOTE: This is required for some rockchip soc based 641 * platforms on their host-only dwc2. 642 */ 643 if (!dwc2_hw_is_otg(hsotg)) 644 msleep(50); 645 646 break; 647 case USB_DR_MODE_PERIPHERAL: 648 dwc2_force_mode(hsotg, false); 649 break; 650 case USB_DR_MODE_OTG: 651 dwc2_clear_force_mode(hsotg); 652 break; 653 default: 654 dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n", 655 __func__, hsotg->dr_mode); 656 break; 657 } 658 } 659 660 /* 661 * dwc2_enable_acg - enable active clock gating feature 662 */ 663 void dwc2_enable_acg(struct dwc2_hsotg *hsotg) 664 { 665 if (hsotg->params.acg_enable) { 666 u32 pcgcctl1 = dwc2_readl(hsotg->regs + PCGCCTL1); 667 668 dev_dbg(hsotg->dev, "Enabling Active Clock Gating\n"); 669 pcgcctl1 |= PCGCCTL1_GATEEN; 670 dwc2_writel(pcgcctl1, hsotg->regs + PCGCCTL1); 671 } 672 } 673 674 /** 675 * dwc2_dump_host_registers() - Prints the host registers 676 * 677 * @hsotg: Programming view of DWC_otg controller 678 * 679 * NOTE: This function will be removed once the peripheral controller code 680 * is integrated and the driver is stable 681 */ 682 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg) 683 { 684 #ifdef DEBUG 685 u32 __iomem *addr; 686 int i; 687 688 dev_dbg(hsotg->dev, "Host Global Registers\n"); 689 addr = hsotg->regs + HCFG; 690 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n", 691 (unsigned long)addr, dwc2_readl(addr)); 692 addr = hsotg->regs + HFIR; 693 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n", 694 (unsigned long)addr, dwc2_readl(addr)); 695 addr = hsotg->regs + HFNUM; 696 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n", 697 (unsigned long)addr, dwc2_readl(addr)); 698 addr = hsotg->regs + HPTXSTS; 699 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n", 700 (unsigned long)addr, dwc2_readl(addr)); 701 addr = hsotg->regs + HAINT; 702 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n", 703 (unsigned long)addr, dwc2_readl(addr)); 704 addr = hsotg->regs + HAINTMSK; 705 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n", 706 (unsigned long)addr, dwc2_readl(addr)); 707 if (hsotg->params.dma_desc_enable) { 708 addr = hsotg->regs + HFLBADDR; 709 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n", 710 (unsigned long)addr, dwc2_readl(addr)); 711 } 712 713 addr = hsotg->regs + HPRT0; 714 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n", 715 (unsigned long)addr, dwc2_readl(addr)); 716 717 for (i = 0; i < hsotg->params.host_channels; i++) { 718 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i); 719 addr = hsotg->regs + HCCHAR(i); 720 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n", 721 (unsigned long)addr, dwc2_readl(addr)); 722 addr = hsotg->regs + HCSPLT(i); 723 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n", 724 (unsigned long)addr, dwc2_readl(addr)); 725 addr = hsotg->regs + HCINT(i); 726 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n", 727 (unsigned long)addr, dwc2_readl(addr)); 728 addr = hsotg->regs + HCINTMSK(i); 729 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n", 730 (unsigned long)addr, dwc2_readl(addr)); 731 addr = hsotg->regs + HCTSIZ(i); 732 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n", 733 (unsigned long)addr, dwc2_readl(addr)); 734 addr = hsotg->regs + HCDMA(i); 735 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n", 736 (unsigned long)addr, dwc2_readl(addr)); 737 if (hsotg->params.dma_desc_enable) { 738 addr = hsotg->regs + HCDMAB(i); 739 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n", 740 (unsigned long)addr, dwc2_readl(addr)); 741 } 742 } 743 #endif 744 } 745 746 /** 747 * dwc2_dump_global_registers() - Prints the core global registers 748 * 749 * @hsotg: Programming view of DWC_otg controller 750 * 751 * NOTE: This function will be removed once the peripheral controller code 752 * is integrated and the driver is stable 753 */ 754 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg) 755 { 756 #ifdef DEBUG 757 u32 __iomem *addr; 758 759 dev_dbg(hsotg->dev, "Core Global Registers\n"); 760 addr = hsotg->regs + GOTGCTL; 761 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n", 762 (unsigned long)addr, dwc2_readl(addr)); 763 addr = hsotg->regs + GOTGINT; 764 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n", 765 (unsigned long)addr, dwc2_readl(addr)); 766 addr = hsotg->regs + GAHBCFG; 767 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n", 768 (unsigned long)addr, dwc2_readl(addr)); 769 addr = hsotg->regs + GUSBCFG; 770 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n", 771 (unsigned long)addr, dwc2_readl(addr)); 772 addr = hsotg->regs + GRSTCTL; 773 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n", 774 (unsigned long)addr, dwc2_readl(addr)); 775 addr = hsotg->regs + GINTSTS; 776 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n", 777 (unsigned long)addr, dwc2_readl(addr)); 778 addr = hsotg->regs + GINTMSK; 779 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n", 780 (unsigned long)addr, dwc2_readl(addr)); 781 addr = hsotg->regs + GRXSTSR; 782 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n", 783 (unsigned long)addr, dwc2_readl(addr)); 784 addr = hsotg->regs + GRXFSIZ; 785 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n", 786 (unsigned long)addr, dwc2_readl(addr)); 787 addr = hsotg->regs + GNPTXFSIZ; 788 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n", 789 (unsigned long)addr, dwc2_readl(addr)); 790 addr = hsotg->regs + GNPTXSTS; 791 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n", 792 (unsigned long)addr, dwc2_readl(addr)); 793 addr = hsotg->regs + GI2CCTL; 794 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n", 795 (unsigned long)addr, dwc2_readl(addr)); 796 addr = hsotg->regs + GPVNDCTL; 797 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n", 798 (unsigned long)addr, dwc2_readl(addr)); 799 addr = hsotg->regs + GGPIO; 800 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n", 801 (unsigned long)addr, dwc2_readl(addr)); 802 addr = hsotg->regs + GUID; 803 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n", 804 (unsigned long)addr, dwc2_readl(addr)); 805 addr = hsotg->regs + GSNPSID; 806 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n", 807 (unsigned long)addr, dwc2_readl(addr)); 808 addr = hsotg->regs + GHWCFG1; 809 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n", 810 (unsigned long)addr, dwc2_readl(addr)); 811 addr = hsotg->regs + GHWCFG2; 812 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n", 813 (unsigned long)addr, dwc2_readl(addr)); 814 addr = hsotg->regs + GHWCFG3; 815 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n", 816 (unsigned long)addr, dwc2_readl(addr)); 817 addr = hsotg->regs + GHWCFG4; 818 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n", 819 (unsigned long)addr, dwc2_readl(addr)); 820 addr = hsotg->regs + GLPMCFG; 821 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n", 822 (unsigned long)addr, dwc2_readl(addr)); 823 addr = hsotg->regs + GPWRDN; 824 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n", 825 (unsigned long)addr, dwc2_readl(addr)); 826 addr = hsotg->regs + GDFIFOCFG; 827 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n", 828 (unsigned long)addr, dwc2_readl(addr)); 829 addr = hsotg->regs + HPTXFSIZ; 830 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n", 831 (unsigned long)addr, dwc2_readl(addr)); 832 833 addr = hsotg->regs + PCGCTL; 834 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n", 835 (unsigned long)addr, dwc2_readl(addr)); 836 #endif 837 } 838 839 /** 840 * dwc2_flush_tx_fifo() - Flushes a Tx FIFO 841 * 842 * @hsotg: Programming view of DWC_otg controller 843 * @num: Tx FIFO to flush 844 */ 845 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num) 846 { 847 u32 greset; 848 849 dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num); 850 851 /* Wait for AHB master IDLE state */ 852 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000)) 853 dev_warn(hsotg->dev, "%s: HANG! AHB Idle GRSCTL\n", 854 __func__); 855 856 greset = GRSTCTL_TXFFLSH; 857 greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK; 858 dwc2_writel(greset, hsotg->regs + GRSTCTL); 859 860 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 10000)) 861 dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_TXFFLSH\n", 862 __func__); 863 864 /* Wait for at least 3 PHY Clocks */ 865 udelay(1); 866 } 867 868 /** 869 * dwc2_flush_rx_fifo() - Flushes the Rx FIFO 870 * 871 * @hsotg: Programming view of DWC_otg controller 872 */ 873 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg) 874 { 875 u32 greset; 876 877 dev_vdbg(hsotg->dev, "%s()\n", __func__); 878 879 /* Wait for AHB master IDLE state */ 880 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000)) 881 dev_warn(hsotg->dev, "%s: HANG! AHB Idle GRSCTL\n", 882 __func__); 883 884 greset = GRSTCTL_RXFFLSH; 885 dwc2_writel(greset, hsotg->regs + GRSTCTL); 886 887 /* Wait for RxFIFO flush done */ 888 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_RXFFLSH, 10000)) 889 dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_RXFFLSH\n", 890 __func__); 891 892 /* Wait for at least 3 PHY Clocks */ 893 udelay(1); 894 } 895 896 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg) 897 { 898 if (dwc2_readl(hsotg->regs + GSNPSID) == 0xffffffff) 899 return false; 900 else 901 return true; 902 } 903 904 /** 905 * dwc2_enable_global_interrupts() - Enables the controller's Global 906 * Interrupt in the AHB Config register 907 * 908 * @hsotg: Programming view of DWC_otg controller 909 */ 910 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg) 911 { 912 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 913 914 ahbcfg |= GAHBCFG_GLBL_INTR_EN; 915 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 916 } 917 918 /** 919 * dwc2_disable_global_interrupts() - Disables the controller's Global 920 * Interrupt in the AHB Config register 921 * 922 * @hsotg: Programming view of DWC_otg controller 923 */ 924 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg) 925 { 926 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 927 928 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 929 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 930 } 931 932 /* Returns the controller's GHWCFG2.OTG_MODE. */ 933 unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg) 934 { 935 u32 ghwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2); 936 937 return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >> 938 GHWCFG2_OP_MODE_SHIFT; 939 } 940 941 /* Returns true if the controller is capable of DRD. */ 942 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg) 943 { 944 unsigned int op_mode = dwc2_op_mode(hsotg); 945 946 return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) || 947 (op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) || 948 (op_mode == GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE); 949 } 950 951 /* Returns true if the controller is host-only. */ 952 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg) 953 { 954 unsigned int op_mode = dwc2_op_mode(hsotg); 955 956 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) || 957 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST); 958 } 959 960 /* Returns true if the controller is device-only. */ 961 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg) 962 { 963 unsigned int op_mode = dwc2_op_mode(hsotg); 964 965 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) || 966 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE); 967 } 968 969 /** 970 * dwc2_hsotg_wait_bit_set - Waits for bit to be set. 971 * @hsotg: Programming view of DWC_otg controller. 972 * @offset: Register's offset where bit/bits must be set. 973 * @mask: Mask of the bit/bits which must be set. 974 * @timeout: Timeout to wait. 975 * 976 * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout. 977 */ 978 int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hsotg, u32 offset, u32 mask, 979 u32 timeout) 980 { 981 u32 i; 982 983 for (i = 0; i < timeout; i++) { 984 if (dwc2_readl(hsotg->regs + offset) & mask) 985 return 0; 986 udelay(1); 987 } 988 989 return -ETIMEDOUT; 990 } 991 992 /** 993 * dwc2_hsotg_wait_bit_clear - Waits for bit to be clear. 994 * @hsotg: Programming view of DWC_otg controller. 995 * @offset: Register's offset where bit/bits must be set. 996 * @mask: Mask of the bit/bits which must be set. 997 * @timeout: Timeout to wait. 998 * 999 * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout. 1000 */ 1001 int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hsotg, u32 offset, u32 mask, 1002 u32 timeout) 1003 { 1004 u32 i; 1005 1006 for (i = 0; i < timeout; i++) { 1007 if (!(dwc2_readl(hsotg->regs + offset) & mask)) 1008 return 0; 1009 udelay(1); 1010 } 1011 1012 return -ETIMEDOUT; 1013 } 1014 1015 MODULE_DESCRIPTION("DESIGNWARE HS OTG Core"); 1016 MODULE_AUTHOR("Synopsys, Inc."); 1017 MODULE_LICENSE("Dual BSD/GPL"); 1018