1config USB_DWC2 2 tristate "DesignWare USB2 DRD Core Support" 3 depends on USB 4 help 5 Say Y or M here if your system has a Dual Role HighSpeed 6 USB controller based on the DesignWare HSOTG IP Core. 7 8 If you choose to build this driver as dynamically linked 9 modules, the core module will be called dwc2.ko, the 10 PCI bus interface module (if you have a PCI bus system) 11 will be called dwc2_pci.ko and the platform interface module 12 (for controllers directly connected to the CPU) will be called 13 dwc2_platform.ko. 14 15 NOTE: This driver at present only implements the Host mode 16 of the controller. The existing s3c-hsotg driver supports 17 Peripheral mode, but only for the Samsung S3C platforms. 18 There are plans to merge the s3c-hsotg driver with this 19 driver in the near future to create a dual-role driver. 20 21if USB_DWC2 22 23config USB_DWC2_DEBUG 24 bool "Enable Debugging Messages" 25 help 26 Say Y here to enable debugging messages in the DWC2 Driver. 27 28config USB_DWC2_VERBOSE 29 bool "Enable Verbose Debugging Messages" 30 depends on USB_DWC2_DEBUG 31 help 32 Say Y here to enable verbose debugging messages in the DWC2 Driver. 33 WARNING: Enabling this will quickly fill your message log. 34 If in doubt, say N. 35 36config USB_DWC2_TRACK_MISSED_SOFS 37 bool "Enable Missed SOF Tracking" 38 help 39 Say Y here to enable logging of missed SOF events to the dmesg log. 40 WARNING: This feature is still experimental. 41 If in doubt, say N. 42 43config USB_DWC2_DEBUG_PERIODIC 44 bool "Enable Debugging Messages For Periodic Transfers" 45 depends on USB_DWC2_DEBUG || USB_DWC2_VERBOSE 46 default y 47 help 48 Say N here to disable (verbose) debugging messages to be 49 logged for periodic transfers. This allows better debugging of 50 non-periodic transfers, but of course the debug logs will be 51 incomplete. Note that this also disables some debug messages 52 for which the transfer type cannot be deduced. 53endif 54