1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * 4 * Includes for cdc-acm.c 5 * 6 * Mainly take from usbnet's cdc-ether part 7 * 8 */ 9 10 /* 11 * CMSPAR, some architectures can't have space and mark parity. 12 */ 13 14 #ifndef CMSPAR 15 #define CMSPAR 0 16 #endif 17 18 /* 19 * Major and minor numbers. 20 */ 21 22 #define ACM_TTY_MAJOR 166 23 #define ACM_TTY_MINORS 256 24 25 /* 26 * Requests. 27 */ 28 29 #define USB_RT_ACM (USB_TYPE_CLASS | USB_RECIP_INTERFACE) 30 31 /* 32 * Output control lines. 33 */ 34 35 #define ACM_CTRL_DTR 0x01 36 #define ACM_CTRL_RTS 0x02 37 38 /* 39 * Input control lines and line errors. 40 */ 41 42 #define ACM_CTRL_DCD 0x01 43 #define ACM_CTRL_DSR 0x02 44 #define ACM_CTRL_BRK 0x04 45 #define ACM_CTRL_RI 0x08 46 47 #define ACM_CTRL_FRAMING 0x10 48 #define ACM_CTRL_PARITY 0x20 49 #define ACM_CTRL_OVERRUN 0x40 50 51 /* 52 * Internal driver structures. 53 */ 54 55 /* 56 * The only reason to have several buffers is to accommodate assumptions 57 * in line disciplines. They ask for empty space amount, receive our URB size, 58 * and proceed to issue several 1-character writes, assuming they will fit. 59 * The very first write takes a complete URB. Fortunately, this only happens 60 * when processing onlcr, so we only need 2 buffers. These values must be 61 * powers of 2. 62 */ 63 #define ACM_NW 16 64 #define ACM_NR 16 65 66 struct acm_wb { 67 unsigned char *buf; 68 dma_addr_t dmah; 69 int len; 70 int use; 71 struct urb *urb; 72 struct acm *instance; 73 }; 74 75 struct acm_rb { 76 int size; 77 unsigned char *base; 78 dma_addr_t dma; 79 int index; 80 struct acm *instance; 81 }; 82 83 struct acm { 84 struct usb_device *dev; /* the corresponding usb device */ 85 struct usb_interface *control; /* control interface */ 86 struct usb_interface *data; /* data interface */ 87 unsigned in, out; /* i/o pipes */ 88 struct tty_port port; /* our tty port data */ 89 struct urb *ctrlurb; /* urbs */ 90 u8 *ctrl_buffer; /* buffers of urbs */ 91 dma_addr_t ctrl_dma; /* dma handles of buffers */ 92 u8 *country_codes; /* country codes from device */ 93 unsigned int country_code_size; /* size of this buffer */ 94 unsigned int country_rel_date; /* release date of version */ 95 struct acm_wb wb[ACM_NW]; 96 unsigned long read_urbs_free; 97 struct urb *read_urbs[ACM_NR]; 98 struct acm_rb read_buffers[ACM_NR]; 99 struct acm_wb *putbuffer; /* for acm_tty_put_char() */ 100 int rx_buflimit; 101 spinlock_t read_lock; 102 u8 *notification_buffer; /* to reassemble fragmented notifications */ 103 unsigned int nb_index; 104 unsigned int nb_size; 105 int transmitting; 106 spinlock_t write_lock; 107 struct mutex mutex; 108 bool disconnected; 109 unsigned long flags; 110 # define EVENT_TTY_WAKEUP 0 111 # define EVENT_RX_STALL 1 112 struct usb_cdc_line_coding line; /* bits, stop, parity */ 113 struct work_struct work; /* work queue entry for line discipline waking up */ 114 unsigned int ctrlin; /* input control lines (DCD, DSR, RI, break, overruns) */ 115 unsigned int ctrlout; /* output control lines (DTR, RTS) */ 116 struct async_icount iocount; /* counters for control line changes */ 117 struct async_icount oldcount; /* for comparison of counter */ 118 wait_queue_head_t wioctl; /* for ioctl */ 119 unsigned int writesize; /* max packet size for the output bulk endpoint */ 120 unsigned int readsize,ctrlsize; /* buffer sizes for freeing */ 121 unsigned int minor; /* acm minor number */ 122 unsigned char clocal; /* termios CLOCAL */ 123 unsigned int ctrl_caps; /* control capabilities from the class specific header */ 124 unsigned int susp_count; /* number of suspended interfaces */ 125 unsigned int combined_interfaces:1; /* control and data collapsed */ 126 unsigned int throttled:1; /* actually throttled */ 127 unsigned int throttle_req:1; /* throttle requested */ 128 u8 bInterval; 129 struct usb_anchor delayed; /* writes queued for a device about to be woken */ 130 unsigned long quirks; 131 }; 132 133 #define CDC_DATA_INTERFACE_TYPE 0x0a 134 135 /* constants describing various quirks and errors */ 136 #define NO_UNION_NORMAL BIT(0) 137 #define SINGLE_RX_URB BIT(1) 138 #define NO_CAP_LINE BIT(2) 139 #define NO_DATA_INTERFACE BIT(4) 140 #define IGNORE_DEVICE BIT(5) 141 #define QUIRK_CONTROL_LINE_STATE BIT(6) 142 #define CLEAR_HALT_CONDITIONS BIT(7) 143 #define SEND_ZERO_PACKET BIT(8) 144