1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * 4 * Includes for cdc-acm.c 5 * 6 * Mainly take from usbnet's cdc-ether part 7 * 8 */ 9 10 /* 11 * CMSPAR, some architectures can't have space and mark parity. 12 */ 13 14 #ifndef CMSPAR 15 #define CMSPAR 0 16 #endif 17 18 /* 19 * Major and minor numbers. 20 */ 21 22 #define ACM_TTY_MAJOR 166 23 #define ACM_TTY_MINORS 256 24 25 #define ACM_MINOR_INVALID ACM_TTY_MINORS 26 27 /* 28 * Requests. 29 */ 30 31 #define USB_RT_ACM (USB_TYPE_CLASS | USB_RECIP_INTERFACE) 32 33 /* 34 * Output control lines. 35 */ 36 37 #define ACM_CTRL_DTR 0x01 38 #define ACM_CTRL_RTS 0x02 39 40 /* 41 * Input control lines and line errors. 42 */ 43 44 #define ACM_CTRL_DCD 0x01 45 #define ACM_CTRL_DSR 0x02 46 #define ACM_CTRL_BRK 0x04 47 #define ACM_CTRL_RI 0x08 48 49 #define ACM_CTRL_FRAMING 0x10 50 #define ACM_CTRL_PARITY 0x20 51 #define ACM_CTRL_OVERRUN 0x40 52 53 /* 54 * Internal driver structures. 55 */ 56 57 /* 58 * The only reason to have several buffers is to accommodate assumptions 59 * in line disciplines. They ask for empty space amount, receive our URB size, 60 * and proceed to issue several 1-character writes, assuming they will fit. 61 * The very first write takes a complete URB. Fortunately, this only happens 62 * when processing onlcr, so we only need 2 buffers. These values must be 63 * powers of 2. 64 */ 65 #define ACM_NW 16 66 #define ACM_NR 16 67 68 struct acm_wb { 69 u8 *buf; 70 dma_addr_t dmah; 71 unsigned int len; 72 struct urb *urb; 73 struct acm *instance; 74 bool use; 75 }; 76 77 struct acm_rb { 78 int size; 79 unsigned char *base; 80 dma_addr_t dma; 81 int index; 82 struct acm *instance; 83 }; 84 85 struct acm { 86 struct usb_device *dev; /* the corresponding usb device */ 87 struct usb_interface *control; /* control interface */ 88 struct usb_interface *data; /* data interface */ 89 unsigned in, out; /* i/o pipes */ 90 struct tty_port port; /* our tty port data */ 91 struct urb *ctrlurb; /* urbs */ 92 u8 *ctrl_buffer; /* buffers of urbs */ 93 dma_addr_t ctrl_dma; /* dma handles of buffers */ 94 u8 *country_codes; /* country codes from device */ 95 unsigned int country_code_size; /* size of this buffer */ 96 unsigned int country_rel_date; /* release date of version */ 97 struct acm_wb wb[ACM_NW]; 98 unsigned long read_urbs_free; 99 struct urb *read_urbs[ACM_NR]; 100 struct acm_rb read_buffers[ACM_NR]; 101 int rx_buflimit; 102 spinlock_t read_lock; 103 u8 *notification_buffer; /* to reassemble fragmented notifications */ 104 unsigned int nb_index; 105 unsigned int nb_size; 106 int transmitting; 107 spinlock_t write_lock; 108 struct mutex mutex; 109 bool disconnected; 110 unsigned long flags; 111 # define EVENT_TTY_WAKEUP 0 112 # define EVENT_RX_STALL 1 113 # define ACM_THROTTLED 2 114 # define ACM_ERROR_DELAY 3 115 unsigned long urbs_in_error_delay; /* these need to be restarted after a delay */ 116 struct usb_cdc_line_coding line; /* bits, stop, parity */ 117 struct delayed_work dwork; /* work queue entry for various purposes */ 118 unsigned int ctrlin; /* input control lines (DCD, DSR, RI, break, overruns) */ 119 unsigned int ctrlout; /* output control lines (DTR, RTS) */ 120 struct async_icount iocount; /* counters for control line changes */ 121 struct async_icount oldcount; /* for comparison of counter */ 122 wait_queue_head_t wioctl; /* for ioctl */ 123 unsigned int writesize; /* max packet size for the output bulk endpoint */ 124 unsigned int readsize,ctrlsize; /* buffer sizes for freeing */ 125 unsigned int minor; /* acm minor number */ 126 unsigned char clocal; /* termios CLOCAL */ 127 unsigned int ctrl_caps; /* control capabilities from the class specific header */ 128 unsigned int susp_count; /* number of suspended interfaces */ 129 unsigned int combined_interfaces:1; /* control and data collapsed */ 130 u8 bInterval; 131 struct usb_anchor delayed; /* writes queued for a device about to be woken */ 132 unsigned long quirks; 133 }; 134 135 /* constants describing various quirks and errors */ 136 #define NO_UNION_NORMAL BIT(0) 137 #define SINGLE_RX_URB BIT(1) 138 #define NO_CAP_LINE BIT(2) 139 #define IGNORE_DEVICE BIT(3) 140 #define QUIRK_CONTROL_LINE_STATE BIT(4) 141 #define CLEAR_HALT_CONDITIONS BIT(5) 142 #define SEND_ZERO_PACKET BIT(6) 143 #define DISABLE_ECHO BIT(7) 144