1 /* 2 * core.c - ChipIdea USB IP core family device controller 3 * 4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. 5 * 6 * Author: David Lopo 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 /* 14 * Description: ChipIdea USB IP core family device controller 15 * 16 * This driver is composed of several blocks: 17 * - HW: hardware interface 18 * - DBG: debug facilities (optional) 19 * - UTIL: utilities 20 * - ISR: interrupts handling 21 * - ENDPT: endpoint operations (Gadget API) 22 * - GADGET: gadget operations (Gadget API) 23 * - BUS: bus glue code, bus abstraction layer 24 * 25 * Compile Options 26 * - CONFIG_USB_CHIPIDEA_DEBUG: enable debug facilities 27 * - STALL_IN: non-empty bulk-in pipes cannot be halted 28 * if defined mass storage compliance succeeds but with warnings 29 * => case 4: Hi > Dn 30 * => case 5: Hi > Di 31 * => case 8: Hi <> Do 32 * if undefined usbtest 13 fails 33 * - TRACE: enable function tracing (depends on DEBUG) 34 * 35 * Main Features 36 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage 37 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined) 38 * - Normal & LPM support 39 * 40 * USBTEST Report 41 * - OK: 0-12, 13 (STALL_IN defined) & 14 42 * - Not Supported: 15 & 16 (ISO) 43 * 44 * TODO List 45 * - Suspend & Remote Wakeup 46 */ 47 #include <linux/delay.h> 48 #include <linux/device.h> 49 #include <linux/dma-mapping.h> 50 #include <linux/phy/phy.h> 51 #include <linux/platform_device.h> 52 #include <linux/module.h> 53 #include <linux/idr.h> 54 #include <linux/interrupt.h> 55 #include <linux/io.h> 56 #include <linux/kernel.h> 57 #include <linux/slab.h> 58 #include <linux/pm_runtime.h> 59 #include <linux/usb/ch9.h> 60 #include <linux/usb/gadget.h> 61 #include <linux/usb/otg.h> 62 #include <linux/usb/chipidea.h> 63 #include <linux/usb/of.h> 64 #include <linux/of.h> 65 #include <linux/phy.h> 66 #include <linux/regulator/consumer.h> 67 68 #include "ci.h" 69 #include "udc.h" 70 #include "bits.h" 71 #include "host.h" 72 #include "debug.h" 73 #include "otg.h" 74 #include "otg_fsm.h" 75 76 /* Controller register map */ 77 static const u8 ci_regs_nolpm[] = { 78 [CAP_CAPLENGTH] = 0x00U, 79 [CAP_HCCPARAMS] = 0x08U, 80 [CAP_DCCPARAMS] = 0x24U, 81 [CAP_TESTMODE] = 0x38U, 82 [OP_USBCMD] = 0x00U, 83 [OP_USBSTS] = 0x04U, 84 [OP_USBINTR] = 0x08U, 85 [OP_DEVICEADDR] = 0x14U, 86 [OP_ENDPTLISTADDR] = 0x18U, 87 [OP_PORTSC] = 0x44U, 88 [OP_DEVLC] = 0x84U, 89 [OP_OTGSC] = 0x64U, 90 [OP_USBMODE] = 0x68U, 91 [OP_ENDPTSETUPSTAT] = 0x6CU, 92 [OP_ENDPTPRIME] = 0x70U, 93 [OP_ENDPTFLUSH] = 0x74U, 94 [OP_ENDPTSTAT] = 0x78U, 95 [OP_ENDPTCOMPLETE] = 0x7CU, 96 [OP_ENDPTCTRL] = 0x80U, 97 }; 98 99 static const u8 ci_regs_lpm[] = { 100 [CAP_CAPLENGTH] = 0x00U, 101 [CAP_HCCPARAMS] = 0x08U, 102 [CAP_DCCPARAMS] = 0x24U, 103 [CAP_TESTMODE] = 0xFCU, 104 [OP_USBCMD] = 0x00U, 105 [OP_USBSTS] = 0x04U, 106 [OP_USBINTR] = 0x08U, 107 [OP_DEVICEADDR] = 0x14U, 108 [OP_ENDPTLISTADDR] = 0x18U, 109 [OP_PORTSC] = 0x44U, 110 [OP_DEVLC] = 0x84U, 111 [OP_OTGSC] = 0xC4U, 112 [OP_USBMODE] = 0xC8U, 113 [OP_ENDPTSETUPSTAT] = 0xD8U, 114 [OP_ENDPTPRIME] = 0xDCU, 115 [OP_ENDPTFLUSH] = 0xE0U, 116 [OP_ENDPTSTAT] = 0xE4U, 117 [OP_ENDPTCOMPLETE] = 0xE8U, 118 [OP_ENDPTCTRL] = 0xECU, 119 }; 120 121 static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm) 122 { 123 int i; 124 125 for (i = 0; i < OP_ENDPTCTRL; i++) 126 ci->hw_bank.regmap[i] = 127 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) + 128 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]); 129 130 for (; i <= OP_LAST; i++) 131 ci->hw_bank.regmap[i] = ci->hw_bank.op + 132 4 * (i - OP_ENDPTCTRL) + 133 (is_lpm 134 ? ci_regs_lpm[OP_ENDPTCTRL] 135 : ci_regs_nolpm[OP_ENDPTCTRL]); 136 137 return 0; 138 } 139 140 /** 141 * hw_read_intr_enable: returns interrupt enable register 142 * 143 * @ci: the controller 144 * 145 * This function returns register data 146 */ 147 u32 hw_read_intr_enable(struct ci_hdrc *ci) 148 { 149 return hw_read(ci, OP_USBINTR, ~0); 150 } 151 152 /** 153 * hw_read_intr_status: returns interrupt status register 154 * 155 * @ci: the controller 156 * 157 * This function returns register data 158 */ 159 u32 hw_read_intr_status(struct ci_hdrc *ci) 160 { 161 return hw_read(ci, OP_USBSTS, ~0); 162 } 163 164 /** 165 * hw_port_test_set: writes port test mode (execute without interruption) 166 * @mode: new value 167 * 168 * This function returns an error code 169 */ 170 int hw_port_test_set(struct ci_hdrc *ci, u8 mode) 171 { 172 const u8 TEST_MODE_MAX = 7; 173 174 if (mode > TEST_MODE_MAX) 175 return -EINVAL; 176 177 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC)); 178 return 0; 179 } 180 181 /** 182 * hw_port_test_get: reads port test mode value 183 * 184 * @ci: the controller 185 * 186 * This function returns port test mode value 187 */ 188 u8 hw_port_test_get(struct ci_hdrc *ci) 189 { 190 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC); 191 } 192 193 static void hw_wait_phy_stable(void) 194 { 195 /* 196 * The phy needs some delay to output the stable status from low 197 * power mode. And for OTGSC, the status inputs are debounced 198 * using a 1 ms time constant, so, delay 2ms for controller to get 199 * the stable status, like vbus and id when the phy leaves low power. 200 */ 201 usleep_range(2000, 2500); 202 } 203 204 /* The PHY enters/leaves low power mode */ 205 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable) 206 { 207 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC; 208 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm))); 209 210 if (enable && !lpm) 211 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), 212 PORTSC_PHCD(ci->hw_bank.lpm)); 213 else if (!enable && lpm) 214 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), 215 0); 216 } 217 218 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base) 219 { 220 u32 reg; 221 222 /* bank is a module variable */ 223 ci->hw_bank.abs = base; 224 225 ci->hw_bank.cap = ci->hw_bank.abs; 226 ci->hw_bank.cap += ci->platdata->capoffset; 227 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff); 228 229 hw_alloc_regmap(ci, false); 230 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >> 231 __ffs(HCCPARAMS_LEN); 232 ci->hw_bank.lpm = reg; 233 if (reg) 234 hw_alloc_regmap(ci, !!reg); 235 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs; 236 ci->hw_bank.size += OP_LAST; 237 ci->hw_bank.size /= sizeof(u32); 238 239 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >> 240 __ffs(DCCPARAMS_DEN); 241 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */ 242 243 if (ci->hw_ep_max > ENDPT_MAX) 244 return -ENODEV; 245 246 ci_hdrc_enter_lpm(ci, false); 247 248 /* Disable all interrupts bits */ 249 hw_write(ci, OP_USBINTR, 0xffffffff, 0); 250 251 /* Clear all interrupts status bits*/ 252 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff); 253 254 dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n", 255 ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op); 256 257 /* setup lock mode ? */ 258 259 /* ENDPTSETUPSTAT is '0' by default */ 260 261 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */ 262 263 return 0; 264 } 265 266 static void hw_phymode_configure(struct ci_hdrc *ci) 267 { 268 u32 portsc, lpm, sts = 0; 269 270 switch (ci->platdata->phy_mode) { 271 case USBPHY_INTERFACE_MODE_UTMI: 272 portsc = PORTSC_PTS(PTS_UTMI); 273 lpm = DEVLC_PTS(PTS_UTMI); 274 break; 275 case USBPHY_INTERFACE_MODE_UTMIW: 276 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW; 277 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW; 278 break; 279 case USBPHY_INTERFACE_MODE_ULPI: 280 portsc = PORTSC_PTS(PTS_ULPI); 281 lpm = DEVLC_PTS(PTS_ULPI); 282 break; 283 case USBPHY_INTERFACE_MODE_SERIAL: 284 portsc = PORTSC_PTS(PTS_SERIAL); 285 lpm = DEVLC_PTS(PTS_SERIAL); 286 sts = 1; 287 break; 288 case USBPHY_INTERFACE_MODE_HSIC: 289 portsc = PORTSC_PTS(PTS_HSIC); 290 lpm = DEVLC_PTS(PTS_HSIC); 291 break; 292 default: 293 return; 294 } 295 296 if (ci->hw_bank.lpm) { 297 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm); 298 if (sts) 299 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS); 300 } else { 301 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc); 302 if (sts) 303 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS); 304 } 305 } 306 307 /** 308 * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy 309 * interfaces 310 * @ci: the controller 311 * 312 * This function returns an error code if the phy failed to init 313 */ 314 static int _ci_usb_phy_init(struct ci_hdrc *ci) 315 { 316 int ret; 317 318 if (ci->phy) { 319 ret = phy_init(ci->phy); 320 if (ret) 321 return ret; 322 323 ret = phy_power_on(ci->phy); 324 if (ret) { 325 phy_exit(ci->phy); 326 return ret; 327 } 328 } else { 329 ret = usb_phy_init(ci->usb_phy); 330 } 331 332 return ret; 333 } 334 335 /** 336 * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy 337 * interfaces 338 * @ci: the controller 339 */ 340 static void ci_usb_phy_exit(struct ci_hdrc *ci) 341 { 342 if (ci->phy) { 343 phy_power_off(ci->phy); 344 phy_exit(ci->phy); 345 } else { 346 usb_phy_shutdown(ci->usb_phy); 347 } 348 } 349 350 /** 351 * ci_usb_phy_init: initialize phy according to different phy type 352 * @ci: the controller 353 * 354 * This function returns an error code if usb_phy_init has failed 355 */ 356 static int ci_usb_phy_init(struct ci_hdrc *ci) 357 { 358 int ret; 359 360 switch (ci->platdata->phy_mode) { 361 case USBPHY_INTERFACE_MODE_UTMI: 362 case USBPHY_INTERFACE_MODE_UTMIW: 363 case USBPHY_INTERFACE_MODE_HSIC: 364 ret = _ci_usb_phy_init(ci); 365 if (!ret) 366 hw_wait_phy_stable(); 367 else 368 return ret; 369 hw_phymode_configure(ci); 370 break; 371 case USBPHY_INTERFACE_MODE_ULPI: 372 case USBPHY_INTERFACE_MODE_SERIAL: 373 hw_phymode_configure(ci); 374 ret = _ci_usb_phy_init(ci); 375 if (ret) 376 return ret; 377 break; 378 default: 379 ret = _ci_usb_phy_init(ci); 380 if (!ret) 381 hw_wait_phy_stable(); 382 } 383 384 return ret; 385 } 386 387 /** 388 * hw_controller_reset: do controller reset 389 * @ci: the controller 390 * 391 * This function returns an error code 392 */ 393 static int hw_controller_reset(struct ci_hdrc *ci) 394 { 395 int count = 0; 396 397 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST); 398 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) { 399 udelay(10); 400 if (count++ > 1000) 401 return -ETIMEDOUT; 402 } 403 404 return 0; 405 } 406 407 /** 408 * hw_device_reset: resets chip (execute without interruption) 409 * @ci: the controller 410 * 411 * This function returns an error code 412 */ 413 int hw_device_reset(struct ci_hdrc *ci) 414 { 415 int ret; 416 417 /* should flush & stop before reset */ 418 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0); 419 hw_write(ci, OP_USBCMD, USBCMD_RS, 0); 420 421 ret = hw_controller_reset(ci); 422 if (ret) { 423 dev_err(ci->dev, "error resetting controller, ret=%d\n", ret); 424 return ret; 425 } 426 427 if (ci->platdata->notify_event) 428 ci->platdata->notify_event(ci, 429 CI_HDRC_CONTROLLER_RESET_EVENT); 430 431 if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING) 432 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS); 433 434 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) { 435 if (ci->hw_bank.lpm) 436 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC); 437 else 438 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC); 439 } 440 441 /* USBMODE should be configured step by step */ 442 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE); 443 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC); 444 /* HW >= 2.3 */ 445 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); 446 447 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) { 448 pr_err("cannot enter in %s device mode", ci_role(ci)->name); 449 pr_err("lpm = %i", ci->hw_bank.lpm); 450 return -ENODEV; 451 } 452 453 return 0; 454 } 455 456 /** 457 * hw_wait_reg: wait the register value 458 * 459 * Sometimes, it needs to wait register value before going on. 460 * Eg, when switch to device mode, the vbus value should be lower 461 * than OTGSC_BSV before connects to host. 462 * 463 * @ci: the controller 464 * @reg: register index 465 * @mask: mast bit 466 * @value: the bit value to wait 467 * @timeout_ms: timeout in millisecond 468 * 469 * This function returns an error code if timeout 470 */ 471 int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask, 472 u32 value, unsigned int timeout_ms) 473 { 474 unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms); 475 476 while (hw_read(ci, reg, mask) != value) { 477 if (time_after(jiffies, elapse)) { 478 dev_err(ci->dev, "timeout waiting for %08x in %d\n", 479 mask, reg); 480 return -ETIMEDOUT; 481 } 482 msleep(20); 483 } 484 485 return 0; 486 } 487 488 static irqreturn_t ci_irq(int irq, void *data) 489 { 490 struct ci_hdrc *ci = data; 491 irqreturn_t ret = IRQ_NONE; 492 u32 otgsc = 0; 493 494 if (ci->is_otg) { 495 otgsc = hw_read_otgsc(ci, ~0); 496 if (ci_otg_is_fsm_mode(ci)) { 497 ret = ci_otg_fsm_irq(ci); 498 if (ret == IRQ_HANDLED) 499 return ret; 500 } 501 } 502 503 /* 504 * Handle id change interrupt, it indicates device/host function 505 * switch. 506 */ 507 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) { 508 ci->id_event = true; 509 /* Clear ID change irq status */ 510 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS); 511 ci_otg_queue_work(ci); 512 return IRQ_HANDLED; 513 } 514 515 /* 516 * Handle vbus change interrupt, it indicates device connection 517 * and disconnection events. 518 */ 519 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) { 520 ci->b_sess_valid_event = true; 521 /* Clear BSV irq */ 522 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS); 523 ci_otg_queue_work(ci); 524 return IRQ_HANDLED; 525 } 526 527 /* Handle device/host interrupt */ 528 if (ci->role != CI_ROLE_END) 529 ret = ci_role(ci)->irq(ci); 530 531 return ret; 532 } 533 534 static int ci_get_platdata(struct device *dev, 535 struct ci_hdrc_platform_data *platdata) 536 { 537 if (!platdata->phy_mode) 538 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node); 539 540 if (!platdata->dr_mode) 541 platdata->dr_mode = of_usb_get_dr_mode(dev->of_node); 542 543 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN) 544 platdata->dr_mode = USB_DR_MODE_OTG; 545 546 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) { 547 /* Get the vbus regulator */ 548 platdata->reg_vbus = devm_regulator_get(dev, "vbus"); 549 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) { 550 return -EPROBE_DEFER; 551 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) { 552 /* no vbus regulator is needed */ 553 platdata->reg_vbus = NULL; 554 } else if (IS_ERR(platdata->reg_vbus)) { 555 dev_err(dev, "Getting regulator error: %ld\n", 556 PTR_ERR(platdata->reg_vbus)); 557 return PTR_ERR(platdata->reg_vbus); 558 } 559 /* Get TPL support */ 560 if (!platdata->tpl_support) 561 platdata->tpl_support = 562 of_usb_host_tpl_support(dev->of_node); 563 } 564 565 if (of_usb_get_maximum_speed(dev->of_node) == USB_SPEED_FULL) 566 platdata->flags |= CI_HDRC_FORCE_FULLSPEED; 567 568 return 0; 569 } 570 571 static DEFINE_IDA(ci_ida); 572 573 struct platform_device *ci_hdrc_add_device(struct device *dev, 574 struct resource *res, int nres, 575 struct ci_hdrc_platform_data *platdata) 576 { 577 struct platform_device *pdev; 578 int id, ret; 579 580 ret = ci_get_platdata(dev, platdata); 581 if (ret) 582 return ERR_PTR(ret); 583 584 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL); 585 if (id < 0) 586 return ERR_PTR(id); 587 588 pdev = platform_device_alloc("ci_hdrc", id); 589 if (!pdev) { 590 ret = -ENOMEM; 591 goto put_id; 592 } 593 594 pdev->dev.parent = dev; 595 pdev->dev.dma_mask = dev->dma_mask; 596 pdev->dev.dma_parms = dev->dma_parms; 597 dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask); 598 599 ret = platform_device_add_resources(pdev, res, nres); 600 if (ret) 601 goto err; 602 603 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata)); 604 if (ret) 605 goto err; 606 607 ret = platform_device_add(pdev); 608 if (ret) 609 goto err; 610 611 return pdev; 612 613 err: 614 platform_device_put(pdev); 615 put_id: 616 ida_simple_remove(&ci_ida, id); 617 return ERR_PTR(ret); 618 } 619 EXPORT_SYMBOL_GPL(ci_hdrc_add_device); 620 621 void ci_hdrc_remove_device(struct platform_device *pdev) 622 { 623 int id = pdev->id; 624 platform_device_unregister(pdev); 625 ida_simple_remove(&ci_ida, id); 626 } 627 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device); 628 629 static inline void ci_role_destroy(struct ci_hdrc *ci) 630 { 631 ci_hdrc_gadget_destroy(ci); 632 ci_hdrc_host_destroy(ci); 633 if (ci->is_otg) 634 ci_hdrc_otg_destroy(ci); 635 } 636 637 static void ci_get_otg_capable(struct ci_hdrc *ci) 638 { 639 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG) 640 ci->is_otg = false; 641 else 642 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS, 643 DCCPARAMS_DC | DCCPARAMS_HC) 644 == (DCCPARAMS_DC | DCCPARAMS_HC)); 645 if (ci->is_otg) 646 dev_dbg(ci->dev, "It is OTG capable controller\n"); 647 } 648 649 static int ci_hdrc_probe(struct platform_device *pdev) 650 { 651 struct device *dev = &pdev->dev; 652 struct ci_hdrc *ci; 653 struct resource *res; 654 void __iomem *base; 655 int ret; 656 enum usb_dr_mode dr_mode; 657 658 if (!dev_get_platdata(dev)) { 659 dev_err(dev, "platform data missing\n"); 660 return -ENODEV; 661 } 662 663 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 664 base = devm_ioremap_resource(dev, res); 665 if (IS_ERR(base)) 666 return PTR_ERR(base); 667 668 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL); 669 if (!ci) 670 return -ENOMEM; 671 672 ci->dev = dev; 673 ci->platdata = dev_get_platdata(dev); 674 ci->imx28_write_fix = !!(ci->platdata->flags & 675 CI_HDRC_IMX28_WRITE_FIX); 676 677 ret = hw_device_init(ci, base); 678 if (ret < 0) { 679 dev_err(dev, "can't initialize hardware\n"); 680 return -ENODEV; 681 } 682 683 if (ci->platdata->phy) { 684 ci->phy = ci->platdata->phy; 685 } else if (ci->platdata->usb_phy) { 686 ci->usb_phy = ci->platdata->usb_phy; 687 } else { 688 ci->phy = devm_phy_get(dev->parent, "usb-phy"); 689 ci->usb_phy = devm_usb_get_phy(dev->parent, USB_PHY_TYPE_USB2); 690 691 /* if both generic PHY and USB PHY layers aren't enabled */ 692 if (PTR_ERR(ci->phy) == -ENOSYS && 693 PTR_ERR(ci->usb_phy) == -ENXIO) 694 return -ENXIO; 695 696 if (IS_ERR(ci->phy) && IS_ERR(ci->usb_phy)) 697 return -EPROBE_DEFER; 698 699 if (IS_ERR(ci->phy)) 700 ci->phy = NULL; 701 else if (IS_ERR(ci->usb_phy)) 702 ci->usb_phy = NULL; 703 } 704 705 ret = ci_usb_phy_init(ci); 706 if (ret) { 707 dev_err(dev, "unable to init phy: %d\n", ret); 708 return ret; 709 } 710 711 ci->hw_bank.phys = res->start; 712 713 ci->irq = platform_get_irq(pdev, 0); 714 if (ci->irq < 0) { 715 dev_err(dev, "missing IRQ\n"); 716 ret = ci->irq; 717 goto deinit_phy; 718 } 719 720 ci_get_otg_capable(ci); 721 722 dr_mode = ci->platdata->dr_mode; 723 /* initialize role(s) before the interrupt is requested */ 724 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) { 725 ret = ci_hdrc_host_init(ci); 726 if (ret) 727 dev_info(dev, "doesn't support host\n"); 728 } 729 730 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) { 731 ret = ci_hdrc_gadget_init(ci); 732 if (ret) 733 dev_info(dev, "doesn't support gadget\n"); 734 } 735 736 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) { 737 dev_err(dev, "no supported roles\n"); 738 ret = -ENODEV; 739 goto deinit_phy; 740 } 741 742 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) { 743 /* Disable and clear all OTG irq */ 744 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS, 745 OTGSC_INT_STATUS_BITS); 746 ret = ci_hdrc_otg_init(ci); 747 if (ret) { 748 dev_err(dev, "init otg fails, ret = %d\n", ret); 749 goto stop; 750 } 751 } 752 753 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) { 754 if (ci->is_otg) { 755 ci->role = ci_otg_role(ci); 756 /* Enable ID change irq */ 757 hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE); 758 } else { 759 /* 760 * If the controller is not OTG capable, but support 761 * role switch, the defalt role is gadget, and the 762 * user can switch it through debugfs. 763 */ 764 ci->role = CI_ROLE_GADGET; 765 } 766 } else { 767 ci->role = ci->roles[CI_ROLE_HOST] 768 ? CI_ROLE_HOST 769 : CI_ROLE_GADGET; 770 } 771 772 /* only update vbus status for peripheral */ 773 if (ci->role == CI_ROLE_GADGET) 774 ci_handle_vbus_change(ci); 775 776 if (!ci_otg_is_fsm_mode(ci)) { 777 ret = ci_role_start(ci, ci->role); 778 if (ret) { 779 dev_err(dev, "can't start %s role\n", 780 ci_role(ci)->name); 781 goto stop; 782 } 783 } 784 785 platform_set_drvdata(pdev, ci); 786 ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED, 787 ci->platdata->name, ci); 788 if (ret) 789 goto stop; 790 791 if (ci_otg_is_fsm_mode(ci)) 792 ci_hdrc_otg_fsm_start(ci); 793 794 ret = dbg_create_files(ci); 795 if (!ret) 796 return 0; 797 798 stop: 799 ci_role_destroy(ci); 800 deinit_phy: 801 ci_usb_phy_exit(ci); 802 803 return ret; 804 } 805 806 static int ci_hdrc_remove(struct platform_device *pdev) 807 { 808 struct ci_hdrc *ci = platform_get_drvdata(pdev); 809 810 dbg_remove_files(ci); 811 ci_role_destroy(ci); 812 ci_hdrc_enter_lpm(ci, true); 813 ci_usb_phy_exit(ci); 814 815 return 0; 816 } 817 818 #ifdef CONFIG_PM_SLEEP 819 static void ci_controller_suspend(struct ci_hdrc *ci) 820 { 821 ci_hdrc_enter_lpm(ci, true); 822 823 if (ci->usb_phy) 824 usb_phy_set_suspend(ci->usb_phy, 1); 825 } 826 827 static int ci_controller_resume(struct device *dev) 828 { 829 struct ci_hdrc *ci = dev_get_drvdata(dev); 830 831 dev_dbg(dev, "at %s\n", __func__); 832 833 ci_hdrc_enter_lpm(ci, false); 834 835 if (ci->usb_phy) { 836 usb_phy_set_suspend(ci->usb_phy, 0); 837 usb_phy_set_wakeup(ci->usb_phy, false); 838 hw_wait_phy_stable(); 839 } 840 841 return 0; 842 } 843 844 static int ci_suspend(struct device *dev) 845 { 846 struct ci_hdrc *ci = dev_get_drvdata(dev); 847 848 if (ci->wq) 849 flush_workqueue(ci->wq); 850 851 ci_controller_suspend(ci); 852 853 return 0; 854 } 855 856 static int ci_resume(struct device *dev) 857 { 858 return ci_controller_resume(dev); 859 } 860 #endif /* CONFIG_PM_SLEEP */ 861 862 static const struct dev_pm_ops ci_pm_ops = { 863 SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume) 864 }; 865 static struct platform_driver ci_hdrc_driver = { 866 .probe = ci_hdrc_probe, 867 .remove = ci_hdrc_remove, 868 .driver = { 869 .name = "ci_hdrc", 870 .pm = &ci_pm_ops, 871 }, 872 }; 873 874 module_platform_driver(ci_hdrc_driver); 875 876 MODULE_ALIAS("platform:ci_hdrc"); 877 MODULE_LICENSE("GPL v2"); 878 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>"); 879 MODULE_DESCRIPTION("ChipIdea HDRC Driver"); 880