1 /* 2 * core.c - ChipIdea USB IP core family device controller 3 * 4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. 5 * 6 * Author: David Lopo 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 /* 14 * Description: ChipIdea USB IP core family device controller 15 * 16 * This driver is composed of several blocks: 17 * - HW: hardware interface 18 * - DBG: debug facilities (optional) 19 * - UTIL: utilities 20 * - ISR: interrupts handling 21 * - ENDPT: endpoint operations (Gadget API) 22 * - GADGET: gadget operations (Gadget API) 23 * - BUS: bus glue code, bus abstraction layer 24 * 25 * Compile Options 26 * - STALL_IN: non-empty bulk-in pipes cannot be halted 27 * if defined mass storage compliance succeeds but with warnings 28 * => case 4: Hi > Dn 29 * => case 5: Hi > Di 30 * => case 8: Hi <> Do 31 * if undefined usbtest 13 fails 32 * - TRACE: enable function tracing (depends on DEBUG) 33 * 34 * Main Features 35 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage 36 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined) 37 * - Normal & LPM support 38 * 39 * USBTEST Report 40 * - OK: 0-12, 13 (STALL_IN defined) & 14 41 * - Not Supported: 15 & 16 (ISO) 42 * 43 * TODO List 44 * - Suspend & Remote Wakeup 45 */ 46 #include <linux/delay.h> 47 #include <linux/device.h> 48 #include <linux/dma-mapping.h> 49 #include <linux/extcon.h> 50 #include <linux/phy/phy.h> 51 #include <linux/platform_device.h> 52 #include <linux/module.h> 53 #include <linux/idr.h> 54 #include <linux/interrupt.h> 55 #include <linux/io.h> 56 #include <linux/kernel.h> 57 #include <linux/slab.h> 58 #include <linux/pm_runtime.h> 59 #include <linux/usb/ch9.h> 60 #include <linux/usb/gadget.h> 61 #include <linux/usb/otg.h> 62 #include <linux/usb/chipidea.h> 63 #include <linux/usb/of.h> 64 #include <linux/of.h> 65 #include <linux/phy.h> 66 #include <linux/regulator/consumer.h> 67 #include <linux/usb/ehci_def.h> 68 69 #include "ci.h" 70 #include "udc.h" 71 #include "bits.h" 72 #include "host.h" 73 #include "otg.h" 74 #include "otg_fsm.h" 75 76 /* Controller register map */ 77 static const u8 ci_regs_nolpm[] = { 78 [CAP_CAPLENGTH] = 0x00U, 79 [CAP_HCCPARAMS] = 0x08U, 80 [CAP_DCCPARAMS] = 0x24U, 81 [CAP_TESTMODE] = 0x38U, 82 [OP_USBCMD] = 0x00U, 83 [OP_USBSTS] = 0x04U, 84 [OP_USBINTR] = 0x08U, 85 [OP_DEVICEADDR] = 0x14U, 86 [OP_ENDPTLISTADDR] = 0x18U, 87 [OP_TTCTRL] = 0x1CU, 88 [OP_BURSTSIZE] = 0x20U, 89 [OP_PORTSC] = 0x44U, 90 [OP_DEVLC] = 0x84U, 91 [OP_OTGSC] = 0x64U, 92 [OP_USBMODE] = 0x68U, 93 [OP_ENDPTSETUPSTAT] = 0x6CU, 94 [OP_ENDPTPRIME] = 0x70U, 95 [OP_ENDPTFLUSH] = 0x74U, 96 [OP_ENDPTSTAT] = 0x78U, 97 [OP_ENDPTCOMPLETE] = 0x7CU, 98 [OP_ENDPTCTRL] = 0x80U, 99 }; 100 101 static const u8 ci_regs_lpm[] = { 102 [CAP_CAPLENGTH] = 0x00U, 103 [CAP_HCCPARAMS] = 0x08U, 104 [CAP_DCCPARAMS] = 0x24U, 105 [CAP_TESTMODE] = 0xFCU, 106 [OP_USBCMD] = 0x00U, 107 [OP_USBSTS] = 0x04U, 108 [OP_USBINTR] = 0x08U, 109 [OP_DEVICEADDR] = 0x14U, 110 [OP_ENDPTLISTADDR] = 0x18U, 111 [OP_TTCTRL] = 0x1CU, 112 [OP_BURSTSIZE] = 0x20U, 113 [OP_PORTSC] = 0x44U, 114 [OP_DEVLC] = 0x84U, 115 [OP_OTGSC] = 0xC4U, 116 [OP_USBMODE] = 0xC8U, 117 [OP_ENDPTSETUPSTAT] = 0xD8U, 118 [OP_ENDPTPRIME] = 0xDCU, 119 [OP_ENDPTFLUSH] = 0xE0U, 120 [OP_ENDPTSTAT] = 0xE4U, 121 [OP_ENDPTCOMPLETE] = 0xE8U, 122 [OP_ENDPTCTRL] = 0xECU, 123 }; 124 125 static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm) 126 { 127 int i; 128 129 for (i = 0; i < OP_ENDPTCTRL; i++) 130 ci->hw_bank.regmap[i] = 131 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) + 132 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]); 133 134 for (; i <= OP_LAST; i++) 135 ci->hw_bank.regmap[i] = ci->hw_bank.op + 136 4 * (i - OP_ENDPTCTRL) + 137 (is_lpm 138 ? ci_regs_lpm[OP_ENDPTCTRL] 139 : ci_regs_nolpm[OP_ENDPTCTRL]); 140 141 } 142 143 static enum ci_revision ci_get_revision(struct ci_hdrc *ci) 144 { 145 int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION); 146 enum ci_revision rev = CI_REVISION_UNKNOWN; 147 148 if (ver == 0x2) { 149 rev = hw_read_id_reg(ci, ID_ID, REVISION) 150 >> __ffs(REVISION); 151 rev += CI_REVISION_20; 152 } else if (ver == 0x0) { 153 rev = CI_REVISION_1X; 154 } 155 156 return rev; 157 } 158 159 /** 160 * hw_read_intr_enable: returns interrupt enable register 161 * 162 * @ci: the controller 163 * 164 * This function returns register data 165 */ 166 u32 hw_read_intr_enable(struct ci_hdrc *ci) 167 { 168 return hw_read(ci, OP_USBINTR, ~0); 169 } 170 171 /** 172 * hw_read_intr_status: returns interrupt status register 173 * 174 * @ci: the controller 175 * 176 * This function returns register data 177 */ 178 u32 hw_read_intr_status(struct ci_hdrc *ci) 179 { 180 return hw_read(ci, OP_USBSTS, ~0); 181 } 182 183 /** 184 * hw_port_test_set: writes port test mode (execute without interruption) 185 * @mode: new value 186 * 187 * This function returns an error code 188 */ 189 int hw_port_test_set(struct ci_hdrc *ci, u8 mode) 190 { 191 const u8 TEST_MODE_MAX = 7; 192 193 if (mode > TEST_MODE_MAX) 194 return -EINVAL; 195 196 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC)); 197 return 0; 198 } 199 200 /** 201 * hw_port_test_get: reads port test mode value 202 * 203 * @ci: the controller 204 * 205 * This function returns port test mode value 206 */ 207 u8 hw_port_test_get(struct ci_hdrc *ci) 208 { 209 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC); 210 } 211 212 static void hw_wait_phy_stable(void) 213 { 214 /* 215 * The phy needs some delay to output the stable status from low 216 * power mode. And for OTGSC, the status inputs are debounced 217 * using a 1 ms time constant, so, delay 2ms for controller to get 218 * the stable status, like vbus and id when the phy leaves low power. 219 */ 220 usleep_range(2000, 2500); 221 } 222 223 /* The PHY enters/leaves low power mode */ 224 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable) 225 { 226 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC; 227 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm))); 228 229 if (enable && !lpm) 230 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), 231 PORTSC_PHCD(ci->hw_bank.lpm)); 232 else if (!enable && lpm) 233 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), 234 0); 235 } 236 237 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base) 238 { 239 u32 reg; 240 241 /* bank is a module variable */ 242 ci->hw_bank.abs = base; 243 244 ci->hw_bank.cap = ci->hw_bank.abs; 245 ci->hw_bank.cap += ci->platdata->capoffset; 246 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff); 247 248 hw_alloc_regmap(ci, false); 249 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >> 250 __ffs(HCCPARAMS_LEN); 251 ci->hw_bank.lpm = reg; 252 if (reg) 253 hw_alloc_regmap(ci, !!reg); 254 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs; 255 ci->hw_bank.size += OP_LAST; 256 ci->hw_bank.size /= sizeof(u32); 257 258 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >> 259 __ffs(DCCPARAMS_DEN); 260 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */ 261 262 if (ci->hw_ep_max > ENDPT_MAX) 263 return -ENODEV; 264 265 ci_hdrc_enter_lpm(ci, false); 266 267 /* Disable all interrupts bits */ 268 hw_write(ci, OP_USBINTR, 0xffffffff, 0); 269 270 /* Clear all interrupts status bits*/ 271 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff); 272 273 ci->rev = ci_get_revision(ci); 274 275 dev_dbg(ci->dev, 276 "ChipIdea HDRC found, revision: %d, lpm: %d; cap: %p op: %p\n", 277 ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op); 278 279 /* setup lock mode ? */ 280 281 /* ENDPTSETUPSTAT is '0' by default */ 282 283 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */ 284 285 return 0; 286 } 287 288 static void hw_phymode_configure(struct ci_hdrc *ci) 289 { 290 u32 portsc, lpm, sts = 0; 291 292 switch (ci->platdata->phy_mode) { 293 case USBPHY_INTERFACE_MODE_UTMI: 294 portsc = PORTSC_PTS(PTS_UTMI); 295 lpm = DEVLC_PTS(PTS_UTMI); 296 break; 297 case USBPHY_INTERFACE_MODE_UTMIW: 298 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW; 299 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW; 300 break; 301 case USBPHY_INTERFACE_MODE_ULPI: 302 portsc = PORTSC_PTS(PTS_ULPI); 303 lpm = DEVLC_PTS(PTS_ULPI); 304 break; 305 case USBPHY_INTERFACE_MODE_SERIAL: 306 portsc = PORTSC_PTS(PTS_SERIAL); 307 lpm = DEVLC_PTS(PTS_SERIAL); 308 sts = 1; 309 break; 310 case USBPHY_INTERFACE_MODE_HSIC: 311 portsc = PORTSC_PTS(PTS_HSIC); 312 lpm = DEVLC_PTS(PTS_HSIC); 313 break; 314 default: 315 return; 316 } 317 318 if (ci->hw_bank.lpm) { 319 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm); 320 if (sts) 321 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS); 322 } else { 323 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc); 324 if (sts) 325 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS); 326 } 327 } 328 329 /** 330 * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy 331 * interfaces 332 * @ci: the controller 333 * 334 * This function returns an error code if the phy failed to init 335 */ 336 static int _ci_usb_phy_init(struct ci_hdrc *ci) 337 { 338 int ret; 339 340 if (ci->phy) { 341 ret = phy_init(ci->phy); 342 if (ret) 343 return ret; 344 345 ret = phy_power_on(ci->phy); 346 if (ret) { 347 phy_exit(ci->phy); 348 return ret; 349 } 350 } else { 351 ret = usb_phy_init(ci->usb_phy); 352 } 353 354 return ret; 355 } 356 357 /** 358 * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy 359 * interfaces 360 * @ci: the controller 361 */ 362 static void ci_usb_phy_exit(struct ci_hdrc *ci) 363 { 364 if (ci->phy) { 365 phy_power_off(ci->phy); 366 phy_exit(ci->phy); 367 } else { 368 usb_phy_shutdown(ci->usb_phy); 369 } 370 } 371 372 /** 373 * ci_usb_phy_init: initialize phy according to different phy type 374 * @ci: the controller 375 * 376 * This function returns an error code if usb_phy_init has failed 377 */ 378 static int ci_usb_phy_init(struct ci_hdrc *ci) 379 { 380 int ret; 381 382 switch (ci->platdata->phy_mode) { 383 case USBPHY_INTERFACE_MODE_UTMI: 384 case USBPHY_INTERFACE_MODE_UTMIW: 385 case USBPHY_INTERFACE_MODE_HSIC: 386 ret = _ci_usb_phy_init(ci); 387 if (!ret) 388 hw_wait_phy_stable(); 389 else 390 return ret; 391 hw_phymode_configure(ci); 392 break; 393 case USBPHY_INTERFACE_MODE_ULPI: 394 case USBPHY_INTERFACE_MODE_SERIAL: 395 hw_phymode_configure(ci); 396 ret = _ci_usb_phy_init(ci); 397 if (ret) 398 return ret; 399 break; 400 default: 401 ret = _ci_usb_phy_init(ci); 402 if (!ret) 403 hw_wait_phy_stable(); 404 } 405 406 return ret; 407 } 408 409 410 /** 411 * ci_platform_configure: do controller configure 412 * @ci: the controller 413 * 414 */ 415 void ci_platform_configure(struct ci_hdrc *ci) 416 { 417 bool is_device_mode, is_host_mode; 418 419 is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC; 420 is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC; 421 422 if (is_device_mode && 423 (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING)) 424 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS); 425 426 if (is_host_mode && 427 (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING)) 428 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS); 429 430 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) { 431 if (ci->hw_bank.lpm) 432 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC); 433 else 434 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC); 435 } 436 437 if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA) 438 hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA); 439 440 hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16); 441 442 if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST) 443 hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK, 444 ci->platdata->ahb_burst_config); 445 446 /* override burst size, take effect only when ahb_burst_config is 0 */ 447 if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) { 448 if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST) 449 hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK, 450 ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK)); 451 452 if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST) 453 hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK, 454 ci->platdata->rx_burst_size); 455 } 456 } 457 458 /** 459 * hw_controller_reset: do controller reset 460 * @ci: the controller 461 * 462 * This function returns an error code 463 */ 464 static int hw_controller_reset(struct ci_hdrc *ci) 465 { 466 int count = 0; 467 468 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST); 469 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) { 470 udelay(10); 471 if (count++ > 1000) 472 return -ETIMEDOUT; 473 } 474 475 return 0; 476 } 477 478 /** 479 * hw_device_reset: resets chip (execute without interruption) 480 * @ci: the controller 481 * 482 * This function returns an error code 483 */ 484 int hw_device_reset(struct ci_hdrc *ci) 485 { 486 int ret; 487 488 /* should flush & stop before reset */ 489 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0); 490 hw_write(ci, OP_USBCMD, USBCMD_RS, 0); 491 492 ret = hw_controller_reset(ci); 493 if (ret) { 494 dev_err(ci->dev, "error resetting controller, ret=%d\n", ret); 495 return ret; 496 } 497 498 if (ci->platdata->notify_event) 499 ci->platdata->notify_event(ci, 500 CI_HDRC_CONTROLLER_RESET_EVENT); 501 502 /* USBMODE should be configured step by step */ 503 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE); 504 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC); 505 /* HW >= 2.3 */ 506 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); 507 508 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) { 509 pr_err("cannot enter in %s device mode", ci_role(ci)->name); 510 pr_err("lpm = %i", ci->hw_bank.lpm); 511 return -ENODEV; 512 } 513 514 ci_platform_configure(ci); 515 516 return 0; 517 } 518 519 /** 520 * hw_wait_reg: wait the register value 521 * 522 * Sometimes, it needs to wait register value before going on. 523 * Eg, when switch to device mode, the vbus value should be lower 524 * than OTGSC_BSV before connects to host. 525 * 526 * @ci: the controller 527 * @reg: register index 528 * @mask: mast bit 529 * @value: the bit value to wait 530 * @timeout_ms: timeout in millisecond 531 * 532 * This function returns an error code if timeout 533 */ 534 int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask, 535 u32 value, unsigned int timeout_ms) 536 { 537 unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms); 538 539 while (hw_read(ci, reg, mask) != value) { 540 if (time_after(jiffies, elapse)) { 541 dev_err(ci->dev, "timeout waiting for %08x in %d\n", 542 mask, reg); 543 return -ETIMEDOUT; 544 } 545 msleep(20); 546 } 547 548 return 0; 549 } 550 551 static irqreturn_t ci_irq(int irq, void *data) 552 { 553 struct ci_hdrc *ci = data; 554 irqreturn_t ret = IRQ_NONE; 555 u32 otgsc = 0; 556 557 if (ci->in_lpm) { 558 disable_irq_nosync(irq); 559 ci->wakeup_int = true; 560 pm_runtime_get(ci->dev); 561 return IRQ_HANDLED; 562 } 563 564 if (ci->is_otg) { 565 otgsc = hw_read_otgsc(ci, ~0); 566 if (ci_otg_is_fsm_mode(ci)) { 567 ret = ci_otg_fsm_irq(ci); 568 if (ret == IRQ_HANDLED) 569 return ret; 570 } 571 } 572 573 /* 574 * Handle id change interrupt, it indicates device/host function 575 * switch. 576 */ 577 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) { 578 ci->id_event = true; 579 /* Clear ID change irq status */ 580 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS); 581 ci_otg_queue_work(ci); 582 return IRQ_HANDLED; 583 } 584 585 /* 586 * Handle vbus change interrupt, it indicates device connection 587 * and disconnection events. 588 */ 589 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) { 590 ci->b_sess_valid_event = true; 591 /* Clear BSV irq */ 592 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS); 593 ci_otg_queue_work(ci); 594 return IRQ_HANDLED; 595 } 596 597 /* Handle device/host interrupt */ 598 if (ci->role != CI_ROLE_END) 599 ret = ci_role(ci)->irq(ci); 600 601 return ret; 602 } 603 604 static int ci_vbus_notifier(struct notifier_block *nb, unsigned long event, 605 void *ptr) 606 { 607 struct ci_hdrc_cable *vbus = container_of(nb, struct ci_hdrc_cable, nb); 608 struct ci_hdrc *ci = vbus->ci; 609 610 if (event) 611 vbus->state = true; 612 else 613 vbus->state = false; 614 615 vbus->changed = true; 616 617 ci_irq(ci->irq, ci); 618 return NOTIFY_DONE; 619 } 620 621 static int ci_id_notifier(struct notifier_block *nb, unsigned long event, 622 void *ptr) 623 { 624 struct ci_hdrc_cable *id = container_of(nb, struct ci_hdrc_cable, nb); 625 struct ci_hdrc *ci = id->ci; 626 627 if (event) 628 id->state = false; 629 else 630 id->state = true; 631 632 id->changed = true; 633 634 ci_irq(ci->irq, ci); 635 return NOTIFY_DONE; 636 } 637 638 static int ci_get_platdata(struct device *dev, 639 struct ci_hdrc_platform_data *platdata) 640 { 641 struct extcon_dev *ext_vbus, *ext_id; 642 struct ci_hdrc_cable *cable; 643 int ret; 644 645 if (!platdata->phy_mode) 646 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node); 647 648 if (!platdata->dr_mode) 649 platdata->dr_mode = usb_get_dr_mode(dev); 650 651 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN) 652 platdata->dr_mode = USB_DR_MODE_OTG; 653 654 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) { 655 /* Get the vbus regulator */ 656 platdata->reg_vbus = devm_regulator_get(dev, "vbus"); 657 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) { 658 return -EPROBE_DEFER; 659 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) { 660 /* no vbus regulator is needed */ 661 platdata->reg_vbus = NULL; 662 } else if (IS_ERR(platdata->reg_vbus)) { 663 dev_err(dev, "Getting regulator error: %ld\n", 664 PTR_ERR(platdata->reg_vbus)); 665 return PTR_ERR(platdata->reg_vbus); 666 } 667 /* Get TPL support */ 668 if (!platdata->tpl_support) 669 platdata->tpl_support = 670 of_usb_host_tpl_support(dev->of_node); 671 } 672 673 if (platdata->dr_mode == USB_DR_MODE_OTG) { 674 /* We can support HNP and SRP of OTG 2.0 */ 675 platdata->ci_otg_caps.otg_rev = 0x0200; 676 platdata->ci_otg_caps.hnp_support = true; 677 platdata->ci_otg_caps.srp_support = true; 678 679 /* Update otg capabilities by DT properties */ 680 ret = of_usb_update_otg_caps(dev->of_node, 681 &platdata->ci_otg_caps); 682 if (ret) 683 return ret; 684 } 685 686 if (usb_get_maximum_speed(dev) == USB_SPEED_FULL) 687 platdata->flags |= CI_HDRC_FORCE_FULLSPEED; 688 689 of_property_read_u32(dev->of_node, "phy-clkgate-delay-us", 690 &platdata->phy_clkgate_delay_us); 691 692 platdata->itc_setting = 1; 693 694 of_property_read_u32(dev->of_node, "itc-setting", 695 &platdata->itc_setting); 696 697 ret = of_property_read_u32(dev->of_node, "ahb-burst-config", 698 &platdata->ahb_burst_config); 699 if (!ret) { 700 platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST; 701 } else if (ret != -EINVAL) { 702 dev_err(dev, "failed to get ahb-burst-config\n"); 703 return ret; 704 } 705 706 ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword", 707 &platdata->tx_burst_size); 708 if (!ret) { 709 platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST; 710 } else if (ret != -EINVAL) { 711 dev_err(dev, "failed to get tx-burst-size-dword\n"); 712 return ret; 713 } 714 715 ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword", 716 &platdata->rx_burst_size); 717 if (!ret) { 718 platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST; 719 } else if (ret != -EINVAL) { 720 dev_err(dev, "failed to get rx-burst-size-dword\n"); 721 return ret; 722 } 723 724 ext_id = ERR_PTR(-ENODEV); 725 ext_vbus = ERR_PTR(-ENODEV); 726 if (of_property_read_bool(dev->of_node, "extcon")) { 727 /* Each one of them is not mandatory */ 728 ext_vbus = extcon_get_edev_by_phandle(dev, 0); 729 if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV) 730 return PTR_ERR(ext_vbus); 731 732 ext_id = extcon_get_edev_by_phandle(dev, 1); 733 if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV) 734 return PTR_ERR(ext_id); 735 } 736 737 cable = &platdata->vbus_extcon; 738 cable->nb.notifier_call = ci_vbus_notifier; 739 cable->edev = ext_vbus; 740 741 if (!IS_ERR(ext_vbus)) { 742 ret = extcon_get_cable_state_(cable->edev, EXTCON_USB); 743 if (ret) 744 cable->state = true; 745 else 746 cable->state = false; 747 } 748 749 cable = &platdata->id_extcon; 750 cable->nb.notifier_call = ci_id_notifier; 751 cable->edev = ext_id; 752 753 if (!IS_ERR(ext_id)) { 754 ret = extcon_get_cable_state_(cable->edev, EXTCON_USB_HOST); 755 if (ret) 756 cable->state = false; 757 else 758 cable->state = true; 759 } 760 return 0; 761 } 762 763 static int ci_extcon_register(struct ci_hdrc *ci) 764 { 765 struct ci_hdrc_cable *id, *vbus; 766 int ret; 767 768 id = &ci->platdata->id_extcon; 769 id->ci = ci; 770 if (!IS_ERR(id->edev)) { 771 ret = extcon_register_notifier(id->edev, EXTCON_USB_HOST, 772 &id->nb); 773 if (ret < 0) { 774 dev_err(ci->dev, "register ID failed\n"); 775 return ret; 776 } 777 } 778 779 vbus = &ci->platdata->vbus_extcon; 780 vbus->ci = ci; 781 if (!IS_ERR(vbus->edev)) { 782 ret = extcon_register_notifier(vbus->edev, EXTCON_USB, 783 &vbus->nb); 784 if (ret < 0) { 785 extcon_unregister_notifier(id->edev, EXTCON_USB_HOST, 786 &id->nb); 787 dev_err(ci->dev, "register VBUS failed\n"); 788 return ret; 789 } 790 } 791 792 return 0; 793 } 794 795 static void ci_extcon_unregister(struct ci_hdrc *ci) 796 { 797 struct ci_hdrc_cable *cable; 798 799 cable = &ci->platdata->id_extcon; 800 if (!IS_ERR(cable->edev)) 801 extcon_unregister_notifier(cable->edev, EXTCON_USB_HOST, 802 &cable->nb); 803 804 cable = &ci->platdata->vbus_extcon; 805 if (!IS_ERR(cable->edev)) 806 extcon_unregister_notifier(cable->edev, EXTCON_USB, &cable->nb); 807 } 808 809 static DEFINE_IDA(ci_ida); 810 811 struct platform_device *ci_hdrc_add_device(struct device *dev, 812 struct resource *res, int nres, 813 struct ci_hdrc_platform_data *platdata) 814 { 815 struct platform_device *pdev; 816 int id, ret; 817 818 ret = ci_get_platdata(dev, platdata); 819 if (ret) 820 return ERR_PTR(ret); 821 822 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL); 823 if (id < 0) 824 return ERR_PTR(id); 825 826 pdev = platform_device_alloc("ci_hdrc", id); 827 if (!pdev) { 828 ret = -ENOMEM; 829 goto put_id; 830 } 831 832 pdev->dev.parent = dev; 833 pdev->dev.dma_mask = dev->dma_mask; 834 pdev->dev.dma_parms = dev->dma_parms; 835 dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask); 836 837 ret = platform_device_add_resources(pdev, res, nres); 838 if (ret) 839 goto err; 840 841 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata)); 842 if (ret) 843 goto err; 844 845 ret = platform_device_add(pdev); 846 if (ret) 847 goto err; 848 849 return pdev; 850 851 err: 852 platform_device_put(pdev); 853 put_id: 854 ida_simple_remove(&ci_ida, id); 855 return ERR_PTR(ret); 856 } 857 EXPORT_SYMBOL_GPL(ci_hdrc_add_device); 858 859 void ci_hdrc_remove_device(struct platform_device *pdev) 860 { 861 int id = pdev->id; 862 platform_device_unregister(pdev); 863 ida_simple_remove(&ci_ida, id); 864 } 865 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device); 866 867 static inline void ci_role_destroy(struct ci_hdrc *ci) 868 { 869 ci_hdrc_gadget_destroy(ci); 870 ci_hdrc_host_destroy(ci); 871 if (ci->is_otg) 872 ci_hdrc_otg_destroy(ci); 873 } 874 875 static void ci_get_otg_capable(struct ci_hdrc *ci) 876 { 877 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG) 878 ci->is_otg = false; 879 else 880 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS, 881 DCCPARAMS_DC | DCCPARAMS_HC) 882 == (DCCPARAMS_DC | DCCPARAMS_HC)); 883 if (ci->is_otg) { 884 dev_dbg(ci->dev, "It is OTG capable controller\n"); 885 /* Disable and clear all OTG irq */ 886 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS, 887 OTGSC_INT_STATUS_BITS); 888 } 889 } 890 891 static int ci_hdrc_probe(struct platform_device *pdev) 892 { 893 struct device *dev = &pdev->dev; 894 struct ci_hdrc *ci; 895 struct resource *res; 896 void __iomem *base; 897 int ret; 898 enum usb_dr_mode dr_mode; 899 900 if (!dev_get_platdata(dev)) { 901 dev_err(dev, "platform data missing\n"); 902 return -ENODEV; 903 } 904 905 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 906 base = devm_ioremap_resource(dev, res); 907 if (IS_ERR(base)) 908 return PTR_ERR(base); 909 910 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL); 911 if (!ci) 912 return -ENOMEM; 913 914 ci->dev = dev; 915 ci->platdata = dev_get_platdata(dev); 916 ci->imx28_write_fix = !!(ci->platdata->flags & 917 CI_HDRC_IMX28_WRITE_FIX); 918 ci->supports_runtime_pm = !!(ci->platdata->flags & 919 CI_HDRC_SUPPORTS_RUNTIME_PM); 920 921 ret = hw_device_init(ci, base); 922 if (ret < 0) { 923 dev_err(dev, "can't initialize hardware\n"); 924 return -ENODEV; 925 } 926 927 if (ci->platdata->phy) { 928 ci->phy = ci->platdata->phy; 929 } else if (ci->platdata->usb_phy) { 930 ci->usb_phy = ci->platdata->usb_phy; 931 } else { 932 ci->phy = devm_phy_get(dev->parent, "usb-phy"); 933 ci->usb_phy = devm_usb_get_phy(dev->parent, USB_PHY_TYPE_USB2); 934 935 /* if both generic PHY and USB PHY layers aren't enabled */ 936 if (PTR_ERR(ci->phy) == -ENOSYS && 937 PTR_ERR(ci->usb_phy) == -ENXIO) 938 return -ENXIO; 939 940 if (IS_ERR(ci->phy) && IS_ERR(ci->usb_phy)) 941 return -EPROBE_DEFER; 942 943 if (IS_ERR(ci->phy)) 944 ci->phy = NULL; 945 else if (IS_ERR(ci->usb_phy)) 946 ci->usb_phy = NULL; 947 } 948 949 ret = ci_usb_phy_init(ci); 950 if (ret) { 951 dev_err(dev, "unable to init phy: %d\n", ret); 952 return ret; 953 } 954 955 ci->hw_bank.phys = res->start; 956 957 ci->irq = platform_get_irq(pdev, 0); 958 if (ci->irq < 0) { 959 dev_err(dev, "missing IRQ\n"); 960 ret = ci->irq; 961 goto deinit_phy; 962 } 963 964 ci_get_otg_capable(ci); 965 966 dr_mode = ci->platdata->dr_mode; 967 /* initialize role(s) before the interrupt is requested */ 968 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) { 969 ret = ci_hdrc_host_init(ci); 970 if (ret) 971 dev_info(dev, "doesn't support host\n"); 972 } 973 974 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) { 975 ret = ci_hdrc_gadget_init(ci); 976 if (ret) 977 dev_info(dev, "doesn't support gadget\n"); 978 } 979 980 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) { 981 dev_err(dev, "no supported roles\n"); 982 ret = -ENODEV; 983 goto deinit_phy; 984 } 985 986 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) { 987 ret = ci_hdrc_otg_init(ci); 988 if (ret) { 989 dev_err(dev, "init otg fails, ret = %d\n", ret); 990 goto stop; 991 } 992 } 993 994 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) { 995 if (ci->is_otg) { 996 ci->role = ci_otg_role(ci); 997 /* Enable ID change irq */ 998 hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE); 999 } else { 1000 /* 1001 * If the controller is not OTG capable, but support 1002 * role switch, the defalt role is gadget, and the 1003 * user can switch it through debugfs. 1004 */ 1005 ci->role = CI_ROLE_GADGET; 1006 } 1007 } else { 1008 ci->role = ci->roles[CI_ROLE_HOST] 1009 ? CI_ROLE_HOST 1010 : CI_ROLE_GADGET; 1011 } 1012 1013 if (!ci_otg_is_fsm_mode(ci)) { 1014 /* only update vbus status for peripheral */ 1015 if (ci->role == CI_ROLE_GADGET) 1016 ci_handle_vbus_change(ci); 1017 1018 ret = ci_role_start(ci, ci->role); 1019 if (ret) { 1020 dev_err(dev, "can't start %s role\n", 1021 ci_role(ci)->name); 1022 goto stop; 1023 } 1024 } 1025 1026 platform_set_drvdata(pdev, ci); 1027 ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED, 1028 ci->platdata->name, ci); 1029 if (ret) 1030 goto stop; 1031 1032 ret = ci_extcon_register(ci); 1033 if (ret) 1034 goto stop; 1035 1036 if (ci->supports_runtime_pm) { 1037 pm_runtime_set_active(&pdev->dev); 1038 pm_runtime_enable(&pdev->dev); 1039 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000); 1040 pm_runtime_mark_last_busy(ci->dev); 1041 pm_runtime_use_autosuspend(&pdev->dev); 1042 } 1043 1044 if (ci_otg_is_fsm_mode(ci)) 1045 ci_hdrc_otg_fsm_start(ci); 1046 1047 device_set_wakeup_capable(&pdev->dev, true); 1048 1049 ret = dbg_create_files(ci); 1050 if (!ret) 1051 return 0; 1052 1053 ci_extcon_unregister(ci); 1054 stop: 1055 ci_role_destroy(ci); 1056 deinit_phy: 1057 ci_usb_phy_exit(ci); 1058 1059 return ret; 1060 } 1061 1062 static int ci_hdrc_remove(struct platform_device *pdev) 1063 { 1064 struct ci_hdrc *ci = platform_get_drvdata(pdev); 1065 1066 if (ci->supports_runtime_pm) { 1067 pm_runtime_get_sync(&pdev->dev); 1068 pm_runtime_disable(&pdev->dev); 1069 pm_runtime_put_noidle(&pdev->dev); 1070 } 1071 1072 dbg_remove_files(ci); 1073 ci_extcon_unregister(ci); 1074 ci_role_destroy(ci); 1075 ci_hdrc_enter_lpm(ci, true); 1076 ci_usb_phy_exit(ci); 1077 1078 return 0; 1079 } 1080 1081 #ifdef CONFIG_PM 1082 /* Prepare wakeup by SRP before suspend */ 1083 static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci) 1084 { 1085 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) && 1086 !hw_read_otgsc(ci, OTGSC_ID)) { 1087 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP, 1088 PORTSC_PP); 1089 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN, 1090 PORTSC_WKCN); 1091 } 1092 } 1093 1094 /* Handle SRP when wakeup by data pulse */ 1095 static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci) 1096 { 1097 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) && 1098 (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) { 1099 if (!hw_read_otgsc(ci, OTGSC_ID)) { 1100 ci->fsm.a_srp_det = 1; 1101 ci->fsm.a_bus_drop = 0; 1102 } else { 1103 ci->fsm.id = 1; 1104 } 1105 ci_otg_queue_work(ci); 1106 } 1107 } 1108 1109 static void ci_controller_suspend(struct ci_hdrc *ci) 1110 { 1111 disable_irq(ci->irq); 1112 ci_hdrc_enter_lpm(ci, true); 1113 if (ci->platdata->phy_clkgate_delay_us) 1114 usleep_range(ci->platdata->phy_clkgate_delay_us, 1115 ci->platdata->phy_clkgate_delay_us + 50); 1116 usb_phy_set_suspend(ci->usb_phy, 1); 1117 ci->in_lpm = true; 1118 enable_irq(ci->irq); 1119 } 1120 1121 static int ci_controller_resume(struct device *dev) 1122 { 1123 struct ci_hdrc *ci = dev_get_drvdata(dev); 1124 1125 dev_dbg(dev, "at %s\n", __func__); 1126 1127 if (!ci->in_lpm) { 1128 WARN_ON(1); 1129 return 0; 1130 } 1131 1132 ci_hdrc_enter_lpm(ci, false); 1133 if (ci->usb_phy) { 1134 usb_phy_set_suspend(ci->usb_phy, 0); 1135 usb_phy_set_wakeup(ci->usb_phy, false); 1136 hw_wait_phy_stable(); 1137 } 1138 1139 ci->in_lpm = false; 1140 if (ci->wakeup_int) { 1141 ci->wakeup_int = false; 1142 pm_runtime_mark_last_busy(ci->dev); 1143 pm_runtime_put_autosuspend(ci->dev); 1144 enable_irq(ci->irq); 1145 if (ci_otg_is_fsm_mode(ci)) 1146 ci_otg_fsm_wakeup_by_srp(ci); 1147 } 1148 1149 return 0; 1150 } 1151 1152 #ifdef CONFIG_PM_SLEEP 1153 static int ci_suspend(struct device *dev) 1154 { 1155 struct ci_hdrc *ci = dev_get_drvdata(dev); 1156 1157 if (ci->wq) 1158 flush_workqueue(ci->wq); 1159 /* 1160 * Controller needs to be active during suspend, otherwise the core 1161 * may run resume when the parent is at suspend if other driver's 1162 * suspend fails, it occurs before parent's suspend has not started, 1163 * but the core suspend has finished. 1164 */ 1165 if (ci->in_lpm) 1166 pm_runtime_resume(dev); 1167 1168 if (ci->in_lpm) { 1169 WARN_ON(1); 1170 return 0; 1171 } 1172 1173 if (device_may_wakeup(dev)) { 1174 if (ci_otg_is_fsm_mode(ci)) 1175 ci_otg_fsm_suspend_for_srp(ci); 1176 1177 usb_phy_set_wakeup(ci->usb_phy, true); 1178 enable_irq_wake(ci->irq); 1179 } 1180 1181 ci_controller_suspend(ci); 1182 1183 return 0; 1184 } 1185 1186 static int ci_resume(struct device *dev) 1187 { 1188 struct ci_hdrc *ci = dev_get_drvdata(dev); 1189 int ret; 1190 1191 if (device_may_wakeup(dev)) 1192 disable_irq_wake(ci->irq); 1193 1194 ret = ci_controller_resume(dev); 1195 if (ret) 1196 return ret; 1197 1198 if (ci->supports_runtime_pm) { 1199 pm_runtime_disable(dev); 1200 pm_runtime_set_active(dev); 1201 pm_runtime_enable(dev); 1202 } 1203 1204 return ret; 1205 } 1206 #endif /* CONFIG_PM_SLEEP */ 1207 1208 static int ci_runtime_suspend(struct device *dev) 1209 { 1210 struct ci_hdrc *ci = dev_get_drvdata(dev); 1211 1212 dev_dbg(dev, "at %s\n", __func__); 1213 1214 if (ci->in_lpm) { 1215 WARN_ON(1); 1216 return 0; 1217 } 1218 1219 if (ci_otg_is_fsm_mode(ci)) 1220 ci_otg_fsm_suspend_for_srp(ci); 1221 1222 usb_phy_set_wakeup(ci->usb_phy, true); 1223 ci_controller_suspend(ci); 1224 1225 return 0; 1226 } 1227 1228 static int ci_runtime_resume(struct device *dev) 1229 { 1230 return ci_controller_resume(dev); 1231 } 1232 1233 #endif /* CONFIG_PM */ 1234 static const struct dev_pm_ops ci_pm_ops = { 1235 SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume) 1236 SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL) 1237 }; 1238 1239 static struct platform_driver ci_hdrc_driver = { 1240 .probe = ci_hdrc_probe, 1241 .remove = ci_hdrc_remove, 1242 .driver = { 1243 .name = "ci_hdrc", 1244 .pm = &ci_pm_ops, 1245 }, 1246 }; 1247 1248 static int __init ci_hdrc_platform_register(void) 1249 { 1250 ci_hdrc_host_driver_init(); 1251 return platform_driver_register(&ci_hdrc_driver); 1252 } 1253 module_init(ci_hdrc_platform_register); 1254 1255 static void __exit ci_hdrc_platform_unregister(void) 1256 { 1257 platform_driver_unregister(&ci_hdrc_driver); 1258 } 1259 module_exit(ci_hdrc_platform_unregister); 1260 1261 MODULE_ALIAS("platform:ci_hdrc"); 1262 MODULE_LICENSE("GPL v2"); 1263 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>"); 1264 MODULE_DESCRIPTION("ChipIdea HDRC Driver"); 1265