1 /* 2 * core.c - ChipIdea USB IP core family device controller 3 * 4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. 5 * 6 * Author: David Lopo 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 /* 14 * Description: ChipIdea USB IP core family device controller 15 * 16 * This driver is composed of several blocks: 17 * - HW: hardware interface 18 * - DBG: debug facilities (optional) 19 * - UTIL: utilities 20 * - ISR: interrupts handling 21 * - ENDPT: endpoint operations (Gadget API) 22 * - GADGET: gadget operations (Gadget API) 23 * - BUS: bus glue code, bus abstraction layer 24 * 25 * Compile Options 26 * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities 27 * - STALL_IN: non-empty bulk-in pipes cannot be halted 28 * if defined mass storage compliance succeeds but with warnings 29 * => case 4: Hi > Dn 30 * => case 5: Hi > Di 31 * => case 8: Hi <> Do 32 * if undefined usbtest 13 fails 33 * - TRACE: enable function tracing (depends on DEBUG) 34 * 35 * Main Features 36 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage 37 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined) 38 * - Normal & LPM support 39 * 40 * USBTEST Report 41 * - OK: 0-12, 13 (STALL_IN defined) & 14 42 * - Not Supported: 15 & 16 (ISO) 43 * 44 * TODO List 45 * - OTG 46 * - Isochronous & Interrupt Traffic 47 * - Handle requests which spawns into several TDs 48 * - GET_STATUS(device) - always reports 0 49 * - Gadget API (majority of optional features) 50 * - Suspend & Remote Wakeup 51 */ 52 #include <linux/delay.h> 53 #include <linux/device.h> 54 #include <linux/dmapool.h> 55 #include <linux/dma-mapping.h> 56 #include <linux/init.h> 57 #include <linux/platform_device.h> 58 #include <linux/module.h> 59 #include <linux/idr.h> 60 #include <linux/interrupt.h> 61 #include <linux/io.h> 62 #include <linux/irq.h> 63 #include <linux/kernel.h> 64 #include <linux/slab.h> 65 #include <linux/pm_runtime.h> 66 #include <linux/usb/ch9.h> 67 #include <linux/usb/gadget.h> 68 #include <linux/usb/otg.h> 69 #include <linux/usb/chipidea.h> 70 71 #include "ci.h" 72 #include "udc.h" 73 #include "bits.h" 74 #include "host.h" 75 #include "debug.h" 76 77 /* Controller register map */ 78 static uintptr_t ci_regs_nolpm[] = { 79 [CAP_CAPLENGTH] = 0x000UL, 80 [CAP_HCCPARAMS] = 0x008UL, 81 [CAP_DCCPARAMS] = 0x024UL, 82 [CAP_TESTMODE] = 0x038UL, 83 [OP_USBCMD] = 0x000UL, 84 [OP_USBSTS] = 0x004UL, 85 [OP_USBINTR] = 0x008UL, 86 [OP_DEVICEADDR] = 0x014UL, 87 [OP_ENDPTLISTADDR] = 0x018UL, 88 [OP_PORTSC] = 0x044UL, 89 [OP_DEVLC] = 0x084UL, 90 [OP_OTGSC] = 0x064UL, 91 [OP_USBMODE] = 0x068UL, 92 [OP_ENDPTSETUPSTAT] = 0x06CUL, 93 [OP_ENDPTPRIME] = 0x070UL, 94 [OP_ENDPTFLUSH] = 0x074UL, 95 [OP_ENDPTSTAT] = 0x078UL, 96 [OP_ENDPTCOMPLETE] = 0x07CUL, 97 [OP_ENDPTCTRL] = 0x080UL, 98 }; 99 100 static uintptr_t ci_regs_lpm[] = { 101 [CAP_CAPLENGTH] = 0x000UL, 102 [CAP_HCCPARAMS] = 0x008UL, 103 [CAP_DCCPARAMS] = 0x024UL, 104 [CAP_TESTMODE] = 0x0FCUL, 105 [OP_USBCMD] = 0x000UL, 106 [OP_USBSTS] = 0x004UL, 107 [OP_USBINTR] = 0x008UL, 108 [OP_DEVICEADDR] = 0x014UL, 109 [OP_ENDPTLISTADDR] = 0x018UL, 110 [OP_PORTSC] = 0x044UL, 111 [OP_DEVLC] = 0x084UL, 112 [OP_OTGSC] = 0x0C4UL, 113 [OP_USBMODE] = 0x0C8UL, 114 [OP_ENDPTSETUPSTAT] = 0x0D8UL, 115 [OP_ENDPTPRIME] = 0x0DCUL, 116 [OP_ENDPTFLUSH] = 0x0E0UL, 117 [OP_ENDPTSTAT] = 0x0E4UL, 118 [OP_ENDPTCOMPLETE] = 0x0E8UL, 119 [OP_ENDPTCTRL] = 0x0ECUL, 120 }; 121 122 static int hw_alloc_regmap(struct ci13xxx *ci, bool is_lpm) 123 { 124 int i; 125 126 kfree(ci->hw_bank.regmap); 127 128 ci->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *), 129 GFP_KERNEL); 130 if (!ci->hw_bank.regmap) 131 return -ENOMEM; 132 133 for (i = 0; i < OP_ENDPTCTRL; i++) 134 ci->hw_bank.regmap[i] = 135 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) + 136 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]); 137 138 for (; i <= OP_LAST; i++) 139 ci->hw_bank.regmap[i] = ci->hw_bank.op + 140 4 * (i - OP_ENDPTCTRL) + 141 (is_lpm 142 ? ci_regs_lpm[OP_ENDPTCTRL] 143 : ci_regs_nolpm[OP_ENDPTCTRL]); 144 145 return 0; 146 } 147 148 /** 149 * hw_port_test_set: writes port test mode (execute without interruption) 150 * @mode: new value 151 * 152 * This function returns an error code 153 */ 154 int hw_port_test_set(struct ci13xxx *ci, u8 mode) 155 { 156 const u8 TEST_MODE_MAX = 7; 157 158 if (mode > TEST_MODE_MAX) 159 return -EINVAL; 160 161 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << ffs_nr(PORTSC_PTC)); 162 return 0; 163 } 164 165 /** 166 * hw_port_test_get: reads port test mode value 167 * 168 * This function returns port test mode value 169 */ 170 u8 hw_port_test_get(struct ci13xxx *ci) 171 { 172 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> ffs_nr(PORTSC_PTC); 173 } 174 175 static int hw_device_init(struct ci13xxx *ci, void __iomem *base) 176 { 177 u32 reg; 178 179 /* bank is a module variable */ 180 ci->hw_bank.abs = base; 181 182 ci->hw_bank.cap = ci->hw_bank.abs; 183 ci->hw_bank.cap += ci->platdata->capoffset; 184 ci->hw_bank.op = ci->hw_bank.cap + ioread8(ci->hw_bank.cap); 185 186 hw_alloc_regmap(ci, false); 187 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >> 188 ffs_nr(HCCPARAMS_LEN); 189 ci->hw_bank.lpm = reg; 190 hw_alloc_regmap(ci, !!reg); 191 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs; 192 ci->hw_bank.size += OP_LAST; 193 ci->hw_bank.size /= sizeof(u32); 194 195 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >> 196 ffs_nr(DCCPARAMS_DEN); 197 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */ 198 199 if (ci->hw_ep_max > ENDPT_MAX) 200 return -ENODEV; 201 202 dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n", 203 ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op); 204 205 /* setup lock mode ? */ 206 207 /* ENDPTSETUPSTAT is '0' by default */ 208 209 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */ 210 211 return 0; 212 } 213 214 /** 215 * hw_device_reset: resets chip (execute without interruption) 216 * @ci: the controller 217 * 218 * This function returns an error code 219 */ 220 int hw_device_reset(struct ci13xxx *ci, u32 mode) 221 { 222 /* should flush & stop before reset */ 223 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0); 224 hw_write(ci, OP_USBCMD, USBCMD_RS, 0); 225 226 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST); 227 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) 228 udelay(10); /* not RTOS friendly */ 229 230 231 if (ci->platdata->notify_event) 232 ci->platdata->notify_event(ci, 233 CI13XXX_CONTROLLER_RESET_EVENT); 234 235 if (ci->platdata->flags & CI13XXX_DISABLE_STREAMING) 236 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS); 237 238 /* USBMODE should be configured step by step */ 239 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE); 240 hw_write(ci, OP_USBMODE, USBMODE_CM, mode); 241 /* HW >= 2.3 */ 242 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); 243 244 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) { 245 pr_err("cannot enter in %s mode", ci_role(ci)->name); 246 pr_err("lpm = %i", ci->hw_bank.lpm); 247 return -ENODEV; 248 } 249 250 return 0; 251 } 252 253 /** 254 * ci_otg_role - pick role based on ID pin state 255 * @ci: the controller 256 */ 257 static enum ci_role ci_otg_role(struct ci13xxx *ci) 258 { 259 u32 sts = hw_read(ci, OP_OTGSC, ~0); 260 enum ci_role role = sts & OTGSC_ID 261 ? CI_ROLE_GADGET 262 : CI_ROLE_HOST; 263 264 return role; 265 } 266 267 /** 268 * ci_role_work - perform role changing based on ID pin 269 * @work: work struct 270 */ 271 static void ci_role_work(struct work_struct *work) 272 { 273 struct ci13xxx *ci = container_of(work, struct ci13xxx, work); 274 enum ci_role role = ci_otg_role(ci); 275 276 if (role != ci->role) { 277 dev_dbg(ci->dev, "switching from %s to %s\n", 278 ci_role(ci)->name, ci->roles[role]->name); 279 280 ci_role_stop(ci); 281 ci_role_start(ci, role); 282 enable_irq(ci->irq); 283 } 284 } 285 286 static ssize_t show_role(struct device *dev, struct device_attribute *attr, 287 char *buf) 288 { 289 struct ci13xxx *ci = dev_get_drvdata(dev); 290 291 return sprintf(buf, "%s\n", ci_role(ci)->name); 292 } 293 294 static ssize_t store_role(struct device *dev, struct device_attribute *attr, 295 const char *buf, size_t count) 296 { 297 struct ci13xxx *ci = dev_get_drvdata(dev); 298 enum ci_role role; 299 int ret; 300 301 for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++) 302 if (ci->roles[role] && !strcmp(buf, ci->roles[role]->name)) 303 break; 304 305 if (role == CI_ROLE_END || role == ci->role) 306 return -EINVAL; 307 308 ci_role_stop(ci); 309 ret = ci_role_start(ci, role); 310 if (ret) 311 return ret; 312 313 return count; 314 } 315 316 static DEVICE_ATTR(role, S_IRUSR | S_IWUSR, show_role, store_role); 317 318 static irqreturn_t ci_irq(int irq, void *data) 319 { 320 struct ci13xxx *ci = data; 321 irqreturn_t ret = IRQ_NONE; 322 u32 otgsc = 0; 323 324 if (ci->is_otg) 325 otgsc = hw_read(ci, OP_OTGSC, ~0); 326 327 if (ci->role != CI_ROLE_END) 328 ret = ci_role(ci)->irq(ci); 329 330 if (ci->is_otg && (otgsc & OTGSC_IDIS)) { 331 hw_write(ci, OP_OTGSC, OTGSC_IDIS, OTGSC_IDIS); 332 disable_irq_nosync(ci->irq); 333 queue_work(ci->wq, &ci->work); 334 ret = IRQ_HANDLED; 335 } 336 337 return ret; 338 } 339 340 static DEFINE_IDA(ci_ida); 341 342 struct platform_device *ci13xxx_add_device(struct device *dev, 343 struct resource *res, int nres, 344 struct ci13xxx_platform_data *platdata) 345 { 346 struct platform_device *pdev; 347 int id, ret; 348 349 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL); 350 if (id < 0) 351 return ERR_PTR(id); 352 353 pdev = platform_device_alloc("ci_hdrc", id); 354 if (!pdev) { 355 ret = -ENOMEM; 356 goto put_id; 357 } 358 359 pdev->dev.parent = dev; 360 pdev->dev.dma_mask = dev->dma_mask; 361 pdev->dev.dma_parms = dev->dma_parms; 362 dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask); 363 364 ret = platform_device_add_resources(pdev, res, nres); 365 if (ret) 366 goto err; 367 368 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata)); 369 if (ret) 370 goto err; 371 372 ret = platform_device_add(pdev); 373 if (ret) 374 goto err; 375 376 return pdev; 377 378 err: 379 platform_device_put(pdev); 380 put_id: 381 ida_simple_remove(&ci_ida, id); 382 return ERR_PTR(ret); 383 } 384 EXPORT_SYMBOL_GPL(ci13xxx_add_device); 385 386 void ci13xxx_remove_device(struct platform_device *pdev) 387 { 388 int id = pdev->id; 389 platform_device_unregister(pdev); 390 ida_simple_remove(&ci_ida, id); 391 } 392 EXPORT_SYMBOL_GPL(ci13xxx_remove_device); 393 394 static int ci_hdrc_probe(struct platform_device *pdev) 395 { 396 struct device *dev = &pdev->dev; 397 struct ci13xxx *ci; 398 struct resource *res; 399 void __iomem *base; 400 int ret; 401 402 if (!dev->platform_data) { 403 dev_err(dev, "platform data missing\n"); 404 return -ENODEV; 405 } 406 407 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 408 if (!res) { 409 dev_err(dev, "missing resource\n"); 410 return -ENODEV; 411 } 412 413 base = devm_request_and_ioremap(dev, res); 414 if (!res) { 415 dev_err(dev, "can't request and ioremap resource\n"); 416 return -ENOMEM; 417 } 418 419 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL); 420 if (!ci) { 421 dev_err(dev, "can't allocate device\n"); 422 return -ENOMEM; 423 } 424 425 ci->dev = dev; 426 ci->platdata = dev->platform_data; 427 if (ci->platdata->phy) 428 ci->transceiver = ci->platdata->phy; 429 else 430 ci->global_phy = true; 431 432 ret = hw_device_init(ci, base); 433 if (ret < 0) { 434 dev_err(dev, "can't initialize hardware\n"); 435 return -ENODEV; 436 } 437 438 ci->hw_bank.phys = res->start; 439 440 ci->irq = platform_get_irq(pdev, 0); 441 if (ci->irq < 0) { 442 dev_err(dev, "missing IRQ\n"); 443 return -ENODEV; 444 } 445 446 INIT_WORK(&ci->work, ci_role_work); 447 ci->wq = create_singlethread_workqueue("ci_otg"); 448 if (!ci->wq) { 449 dev_err(dev, "can't create workqueue\n"); 450 return -ENODEV; 451 } 452 453 /* initialize role(s) before the interrupt is requested */ 454 ret = ci_hdrc_host_init(ci); 455 if (ret) 456 dev_info(dev, "doesn't support host\n"); 457 458 ret = ci_hdrc_gadget_init(ci); 459 if (ret) 460 dev_info(dev, "doesn't support gadget\n"); 461 462 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) { 463 dev_err(dev, "no supported roles\n"); 464 ret = -ENODEV; 465 goto rm_wq; 466 } 467 468 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) { 469 ci->is_otg = true; 470 /* ID pin needs 1ms debouce time, we delay 2ms for safe */ 471 mdelay(2); 472 ci->role = ci_otg_role(ci); 473 } else { 474 ci->role = ci->roles[CI_ROLE_HOST] 475 ? CI_ROLE_HOST 476 : CI_ROLE_GADGET; 477 } 478 479 ret = ci_role_start(ci, ci->role); 480 if (ret) { 481 dev_err(dev, "can't start %s role\n", ci_role(ci)->name); 482 ret = -ENODEV; 483 goto rm_wq; 484 } 485 486 platform_set_drvdata(pdev, ci); 487 ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name, 488 ci); 489 if (ret) 490 goto stop; 491 492 ret = device_create_file(dev, &dev_attr_role); 493 if (ret) 494 goto rm_attr; 495 496 if (ci->is_otg) 497 hw_write(ci, OP_OTGSC, OTGSC_IDIE, OTGSC_IDIE); 498 499 return ret; 500 501 rm_attr: 502 device_remove_file(dev, &dev_attr_role); 503 stop: 504 ci_role_stop(ci); 505 rm_wq: 506 flush_workqueue(ci->wq); 507 destroy_workqueue(ci->wq); 508 509 return ret; 510 } 511 512 static int ci_hdrc_remove(struct platform_device *pdev) 513 { 514 struct ci13xxx *ci = platform_get_drvdata(pdev); 515 516 flush_workqueue(ci->wq); 517 destroy_workqueue(ci->wq); 518 device_remove_file(ci->dev, &dev_attr_role); 519 free_irq(ci->irq, ci); 520 ci_role_stop(ci); 521 522 return 0; 523 } 524 525 static struct platform_driver ci_hdrc_driver = { 526 .probe = ci_hdrc_probe, 527 .remove = ci_hdrc_remove, 528 .driver = { 529 .name = "ci_hdrc", 530 }, 531 }; 532 533 module_platform_driver(ci_hdrc_driver); 534 535 MODULE_ALIAS("platform:ci_hdrc"); 536 MODULE_ALIAS("platform:ci13xxx"); 537 MODULE_LICENSE("GPL v2"); 538 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>"); 539 MODULE_DESCRIPTION("ChipIdea HDRC Driver"); 540