1 /* 2 * core.c - ChipIdea USB IP core family device controller 3 * 4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. 5 * 6 * Author: David Lopo 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 /* 14 * Description: ChipIdea USB IP core family device controller 15 * 16 * This driver is composed of several blocks: 17 * - HW: hardware interface 18 * - DBG: debug facilities (optional) 19 * - UTIL: utilities 20 * - ISR: interrupts handling 21 * - ENDPT: endpoint operations (Gadget API) 22 * - GADGET: gadget operations (Gadget API) 23 * - BUS: bus glue code, bus abstraction layer 24 * 25 * Compile Options 26 * - CONFIG_USB_CHIPIDEA_DEBUG: enable debug facilities 27 * - STALL_IN: non-empty bulk-in pipes cannot be halted 28 * if defined mass storage compliance succeeds but with warnings 29 * => case 4: Hi > Dn 30 * => case 5: Hi > Di 31 * => case 8: Hi <> Do 32 * if undefined usbtest 13 fails 33 * - TRACE: enable function tracing (depends on DEBUG) 34 * 35 * Main Features 36 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage 37 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined) 38 * - Normal & LPM support 39 * 40 * USBTEST Report 41 * - OK: 0-12, 13 (STALL_IN defined) & 14 42 * - Not Supported: 15 & 16 (ISO) 43 * 44 * TODO List 45 * - Suspend & Remote Wakeup 46 */ 47 #include <linux/delay.h> 48 #include <linux/device.h> 49 #include <linux/dma-mapping.h> 50 #include <linux/platform_device.h> 51 #include <linux/module.h> 52 #include <linux/idr.h> 53 #include <linux/interrupt.h> 54 #include <linux/io.h> 55 #include <linux/kernel.h> 56 #include <linux/slab.h> 57 #include <linux/pm_runtime.h> 58 #include <linux/usb/ch9.h> 59 #include <linux/usb/gadget.h> 60 #include <linux/usb/otg.h> 61 #include <linux/usb/chipidea.h> 62 #include <linux/usb/of.h> 63 #include <linux/of.h> 64 #include <linux/phy.h> 65 #include <linux/regulator/consumer.h> 66 67 #include "ci.h" 68 #include "udc.h" 69 #include "bits.h" 70 #include "host.h" 71 #include "debug.h" 72 #include "otg.h" 73 #include "otg_fsm.h" 74 75 /* Controller register map */ 76 static const u8 ci_regs_nolpm[] = { 77 [CAP_CAPLENGTH] = 0x00U, 78 [CAP_HCCPARAMS] = 0x08U, 79 [CAP_DCCPARAMS] = 0x24U, 80 [CAP_TESTMODE] = 0x38U, 81 [OP_USBCMD] = 0x00U, 82 [OP_USBSTS] = 0x04U, 83 [OP_USBINTR] = 0x08U, 84 [OP_DEVICEADDR] = 0x14U, 85 [OP_ENDPTLISTADDR] = 0x18U, 86 [OP_PORTSC] = 0x44U, 87 [OP_DEVLC] = 0x84U, 88 [OP_OTGSC] = 0x64U, 89 [OP_USBMODE] = 0x68U, 90 [OP_ENDPTSETUPSTAT] = 0x6CU, 91 [OP_ENDPTPRIME] = 0x70U, 92 [OP_ENDPTFLUSH] = 0x74U, 93 [OP_ENDPTSTAT] = 0x78U, 94 [OP_ENDPTCOMPLETE] = 0x7CU, 95 [OP_ENDPTCTRL] = 0x80U, 96 }; 97 98 static const u8 ci_regs_lpm[] = { 99 [CAP_CAPLENGTH] = 0x00U, 100 [CAP_HCCPARAMS] = 0x08U, 101 [CAP_DCCPARAMS] = 0x24U, 102 [CAP_TESTMODE] = 0xFCU, 103 [OP_USBCMD] = 0x00U, 104 [OP_USBSTS] = 0x04U, 105 [OP_USBINTR] = 0x08U, 106 [OP_DEVICEADDR] = 0x14U, 107 [OP_ENDPTLISTADDR] = 0x18U, 108 [OP_PORTSC] = 0x44U, 109 [OP_DEVLC] = 0x84U, 110 [OP_OTGSC] = 0xC4U, 111 [OP_USBMODE] = 0xC8U, 112 [OP_ENDPTSETUPSTAT] = 0xD8U, 113 [OP_ENDPTPRIME] = 0xDCU, 114 [OP_ENDPTFLUSH] = 0xE0U, 115 [OP_ENDPTSTAT] = 0xE4U, 116 [OP_ENDPTCOMPLETE] = 0xE8U, 117 [OP_ENDPTCTRL] = 0xECU, 118 }; 119 120 static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm) 121 { 122 int i; 123 124 for (i = 0; i < OP_ENDPTCTRL; i++) 125 ci->hw_bank.regmap[i] = 126 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) + 127 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]); 128 129 for (; i <= OP_LAST; i++) 130 ci->hw_bank.regmap[i] = ci->hw_bank.op + 131 4 * (i - OP_ENDPTCTRL) + 132 (is_lpm 133 ? ci_regs_lpm[OP_ENDPTCTRL] 134 : ci_regs_nolpm[OP_ENDPTCTRL]); 135 136 return 0; 137 } 138 139 /** 140 * hw_read_intr_enable: returns interrupt enable register 141 * 142 * @ci: the controller 143 * 144 * This function returns register data 145 */ 146 u32 hw_read_intr_enable(struct ci_hdrc *ci) 147 { 148 return hw_read(ci, OP_USBINTR, ~0); 149 } 150 151 /** 152 * hw_read_intr_status: returns interrupt status register 153 * 154 * @ci: the controller 155 * 156 * This function returns register data 157 */ 158 u32 hw_read_intr_status(struct ci_hdrc *ci) 159 { 160 return hw_read(ci, OP_USBSTS, ~0); 161 } 162 163 /** 164 * hw_port_test_set: writes port test mode (execute without interruption) 165 * @mode: new value 166 * 167 * This function returns an error code 168 */ 169 int hw_port_test_set(struct ci_hdrc *ci, u8 mode) 170 { 171 const u8 TEST_MODE_MAX = 7; 172 173 if (mode > TEST_MODE_MAX) 174 return -EINVAL; 175 176 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC)); 177 return 0; 178 } 179 180 /** 181 * hw_port_test_get: reads port test mode value 182 * 183 * @ci: the controller 184 * 185 * This function returns port test mode value 186 */ 187 u8 hw_port_test_get(struct ci_hdrc *ci) 188 { 189 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC); 190 } 191 192 /* The PHY enters/leaves low power mode */ 193 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable) 194 { 195 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC; 196 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm))); 197 198 if (enable && !lpm) { 199 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), 200 PORTSC_PHCD(ci->hw_bank.lpm)); 201 } else if (!enable && lpm) { 202 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), 203 0); 204 /* 205 * the PHY needs some time (less 206 * than 1ms) to leave low power mode. 207 */ 208 usleep_range(1000, 1100); 209 } 210 } 211 212 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base) 213 { 214 u32 reg; 215 216 /* bank is a module variable */ 217 ci->hw_bank.abs = base; 218 219 ci->hw_bank.cap = ci->hw_bank.abs; 220 ci->hw_bank.cap += ci->platdata->capoffset; 221 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff); 222 223 hw_alloc_regmap(ci, false); 224 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >> 225 __ffs(HCCPARAMS_LEN); 226 ci->hw_bank.lpm = reg; 227 if (reg) 228 hw_alloc_regmap(ci, !!reg); 229 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs; 230 ci->hw_bank.size += OP_LAST; 231 ci->hw_bank.size /= sizeof(u32); 232 233 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >> 234 __ffs(DCCPARAMS_DEN); 235 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */ 236 237 if (ci->hw_ep_max > ENDPT_MAX) 238 return -ENODEV; 239 240 ci_hdrc_enter_lpm(ci, false); 241 242 /* Disable all interrupts bits */ 243 hw_write(ci, OP_USBINTR, 0xffffffff, 0); 244 245 /* Clear all interrupts status bits*/ 246 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff); 247 248 dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n", 249 ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op); 250 251 /* setup lock mode ? */ 252 253 /* ENDPTSETUPSTAT is '0' by default */ 254 255 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */ 256 257 return 0; 258 } 259 260 static void hw_phymode_configure(struct ci_hdrc *ci) 261 { 262 u32 portsc, lpm, sts = 0; 263 264 switch (ci->platdata->phy_mode) { 265 case USBPHY_INTERFACE_MODE_UTMI: 266 portsc = PORTSC_PTS(PTS_UTMI); 267 lpm = DEVLC_PTS(PTS_UTMI); 268 break; 269 case USBPHY_INTERFACE_MODE_UTMIW: 270 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW; 271 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW; 272 break; 273 case USBPHY_INTERFACE_MODE_ULPI: 274 portsc = PORTSC_PTS(PTS_ULPI); 275 lpm = DEVLC_PTS(PTS_ULPI); 276 break; 277 case USBPHY_INTERFACE_MODE_SERIAL: 278 portsc = PORTSC_PTS(PTS_SERIAL); 279 lpm = DEVLC_PTS(PTS_SERIAL); 280 sts = 1; 281 break; 282 case USBPHY_INTERFACE_MODE_HSIC: 283 portsc = PORTSC_PTS(PTS_HSIC); 284 lpm = DEVLC_PTS(PTS_HSIC); 285 break; 286 default: 287 return; 288 } 289 290 if (ci->hw_bank.lpm) { 291 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm); 292 if (sts) 293 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS); 294 } else { 295 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc); 296 if (sts) 297 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS); 298 } 299 } 300 301 /** 302 * ci_usb_phy_init: initialize phy according to different phy type 303 * @ci: the controller 304 * 305 * This function returns an error code if usb_phy_init has failed 306 */ 307 static int ci_usb_phy_init(struct ci_hdrc *ci) 308 { 309 int ret; 310 311 switch (ci->platdata->phy_mode) { 312 case USBPHY_INTERFACE_MODE_UTMI: 313 case USBPHY_INTERFACE_MODE_UTMIW: 314 case USBPHY_INTERFACE_MODE_HSIC: 315 ret = usb_phy_init(ci->transceiver); 316 if (ret) 317 return ret; 318 hw_phymode_configure(ci); 319 break; 320 case USBPHY_INTERFACE_MODE_ULPI: 321 case USBPHY_INTERFACE_MODE_SERIAL: 322 hw_phymode_configure(ci); 323 ret = usb_phy_init(ci->transceiver); 324 if (ret) 325 return ret; 326 break; 327 default: 328 ret = usb_phy_init(ci->transceiver); 329 } 330 331 return ret; 332 } 333 334 /** 335 * hw_device_reset: resets chip (execute without interruption) 336 * @ci: the controller 337 * 338 * This function returns an error code 339 */ 340 int hw_device_reset(struct ci_hdrc *ci, u32 mode) 341 { 342 /* should flush & stop before reset */ 343 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0); 344 hw_write(ci, OP_USBCMD, USBCMD_RS, 0); 345 346 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST); 347 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) 348 udelay(10); /* not RTOS friendly */ 349 350 if (ci->platdata->notify_event) 351 ci->platdata->notify_event(ci, 352 CI_HDRC_CONTROLLER_RESET_EVENT); 353 354 if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING) 355 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS); 356 357 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) { 358 if (ci->hw_bank.lpm) 359 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC); 360 else 361 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC); 362 } 363 364 /* USBMODE should be configured step by step */ 365 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE); 366 hw_write(ci, OP_USBMODE, USBMODE_CM, mode); 367 /* HW >= 2.3 */ 368 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); 369 370 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) { 371 pr_err("cannot enter in %s mode", ci_role(ci)->name); 372 pr_err("lpm = %i", ci->hw_bank.lpm); 373 return -ENODEV; 374 } 375 376 return 0; 377 } 378 379 /** 380 * hw_wait_reg: wait the register value 381 * 382 * Sometimes, it needs to wait register value before going on. 383 * Eg, when switch to device mode, the vbus value should be lower 384 * than OTGSC_BSV before connects to host. 385 * 386 * @ci: the controller 387 * @reg: register index 388 * @mask: mast bit 389 * @value: the bit value to wait 390 * @timeout_ms: timeout in millisecond 391 * 392 * This function returns an error code if timeout 393 */ 394 int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask, 395 u32 value, unsigned int timeout_ms) 396 { 397 unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms); 398 399 while (hw_read(ci, reg, mask) != value) { 400 if (time_after(jiffies, elapse)) { 401 dev_err(ci->dev, "timeout waiting for %08x in %d\n", 402 mask, reg); 403 return -ETIMEDOUT; 404 } 405 msleep(20); 406 } 407 408 return 0; 409 } 410 411 static irqreturn_t ci_irq(int irq, void *data) 412 { 413 struct ci_hdrc *ci = data; 414 irqreturn_t ret = IRQ_NONE; 415 u32 otgsc = 0; 416 417 if (ci->is_otg) { 418 otgsc = hw_read_otgsc(ci, ~0); 419 if (ci_otg_is_fsm_mode(ci)) { 420 ret = ci_otg_fsm_irq(ci); 421 if (ret == IRQ_HANDLED) 422 return ret; 423 } 424 } 425 426 /* 427 * Handle id change interrupt, it indicates device/host function 428 * switch. 429 */ 430 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) { 431 ci->id_event = true; 432 /* Clear ID change irq status */ 433 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS); 434 ci_otg_queue_work(ci); 435 return IRQ_HANDLED; 436 } 437 438 /* 439 * Handle vbus change interrupt, it indicates device connection 440 * and disconnection events. 441 */ 442 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) { 443 ci->b_sess_valid_event = true; 444 /* Clear BSV irq */ 445 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS); 446 ci_otg_queue_work(ci); 447 return IRQ_HANDLED; 448 } 449 450 /* Handle device/host interrupt */ 451 if (ci->role != CI_ROLE_END) 452 ret = ci_role(ci)->irq(ci); 453 454 return ret; 455 } 456 457 static int ci_get_platdata(struct device *dev, 458 struct ci_hdrc_platform_data *platdata) 459 { 460 if (!platdata->phy_mode) 461 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node); 462 463 if (!platdata->dr_mode) 464 platdata->dr_mode = of_usb_get_dr_mode(dev->of_node); 465 466 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN) 467 platdata->dr_mode = USB_DR_MODE_OTG; 468 469 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) { 470 /* Get the vbus regulator */ 471 platdata->reg_vbus = devm_regulator_get(dev, "vbus"); 472 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) { 473 return -EPROBE_DEFER; 474 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) { 475 /* no vbus regualator is needed */ 476 platdata->reg_vbus = NULL; 477 } else if (IS_ERR(platdata->reg_vbus)) { 478 dev_err(dev, "Getting regulator error: %ld\n", 479 PTR_ERR(platdata->reg_vbus)); 480 return PTR_ERR(platdata->reg_vbus); 481 } 482 /* Get TPL support */ 483 if (!platdata->tpl_support) 484 platdata->tpl_support = 485 of_usb_host_tpl_support(dev->of_node); 486 } 487 488 if (of_usb_get_maximum_speed(dev->of_node) == USB_SPEED_FULL) 489 platdata->flags |= CI_HDRC_FORCE_FULLSPEED; 490 491 return 0; 492 } 493 494 static DEFINE_IDA(ci_ida); 495 496 struct platform_device *ci_hdrc_add_device(struct device *dev, 497 struct resource *res, int nres, 498 struct ci_hdrc_platform_data *platdata) 499 { 500 struct platform_device *pdev; 501 int id, ret; 502 503 ret = ci_get_platdata(dev, platdata); 504 if (ret) 505 return ERR_PTR(ret); 506 507 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL); 508 if (id < 0) 509 return ERR_PTR(id); 510 511 pdev = platform_device_alloc("ci_hdrc", id); 512 if (!pdev) { 513 ret = -ENOMEM; 514 goto put_id; 515 } 516 517 pdev->dev.parent = dev; 518 pdev->dev.dma_mask = dev->dma_mask; 519 pdev->dev.dma_parms = dev->dma_parms; 520 dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask); 521 522 ret = platform_device_add_resources(pdev, res, nres); 523 if (ret) 524 goto err; 525 526 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata)); 527 if (ret) 528 goto err; 529 530 ret = platform_device_add(pdev); 531 if (ret) 532 goto err; 533 534 return pdev; 535 536 err: 537 platform_device_put(pdev); 538 put_id: 539 ida_simple_remove(&ci_ida, id); 540 return ERR_PTR(ret); 541 } 542 EXPORT_SYMBOL_GPL(ci_hdrc_add_device); 543 544 void ci_hdrc_remove_device(struct platform_device *pdev) 545 { 546 int id = pdev->id; 547 platform_device_unregister(pdev); 548 ida_simple_remove(&ci_ida, id); 549 } 550 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device); 551 552 static inline void ci_role_destroy(struct ci_hdrc *ci) 553 { 554 ci_hdrc_gadget_destroy(ci); 555 ci_hdrc_host_destroy(ci); 556 if (ci->is_otg) 557 ci_hdrc_otg_destroy(ci); 558 } 559 560 static void ci_get_otg_capable(struct ci_hdrc *ci) 561 { 562 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG) 563 ci->is_otg = false; 564 else 565 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS, 566 DCCPARAMS_DC | DCCPARAMS_HC) 567 == (DCCPARAMS_DC | DCCPARAMS_HC)); 568 if (ci->is_otg) 569 dev_dbg(ci->dev, "It is OTG capable controller\n"); 570 } 571 572 static int ci_hdrc_probe(struct platform_device *pdev) 573 { 574 struct device *dev = &pdev->dev; 575 struct ci_hdrc *ci; 576 struct resource *res; 577 void __iomem *base; 578 int ret; 579 enum usb_dr_mode dr_mode; 580 581 if (!dev_get_platdata(dev)) { 582 dev_err(dev, "platform data missing\n"); 583 return -ENODEV; 584 } 585 586 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 587 base = devm_ioremap_resource(dev, res); 588 if (IS_ERR(base)) 589 return PTR_ERR(base); 590 591 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL); 592 if (!ci) { 593 dev_err(dev, "can't allocate device\n"); 594 return -ENOMEM; 595 } 596 597 ci->dev = dev; 598 ci->platdata = dev_get_platdata(dev); 599 ci->imx28_write_fix = !!(ci->platdata->flags & 600 CI_HDRC_IMX28_WRITE_FIX); 601 602 ret = hw_device_init(ci, base); 603 if (ret < 0) { 604 dev_err(dev, "can't initialize hardware\n"); 605 return -ENODEV; 606 } 607 608 if (ci->platdata->phy) 609 ci->transceiver = ci->platdata->phy; 610 else 611 ci->transceiver = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 612 613 if (IS_ERR(ci->transceiver)) { 614 ret = PTR_ERR(ci->transceiver); 615 /* 616 * if -ENXIO is returned, it means PHY layer wasn't 617 * enabled, so it makes no sense to return -EPROBE_DEFER 618 * in that case, since no PHY driver will ever probe. 619 */ 620 if (ret == -ENXIO) 621 return ret; 622 623 dev_err(dev, "no usb2 phy configured\n"); 624 return -EPROBE_DEFER; 625 } 626 627 ret = ci_usb_phy_init(ci); 628 if (ret) { 629 dev_err(dev, "unable to init phy: %d\n", ret); 630 return ret; 631 } else { 632 /* 633 * The delay to sync PHY's status, the maximum delay is 634 * 2ms since the otgsc uses 1ms timer to debounce the 635 * PHY's input 636 */ 637 usleep_range(2000, 2500); 638 } 639 640 ci->hw_bank.phys = res->start; 641 642 ci->irq = platform_get_irq(pdev, 0); 643 if (ci->irq < 0) { 644 dev_err(dev, "missing IRQ\n"); 645 ret = ci->irq; 646 goto deinit_phy; 647 } 648 649 ci_get_otg_capable(ci); 650 651 dr_mode = ci->platdata->dr_mode; 652 /* initialize role(s) before the interrupt is requested */ 653 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) { 654 ret = ci_hdrc_host_init(ci); 655 if (ret) 656 dev_info(dev, "doesn't support host\n"); 657 } 658 659 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) { 660 ret = ci_hdrc_gadget_init(ci); 661 if (ret) 662 dev_info(dev, "doesn't support gadget\n"); 663 } 664 665 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) { 666 dev_err(dev, "no supported roles\n"); 667 ret = -ENODEV; 668 goto deinit_phy; 669 } 670 671 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) { 672 /* Disable and clear all OTG irq */ 673 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS, 674 OTGSC_INT_STATUS_BITS); 675 ret = ci_hdrc_otg_init(ci); 676 if (ret) { 677 dev_err(dev, "init otg fails, ret = %d\n", ret); 678 goto stop; 679 } 680 } 681 682 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) { 683 if (ci->is_otg) { 684 ci->role = ci_otg_role(ci); 685 /* Enable ID change irq */ 686 hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE); 687 } else { 688 /* 689 * If the controller is not OTG capable, but support 690 * role switch, the defalt role is gadget, and the 691 * user can switch it through debugfs. 692 */ 693 ci->role = CI_ROLE_GADGET; 694 } 695 } else { 696 ci->role = ci->roles[CI_ROLE_HOST] 697 ? CI_ROLE_HOST 698 : CI_ROLE_GADGET; 699 } 700 701 /* only update vbus status for peripheral */ 702 if (ci->role == CI_ROLE_GADGET) 703 ci_handle_vbus_change(ci); 704 705 if (!ci_otg_is_fsm_mode(ci)) { 706 ret = ci_role_start(ci, ci->role); 707 if (ret) { 708 dev_err(dev, "can't start %s role\n", 709 ci_role(ci)->name); 710 goto stop; 711 } 712 } 713 714 platform_set_drvdata(pdev, ci); 715 ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name, 716 ci); 717 if (ret) 718 goto stop; 719 720 if (ci_otg_is_fsm_mode(ci)) 721 ci_hdrc_otg_fsm_start(ci); 722 723 ret = dbg_create_files(ci); 724 if (!ret) 725 return 0; 726 727 free_irq(ci->irq, ci); 728 stop: 729 ci_role_destroy(ci); 730 deinit_phy: 731 usb_phy_shutdown(ci->transceiver); 732 733 return ret; 734 } 735 736 static int ci_hdrc_remove(struct platform_device *pdev) 737 { 738 struct ci_hdrc *ci = platform_get_drvdata(pdev); 739 740 dbg_remove_files(ci); 741 free_irq(ci->irq, ci); 742 ci_role_destroy(ci); 743 ci_hdrc_enter_lpm(ci, true); 744 usb_phy_shutdown(ci->transceiver); 745 746 return 0; 747 } 748 749 static struct platform_driver ci_hdrc_driver = { 750 .probe = ci_hdrc_probe, 751 .remove = ci_hdrc_remove, 752 .driver = { 753 .name = "ci_hdrc", 754 .owner = THIS_MODULE, 755 }, 756 }; 757 758 module_platform_driver(ci_hdrc_driver); 759 760 MODULE_ALIAS("platform:ci_hdrc"); 761 MODULE_LICENSE("GPL v2"); 762 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>"); 763 MODULE_DESCRIPTION("ChipIdea HDRC Driver"); 764