1 /* 2 * core.c - ChipIdea USB IP core family device controller 3 * 4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. 5 * 6 * Author: David Lopo 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 /* 14 * Description: ChipIdea USB IP core family device controller 15 * 16 * This driver is composed of several blocks: 17 * - HW: hardware interface 18 * - DBG: debug facilities (optional) 19 * - UTIL: utilities 20 * - ISR: interrupts handling 21 * - ENDPT: endpoint operations (Gadget API) 22 * - GADGET: gadget operations (Gadget API) 23 * - BUS: bus glue code, bus abstraction layer 24 * 25 * Compile Options 26 * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities 27 * - STALL_IN: non-empty bulk-in pipes cannot be halted 28 * if defined mass storage compliance succeeds but with warnings 29 * => case 4: Hi > Dn 30 * => case 5: Hi > Di 31 * => case 8: Hi <> Do 32 * if undefined usbtest 13 fails 33 * - TRACE: enable function tracing (depends on DEBUG) 34 * 35 * Main Features 36 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage 37 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined) 38 * - Normal & LPM support 39 * 40 * USBTEST Report 41 * - OK: 0-12, 13 (STALL_IN defined) & 14 42 * - Not Supported: 15 & 16 (ISO) 43 * 44 * TODO List 45 * - OTG 46 * - Interrupt Traffic 47 * - GET_STATUS(device) - always reports 0 48 * - Gadget API (majority of optional features) 49 * - Suspend & Remote Wakeup 50 */ 51 #include <linux/delay.h> 52 #include <linux/device.h> 53 #include <linux/dma-mapping.h> 54 #include <linux/platform_device.h> 55 #include <linux/module.h> 56 #include <linux/idr.h> 57 #include <linux/interrupt.h> 58 #include <linux/io.h> 59 #include <linux/kernel.h> 60 #include <linux/slab.h> 61 #include <linux/pm_runtime.h> 62 #include <linux/usb/ch9.h> 63 #include <linux/usb/gadget.h> 64 #include <linux/usb/otg.h> 65 #include <linux/usb/chipidea.h> 66 #include <linux/usb/of.h> 67 #include <linux/phy.h> 68 #include <linux/regulator/consumer.h> 69 70 #include "ci.h" 71 #include "udc.h" 72 #include "bits.h" 73 #include "host.h" 74 #include "debug.h" 75 #include "otg.h" 76 77 /* Controller register map */ 78 static const u8 ci_regs_nolpm[] = { 79 [CAP_CAPLENGTH] = 0x00U, 80 [CAP_HCCPARAMS] = 0x08U, 81 [CAP_DCCPARAMS] = 0x24U, 82 [CAP_TESTMODE] = 0x38U, 83 [OP_USBCMD] = 0x00U, 84 [OP_USBSTS] = 0x04U, 85 [OP_USBINTR] = 0x08U, 86 [OP_DEVICEADDR] = 0x14U, 87 [OP_ENDPTLISTADDR] = 0x18U, 88 [OP_PORTSC] = 0x44U, 89 [OP_DEVLC] = 0x84U, 90 [OP_OTGSC] = 0x64U, 91 [OP_USBMODE] = 0x68U, 92 [OP_ENDPTSETUPSTAT] = 0x6CU, 93 [OP_ENDPTPRIME] = 0x70U, 94 [OP_ENDPTFLUSH] = 0x74U, 95 [OP_ENDPTSTAT] = 0x78U, 96 [OP_ENDPTCOMPLETE] = 0x7CU, 97 [OP_ENDPTCTRL] = 0x80U, 98 }; 99 100 static const u8 ci_regs_lpm[] = { 101 [CAP_CAPLENGTH] = 0x00U, 102 [CAP_HCCPARAMS] = 0x08U, 103 [CAP_DCCPARAMS] = 0x24U, 104 [CAP_TESTMODE] = 0xFCU, 105 [OP_USBCMD] = 0x00U, 106 [OP_USBSTS] = 0x04U, 107 [OP_USBINTR] = 0x08U, 108 [OP_DEVICEADDR] = 0x14U, 109 [OP_ENDPTLISTADDR] = 0x18U, 110 [OP_PORTSC] = 0x44U, 111 [OP_DEVLC] = 0x84U, 112 [OP_OTGSC] = 0xC4U, 113 [OP_USBMODE] = 0xC8U, 114 [OP_ENDPTSETUPSTAT] = 0xD8U, 115 [OP_ENDPTPRIME] = 0xDCU, 116 [OP_ENDPTFLUSH] = 0xE0U, 117 [OP_ENDPTSTAT] = 0xE4U, 118 [OP_ENDPTCOMPLETE] = 0xE8U, 119 [OP_ENDPTCTRL] = 0xECU, 120 }; 121 122 static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm) 123 { 124 int i; 125 126 for (i = 0; i < OP_ENDPTCTRL; i++) 127 ci->hw_bank.regmap[i] = 128 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) + 129 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]); 130 131 for (; i <= OP_LAST; i++) 132 ci->hw_bank.regmap[i] = ci->hw_bank.op + 133 4 * (i - OP_ENDPTCTRL) + 134 (is_lpm 135 ? ci_regs_lpm[OP_ENDPTCTRL] 136 : ci_regs_nolpm[OP_ENDPTCTRL]); 137 138 return 0; 139 } 140 141 /** 142 * hw_port_test_set: writes port test mode (execute without interruption) 143 * @mode: new value 144 * 145 * This function returns an error code 146 */ 147 int hw_port_test_set(struct ci_hdrc *ci, u8 mode) 148 { 149 const u8 TEST_MODE_MAX = 7; 150 151 if (mode > TEST_MODE_MAX) 152 return -EINVAL; 153 154 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC)); 155 return 0; 156 } 157 158 /** 159 * hw_port_test_get: reads port test mode value 160 * 161 * This function returns port test mode value 162 */ 163 u8 hw_port_test_get(struct ci_hdrc *ci) 164 { 165 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC); 166 } 167 168 /* The PHY enters/leaves low power mode */ 169 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable) 170 { 171 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC; 172 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm))); 173 174 if (enable && !lpm) { 175 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), 176 PORTSC_PHCD(ci->hw_bank.lpm)); 177 } else if (!enable && lpm) { 178 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), 179 0); 180 /* 181 * The controller needs at least 1ms to reflect 182 * PHY's status, the PHY also needs some time (less 183 * than 1ms) to leave low power mode. 184 */ 185 usleep_range(1500, 2000); 186 } 187 } 188 189 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base) 190 { 191 u32 reg; 192 193 /* bank is a module variable */ 194 ci->hw_bank.abs = base; 195 196 ci->hw_bank.cap = ci->hw_bank.abs; 197 ci->hw_bank.cap += ci->platdata->capoffset; 198 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff); 199 200 hw_alloc_regmap(ci, false); 201 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >> 202 __ffs(HCCPARAMS_LEN); 203 ci->hw_bank.lpm = reg; 204 if (reg) 205 hw_alloc_regmap(ci, !!reg); 206 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs; 207 ci->hw_bank.size += OP_LAST; 208 ci->hw_bank.size /= sizeof(u32); 209 210 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >> 211 __ffs(DCCPARAMS_DEN); 212 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */ 213 214 if (ci->hw_ep_max > ENDPT_MAX) 215 return -ENODEV; 216 217 ci_hdrc_enter_lpm(ci, false); 218 219 /* Disable all interrupts bits */ 220 hw_write(ci, OP_USBINTR, 0xffffffff, 0); 221 222 /* Clear all interrupts status bits*/ 223 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff); 224 225 dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n", 226 ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op); 227 228 /* setup lock mode ? */ 229 230 /* ENDPTSETUPSTAT is '0' by default */ 231 232 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */ 233 234 return 0; 235 } 236 237 static void hw_phymode_configure(struct ci_hdrc *ci) 238 { 239 u32 portsc, lpm, sts = 0; 240 241 switch (ci->platdata->phy_mode) { 242 case USBPHY_INTERFACE_MODE_UTMI: 243 portsc = PORTSC_PTS(PTS_UTMI); 244 lpm = DEVLC_PTS(PTS_UTMI); 245 break; 246 case USBPHY_INTERFACE_MODE_UTMIW: 247 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW; 248 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW; 249 break; 250 case USBPHY_INTERFACE_MODE_ULPI: 251 portsc = PORTSC_PTS(PTS_ULPI); 252 lpm = DEVLC_PTS(PTS_ULPI); 253 break; 254 case USBPHY_INTERFACE_MODE_SERIAL: 255 portsc = PORTSC_PTS(PTS_SERIAL); 256 lpm = DEVLC_PTS(PTS_SERIAL); 257 sts = 1; 258 break; 259 case USBPHY_INTERFACE_MODE_HSIC: 260 portsc = PORTSC_PTS(PTS_HSIC); 261 lpm = DEVLC_PTS(PTS_HSIC); 262 break; 263 default: 264 return; 265 } 266 267 if (ci->hw_bank.lpm) { 268 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm); 269 if (sts) 270 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS); 271 } else { 272 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc); 273 if (sts) 274 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS); 275 } 276 } 277 278 /** 279 * hw_device_reset: resets chip (execute without interruption) 280 * @ci: the controller 281 * 282 * This function returns an error code 283 */ 284 int hw_device_reset(struct ci_hdrc *ci, u32 mode) 285 { 286 /* should flush & stop before reset */ 287 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0); 288 hw_write(ci, OP_USBCMD, USBCMD_RS, 0); 289 290 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST); 291 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) 292 udelay(10); /* not RTOS friendly */ 293 294 if (ci->platdata->notify_event) 295 ci->platdata->notify_event(ci, 296 CI_HDRC_CONTROLLER_RESET_EVENT); 297 298 if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING) 299 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS); 300 301 /* USBMODE should be configured step by step */ 302 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE); 303 hw_write(ci, OP_USBMODE, USBMODE_CM, mode); 304 /* HW >= 2.3 */ 305 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); 306 307 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) { 308 pr_err("cannot enter in %s mode", ci_role(ci)->name); 309 pr_err("lpm = %i", ci->hw_bank.lpm); 310 return -ENODEV; 311 } 312 313 return 0; 314 } 315 316 /** 317 * hw_wait_reg: wait the register value 318 * 319 * Sometimes, it needs to wait register value before going on. 320 * Eg, when switch to device mode, the vbus value should be lower 321 * than OTGSC_BSV before connects to host. 322 * 323 * @ci: the controller 324 * @reg: register index 325 * @mask: mast bit 326 * @value: the bit value to wait 327 * @timeout_ms: timeout in millisecond 328 * 329 * This function returns an error code if timeout 330 */ 331 int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask, 332 u32 value, unsigned int timeout_ms) 333 { 334 unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms); 335 336 while (hw_read(ci, reg, mask) != value) { 337 if (time_after(jiffies, elapse)) { 338 dev_err(ci->dev, "timeout waiting for %08x in %d\n", 339 mask, reg); 340 return -ETIMEDOUT; 341 } 342 msleep(20); 343 } 344 345 return 0; 346 } 347 348 static irqreturn_t ci_irq(int irq, void *data) 349 { 350 struct ci_hdrc *ci = data; 351 irqreturn_t ret = IRQ_NONE; 352 u32 otgsc = 0; 353 354 if (ci->is_otg) 355 otgsc = hw_read(ci, OP_OTGSC, ~0); 356 357 /* 358 * Handle id change interrupt, it indicates device/host function 359 * switch. 360 */ 361 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) { 362 ci->id_event = true; 363 ci_clear_otg_interrupt(ci, OTGSC_IDIS); 364 disable_irq_nosync(ci->irq); 365 queue_work(ci->wq, &ci->work); 366 return IRQ_HANDLED; 367 } 368 369 /* 370 * Handle vbus change interrupt, it indicates device connection 371 * and disconnection events. 372 */ 373 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) { 374 ci->b_sess_valid_event = true; 375 ci_clear_otg_interrupt(ci, OTGSC_BSVIS); 376 disable_irq_nosync(ci->irq); 377 queue_work(ci->wq, &ci->work); 378 return IRQ_HANDLED; 379 } 380 381 /* Handle device/host interrupt */ 382 if (ci->role != CI_ROLE_END) 383 ret = ci_role(ci)->irq(ci); 384 385 return ret; 386 } 387 388 static int ci_get_platdata(struct device *dev, 389 struct ci_hdrc_platform_data *platdata) 390 { 391 if (!platdata->phy_mode) 392 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node); 393 394 if (!platdata->dr_mode) 395 platdata->dr_mode = of_usb_get_dr_mode(dev->of_node); 396 397 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN) 398 platdata->dr_mode = USB_DR_MODE_OTG; 399 400 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) { 401 /* Get the vbus regulator */ 402 platdata->reg_vbus = devm_regulator_get(dev, "vbus"); 403 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) { 404 return -EPROBE_DEFER; 405 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) { 406 /* no vbus regualator is needed */ 407 platdata->reg_vbus = NULL; 408 } else if (IS_ERR(platdata->reg_vbus)) { 409 dev_err(dev, "Getting regulator error: %ld\n", 410 PTR_ERR(platdata->reg_vbus)); 411 return PTR_ERR(platdata->reg_vbus); 412 } 413 } 414 415 return 0; 416 } 417 418 static DEFINE_IDA(ci_ida); 419 420 struct platform_device *ci_hdrc_add_device(struct device *dev, 421 struct resource *res, int nres, 422 struct ci_hdrc_platform_data *platdata) 423 { 424 struct platform_device *pdev; 425 int id, ret; 426 427 ret = ci_get_platdata(dev, platdata); 428 if (ret) 429 return ERR_PTR(ret); 430 431 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL); 432 if (id < 0) 433 return ERR_PTR(id); 434 435 pdev = platform_device_alloc("ci_hdrc", id); 436 if (!pdev) { 437 ret = -ENOMEM; 438 goto put_id; 439 } 440 441 pdev->dev.parent = dev; 442 pdev->dev.dma_mask = dev->dma_mask; 443 pdev->dev.dma_parms = dev->dma_parms; 444 dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask); 445 446 ret = platform_device_add_resources(pdev, res, nres); 447 if (ret) 448 goto err; 449 450 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata)); 451 if (ret) 452 goto err; 453 454 ret = platform_device_add(pdev); 455 if (ret) 456 goto err; 457 458 return pdev; 459 460 err: 461 platform_device_put(pdev); 462 put_id: 463 ida_simple_remove(&ci_ida, id); 464 return ERR_PTR(ret); 465 } 466 EXPORT_SYMBOL_GPL(ci_hdrc_add_device); 467 468 void ci_hdrc_remove_device(struct platform_device *pdev) 469 { 470 int id = pdev->id; 471 platform_device_unregister(pdev); 472 ida_simple_remove(&ci_ida, id); 473 } 474 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device); 475 476 static inline void ci_role_destroy(struct ci_hdrc *ci) 477 { 478 ci_hdrc_gadget_destroy(ci); 479 ci_hdrc_host_destroy(ci); 480 if (ci->is_otg) 481 ci_hdrc_otg_destroy(ci); 482 } 483 484 static void ci_get_otg_capable(struct ci_hdrc *ci) 485 { 486 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG) 487 ci->is_otg = false; 488 else 489 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS, 490 DCCPARAMS_DC | DCCPARAMS_HC) 491 == (DCCPARAMS_DC | DCCPARAMS_HC)); 492 if (ci->is_otg) { 493 dev_dbg(ci->dev, "It is OTG capable controller\n"); 494 ci_disable_otg_interrupt(ci, OTGSC_INT_EN_BITS); 495 ci_clear_otg_interrupt(ci, OTGSC_INT_STATUS_BITS); 496 } 497 } 498 499 static int ci_usb_phy_init(struct ci_hdrc *ci) 500 { 501 if (ci->platdata->phy) { 502 ci->transceiver = ci->platdata->phy; 503 return usb_phy_init(ci->transceiver); 504 } else { 505 ci->global_phy = true; 506 ci->transceiver = usb_get_phy(USB_PHY_TYPE_USB2); 507 if (IS_ERR(ci->transceiver)) 508 ci->transceiver = NULL; 509 510 return 0; 511 } 512 } 513 514 static void ci_usb_phy_destroy(struct ci_hdrc *ci) 515 { 516 if (!ci->transceiver) 517 return; 518 519 otg_set_peripheral(ci->transceiver->otg, NULL); 520 if (ci->global_phy) 521 usb_put_phy(ci->transceiver); 522 else 523 usb_phy_shutdown(ci->transceiver); 524 } 525 526 static int ci_hdrc_probe(struct platform_device *pdev) 527 { 528 struct device *dev = &pdev->dev; 529 struct ci_hdrc *ci; 530 struct resource *res; 531 void __iomem *base; 532 int ret; 533 enum usb_dr_mode dr_mode; 534 535 if (!dev->platform_data) { 536 dev_err(dev, "platform data missing\n"); 537 return -ENODEV; 538 } 539 540 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 541 base = devm_ioremap_resource(dev, res); 542 if (IS_ERR(base)) 543 return PTR_ERR(base); 544 545 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL); 546 if (!ci) { 547 dev_err(dev, "can't allocate device\n"); 548 return -ENOMEM; 549 } 550 551 ci->dev = dev; 552 ci->platdata = dev->platform_data; 553 ci->imx28_write_fix = !!(ci->platdata->flags & 554 CI_HDRC_IMX28_WRITE_FIX); 555 556 ret = hw_device_init(ci, base); 557 if (ret < 0) { 558 dev_err(dev, "can't initialize hardware\n"); 559 return -ENODEV; 560 } 561 562 hw_phymode_configure(ci); 563 564 ret = ci_usb_phy_init(ci); 565 if (ret) { 566 dev_err(dev, "unable to init phy: %d\n", ret); 567 return ret; 568 } 569 570 ci->hw_bank.phys = res->start; 571 572 ci->irq = platform_get_irq(pdev, 0); 573 if (ci->irq < 0) { 574 dev_err(dev, "missing IRQ\n"); 575 ret = -ENODEV; 576 goto destroy_phy; 577 } 578 579 ci_get_otg_capable(ci); 580 581 dr_mode = ci->platdata->dr_mode; 582 /* initialize role(s) before the interrupt is requested */ 583 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) { 584 ret = ci_hdrc_host_init(ci); 585 if (ret) 586 dev_info(dev, "doesn't support host\n"); 587 } 588 589 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) { 590 ret = ci_hdrc_gadget_init(ci); 591 if (ret) 592 dev_info(dev, "doesn't support gadget\n"); 593 if (!ret && ci->transceiver) { 594 ret = otg_set_peripheral(ci->transceiver->otg, 595 &ci->gadget); 596 /* 597 * If we implement all USB functions using chipidea drivers, 598 * it doesn't need to call above API, meanwhile, if we only 599 * use gadget function, calling above API is useless. 600 */ 601 if (ret && ret != -ENOTSUPP) 602 goto destroy_phy; 603 } 604 } 605 606 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) { 607 dev_err(dev, "no supported roles\n"); 608 ret = -ENODEV; 609 goto destroy_phy; 610 } 611 612 if (ci->is_otg) { 613 ret = ci_hdrc_otg_init(ci); 614 if (ret) { 615 dev_err(dev, "init otg fails, ret = %d\n", ret); 616 goto stop; 617 } 618 } 619 620 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) { 621 if (ci->is_otg) { 622 /* 623 * ID pin needs 1ms debouce time, 624 * we delay 2ms for safe. 625 */ 626 mdelay(2); 627 ci->role = ci_otg_role(ci); 628 ci_enable_otg_interrupt(ci, OTGSC_IDIE); 629 } else { 630 /* 631 * If the controller is not OTG capable, but support 632 * role switch, the defalt role is gadget, and the 633 * user can switch it through debugfs. 634 */ 635 ci->role = CI_ROLE_GADGET; 636 } 637 } else { 638 ci->role = ci->roles[CI_ROLE_HOST] 639 ? CI_ROLE_HOST 640 : CI_ROLE_GADGET; 641 } 642 643 /* only update vbus status for peripheral */ 644 if (ci->role == CI_ROLE_GADGET) 645 ci_handle_vbus_change(ci); 646 647 ret = ci_role_start(ci, ci->role); 648 if (ret) { 649 dev_err(dev, "can't start %s role\n", ci_role(ci)->name); 650 goto stop; 651 } 652 653 platform_set_drvdata(pdev, ci); 654 ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name, 655 ci); 656 if (ret) 657 goto stop; 658 659 ret = dbg_create_files(ci); 660 if (!ret) 661 return 0; 662 663 free_irq(ci->irq, ci); 664 stop: 665 ci_role_destroy(ci); 666 destroy_phy: 667 ci_usb_phy_destroy(ci); 668 669 return ret; 670 } 671 672 static int ci_hdrc_remove(struct platform_device *pdev) 673 { 674 struct ci_hdrc *ci = platform_get_drvdata(pdev); 675 676 dbg_remove_files(ci); 677 free_irq(ci->irq, ci); 678 ci_role_destroy(ci); 679 ci_hdrc_enter_lpm(ci, true); 680 ci_usb_phy_destroy(ci); 681 682 return 0; 683 } 684 685 static struct platform_driver ci_hdrc_driver = { 686 .probe = ci_hdrc_probe, 687 .remove = ci_hdrc_remove, 688 .driver = { 689 .name = "ci_hdrc", 690 }, 691 }; 692 693 module_platform_driver(ci_hdrc_driver); 694 695 MODULE_ALIAS("platform:ci_hdrc"); 696 MODULE_LICENSE("GPL v2"); 697 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>"); 698 MODULE_DESCRIPTION("ChipIdea HDRC Driver"); 699