1 /* 2 * core.c - ChipIdea USB IP core family device controller 3 * 4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. 5 * 6 * Author: David Lopo 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 /* 14 * Description: ChipIdea USB IP core family device controller 15 * 16 * This driver is composed of several blocks: 17 * - HW: hardware interface 18 * - DBG: debug facilities (optional) 19 * - UTIL: utilities 20 * - ISR: interrupts handling 21 * - ENDPT: endpoint operations (Gadget API) 22 * - GADGET: gadget operations (Gadget API) 23 * - BUS: bus glue code, bus abstraction layer 24 * 25 * Compile Options 26 * - CONFIG_USB_CHIPIDEA_DEBUG: enable debug facilities 27 * - STALL_IN: non-empty bulk-in pipes cannot be halted 28 * if defined mass storage compliance succeeds but with warnings 29 * => case 4: Hi > Dn 30 * => case 5: Hi > Di 31 * => case 8: Hi <> Do 32 * if undefined usbtest 13 fails 33 * - TRACE: enable function tracing (depends on DEBUG) 34 * 35 * Main Features 36 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage 37 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined) 38 * - Normal & LPM support 39 * 40 * USBTEST Report 41 * - OK: 0-12, 13 (STALL_IN defined) & 14 42 * - Not Supported: 15 & 16 (ISO) 43 * 44 * TODO List 45 * - Suspend & Remote Wakeup 46 */ 47 #include <linux/delay.h> 48 #include <linux/device.h> 49 #include <linux/dma-mapping.h> 50 #include <linux/phy/phy.h> 51 #include <linux/platform_device.h> 52 #include <linux/module.h> 53 #include <linux/idr.h> 54 #include <linux/interrupt.h> 55 #include <linux/io.h> 56 #include <linux/kernel.h> 57 #include <linux/slab.h> 58 #include <linux/pm_runtime.h> 59 #include <linux/usb/ch9.h> 60 #include <linux/usb/gadget.h> 61 #include <linux/usb/otg.h> 62 #include <linux/usb/chipidea.h> 63 #include <linux/usb/of.h> 64 #include <linux/of.h> 65 #include <linux/phy.h> 66 #include <linux/regulator/consumer.h> 67 #include <linux/usb/ehci_def.h> 68 69 #include "ci.h" 70 #include "udc.h" 71 #include "bits.h" 72 #include "host.h" 73 #include "debug.h" 74 #include "otg.h" 75 #include "otg_fsm.h" 76 77 /* Controller register map */ 78 static const u8 ci_regs_nolpm[] = { 79 [CAP_CAPLENGTH] = 0x00U, 80 [CAP_HCCPARAMS] = 0x08U, 81 [CAP_DCCPARAMS] = 0x24U, 82 [CAP_TESTMODE] = 0x38U, 83 [OP_USBCMD] = 0x00U, 84 [OP_USBSTS] = 0x04U, 85 [OP_USBINTR] = 0x08U, 86 [OP_DEVICEADDR] = 0x14U, 87 [OP_ENDPTLISTADDR] = 0x18U, 88 [OP_TTCTRL] = 0x1CU, 89 [OP_BURSTSIZE] = 0x20U, 90 [OP_PORTSC] = 0x44U, 91 [OP_DEVLC] = 0x84U, 92 [OP_OTGSC] = 0x64U, 93 [OP_USBMODE] = 0x68U, 94 [OP_ENDPTSETUPSTAT] = 0x6CU, 95 [OP_ENDPTPRIME] = 0x70U, 96 [OP_ENDPTFLUSH] = 0x74U, 97 [OP_ENDPTSTAT] = 0x78U, 98 [OP_ENDPTCOMPLETE] = 0x7CU, 99 [OP_ENDPTCTRL] = 0x80U, 100 }; 101 102 static const u8 ci_regs_lpm[] = { 103 [CAP_CAPLENGTH] = 0x00U, 104 [CAP_HCCPARAMS] = 0x08U, 105 [CAP_DCCPARAMS] = 0x24U, 106 [CAP_TESTMODE] = 0xFCU, 107 [OP_USBCMD] = 0x00U, 108 [OP_USBSTS] = 0x04U, 109 [OP_USBINTR] = 0x08U, 110 [OP_DEVICEADDR] = 0x14U, 111 [OP_ENDPTLISTADDR] = 0x18U, 112 [OP_TTCTRL] = 0x1CU, 113 [OP_BURSTSIZE] = 0x20U, 114 [OP_PORTSC] = 0x44U, 115 [OP_DEVLC] = 0x84U, 116 [OP_OTGSC] = 0xC4U, 117 [OP_USBMODE] = 0xC8U, 118 [OP_ENDPTSETUPSTAT] = 0xD8U, 119 [OP_ENDPTPRIME] = 0xDCU, 120 [OP_ENDPTFLUSH] = 0xE0U, 121 [OP_ENDPTSTAT] = 0xE4U, 122 [OP_ENDPTCOMPLETE] = 0xE8U, 123 [OP_ENDPTCTRL] = 0xECU, 124 }; 125 126 static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm) 127 { 128 int i; 129 130 for (i = 0; i < OP_ENDPTCTRL; i++) 131 ci->hw_bank.regmap[i] = 132 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) + 133 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]); 134 135 for (; i <= OP_LAST; i++) 136 ci->hw_bank.regmap[i] = ci->hw_bank.op + 137 4 * (i - OP_ENDPTCTRL) + 138 (is_lpm 139 ? ci_regs_lpm[OP_ENDPTCTRL] 140 : ci_regs_nolpm[OP_ENDPTCTRL]); 141 142 } 143 144 static enum ci_revision ci_get_revision(struct ci_hdrc *ci) 145 { 146 int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION); 147 enum ci_revision rev = CI_REVISION_UNKNOWN; 148 149 if (ver == 0x2) { 150 rev = hw_read_id_reg(ci, ID_ID, REVISION) 151 >> __ffs(REVISION); 152 rev += CI_REVISION_20; 153 } else if (ver == 0x0) { 154 rev = CI_REVISION_1X; 155 } 156 157 return rev; 158 } 159 160 /** 161 * hw_read_intr_enable: returns interrupt enable register 162 * 163 * @ci: the controller 164 * 165 * This function returns register data 166 */ 167 u32 hw_read_intr_enable(struct ci_hdrc *ci) 168 { 169 return hw_read(ci, OP_USBINTR, ~0); 170 } 171 172 /** 173 * hw_read_intr_status: returns interrupt status register 174 * 175 * @ci: the controller 176 * 177 * This function returns register data 178 */ 179 u32 hw_read_intr_status(struct ci_hdrc *ci) 180 { 181 return hw_read(ci, OP_USBSTS, ~0); 182 } 183 184 /** 185 * hw_port_test_set: writes port test mode (execute without interruption) 186 * @mode: new value 187 * 188 * This function returns an error code 189 */ 190 int hw_port_test_set(struct ci_hdrc *ci, u8 mode) 191 { 192 const u8 TEST_MODE_MAX = 7; 193 194 if (mode > TEST_MODE_MAX) 195 return -EINVAL; 196 197 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC)); 198 return 0; 199 } 200 201 /** 202 * hw_port_test_get: reads port test mode value 203 * 204 * @ci: the controller 205 * 206 * This function returns port test mode value 207 */ 208 u8 hw_port_test_get(struct ci_hdrc *ci) 209 { 210 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC); 211 } 212 213 static void hw_wait_phy_stable(void) 214 { 215 /* 216 * The phy needs some delay to output the stable status from low 217 * power mode. And for OTGSC, the status inputs are debounced 218 * using a 1 ms time constant, so, delay 2ms for controller to get 219 * the stable status, like vbus and id when the phy leaves low power. 220 */ 221 usleep_range(2000, 2500); 222 } 223 224 /* The PHY enters/leaves low power mode */ 225 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable) 226 { 227 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC; 228 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm))); 229 230 if (enable && !lpm) 231 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), 232 PORTSC_PHCD(ci->hw_bank.lpm)); 233 else if (!enable && lpm) 234 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), 235 0); 236 } 237 238 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base) 239 { 240 u32 reg; 241 242 /* bank is a module variable */ 243 ci->hw_bank.abs = base; 244 245 ci->hw_bank.cap = ci->hw_bank.abs; 246 ci->hw_bank.cap += ci->platdata->capoffset; 247 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff); 248 249 hw_alloc_regmap(ci, false); 250 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >> 251 __ffs(HCCPARAMS_LEN); 252 ci->hw_bank.lpm = reg; 253 if (reg) 254 hw_alloc_regmap(ci, !!reg); 255 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs; 256 ci->hw_bank.size += OP_LAST; 257 ci->hw_bank.size /= sizeof(u32); 258 259 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >> 260 __ffs(DCCPARAMS_DEN); 261 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */ 262 263 if (ci->hw_ep_max > ENDPT_MAX) 264 return -ENODEV; 265 266 ci_hdrc_enter_lpm(ci, false); 267 268 /* Disable all interrupts bits */ 269 hw_write(ci, OP_USBINTR, 0xffffffff, 0); 270 271 /* Clear all interrupts status bits*/ 272 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff); 273 274 ci->rev = ci_get_revision(ci); 275 276 dev_dbg(ci->dev, 277 "ChipIdea HDRC found, revision: %d, lpm: %d; cap: %p op: %p\n", 278 ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op); 279 280 /* setup lock mode ? */ 281 282 /* ENDPTSETUPSTAT is '0' by default */ 283 284 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */ 285 286 return 0; 287 } 288 289 static void hw_phymode_configure(struct ci_hdrc *ci) 290 { 291 u32 portsc, lpm, sts = 0; 292 293 switch (ci->platdata->phy_mode) { 294 case USBPHY_INTERFACE_MODE_UTMI: 295 portsc = PORTSC_PTS(PTS_UTMI); 296 lpm = DEVLC_PTS(PTS_UTMI); 297 break; 298 case USBPHY_INTERFACE_MODE_UTMIW: 299 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW; 300 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW; 301 break; 302 case USBPHY_INTERFACE_MODE_ULPI: 303 portsc = PORTSC_PTS(PTS_ULPI); 304 lpm = DEVLC_PTS(PTS_ULPI); 305 break; 306 case USBPHY_INTERFACE_MODE_SERIAL: 307 portsc = PORTSC_PTS(PTS_SERIAL); 308 lpm = DEVLC_PTS(PTS_SERIAL); 309 sts = 1; 310 break; 311 case USBPHY_INTERFACE_MODE_HSIC: 312 portsc = PORTSC_PTS(PTS_HSIC); 313 lpm = DEVLC_PTS(PTS_HSIC); 314 break; 315 default: 316 return; 317 } 318 319 if (ci->hw_bank.lpm) { 320 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm); 321 if (sts) 322 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS); 323 } else { 324 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc); 325 if (sts) 326 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS); 327 } 328 } 329 330 /** 331 * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy 332 * interfaces 333 * @ci: the controller 334 * 335 * This function returns an error code if the phy failed to init 336 */ 337 static int _ci_usb_phy_init(struct ci_hdrc *ci) 338 { 339 int ret; 340 341 if (ci->phy) { 342 ret = phy_init(ci->phy); 343 if (ret) 344 return ret; 345 346 ret = phy_power_on(ci->phy); 347 if (ret) { 348 phy_exit(ci->phy); 349 return ret; 350 } 351 } else { 352 ret = usb_phy_init(ci->usb_phy); 353 } 354 355 return ret; 356 } 357 358 /** 359 * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy 360 * interfaces 361 * @ci: the controller 362 */ 363 static void ci_usb_phy_exit(struct ci_hdrc *ci) 364 { 365 if (ci->phy) { 366 phy_power_off(ci->phy); 367 phy_exit(ci->phy); 368 } else { 369 usb_phy_shutdown(ci->usb_phy); 370 } 371 } 372 373 /** 374 * ci_usb_phy_init: initialize phy according to different phy type 375 * @ci: the controller 376 * 377 * This function returns an error code if usb_phy_init has failed 378 */ 379 static int ci_usb_phy_init(struct ci_hdrc *ci) 380 { 381 int ret; 382 383 switch (ci->platdata->phy_mode) { 384 case USBPHY_INTERFACE_MODE_UTMI: 385 case USBPHY_INTERFACE_MODE_UTMIW: 386 case USBPHY_INTERFACE_MODE_HSIC: 387 ret = _ci_usb_phy_init(ci); 388 if (!ret) 389 hw_wait_phy_stable(); 390 else 391 return ret; 392 hw_phymode_configure(ci); 393 break; 394 case USBPHY_INTERFACE_MODE_ULPI: 395 case USBPHY_INTERFACE_MODE_SERIAL: 396 hw_phymode_configure(ci); 397 ret = _ci_usb_phy_init(ci); 398 if (ret) 399 return ret; 400 break; 401 default: 402 ret = _ci_usb_phy_init(ci); 403 if (!ret) 404 hw_wait_phy_stable(); 405 } 406 407 return ret; 408 } 409 410 411 /** 412 * ci_platform_configure: do controller configure 413 * @ci: the controller 414 * 415 */ 416 void ci_platform_configure(struct ci_hdrc *ci) 417 { 418 bool is_device_mode, is_host_mode; 419 420 is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC; 421 is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC; 422 423 if (is_device_mode && 424 (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING)) 425 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS); 426 427 if (is_host_mode && 428 (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING)) 429 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS); 430 431 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) { 432 if (ci->hw_bank.lpm) 433 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC); 434 else 435 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC); 436 } 437 438 if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA) 439 hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA); 440 441 hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16); 442 443 if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST) 444 hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK, 445 ci->platdata->ahb_burst_config); 446 447 /* override burst size, take effect only when ahb_burst_config is 0 */ 448 if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) { 449 if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST) 450 hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK, 451 ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK)); 452 453 if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST) 454 hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK, 455 ci->platdata->rx_burst_size); 456 } 457 } 458 459 /** 460 * hw_controller_reset: do controller reset 461 * @ci: the controller 462 * 463 * This function returns an error code 464 */ 465 static int hw_controller_reset(struct ci_hdrc *ci) 466 { 467 int count = 0; 468 469 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST); 470 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) { 471 udelay(10); 472 if (count++ > 1000) 473 return -ETIMEDOUT; 474 } 475 476 return 0; 477 } 478 479 /** 480 * hw_device_reset: resets chip (execute without interruption) 481 * @ci: the controller 482 * 483 * This function returns an error code 484 */ 485 int hw_device_reset(struct ci_hdrc *ci) 486 { 487 int ret; 488 489 /* should flush & stop before reset */ 490 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0); 491 hw_write(ci, OP_USBCMD, USBCMD_RS, 0); 492 493 ret = hw_controller_reset(ci); 494 if (ret) { 495 dev_err(ci->dev, "error resetting controller, ret=%d\n", ret); 496 return ret; 497 } 498 499 if (ci->platdata->notify_event) 500 ci->platdata->notify_event(ci, 501 CI_HDRC_CONTROLLER_RESET_EVENT); 502 503 /* USBMODE should be configured step by step */ 504 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE); 505 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC); 506 /* HW >= 2.3 */ 507 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); 508 509 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) { 510 pr_err("cannot enter in %s device mode", ci_role(ci)->name); 511 pr_err("lpm = %i", ci->hw_bank.lpm); 512 return -ENODEV; 513 } 514 515 ci_platform_configure(ci); 516 517 return 0; 518 } 519 520 /** 521 * hw_wait_reg: wait the register value 522 * 523 * Sometimes, it needs to wait register value before going on. 524 * Eg, when switch to device mode, the vbus value should be lower 525 * than OTGSC_BSV before connects to host. 526 * 527 * @ci: the controller 528 * @reg: register index 529 * @mask: mast bit 530 * @value: the bit value to wait 531 * @timeout_ms: timeout in millisecond 532 * 533 * This function returns an error code if timeout 534 */ 535 int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask, 536 u32 value, unsigned int timeout_ms) 537 { 538 unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms); 539 540 while (hw_read(ci, reg, mask) != value) { 541 if (time_after(jiffies, elapse)) { 542 dev_err(ci->dev, "timeout waiting for %08x in %d\n", 543 mask, reg); 544 return -ETIMEDOUT; 545 } 546 msleep(20); 547 } 548 549 return 0; 550 } 551 552 static irqreturn_t ci_irq(int irq, void *data) 553 { 554 struct ci_hdrc *ci = data; 555 irqreturn_t ret = IRQ_NONE; 556 u32 otgsc = 0; 557 558 if (ci->in_lpm) { 559 disable_irq_nosync(irq); 560 ci->wakeup_int = true; 561 pm_runtime_get(ci->dev); 562 return IRQ_HANDLED; 563 } 564 565 if (ci->is_otg) { 566 otgsc = hw_read_otgsc(ci, ~0); 567 if (ci_otg_is_fsm_mode(ci)) { 568 ret = ci_otg_fsm_irq(ci); 569 if (ret == IRQ_HANDLED) 570 return ret; 571 } 572 } 573 574 /* 575 * Handle id change interrupt, it indicates device/host function 576 * switch. 577 */ 578 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) { 579 ci->id_event = true; 580 /* Clear ID change irq status */ 581 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS); 582 ci_otg_queue_work(ci); 583 return IRQ_HANDLED; 584 } 585 586 /* 587 * Handle vbus change interrupt, it indicates device connection 588 * and disconnection events. 589 */ 590 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) { 591 ci->b_sess_valid_event = true; 592 /* Clear BSV irq */ 593 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS); 594 ci_otg_queue_work(ci); 595 return IRQ_HANDLED; 596 } 597 598 /* Handle device/host interrupt */ 599 if (ci->role != CI_ROLE_END) 600 ret = ci_role(ci)->irq(ci); 601 602 return ret; 603 } 604 605 static int ci_get_platdata(struct device *dev, 606 struct ci_hdrc_platform_data *platdata) 607 { 608 int ret; 609 610 if (!platdata->phy_mode) 611 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node); 612 613 if (!platdata->dr_mode) 614 platdata->dr_mode = of_usb_get_dr_mode(dev->of_node); 615 616 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN) 617 platdata->dr_mode = USB_DR_MODE_OTG; 618 619 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) { 620 /* Get the vbus regulator */ 621 platdata->reg_vbus = devm_regulator_get(dev, "vbus"); 622 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) { 623 return -EPROBE_DEFER; 624 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) { 625 /* no vbus regulator is needed */ 626 platdata->reg_vbus = NULL; 627 } else if (IS_ERR(platdata->reg_vbus)) { 628 dev_err(dev, "Getting regulator error: %ld\n", 629 PTR_ERR(platdata->reg_vbus)); 630 return PTR_ERR(platdata->reg_vbus); 631 } 632 /* Get TPL support */ 633 if (!platdata->tpl_support) 634 platdata->tpl_support = 635 of_usb_host_tpl_support(dev->of_node); 636 } 637 638 if (platdata->dr_mode == USB_DR_MODE_OTG) { 639 /* We can support HNP and SRP of OTG 2.0 */ 640 platdata->ci_otg_caps.otg_rev = 0x0200; 641 platdata->ci_otg_caps.hnp_support = true; 642 platdata->ci_otg_caps.srp_support = true; 643 644 /* Update otg capabilities by DT properties */ 645 ret = of_usb_update_otg_caps(dev->of_node, 646 &platdata->ci_otg_caps); 647 if (ret) 648 return ret; 649 } 650 651 if (of_usb_get_maximum_speed(dev->of_node) == USB_SPEED_FULL) 652 platdata->flags |= CI_HDRC_FORCE_FULLSPEED; 653 654 platdata->itc_setting = 1; 655 if (of_find_property(dev->of_node, "itc-setting", NULL)) { 656 ret = of_property_read_u32(dev->of_node, "itc-setting", 657 &platdata->itc_setting); 658 if (ret) { 659 dev_err(dev, 660 "failed to get itc-setting\n"); 661 return ret; 662 } 663 } 664 665 if (of_find_property(dev->of_node, "ahb-burst-config", NULL)) { 666 ret = of_property_read_u32(dev->of_node, "ahb-burst-config", 667 &platdata->ahb_burst_config); 668 if (ret) { 669 dev_err(dev, 670 "failed to get ahb-burst-config\n"); 671 return ret; 672 } 673 platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST; 674 } 675 676 if (of_find_property(dev->of_node, "tx-burst-size-dword", NULL)) { 677 ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword", 678 &platdata->tx_burst_size); 679 if (ret) { 680 dev_err(dev, 681 "failed to get tx-burst-size-dword\n"); 682 return ret; 683 } 684 platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST; 685 } 686 687 if (of_find_property(dev->of_node, "rx-burst-size-dword", NULL)) { 688 ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword", 689 &platdata->rx_burst_size); 690 if (ret) { 691 dev_err(dev, 692 "failed to get rx-burst-size-dword\n"); 693 return ret; 694 } 695 platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST; 696 } 697 698 return 0; 699 } 700 701 static DEFINE_IDA(ci_ida); 702 703 struct platform_device *ci_hdrc_add_device(struct device *dev, 704 struct resource *res, int nres, 705 struct ci_hdrc_platform_data *platdata) 706 { 707 struct platform_device *pdev; 708 int id, ret; 709 710 ret = ci_get_platdata(dev, platdata); 711 if (ret) 712 return ERR_PTR(ret); 713 714 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL); 715 if (id < 0) 716 return ERR_PTR(id); 717 718 pdev = platform_device_alloc("ci_hdrc", id); 719 if (!pdev) { 720 ret = -ENOMEM; 721 goto put_id; 722 } 723 724 pdev->dev.parent = dev; 725 pdev->dev.dma_mask = dev->dma_mask; 726 pdev->dev.dma_parms = dev->dma_parms; 727 dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask); 728 729 ret = platform_device_add_resources(pdev, res, nres); 730 if (ret) 731 goto err; 732 733 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata)); 734 if (ret) 735 goto err; 736 737 ret = platform_device_add(pdev); 738 if (ret) 739 goto err; 740 741 return pdev; 742 743 err: 744 platform_device_put(pdev); 745 put_id: 746 ida_simple_remove(&ci_ida, id); 747 return ERR_PTR(ret); 748 } 749 EXPORT_SYMBOL_GPL(ci_hdrc_add_device); 750 751 void ci_hdrc_remove_device(struct platform_device *pdev) 752 { 753 int id = pdev->id; 754 platform_device_unregister(pdev); 755 ida_simple_remove(&ci_ida, id); 756 } 757 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device); 758 759 static inline void ci_role_destroy(struct ci_hdrc *ci) 760 { 761 ci_hdrc_gadget_destroy(ci); 762 ci_hdrc_host_destroy(ci); 763 if (ci->is_otg) 764 ci_hdrc_otg_destroy(ci); 765 } 766 767 static void ci_get_otg_capable(struct ci_hdrc *ci) 768 { 769 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG) 770 ci->is_otg = false; 771 else 772 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS, 773 DCCPARAMS_DC | DCCPARAMS_HC) 774 == (DCCPARAMS_DC | DCCPARAMS_HC)); 775 if (ci->is_otg) { 776 dev_dbg(ci->dev, "It is OTG capable controller\n"); 777 /* Disable and clear all OTG irq */ 778 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS, 779 OTGSC_INT_STATUS_BITS); 780 } 781 } 782 783 static int ci_hdrc_probe(struct platform_device *pdev) 784 { 785 struct device *dev = &pdev->dev; 786 struct ci_hdrc *ci; 787 struct resource *res; 788 void __iomem *base; 789 int ret; 790 enum usb_dr_mode dr_mode; 791 792 if (!dev_get_platdata(dev)) { 793 dev_err(dev, "platform data missing\n"); 794 return -ENODEV; 795 } 796 797 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 798 base = devm_ioremap_resource(dev, res); 799 if (IS_ERR(base)) 800 return PTR_ERR(base); 801 802 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL); 803 if (!ci) 804 return -ENOMEM; 805 806 ci->dev = dev; 807 ci->platdata = dev_get_platdata(dev); 808 ci->imx28_write_fix = !!(ci->platdata->flags & 809 CI_HDRC_IMX28_WRITE_FIX); 810 ci->supports_runtime_pm = !!(ci->platdata->flags & 811 CI_HDRC_SUPPORTS_RUNTIME_PM); 812 813 ret = hw_device_init(ci, base); 814 if (ret < 0) { 815 dev_err(dev, "can't initialize hardware\n"); 816 return -ENODEV; 817 } 818 819 if (ci->platdata->phy) { 820 ci->phy = ci->platdata->phy; 821 } else if (ci->platdata->usb_phy) { 822 ci->usb_phy = ci->platdata->usb_phy; 823 } else { 824 ci->phy = devm_phy_get(dev->parent, "usb-phy"); 825 ci->usb_phy = devm_usb_get_phy(dev->parent, USB_PHY_TYPE_USB2); 826 827 /* if both generic PHY and USB PHY layers aren't enabled */ 828 if (PTR_ERR(ci->phy) == -ENOSYS && 829 PTR_ERR(ci->usb_phy) == -ENXIO) 830 return -ENXIO; 831 832 if (IS_ERR(ci->phy) && IS_ERR(ci->usb_phy)) 833 return -EPROBE_DEFER; 834 835 if (IS_ERR(ci->phy)) 836 ci->phy = NULL; 837 else if (IS_ERR(ci->usb_phy)) 838 ci->usb_phy = NULL; 839 } 840 841 ret = ci_usb_phy_init(ci); 842 if (ret) { 843 dev_err(dev, "unable to init phy: %d\n", ret); 844 return ret; 845 } 846 847 ci->hw_bank.phys = res->start; 848 849 ci->irq = platform_get_irq(pdev, 0); 850 if (ci->irq < 0) { 851 dev_err(dev, "missing IRQ\n"); 852 ret = ci->irq; 853 goto deinit_phy; 854 } 855 856 ci_get_otg_capable(ci); 857 858 dr_mode = ci->platdata->dr_mode; 859 /* initialize role(s) before the interrupt is requested */ 860 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) { 861 ret = ci_hdrc_host_init(ci); 862 if (ret) 863 dev_info(dev, "doesn't support host\n"); 864 } 865 866 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) { 867 ret = ci_hdrc_gadget_init(ci); 868 if (ret) 869 dev_info(dev, "doesn't support gadget\n"); 870 } 871 872 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) { 873 dev_err(dev, "no supported roles\n"); 874 ret = -ENODEV; 875 goto deinit_phy; 876 } 877 878 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) { 879 ret = ci_hdrc_otg_init(ci); 880 if (ret) { 881 dev_err(dev, "init otg fails, ret = %d\n", ret); 882 goto stop; 883 } 884 } 885 886 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) { 887 if (ci->is_otg) { 888 ci->role = ci_otg_role(ci); 889 /* Enable ID change irq */ 890 hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE); 891 } else { 892 /* 893 * If the controller is not OTG capable, but support 894 * role switch, the defalt role is gadget, and the 895 * user can switch it through debugfs. 896 */ 897 ci->role = CI_ROLE_GADGET; 898 } 899 } else { 900 ci->role = ci->roles[CI_ROLE_HOST] 901 ? CI_ROLE_HOST 902 : CI_ROLE_GADGET; 903 } 904 905 if (!ci_otg_is_fsm_mode(ci)) { 906 /* only update vbus status for peripheral */ 907 if (ci->role == CI_ROLE_GADGET) 908 ci_handle_vbus_change(ci); 909 910 ret = ci_role_start(ci, ci->role); 911 if (ret) { 912 dev_err(dev, "can't start %s role\n", 913 ci_role(ci)->name); 914 goto stop; 915 } 916 } 917 918 platform_set_drvdata(pdev, ci); 919 ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED, 920 ci->platdata->name, ci); 921 if (ret) 922 goto stop; 923 924 if (ci->supports_runtime_pm) { 925 pm_runtime_set_active(&pdev->dev); 926 pm_runtime_enable(&pdev->dev); 927 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000); 928 pm_runtime_mark_last_busy(ci->dev); 929 pm_runtime_use_autosuspend(&pdev->dev); 930 } 931 932 if (ci_otg_is_fsm_mode(ci)) 933 ci_hdrc_otg_fsm_start(ci); 934 935 device_set_wakeup_capable(&pdev->dev, true); 936 937 ret = dbg_create_files(ci); 938 if (!ret) 939 return 0; 940 941 stop: 942 ci_role_destroy(ci); 943 deinit_phy: 944 ci_usb_phy_exit(ci); 945 946 return ret; 947 } 948 949 static int ci_hdrc_remove(struct platform_device *pdev) 950 { 951 struct ci_hdrc *ci = platform_get_drvdata(pdev); 952 953 if (ci->supports_runtime_pm) { 954 pm_runtime_get_sync(&pdev->dev); 955 pm_runtime_disable(&pdev->dev); 956 pm_runtime_put_noidle(&pdev->dev); 957 } 958 959 dbg_remove_files(ci); 960 ci_role_destroy(ci); 961 ci_hdrc_enter_lpm(ci, true); 962 ci_usb_phy_exit(ci); 963 964 return 0; 965 } 966 967 #ifdef CONFIG_PM 968 /* Prepare wakeup by SRP before suspend */ 969 static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci) 970 { 971 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) && 972 !hw_read_otgsc(ci, OTGSC_ID)) { 973 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP, 974 PORTSC_PP); 975 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN, 976 PORTSC_WKCN); 977 } 978 } 979 980 /* Handle SRP when wakeup by data pulse */ 981 static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci) 982 { 983 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) && 984 (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) { 985 if (!hw_read_otgsc(ci, OTGSC_ID)) { 986 ci->fsm.a_srp_det = 1; 987 ci->fsm.a_bus_drop = 0; 988 } else { 989 ci->fsm.id = 1; 990 } 991 ci_otg_queue_work(ci); 992 } 993 } 994 995 static void ci_controller_suspend(struct ci_hdrc *ci) 996 { 997 disable_irq(ci->irq); 998 ci_hdrc_enter_lpm(ci, true); 999 usb_phy_set_suspend(ci->usb_phy, 1); 1000 ci->in_lpm = true; 1001 enable_irq(ci->irq); 1002 } 1003 1004 static int ci_controller_resume(struct device *dev) 1005 { 1006 struct ci_hdrc *ci = dev_get_drvdata(dev); 1007 1008 dev_dbg(dev, "at %s\n", __func__); 1009 1010 if (!ci->in_lpm) { 1011 WARN_ON(1); 1012 return 0; 1013 } 1014 1015 ci_hdrc_enter_lpm(ci, false); 1016 if (ci->usb_phy) { 1017 usb_phy_set_suspend(ci->usb_phy, 0); 1018 usb_phy_set_wakeup(ci->usb_phy, false); 1019 hw_wait_phy_stable(); 1020 } 1021 1022 ci->in_lpm = false; 1023 if (ci->wakeup_int) { 1024 ci->wakeup_int = false; 1025 pm_runtime_mark_last_busy(ci->dev); 1026 pm_runtime_put_autosuspend(ci->dev); 1027 enable_irq(ci->irq); 1028 if (ci_otg_is_fsm_mode(ci)) 1029 ci_otg_fsm_wakeup_by_srp(ci); 1030 } 1031 1032 return 0; 1033 } 1034 1035 #ifdef CONFIG_PM_SLEEP 1036 static int ci_suspend(struct device *dev) 1037 { 1038 struct ci_hdrc *ci = dev_get_drvdata(dev); 1039 1040 if (ci->wq) 1041 flush_workqueue(ci->wq); 1042 /* 1043 * Controller needs to be active during suspend, otherwise the core 1044 * may run resume when the parent is at suspend if other driver's 1045 * suspend fails, it occurs before parent's suspend has not started, 1046 * but the core suspend has finished. 1047 */ 1048 if (ci->in_lpm) 1049 pm_runtime_resume(dev); 1050 1051 if (ci->in_lpm) { 1052 WARN_ON(1); 1053 return 0; 1054 } 1055 1056 if (device_may_wakeup(dev)) { 1057 if (ci_otg_is_fsm_mode(ci)) 1058 ci_otg_fsm_suspend_for_srp(ci); 1059 1060 usb_phy_set_wakeup(ci->usb_phy, true); 1061 enable_irq_wake(ci->irq); 1062 } 1063 1064 ci_controller_suspend(ci); 1065 1066 return 0; 1067 } 1068 1069 static int ci_resume(struct device *dev) 1070 { 1071 struct ci_hdrc *ci = dev_get_drvdata(dev); 1072 int ret; 1073 1074 if (device_may_wakeup(dev)) 1075 disable_irq_wake(ci->irq); 1076 1077 ret = ci_controller_resume(dev); 1078 if (ret) 1079 return ret; 1080 1081 if (ci->supports_runtime_pm) { 1082 pm_runtime_disable(dev); 1083 pm_runtime_set_active(dev); 1084 pm_runtime_enable(dev); 1085 } 1086 1087 return ret; 1088 } 1089 #endif /* CONFIG_PM_SLEEP */ 1090 1091 static int ci_runtime_suspend(struct device *dev) 1092 { 1093 struct ci_hdrc *ci = dev_get_drvdata(dev); 1094 1095 dev_dbg(dev, "at %s\n", __func__); 1096 1097 if (ci->in_lpm) { 1098 WARN_ON(1); 1099 return 0; 1100 } 1101 1102 if (ci_otg_is_fsm_mode(ci)) 1103 ci_otg_fsm_suspend_for_srp(ci); 1104 1105 usb_phy_set_wakeup(ci->usb_phy, true); 1106 ci_controller_suspend(ci); 1107 1108 return 0; 1109 } 1110 1111 static int ci_runtime_resume(struct device *dev) 1112 { 1113 return ci_controller_resume(dev); 1114 } 1115 1116 #endif /* CONFIG_PM */ 1117 static const struct dev_pm_ops ci_pm_ops = { 1118 SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume) 1119 SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL) 1120 }; 1121 1122 static struct platform_driver ci_hdrc_driver = { 1123 .probe = ci_hdrc_probe, 1124 .remove = ci_hdrc_remove, 1125 .driver = { 1126 .name = "ci_hdrc", 1127 .pm = &ci_pm_ops, 1128 }, 1129 }; 1130 1131 static int __init ci_hdrc_platform_register(void) 1132 { 1133 ci_hdrc_host_driver_init(); 1134 return platform_driver_register(&ci_hdrc_driver); 1135 } 1136 module_init(ci_hdrc_platform_register); 1137 1138 static void __exit ci_hdrc_platform_unregister(void) 1139 { 1140 platform_driver_unregister(&ci_hdrc_driver); 1141 } 1142 module_exit(ci_hdrc_platform_unregister); 1143 1144 MODULE_ALIAS("platform:ci_hdrc"); 1145 MODULE_LICENSE("GPL v2"); 1146 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>"); 1147 MODULE_DESCRIPTION("ChipIdea HDRC Driver"); 1148