1 /* 2 * core.c - ChipIdea USB IP core family device controller 3 * 4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. 5 * 6 * Author: David Lopo 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 /* 14 * Description: ChipIdea USB IP core family device controller 15 * 16 * This driver is composed of several blocks: 17 * - HW: hardware interface 18 * - DBG: debug facilities (optional) 19 * - UTIL: utilities 20 * - ISR: interrupts handling 21 * - ENDPT: endpoint operations (Gadget API) 22 * - GADGET: gadget operations (Gadget API) 23 * - BUS: bus glue code, bus abstraction layer 24 * 25 * Compile Options 26 * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities 27 * - STALL_IN: non-empty bulk-in pipes cannot be halted 28 * if defined mass storage compliance succeeds but with warnings 29 * => case 4: Hi > Dn 30 * => case 5: Hi > Di 31 * => case 8: Hi <> Do 32 * if undefined usbtest 13 fails 33 * - TRACE: enable function tracing (depends on DEBUG) 34 * 35 * Main Features 36 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage 37 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined) 38 * - Normal & LPM support 39 * 40 * USBTEST Report 41 * - OK: 0-12, 13 (STALL_IN defined) & 14 42 * - Not Supported: 15 & 16 (ISO) 43 * 44 * TODO List 45 * - OTG 46 * - Interrupt Traffic 47 * - GET_STATUS(device) - always reports 0 48 * - Gadget API (majority of optional features) 49 * - Suspend & Remote Wakeup 50 */ 51 #include <linux/delay.h> 52 #include <linux/device.h> 53 #include <linux/dma-mapping.h> 54 #include <linux/platform_device.h> 55 #include <linux/module.h> 56 #include <linux/idr.h> 57 #include <linux/interrupt.h> 58 #include <linux/io.h> 59 #include <linux/kernel.h> 60 #include <linux/slab.h> 61 #include <linux/pm_runtime.h> 62 #include <linux/usb/ch9.h> 63 #include <linux/usb/gadget.h> 64 #include <linux/usb/otg.h> 65 #include <linux/usb/chipidea.h> 66 #include <linux/usb/of.h> 67 #include <linux/phy.h> 68 #include <linux/regulator/consumer.h> 69 70 #include "ci.h" 71 #include "udc.h" 72 #include "bits.h" 73 #include "host.h" 74 #include "debug.h" 75 #include "otg.h" 76 77 /* Controller register map */ 78 static uintptr_t ci_regs_nolpm[] = { 79 [CAP_CAPLENGTH] = 0x000UL, 80 [CAP_HCCPARAMS] = 0x008UL, 81 [CAP_DCCPARAMS] = 0x024UL, 82 [CAP_TESTMODE] = 0x038UL, 83 [OP_USBCMD] = 0x000UL, 84 [OP_USBSTS] = 0x004UL, 85 [OP_USBINTR] = 0x008UL, 86 [OP_DEVICEADDR] = 0x014UL, 87 [OP_ENDPTLISTADDR] = 0x018UL, 88 [OP_PORTSC] = 0x044UL, 89 [OP_DEVLC] = 0x084UL, 90 [OP_OTGSC] = 0x064UL, 91 [OP_USBMODE] = 0x068UL, 92 [OP_ENDPTSETUPSTAT] = 0x06CUL, 93 [OP_ENDPTPRIME] = 0x070UL, 94 [OP_ENDPTFLUSH] = 0x074UL, 95 [OP_ENDPTSTAT] = 0x078UL, 96 [OP_ENDPTCOMPLETE] = 0x07CUL, 97 [OP_ENDPTCTRL] = 0x080UL, 98 }; 99 100 static uintptr_t ci_regs_lpm[] = { 101 [CAP_CAPLENGTH] = 0x000UL, 102 [CAP_HCCPARAMS] = 0x008UL, 103 [CAP_DCCPARAMS] = 0x024UL, 104 [CAP_TESTMODE] = 0x0FCUL, 105 [OP_USBCMD] = 0x000UL, 106 [OP_USBSTS] = 0x004UL, 107 [OP_USBINTR] = 0x008UL, 108 [OP_DEVICEADDR] = 0x014UL, 109 [OP_ENDPTLISTADDR] = 0x018UL, 110 [OP_PORTSC] = 0x044UL, 111 [OP_DEVLC] = 0x084UL, 112 [OP_OTGSC] = 0x0C4UL, 113 [OP_USBMODE] = 0x0C8UL, 114 [OP_ENDPTSETUPSTAT] = 0x0D8UL, 115 [OP_ENDPTPRIME] = 0x0DCUL, 116 [OP_ENDPTFLUSH] = 0x0E0UL, 117 [OP_ENDPTSTAT] = 0x0E4UL, 118 [OP_ENDPTCOMPLETE] = 0x0E8UL, 119 [OP_ENDPTCTRL] = 0x0ECUL, 120 }; 121 122 static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm) 123 { 124 int i; 125 126 kfree(ci->hw_bank.regmap); 127 128 ci->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *), 129 GFP_KERNEL); 130 if (!ci->hw_bank.regmap) 131 return -ENOMEM; 132 133 for (i = 0; i < OP_ENDPTCTRL; i++) 134 ci->hw_bank.regmap[i] = 135 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) + 136 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]); 137 138 for (; i <= OP_LAST; i++) 139 ci->hw_bank.regmap[i] = ci->hw_bank.op + 140 4 * (i - OP_ENDPTCTRL) + 141 (is_lpm 142 ? ci_regs_lpm[OP_ENDPTCTRL] 143 : ci_regs_nolpm[OP_ENDPTCTRL]); 144 145 return 0; 146 } 147 148 /** 149 * hw_port_test_set: writes port test mode (execute without interruption) 150 * @mode: new value 151 * 152 * This function returns an error code 153 */ 154 int hw_port_test_set(struct ci_hdrc *ci, u8 mode) 155 { 156 const u8 TEST_MODE_MAX = 7; 157 158 if (mode > TEST_MODE_MAX) 159 return -EINVAL; 160 161 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC)); 162 return 0; 163 } 164 165 /** 166 * hw_port_test_get: reads port test mode value 167 * 168 * This function returns port test mode value 169 */ 170 u8 hw_port_test_get(struct ci_hdrc *ci) 171 { 172 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC); 173 } 174 175 /* The PHY enters/leaves low power mode */ 176 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable) 177 { 178 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC; 179 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm))); 180 181 if (enable && !lpm) { 182 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), 183 PORTSC_PHCD(ci->hw_bank.lpm)); 184 } else if (!enable && lpm) { 185 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), 186 0); 187 /* 188 * The controller needs at least 1ms to reflect 189 * PHY's status, the PHY also needs some time (less 190 * than 1ms) to leave low power mode. 191 */ 192 usleep_range(1500, 2000); 193 } 194 } 195 196 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base) 197 { 198 u32 reg; 199 200 /* bank is a module variable */ 201 ci->hw_bank.abs = base; 202 203 ci->hw_bank.cap = ci->hw_bank.abs; 204 ci->hw_bank.cap += ci->platdata->capoffset; 205 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff); 206 207 hw_alloc_regmap(ci, false); 208 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >> 209 __ffs(HCCPARAMS_LEN); 210 ci->hw_bank.lpm = reg; 211 hw_alloc_regmap(ci, !!reg); 212 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs; 213 ci->hw_bank.size += OP_LAST; 214 ci->hw_bank.size /= sizeof(u32); 215 216 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >> 217 __ffs(DCCPARAMS_DEN); 218 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */ 219 220 if (ci->hw_ep_max > ENDPT_MAX) 221 return -ENODEV; 222 223 ci_hdrc_enter_lpm(ci, false); 224 225 /* Disable all interrupts bits */ 226 hw_write(ci, OP_USBINTR, 0xffffffff, 0); 227 228 /* Clear all interrupts status bits*/ 229 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff); 230 231 dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n", 232 ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op); 233 234 /* setup lock mode ? */ 235 236 /* ENDPTSETUPSTAT is '0' by default */ 237 238 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */ 239 240 return 0; 241 } 242 243 static void hw_phymode_configure(struct ci_hdrc *ci) 244 { 245 u32 portsc, lpm, sts; 246 247 switch (ci->platdata->phy_mode) { 248 case USBPHY_INTERFACE_MODE_UTMI: 249 portsc = PORTSC_PTS(PTS_UTMI); 250 lpm = DEVLC_PTS(PTS_UTMI); 251 break; 252 case USBPHY_INTERFACE_MODE_UTMIW: 253 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW; 254 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW; 255 break; 256 case USBPHY_INTERFACE_MODE_ULPI: 257 portsc = PORTSC_PTS(PTS_ULPI); 258 lpm = DEVLC_PTS(PTS_ULPI); 259 break; 260 case USBPHY_INTERFACE_MODE_SERIAL: 261 portsc = PORTSC_PTS(PTS_SERIAL); 262 lpm = DEVLC_PTS(PTS_SERIAL); 263 sts = 1; 264 break; 265 case USBPHY_INTERFACE_MODE_HSIC: 266 portsc = PORTSC_PTS(PTS_HSIC); 267 lpm = DEVLC_PTS(PTS_HSIC); 268 break; 269 default: 270 return; 271 } 272 273 if (ci->hw_bank.lpm) { 274 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm); 275 hw_write(ci, OP_DEVLC, DEVLC_STS, sts); 276 } else { 277 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc); 278 hw_write(ci, OP_PORTSC, PORTSC_STS, sts); 279 } 280 } 281 282 /** 283 * hw_device_reset: resets chip (execute without interruption) 284 * @ci: the controller 285 * 286 * This function returns an error code 287 */ 288 int hw_device_reset(struct ci_hdrc *ci, u32 mode) 289 { 290 /* should flush & stop before reset */ 291 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0); 292 hw_write(ci, OP_USBCMD, USBCMD_RS, 0); 293 294 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST); 295 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) 296 udelay(10); /* not RTOS friendly */ 297 298 if (ci->platdata->notify_event) 299 ci->platdata->notify_event(ci, 300 CI_HDRC_CONTROLLER_RESET_EVENT); 301 302 if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING) 303 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS); 304 305 /* USBMODE should be configured step by step */ 306 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE); 307 hw_write(ci, OP_USBMODE, USBMODE_CM, mode); 308 /* HW >= 2.3 */ 309 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); 310 311 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) { 312 pr_err("cannot enter in %s mode", ci_role(ci)->name); 313 pr_err("lpm = %i", ci->hw_bank.lpm); 314 return -ENODEV; 315 } 316 317 return 0; 318 } 319 320 /** 321 * hw_wait_reg: wait the register value 322 * 323 * Sometimes, it needs to wait register value before going on. 324 * Eg, when switch to device mode, the vbus value should be lower 325 * than OTGSC_BSV before connects to host. 326 * 327 * @ci: the controller 328 * @reg: register index 329 * @mask: mast bit 330 * @value: the bit value to wait 331 * @timeout_ms: timeout in millisecond 332 * 333 * This function returns an error code if timeout 334 */ 335 int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask, 336 u32 value, unsigned int timeout_ms) 337 { 338 unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms); 339 340 while (hw_read(ci, reg, mask) != value) { 341 if (time_after(jiffies, elapse)) { 342 dev_err(ci->dev, "timeout waiting for %08x in %d\n", 343 mask, reg); 344 return -ETIMEDOUT; 345 } 346 msleep(20); 347 } 348 349 return 0; 350 } 351 352 static irqreturn_t ci_irq(int irq, void *data) 353 { 354 struct ci_hdrc *ci = data; 355 irqreturn_t ret = IRQ_NONE; 356 u32 otgsc = 0; 357 358 if (ci->is_otg) 359 otgsc = hw_read(ci, OP_OTGSC, ~0); 360 361 /* 362 * Handle id change interrupt, it indicates device/host function 363 * switch. 364 */ 365 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) { 366 ci->id_event = true; 367 ci_clear_otg_interrupt(ci, OTGSC_IDIS); 368 disable_irq_nosync(ci->irq); 369 queue_work(ci->wq, &ci->work); 370 return IRQ_HANDLED; 371 } 372 373 /* 374 * Handle vbus change interrupt, it indicates device connection 375 * and disconnection events. 376 */ 377 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) { 378 ci->b_sess_valid_event = true; 379 ci_clear_otg_interrupt(ci, OTGSC_BSVIS); 380 disable_irq_nosync(ci->irq); 381 queue_work(ci->wq, &ci->work); 382 return IRQ_HANDLED; 383 } 384 385 /* Handle device/host interrupt */ 386 if (ci->role != CI_ROLE_END) 387 ret = ci_role(ci)->irq(ci); 388 389 return ret; 390 } 391 392 static int ci_get_platdata(struct device *dev, 393 struct ci_hdrc_platform_data *platdata) 394 { 395 if (!platdata->phy_mode) 396 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node); 397 398 if (!platdata->dr_mode) 399 platdata->dr_mode = of_usb_get_dr_mode(dev->of_node); 400 401 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN) 402 platdata->dr_mode = USB_DR_MODE_OTG; 403 404 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) { 405 /* Get the vbus regulator */ 406 platdata->reg_vbus = devm_regulator_get(dev, "vbus"); 407 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) { 408 return -EPROBE_DEFER; 409 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) { 410 /* no vbus regualator is needed */ 411 platdata->reg_vbus = NULL; 412 } else if (IS_ERR(platdata->reg_vbus)) { 413 dev_err(dev, "Getting regulator error: %ld\n", 414 PTR_ERR(platdata->reg_vbus)); 415 return PTR_ERR(platdata->reg_vbus); 416 } 417 } 418 419 return 0; 420 } 421 422 static DEFINE_IDA(ci_ida); 423 424 struct platform_device *ci_hdrc_add_device(struct device *dev, 425 struct resource *res, int nres, 426 struct ci_hdrc_platform_data *platdata) 427 { 428 struct platform_device *pdev; 429 int id, ret; 430 431 ret = ci_get_platdata(dev, platdata); 432 if (ret) 433 return ERR_PTR(ret); 434 435 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL); 436 if (id < 0) 437 return ERR_PTR(id); 438 439 pdev = platform_device_alloc("ci_hdrc", id); 440 if (!pdev) { 441 ret = -ENOMEM; 442 goto put_id; 443 } 444 445 pdev->dev.parent = dev; 446 pdev->dev.dma_mask = dev->dma_mask; 447 pdev->dev.dma_parms = dev->dma_parms; 448 dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask); 449 450 ret = platform_device_add_resources(pdev, res, nres); 451 if (ret) 452 goto err; 453 454 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata)); 455 if (ret) 456 goto err; 457 458 ret = platform_device_add(pdev); 459 if (ret) 460 goto err; 461 462 return pdev; 463 464 err: 465 platform_device_put(pdev); 466 put_id: 467 ida_simple_remove(&ci_ida, id); 468 return ERR_PTR(ret); 469 } 470 EXPORT_SYMBOL_GPL(ci_hdrc_add_device); 471 472 void ci_hdrc_remove_device(struct platform_device *pdev) 473 { 474 int id = pdev->id; 475 platform_device_unregister(pdev); 476 ida_simple_remove(&ci_ida, id); 477 } 478 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device); 479 480 static inline void ci_role_destroy(struct ci_hdrc *ci) 481 { 482 ci_hdrc_gadget_destroy(ci); 483 ci_hdrc_host_destroy(ci); 484 if (ci->is_otg) 485 ci_hdrc_otg_destroy(ci); 486 } 487 488 static void ci_get_otg_capable(struct ci_hdrc *ci) 489 { 490 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG) 491 ci->is_otg = false; 492 else 493 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS, 494 DCCPARAMS_DC | DCCPARAMS_HC) 495 == (DCCPARAMS_DC | DCCPARAMS_HC)); 496 if (ci->is_otg) { 497 dev_dbg(ci->dev, "It is OTG capable controller\n"); 498 ci_disable_otg_interrupt(ci, OTGSC_INT_EN_BITS); 499 ci_clear_otg_interrupt(ci, OTGSC_INT_STATUS_BITS); 500 } 501 } 502 503 static int ci_usb_phy_init(struct ci_hdrc *ci) 504 { 505 if (ci->platdata->phy) { 506 ci->transceiver = ci->platdata->phy; 507 return usb_phy_init(ci->transceiver); 508 } else { 509 ci->global_phy = true; 510 ci->transceiver = usb_get_phy(USB_PHY_TYPE_USB2); 511 if (IS_ERR(ci->transceiver)) 512 ci->transceiver = NULL; 513 514 return 0; 515 } 516 } 517 518 static void ci_usb_phy_destroy(struct ci_hdrc *ci) 519 { 520 if (!ci->transceiver) 521 return; 522 523 otg_set_peripheral(ci->transceiver->otg, NULL); 524 if (ci->global_phy) 525 usb_put_phy(ci->transceiver); 526 else 527 usb_phy_shutdown(ci->transceiver); 528 } 529 530 static int ci_hdrc_probe(struct platform_device *pdev) 531 { 532 struct device *dev = &pdev->dev; 533 struct ci_hdrc *ci; 534 struct resource *res; 535 void __iomem *base; 536 int ret; 537 enum usb_dr_mode dr_mode; 538 539 if (!dev->platform_data) { 540 dev_err(dev, "platform data missing\n"); 541 return -ENODEV; 542 } 543 544 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 545 base = devm_ioremap_resource(dev, res); 546 if (IS_ERR(base)) 547 return PTR_ERR(base); 548 549 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL); 550 if (!ci) { 551 dev_err(dev, "can't allocate device\n"); 552 return -ENOMEM; 553 } 554 555 ci->dev = dev; 556 ci->platdata = dev->platform_data; 557 558 ret = hw_device_init(ci, base); 559 if (ret < 0) { 560 dev_err(dev, "can't initialize hardware\n"); 561 return -ENODEV; 562 } 563 564 ret = ci_usb_phy_init(ci); 565 if (ret) { 566 dev_err(dev, "unable to init phy: %d\n", ret); 567 return ret; 568 } 569 570 ci->hw_bank.phys = res->start; 571 572 ci->irq = platform_get_irq(pdev, 0); 573 if (ci->irq < 0) { 574 dev_err(dev, "missing IRQ\n"); 575 ret = -ENODEV; 576 goto destroy_phy; 577 } 578 579 ci_get_otg_capable(ci); 580 581 hw_phymode_configure(ci); 582 583 dr_mode = ci->platdata->dr_mode; 584 /* initialize role(s) before the interrupt is requested */ 585 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) { 586 ret = ci_hdrc_host_init(ci); 587 if (ret) 588 dev_info(dev, "doesn't support host\n"); 589 } 590 591 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) { 592 ret = ci_hdrc_gadget_init(ci); 593 if (ret) 594 dev_info(dev, "doesn't support gadget\n"); 595 if (!ret && ci->transceiver) { 596 ret = otg_set_peripheral(ci->transceiver->otg, 597 &ci->gadget); 598 /* 599 * If we implement all USB functions using chipidea drivers, 600 * it doesn't need to call above API, meanwhile, if we only 601 * use gadget function, calling above API is useless. 602 */ 603 if (ret && ret != -ENOTSUPP) 604 goto destroy_phy; 605 } 606 } 607 608 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) { 609 dev_err(dev, "no supported roles\n"); 610 ret = -ENODEV; 611 goto destroy_phy; 612 } 613 614 if (ci->is_otg) { 615 ret = ci_hdrc_otg_init(ci); 616 if (ret) { 617 dev_err(dev, "init otg fails, ret = %d\n", ret); 618 goto stop; 619 } 620 } 621 622 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) { 623 if (ci->is_otg) { 624 /* 625 * ID pin needs 1ms debouce time, 626 * we delay 2ms for safe. 627 */ 628 mdelay(2); 629 ci->role = ci_otg_role(ci); 630 ci_enable_otg_interrupt(ci, OTGSC_IDIE); 631 } else { 632 /* 633 * If the controller is not OTG capable, but support 634 * role switch, the defalt role is gadget, and the 635 * user can switch it through debugfs. 636 */ 637 ci->role = CI_ROLE_GADGET; 638 } 639 } else { 640 ci->role = ci->roles[CI_ROLE_HOST] 641 ? CI_ROLE_HOST 642 : CI_ROLE_GADGET; 643 } 644 645 ret = ci_role_start(ci, ci->role); 646 if (ret) { 647 dev_err(dev, "can't start %s role\n", ci_role(ci)->name); 648 goto stop; 649 } 650 651 platform_set_drvdata(pdev, ci); 652 ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name, 653 ci); 654 if (ret) 655 goto stop; 656 657 ret = dbg_create_files(ci); 658 if (!ret) 659 return 0; 660 661 free_irq(ci->irq, ci); 662 stop: 663 ci_role_destroy(ci); 664 destroy_phy: 665 ci_usb_phy_destroy(ci); 666 667 return ret; 668 } 669 670 static int ci_hdrc_remove(struct platform_device *pdev) 671 { 672 struct ci_hdrc *ci = platform_get_drvdata(pdev); 673 674 dbg_remove_files(ci); 675 free_irq(ci->irq, ci); 676 ci_role_destroy(ci); 677 ci_hdrc_enter_lpm(ci, true); 678 ci_usb_phy_destroy(ci); 679 kfree(ci->hw_bank.regmap); 680 681 return 0; 682 } 683 684 static struct platform_driver ci_hdrc_driver = { 685 .probe = ci_hdrc_probe, 686 .remove = ci_hdrc_remove, 687 .driver = { 688 .name = "ci_hdrc", 689 }, 690 }; 691 692 module_platform_driver(ci_hdrc_driver); 693 694 MODULE_ALIAS("platform:ci_hdrc"); 695 MODULE_LICENSE("GPL v2"); 696 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>"); 697 MODULE_DESCRIPTION("ChipIdea HDRC Driver"); 698