1e443b333SAlexander Shishkin /* 2e443b333SAlexander Shishkin * core.c - ChipIdea USB IP core family device controller 3e443b333SAlexander Shishkin * 4e443b333SAlexander Shishkin * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. 5e443b333SAlexander Shishkin * 6e443b333SAlexander Shishkin * Author: David Lopo 7e443b333SAlexander Shishkin * 8e443b333SAlexander Shishkin * This program is free software; you can redistribute it and/or modify 9e443b333SAlexander Shishkin * it under the terms of the GNU General Public License version 2 as 10e443b333SAlexander Shishkin * published by the Free Software Foundation. 11e443b333SAlexander Shishkin */ 12e443b333SAlexander Shishkin 13e443b333SAlexander Shishkin /* 14e443b333SAlexander Shishkin * Description: ChipIdea USB IP core family device controller 15e443b333SAlexander Shishkin * 16e443b333SAlexander Shishkin * This driver is composed of several blocks: 17e443b333SAlexander Shishkin * - HW: hardware interface 18e443b333SAlexander Shishkin * - DBG: debug facilities (optional) 19e443b333SAlexander Shishkin * - UTIL: utilities 20e443b333SAlexander Shishkin * - ISR: interrupts handling 21e443b333SAlexander Shishkin * - ENDPT: endpoint operations (Gadget API) 22e443b333SAlexander Shishkin * - GADGET: gadget operations (Gadget API) 23e443b333SAlexander Shishkin * - BUS: bus glue code, bus abstraction layer 24e443b333SAlexander Shishkin * 25e443b333SAlexander Shishkin * Compile Options 26e443b333SAlexander Shishkin * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities 27e443b333SAlexander Shishkin * - STALL_IN: non-empty bulk-in pipes cannot be halted 28e443b333SAlexander Shishkin * if defined mass storage compliance succeeds but with warnings 29e443b333SAlexander Shishkin * => case 4: Hi > Dn 30e443b333SAlexander Shishkin * => case 5: Hi > Di 31e443b333SAlexander Shishkin * => case 8: Hi <> Do 32e443b333SAlexander Shishkin * if undefined usbtest 13 fails 33e443b333SAlexander Shishkin * - TRACE: enable function tracing (depends on DEBUG) 34e443b333SAlexander Shishkin * 35e443b333SAlexander Shishkin * Main Features 36e443b333SAlexander Shishkin * - Chapter 9 & Mass Storage Compliance with Gadget File Storage 37e443b333SAlexander Shishkin * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined) 38e443b333SAlexander Shishkin * - Normal & LPM support 39e443b333SAlexander Shishkin * 40e443b333SAlexander Shishkin * USBTEST Report 41e443b333SAlexander Shishkin * - OK: 0-12, 13 (STALL_IN defined) & 14 42e443b333SAlexander Shishkin * - Not Supported: 15 & 16 (ISO) 43e443b333SAlexander Shishkin * 44e443b333SAlexander Shishkin * TODO List 45e443b333SAlexander Shishkin * - OTG 46e443b333SAlexander Shishkin * - Isochronous & Interrupt Traffic 47e443b333SAlexander Shishkin * - Handle requests which spawns into several TDs 48e443b333SAlexander Shishkin * - GET_STATUS(device) - always reports 0 49e443b333SAlexander Shishkin * - Gadget API (majority of optional features) 50e443b333SAlexander Shishkin * - Suspend & Remote Wakeup 51e443b333SAlexander Shishkin */ 52e443b333SAlexander Shishkin #include <linux/delay.h> 53e443b333SAlexander Shishkin #include <linux/device.h> 54e443b333SAlexander Shishkin #include <linux/dmapool.h> 55e443b333SAlexander Shishkin #include <linux/dma-mapping.h> 56e443b333SAlexander Shishkin #include <linux/init.h> 57e443b333SAlexander Shishkin #include <linux/platform_device.h> 58e443b333SAlexander Shishkin #include <linux/module.h> 59fe6e125eSRichard Zhao #include <linux/idr.h> 60e443b333SAlexander Shishkin #include <linux/interrupt.h> 61e443b333SAlexander Shishkin #include <linux/io.h> 62e443b333SAlexander Shishkin #include <linux/irq.h> 63e443b333SAlexander Shishkin #include <linux/kernel.h> 64e443b333SAlexander Shishkin #include <linux/slab.h> 65e443b333SAlexander Shishkin #include <linux/pm_runtime.h> 66e443b333SAlexander Shishkin #include <linux/usb/ch9.h> 67e443b333SAlexander Shishkin #include <linux/usb/gadget.h> 68e443b333SAlexander Shishkin #include <linux/usb/otg.h> 69e443b333SAlexander Shishkin #include <linux/usb/chipidea.h> 70e443b333SAlexander Shishkin 71e443b333SAlexander Shishkin #include "ci.h" 72e443b333SAlexander Shishkin #include "udc.h" 73e443b333SAlexander Shishkin #include "bits.h" 74eb70e5abSAlexander Shishkin #include "host.h" 75e443b333SAlexander Shishkin #include "debug.h" 76e443b333SAlexander Shishkin 775f36e231SAlexander Shishkin /* Controller register map */ 78e443b333SAlexander Shishkin static uintptr_t ci_regs_nolpm[] = { 79e443b333SAlexander Shishkin [CAP_CAPLENGTH] = 0x000UL, 80e443b333SAlexander Shishkin [CAP_HCCPARAMS] = 0x008UL, 81e443b333SAlexander Shishkin [CAP_DCCPARAMS] = 0x024UL, 82e443b333SAlexander Shishkin [CAP_TESTMODE] = 0x038UL, 83e443b333SAlexander Shishkin [OP_USBCMD] = 0x000UL, 84e443b333SAlexander Shishkin [OP_USBSTS] = 0x004UL, 85e443b333SAlexander Shishkin [OP_USBINTR] = 0x008UL, 86e443b333SAlexander Shishkin [OP_DEVICEADDR] = 0x014UL, 87e443b333SAlexander Shishkin [OP_ENDPTLISTADDR] = 0x018UL, 88e443b333SAlexander Shishkin [OP_PORTSC] = 0x044UL, 89e443b333SAlexander Shishkin [OP_DEVLC] = 0x084UL, 905f36e231SAlexander Shishkin [OP_OTGSC] = 0x064UL, 91e443b333SAlexander Shishkin [OP_USBMODE] = 0x068UL, 92e443b333SAlexander Shishkin [OP_ENDPTSETUPSTAT] = 0x06CUL, 93e443b333SAlexander Shishkin [OP_ENDPTPRIME] = 0x070UL, 94e443b333SAlexander Shishkin [OP_ENDPTFLUSH] = 0x074UL, 95e443b333SAlexander Shishkin [OP_ENDPTSTAT] = 0x078UL, 96e443b333SAlexander Shishkin [OP_ENDPTCOMPLETE] = 0x07CUL, 97e443b333SAlexander Shishkin [OP_ENDPTCTRL] = 0x080UL, 98e443b333SAlexander Shishkin }; 99e443b333SAlexander Shishkin 100e443b333SAlexander Shishkin static uintptr_t ci_regs_lpm[] = { 101e443b333SAlexander Shishkin [CAP_CAPLENGTH] = 0x000UL, 102e443b333SAlexander Shishkin [CAP_HCCPARAMS] = 0x008UL, 103e443b333SAlexander Shishkin [CAP_DCCPARAMS] = 0x024UL, 104e443b333SAlexander Shishkin [CAP_TESTMODE] = 0x0FCUL, 105e443b333SAlexander Shishkin [OP_USBCMD] = 0x000UL, 106e443b333SAlexander Shishkin [OP_USBSTS] = 0x004UL, 107e443b333SAlexander Shishkin [OP_USBINTR] = 0x008UL, 108e443b333SAlexander Shishkin [OP_DEVICEADDR] = 0x014UL, 109e443b333SAlexander Shishkin [OP_ENDPTLISTADDR] = 0x018UL, 110e443b333SAlexander Shishkin [OP_PORTSC] = 0x044UL, 111e443b333SAlexander Shishkin [OP_DEVLC] = 0x084UL, 1125f36e231SAlexander Shishkin [OP_OTGSC] = 0x0C4UL, 113e443b333SAlexander Shishkin [OP_USBMODE] = 0x0C8UL, 114e443b333SAlexander Shishkin [OP_ENDPTSETUPSTAT] = 0x0D8UL, 115e443b333SAlexander Shishkin [OP_ENDPTPRIME] = 0x0DCUL, 116e443b333SAlexander Shishkin [OP_ENDPTFLUSH] = 0x0E0UL, 117e443b333SAlexander Shishkin [OP_ENDPTSTAT] = 0x0E4UL, 118e443b333SAlexander Shishkin [OP_ENDPTCOMPLETE] = 0x0E8UL, 119e443b333SAlexander Shishkin [OP_ENDPTCTRL] = 0x0ECUL, 120e443b333SAlexander Shishkin }; 121e443b333SAlexander Shishkin 1225f36e231SAlexander Shishkin static int hw_alloc_regmap(struct ci13xxx *ci, bool is_lpm) 123e443b333SAlexander Shishkin { 124e443b333SAlexander Shishkin int i; 125e443b333SAlexander Shishkin 1265f36e231SAlexander Shishkin kfree(ci->hw_bank.regmap); 127e443b333SAlexander Shishkin 1285f36e231SAlexander Shishkin ci->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *), 129e443b333SAlexander Shishkin GFP_KERNEL); 1305f36e231SAlexander Shishkin if (!ci->hw_bank.regmap) 131e443b333SAlexander Shishkin return -ENOMEM; 132e443b333SAlexander Shishkin 133e443b333SAlexander Shishkin for (i = 0; i < OP_ENDPTCTRL; i++) 1345f36e231SAlexander Shishkin ci->hw_bank.regmap[i] = 1355f36e231SAlexander Shishkin (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) + 136e443b333SAlexander Shishkin (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]); 137e443b333SAlexander Shishkin 138e443b333SAlexander Shishkin for (; i <= OP_LAST; i++) 1395f36e231SAlexander Shishkin ci->hw_bank.regmap[i] = ci->hw_bank.op + 140e443b333SAlexander Shishkin 4 * (i - OP_ENDPTCTRL) + 141e443b333SAlexander Shishkin (is_lpm 142e443b333SAlexander Shishkin ? ci_regs_lpm[OP_ENDPTCTRL] 143e443b333SAlexander Shishkin : ci_regs_nolpm[OP_ENDPTCTRL]); 144e443b333SAlexander Shishkin 145e443b333SAlexander Shishkin return 0; 146e443b333SAlexander Shishkin } 147e443b333SAlexander Shishkin 148e443b333SAlexander Shishkin /** 149e443b333SAlexander Shishkin * hw_port_test_set: writes port test mode (execute without interruption) 150e443b333SAlexander Shishkin * @mode: new value 151e443b333SAlexander Shishkin * 152e443b333SAlexander Shishkin * This function returns an error code 153e443b333SAlexander Shishkin */ 154e443b333SAlexander Shishkin int hw_port_test_set(struct ci13xxx *ci, u8 mode) 155e443b333SAlexander Shishkin { 156e443b333SAlexander Shishkin const u8 TEST_MODE_MAX = 7; 157e443b333SAlexander Shishkin 158e443b333SAlexander Shishkin if (mode > TEST_MODE_MAX) 159e443b333SAlexander Shishkin return -EINVAL; 160e443b333SAlexander Shishkin 161e443b333SAlexander Shishkin hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << ffs_nr(PORTSC_PTC)); 162e443b333SAlexander Shishkin return 0; 163e443b333SAlexander Shishkin } 164e443b333SAlexander Shishkin 165e443b333SAlexander Shishkin /** 166e443b333SAlexander Shishkin * hw_port_test_get: reads port test mode value 167e443b333SAlexander Shishkin * 168e443b333SAlexander Shishkin * This function returns port test mode value 169e443b333SAlexander Shishkin */ 170e443b333SAlexander Shishkin u8 hw_port_test_get(struct ci13xxx *ci) 171e443b333SAlexander Shishkin { 172e443b333SAlexander Shishkin return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> ffs_nr(PORTSC_PTC); 173e443b333SAlexander Shishkin } 174e443b333SAlexander Shishkin 1755f36e231SAlexander Shishkin static int hw_device_init(struct ci13xxx *ci, void __iomem *base) 176e443b333SAlexander Shishkin { 177e443b333SAlexander Shishkin u32 reg; 178e443b333SAlexander Shishkin 179e443b333SAlexander Shishkin /* bank is a module variable */ 1805f36e231SAlexander Shishkin ci->hw_bank.abs = base; 181e443b333SAlexander Shishkin 1825f36e231SAlexander Shishkin ci->hw_bank.cap = ci->hw_bank.abs; 18377c4400fSRichard Zhao ci->hw_bank.cap += ci->platdata->capoffset; 1845f36e231SAlexander Shishkin ci->hw_bank.op = ci->hw_bank.cap + ioread8(ci->hw_bank.cap); 185e443b333SAlexander Shishkin 1865f36e231SAlexander Shishkin hw_alloc_regmap(ci, false); 1875f36e231SAlexander Shishkin reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >> 188e443b333SAlexander Shishkin ffs_nr(HCCPARAMS_LEN); 1895f36e231SAlexander Shishkin ci->hw_bank.lpm = reg; 1905f36e231SAlexander Shishkin hw_alloc_regmap(ci, !!reg); 1915f36e231SAlexander Shishkin ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs; 1925f36e231SAlexander Shishkin ci->hw_bank.size += OP_LAST; 1935f36e231SAlexander Shishkin ci->hw_bank.size /= sizeof(u32); 194e443b333SAlexander Shishkin 1955f36e231SAlexander Shishkin reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >> 196e443b333SAlexander Shishkin ffs_nr(DCCPARAMS_DEN); 1975f36e231SAlexander Shishkin ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */ 198e443b333SAlexander Shishkin 19909c94e62SRichard Zhao if (ci->hw_ep_max > ENDPT_MAX) 200e443b333SAlexander Shishkin return -ENODEV; 201e443b333SAlexander Shishkin 2025f36e231SAlexander Shishkin dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n", 2035f36e231SAlexander Shishkin ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op); 204e443b333SAlexander Shishkin 205e443b333SAlexander Shishkin /* setup lock mode ? */ 206e443b333SAlexander Shishkin 207e443b333SAlexander Shishkin /* ENDPTSETUPSTAT is '0' by default */ 208e443b333SAlexander Shishkin 209e443b333SAlexander Shishkin /* HCSPARAMS.bf.ppc SHOULD BE zero for device */ 210e443b333SAlexander Shishkin 211e443b333SAlexander Shishkin return 0; 212e443b333SAlexander Shishkin } 213e443b333SAlexander Shishkin 214e443b333SAlexander Shishkin /** 215e443b333SAlexander Shishkin * hw_device_reset: resets chip (execute without interruption) 216e443b333SAlexander Shishkin * @ci: the controller 217e443b333SAlexander Shishkin * 218e443b333SAlexander Shishkin * This function returns an error code 219e443b333SAlexander Shishkin */ 220eb70e5abSAlexander Shishkin int hw_device_reset(struct ci13xxx *ci, u32 mode) 221e443b333SAlexander Shishkin { 222e443b333SAlexander Shishkin /* should flush & stop before reset */ 223e443b333SAlexander Shishkin hw_write(ci, OP_ENDPTFLUSH, ~0, ~0); 224e443b333SAlexander Shishkin hw_write(ci, OP_USBCMD, USBCMD_RS, 0); 225e443b333SAlexander Shishkin 226e443b333SAlexander Shishkin hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST); 227e443b333SAlexander Shishkin while (hw_read(ci, OP_USBCMD, USBCMD_RST)) 228e443b333SAlexander Shishkin udelay(10); /* not RTOS friendly */ 229e443b333SAlexander Shishkin 230e443b333SAlexander Shishkin 23177c4400fSRichard Zhao if (ci->platdata->notify_event) 23277c4400fSRichard Zhao ci->platdata->notify_event(ci, 233e443b333SAlexander Shishkin CI13XXX_CONTROLLER_RESET_EVENT); 234e443b333SAlexander Shishkin 23577c4400fSRichard Zhao if (ci->platdata->flags & CI13XXX_DISABLE_STREAMING) 236758fc986SAlexander Shishkin hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS); 237e443b333SAlexander Shishkin 238e443b333SAlexander Shishkin /* USBMODE should be configured step by step */ 239e443b333SAlexander Shishkin hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE); 240eb70e5abSAlexander Shishkin hw_write(ci, OP_USBMODE, USBMODE_CM, mode); 241e443b333SAlexander Shishkin /* HW >= 2.3 */ 242e443b333SAlexander Shishkin hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); 243e443b333SAlexander Shishkin 244eb70e5abSAlexander Shishkin if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) { 245eb70e5abSAlexander Shishkin pr_err("cannot enter in %s mode", ci_role(ci)->name); 246e443b333SAlexander Shishkin pr_err("lpm = %i", ci->hw_bank.lpm); 247e443b333SAlexander Shishkin return -ENODEV; 248e443b333SAlexander Shishkin } 249e443b333SAlexander Shishkin 250e443b333SAlexander Shishkin return 0; 251e443b333SAlexander Shishkin } 252e443b333SAlexander Shishkin 2535f36e231SAlexander Shishkin /** 2545f36e231SAlexander Shishkin * ci_otg_role - pick role based on ID pin state 2555f36e231SAlexander Shishkin * @ci: the controller 2565f36e231SAlexander Shishkin */ 2575f36e231SAlexander Shishkin static enum ci_role ci_otg_role(struct ci13xxx *ci) 2585f36e231SAlexander Shishkin { 2595f36e231SAlexander Shishkin u32 sts = hw_read(ci, OP_OTGSC, ~0); 2605f36e231SAlexander Shishkin enum ci_role role = sts & OTGSC_ID 2615f36e231SAlexander Shishkin ? CI_ROLE_GADGET 2625f36e231SAlexander Shishkin : CI_ROLE_HOST; 2635f36e231SAlexander Shishkin 2645f36e231SAlexander Shishkin return role; 2655f36e231SAlexander Shishkin } 2665f36e231SAlexander Shishkin 2675f36e231SAlexander Shishkin /** 2685f36e231SAlexander Shishkin * ci_role_work - perform role changing based on ID pin 2695f36e231SAlexander Shishkin * @work: work struct 2705f36e231SAlexander Shishkin */ 2715f36e231SAlexander Shishkin static void ci_role_work(struct work_struct *work) 2725f36e231SAlexander Shishkin { 2735f36e231SAlexander Shishkin struct ci13xxx *ci = container_of(work, struct ci13xxx, work); 2745f36e231SAlexander Shishkin enum ci_role role = ci_otg_role(ci); 2755f36e231SAlexander Shishkin 2765f36e231SAlexander Shishkin if (role != ci->role) { 2775f36e231SAlexander Shishkin dev_dbg(ci->dev, "switching from %s to %s\n", 2785f36e231SAlexander Shishkin ci_role(ci)->name, ci->roles[role]->name); 2795f36e231SAlexander Shishkin 2805f36e231SAlexander Shishkin ci_role_stop(ci); 2815f36e231SAlexander Shishkin ci_role_start(ci, role); 2825f36e231SAlexander Shishkin } 2835f36e231SAlexander Shishkin } 2845f36e231SAlexander Shishkin 2855f36e231SAlexander Shishkin static ssize_t show_role(struct device *dev, struct device_attribute *attr, 2865f36e231SAlexander Shishkin char *buf) 2875f36e231SAlexander Shishkin { 2885f36e231SAlexander Shishkin struct ci13xxx *ci = dev_get_drvdata(dev); 2895f36e231SAlexander Shishkin 2905f36e231SAlexander Shishkin return sprintf(buf, "%s\n", ci_role(ci)->name); 2915f36e231SAlexander Shishkin } 2925f36e231SAlexander Shishkin 2935f36e231SAlexander Shishkin static ssize_t store_role(struct device *dev, struct device_attribute *attr, 2945f36e231SAlexander Shishkin const char *buf, size_t count) 2955f36e231SAlexander Shishkin { 2965f36e231SAlexander Shishkin struct ci13xxx *ci = dev_get_drvdata(dev); 2975f36e231SAlexander Shishkin enum ci_role role; 2985f36e231SAlexander Shishkin int ret; 2995f36e231SAlexander Shishkin 3005f36e231SAlexander Shishkin for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++) 3015f36e231SAlexander Shishkin if (ci->roles[role] && !strcmp(buf, ci->roles[role]->name)) 3025f36e231SAlexander Shishkin break; 3035f36e231SAlexander Shishkin 3045f36e231SAlexander Shishkin if (role == CI_ROLE_END || role == ci->role) 3055f36e231SAlexander Shishkin return -EINVAL; 3065f36e231SAlexander Shishkin 3075f36e231SAlexander Shishkin ci_role_stop(ci); 3085f36e231SAlexander Shishkin ret = ci_role_start(ci, role); 3095f36e231SAlexander Shishkin if (ret) 3105f36e231SAlexander Shishkin return ret; 3115f36e231SAlexander Shishkin 3125f36e231SAlexander Shishkin return count; 3135f36e231SAlexander Shishkin } 3145f36e231SAlexander Shishkin 3155f36e231SAlexander Shishkin static DEVICE_ATTR(role, S_IRUSR | S_IWUSR, show_role, store_role); 3165f36e231SAlexander Shishkin 3175f36e231SAlexander Shishkin static irqreturn_t ci_irq(int irq, void *data) 3185f36e231SAlexander Shishkin { 3195f36e231SAlexander Shishkin struct ci13xxx *ci = data; 3205f36e231SAlexander Shishkin irqreturn_t ret = IRQ_NONE; 3215f36e231SAlexander Shishkin 3225f36e231SAlexander Shishkin if (ci->is_otg) { 3235f36e231SAlexander Shishkin u32 sts = hw_read(ci, OP_OTGSC, ~0); 3245f36e231SAlexander Shishkin 3255f36e231SAlexander Shishkin if (sts & OTGSC_IDIS) { 326984f753cSRichard Zhao hw_write(ci, OP_OTGSC, OTGSC_IDIS, OTGSC_IDIS); 3275f36e231SAlexander Shishkin queue_work(ci->wq, &ci->work); 3285f36e231SAlexander Shishkin ret = IRQ_HANDLED; 3295f36e231SAlexander Shishkin } 3305f36e231SAlexander Shishkin } 3315f36e231SAlexander Shishkin 3325f36e231SAlexander Shishkin return ci->role == CI_ROLE_END ? ret : ci_role(ci)->irq(ci); 3335f36e231SAlexander Shishkin } 3345f36e231SAlexander Shishkin 335fe6e125eSRichard Zhao static DEFINE_IDA(ci_ida); 336fe6e125eSRichard Zhao 337cbc6dc2aSRichard Zhao struct platform_device *ci13xxx_add_device(struct device *dev, 338cbc6dc2aSRichard Zhao struct resource *res, int nres, 339cbc6dc2aSRichard Zhao struct ci13xxx_platform_data *platdata) 340cbc6dc2aSRichard Zhao { 341cbc6dc2aSRichard Zhao struct platform_device *pdev; 342fe6e125eSRichard Zhao int id, ret; 343cbc6dc2aSRichard Zhao 344fe6e125eSRichard Zhao id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL); 345fe6e125eSRichard Zhao if (id < 0) 346fe6e125eSRichard Zhao return ERR_PTR(id); 347fe6e125eSRichard Zhao 348fe6e125eSRichard Zhao pdev = platform_device_alloc("ci_hdrc", id); 349fe6e125eSRichard Zhao if (!pdev) { 350fe6e125eSRichard Zhao ret = -ENOMEM; 351fe6e125eSRichard Zhao goto put_id; 352fe6e125eSRichard Zhao } 353cbc6dc2aSRichard Zhao 354cbc6dc2aSRichard Zhao pdev->dev.parent = dev; 355cbc6dc2aSRichard Zhao pdev->dev.dma_mask = dev->dma_mask; 356cbc6dc2aSRichard Zhao pdev->dev.dma_parms = dev->dma_parms; 357cbc6dc2aSRichard Zhao dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask); 358cbc6dc2aSRichard Zhao 359cbc6dc2aSRichard Zhao ret = platform_device_add_resources(pdev, res, nres); 360cbc6dc2aSRichard Zhao if (ret) 361cbc6dc2aSRichard Zhao goto err; 362cbc6dc2aSRichard Zhao 363cbc6dc2aSRichard Zhao ret = platform_device_add_data(pdev, platdata, sizeof(*platdata)); 364cbc6dc2aSRichard Zhao if (ret) 365cbc6dc2aSRichard Zhao goto err; 366cbc6dc2aSRichard Zhao 367cbc6dc2aSRichard Zhao ret = platform_device_add(pdev); 368cbc6dc2aSRichard Zhao if (ret) 369cbc6dc2aSRichard Zhao goto err; 370cbc6dc2aSRichard Zhao 371cbc6dc2aSRichard Zhao return pdev; 372cbc6dc2aSRichard Zhao 373cbc6dc2aSRichard Zhao err: 374cbc6dc2aSRichard Zhao platform_device_put(pdev); 375fe6e125eSRichard Zhao put_id: 376fe6e125eSRichard Zhao ida_simple_remove(&ci_ida, id); 377cbc6dc2aSRichard Zhao return ERR_PTR(ret); 378cbc6dc2aSRichard Zhao } 379cbc6dc2aSRichard Zhao EXPORT_SYMBOL_GPL(ci13xxx_add_device); 380cbc6dc2aSRichard Zhao 381cbc6dc2aSRichard Zhao void ci13xxx_remove_device(struct platform_device *pdev) 382cbc6dc2aSRichard Zhao { 383cbc6dc2aSRichard Zhao platform_device_unregister(pdev); 384fe6e125eSRichard Zhao ida_simple_remove(&ci_ida, pdev->id); 385cbc6dc2aSRichard Zhao } 386cbc6dc2aSRichard Zhao EXPORT_SYMBOL_GPL(ci13xxx_remove_device); 387cbc6dc2aSRichard Zhao 3885f36e231SAlexander Shishkin static int __devinit ci_hdrc_probe(struct platform_device *pdev) 389e443b333SAlexander Shishkin { 390e443b333SAlexander Shishkin struct device *dev = &pdev->dev; 3915f36e231SAlexander Shishkin struct ci13xxx *ci; 392e443b333SAlexander Shishkin struct resource *res; 393e443b333SAlexander Shishkin void __iomem *base; 394e443b333SAlexander Shishkin int ret; 395e443b333SAlexander Shishkin 3965f36e231SAlexander Shishkin if (!dev->platform_data) { 397e443b333SAlexander Shishkin dev_err(dev, "platform data missing\n"); 398e443b333SAlexander Shishkin return -ENODEV; 399e443b333SAlexander Shishkin } 400e443b333SAlexander Shishkin 401e443b333SAlexander Shishkin res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 402e443b333SAlexander Shishkin if (!res) { 403e443b333SAlexander Shishkin dev_err(dev, "missing resource\n"); 404e443b333SAlexander Shishkin return -ENODEV; 405e443b333SAlexander Shishkin } 406e443b333SAlexander Shishkin 407e443b333SAlexander Shishkin base = devm_request_and_ioremap(dev, res); 408e443b333SAlexander Shishkin if (!res) { 409e443b333SAlexander Shishkin dev_err(dev, "can't request and ioremap resource\n"); 410e443b333SAlexander Shishkin return -ENOMEM; 411e443b333SAlexander Shishkin } 412e443b333SAlexander Shishkin 4135f36e231SAlexander Shishkin ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL); 4145f36e231SAlexander Shishkin if (!ci) { 4155f36e231SAlexander Shishkin dev_err(dev, "can't allocate device\n"); 4165f36e231SAlexander Shishkin return -ENOMEM; 4175f36e231SAlexander Shishkin } 418e443b333SAlexander Shishkin 4195f36e231SAlexander Shishkin ci->dev = dev; 42077c4400fSRichard Zhao ci->platdata = dev->platform_data; 421a2c3d690SRichard Zhao if (ci->platdata->phy) 422a2c3d690SRichard Zhao ci->transceiver = ci->platdata->phy; 423a2c3d690SRichard Zhao else 424a2c3d690SRichard Zhao ci->global_phy = true; 4255f36e231SAlexander Shishkin 4265f36e231SAlexander Shishkin ret = hw_device_init(ci, base); 4275f36e231SAlexander Shishkin if (ret < 0) { 4285f36e231SAlexander Shishkin dev_err(dev, "can't initialize hardware\n"); 4295f36e231SAlexander Shishkin return -ENODEV; 4305f36e231SAlexander Shishkin } 4315f36e231SAlexander Shishkin 432eb70e5abSAlexander Shishkin ci->hw_bank.phys = res->start; 433eb70e5abSAlexander Shishkin 4345f36e231SAlexander Shishkin ci->irq = platform_get_irq(pdev, 0); 4355f36e231SAlexander Shishkin if (ci->irq < 0) { 436e443b333SAlexander Shishkin dev_err(dev, "missing IRQ\n"); 4375f36e231SAlexander Shishkin return -ENODEV; 438e443b333SAlexander Shishkin } 439e443b333SAlexander Shishkin 4405f36e231SAlexander Shishkin INIT_WORK(&ci->work, ci_role_work); 4415f36e231SAlexander Shishkin ci->wq = create_singlethread_workqueue("ci_otg"); 4425f36e231SAlexander Shishkin if (!ci->wq) { 4435f36e231SAlexander Shishkin dev_err(dev, "can't create workqueue\n"); 4445f36e231SAlexander Shishkin return -ENODEV; 4455f36e231SAlexander Shishkin } 446e443b333SAlexander Shishkin 4475f36e231SAlexander Shishkin /* initialize role(s) before the interrupt is requested */ 448eb70e5abSAlexander Shishkin ret = ci_hdrc_host_init(ci); 449eb70e5abSAlexander Shishkin if (ret) 450eb70e5abSAlexander Shishkin dev_info(dev, "doesn't support host\n"); 451eb70e5abSAlexander Shishkin 4525f36e231SAlexander Shishkin ret = ci_hdrc_gadget_init(ci); 453e443b333SAlexander Shishkin if (ret) 4545f36e231SAlexander Shishkin dev_info(dev, "doesn't support gadget\n"); 4555f36e231SAlexander Shishkin 4565f36e231SAlexander Shishkin if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) { 4575f36e231SAlexander Shishkin dev_err(dev, "no supported roles\n"); 4585f36e231SAlexander Shishkin ret = -ENODEV; 4595f36e231SAlexander Shishkin goto rm_wq; 4605f36e231SAlexander Shishkin } 4615f36e231SAlexander Shishkin 4625f36e231SAlexander Shishkin if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) { 4635f36e231SAlexander Shishkin ci->is_otg = true; 46486ad01a9SRichard Zhao /* ID pin needs 1ms debouce time, we delay 2ms for safe */ 46586ad01a9SRichard Zhao mdelay(2); 4665f36e231SAlexander Shishkin ci->role = ci_otg_role(ci); 4675f36e231SAlexander Shishkin } else { 4685f36e231SAlexander Shishkin ci->role = ci->roles[CI_ROLE_HOST] 4695f36e231SAlexander Shishkin ? CI_ROLE_HOST 4705f36e231SAlexander Shishkin : CI_ROLE_GADGET; 4715f36e231SAlexander Shishkin } 4725f36e231SAlexander Shishkin 4735f36e231SAlexander Shishkin ret = ci_role_start(ci, ci->role); 4745f36e231SAlexander Shishkin if (ret) { 4755f36e231SAlexander Shishkin dev_err(dev, "can't start %s role\n", ci_role(ci)->name); 4765f36e231SAlexander Shishkin ret = -ENODEV; 4775f36e231SAlexander Shishkin goto rm_wq; 4785f36e231SAlexander Shishkin } 4795f36e231SAlexander Shishkin 4805f36e231SAlexander Shishkin platform_set_drvdata(pdev, ci); 48177c4400fSRichard Zhao ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name, 4825f36e231SAlexander Shishkin ci); 4835f36e231SAlexander Shishkin if (ret) 4845f36e231SAlexander Shishkin goto stop; 4855f36e231SAlexander Shishkin 4865f36e231SAlexander Shishkin ret = device_create_file(dev, &dev_attr_role); 4875f36e231SAlexander Shishkin if (ret) 4885f36e231SAlexander Shishkin goto rm_attr; 4895f36e231SAlexander Shishkin 4905f36e231SAlexander Shishkin if (ci->is_otg) 4915f36e231SAlexander Shishkin hw_write(ci, OP_OTGSC, OTGSC_IDIE, OTGSC_IDIE); 4925f36e231SAlexander Shishkin 4935f36e231SAlexander Shishkin return ret; 4945f36e231SAlexander Shishkin 4955f36e231SAlexander Shishkin rm_attr: 4965f36e231SAlexander Shishkin device_remove_file(dev, &dev_attr_role); 4975f36e231SAlexander Shishkin stop: 4985f36e231SAlexander Shishkin ci_role_stop(ci); 4995f36e231SAlexander Shishkin rm_wq: 5005f36e231SAlexander Shishkin flush_workqueue(ci->wq); 5015f36e231SAlexander Shishkin destroy_workqueue(ci->wq); 502e443b333SAlexander Shishkin 503e443b333SAlexander Shishkin return ret; 504e443b333SAlexander Shishkin } 505e443b333SAlexander Shishkin 5065f36e231SAlexander Shishkin static int __devexit ci_hdrc_remove(struct platform_device *pdev) 507e443b333SAlexander Shishkin { 5085f36e231SAlexander Shishkin struct ci13xxx *ci = platform_get_drvdata(pdev); 509e443b333SAlexander Shishkin 5105f36e231SAlexander Shishkin flush_workqueue(ci->wq); 5115f36e231SAlexander Shishkin destroy_workqueue(ci->wq); 5125f36e231SAlexander Shishkin device_remove_file(ci->dev, &dev_attr_role); 5135f36e231SAlexander Shishkin free_irq(ci->irq, ci); 5145f36e231SAlexander Shishkin ci_role_stop(ci); 515e443b333SAlexander Shishkin 516e443b333SAlexander Shishkin return 0; 517e443b333SAlexander Shishkin } 518e443b333SAlexander Shishkin 5195f36e231SAlexander Shishkin static struct platform_driver ci_hdrc_driver = { 5205f36e231SAlexander Shishkin .probe = ci_hdrc_probe, 5215f36e231SAlexander Shishkin .remove = __devexit_p(ci_hdrc_remove), 522e443b333SAlexander Shishkin .driver = { 5235f36e231SAlexander Shishkin .name = "ci_hdrc", 524e443b333SAlexander Shishkin }, 525e443b333SAlexander Shishkin }; 526e443b333SAlexander Shishkin 5275f36e231SAlexander Shishkin module_platform_driver(ci_hdrc_driver); 528e443b333SAlexander Shishkin 5295f36e231SAlexander Shishkin MODULE_ALIAS("platform:ci_hdrc"); 530e443b333SAlexander Shishkin MODULE_ALIAS("platform:ci13xxx"); 531e443b333SAlexander Shishkin MODULE_LICENSE("GPL v2"); 532e443b333SAlexander Shishkin MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>"); 5335f36e231SAlexander Shishkin MODULE_DESCRIPTION("ChipIdea HDRC Driver"); 534