1e443b333SAlexander Shishkin /* 2e443b333SAlexander Shishkin * core.c - ChipIdea USB IP core family device controller 3e443b333SAlexander Shishkin * 4e443b333SAlexander Shishkin * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. 5e443b333SAlexander Shishkin * 6e443b333SAlexander Shishkin * Author: David Lopo 7e443b333SAlexander Shishkin * 8e443b333SAlexander Shishkin * This program is free software; you can redistribute it and/or modify 9e443b333SAlexander Shishkin * it under the terms of the GNU General Public License version 2 as 10e443b333SAlexander Shishkin * published by the Free Software Foundation. 11e443b333SAlexander Shishkin */ 12e443b333SAlexander Shishkin 13e443b333SAlexander Shishkin /* 14e443b333SAlexander Shishkin * Description: ChipIdea USB IP core family device controller 15e443b333SAlexander Shishkin * 16e443b333SAlexander Shishkin * This driver is composed of several blocks: 17e443b333SAlexander Shishkin * - HW: hardware interface 18e443b333SAlexander Shishkin * - DBG: debug facilities (optional) 19e443b333SAlexander Shishkin * - UTIL: utilities 20e443b333SAlexander Shishkin * - ISR: interrupts handling 21e443b333SAlexander Shishkin * - ENDPT: endpoint operations (Gadget API) 22e443b333SAlexander Shishkin * - GADGET: gadget operations (Gadget API) 23e443b333SAlexander Shishkin * - BUS: bus glue code, bus abstraction layer 24e443b333SAlexander Shishkin * 25e443b333SAlexander Shishkin * Compile Options 26e443b333SAlexander Shishkin * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities 27e443b333SAlexander Shishkin * - STALL_IN: non-empty bulk-in pipes cannot be halted 28e443b333SAlexander Shishkin * if defined mass storage compliance succeeds but with warnings 29e443b333SAlexander Shishkin * => case 4: Hi > Dn 30e443b333SAlexander Shishkin * => case 5: Hi > Di 31e443b333SAlexander Shishkin * => case 8: Hi <> Do 32e443b333SAlexander Shishkin * if undefined usbtest 13 fails 33e443b333SAlexander Shishkin * - TRACE: enable function tracing (depends on DEBUG) 34e443b333SAlexander Shishkin * 35e443b333SAlexander Shishkin * Main Features 36e443b333SAlexander Shishkin * - Chapter 9 & Mass Storage Compliance with Gadget File Storage 37e443b333SAlexander Shishkin * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined) 38e443b333SAlexander Shishkin * - Normal & LPM support 39e443b333SAlexander Shishkin * 40e443b333SAlexander Shishkin * USBTEST Report 41e443b333SAlexander Shishkin * - OK: 0-12, 13 (STALL_IN defined) & 14 42e443b333SAlexander Shishkin * - Not Supported: 15 & 16 (ISO) 43e443b333SAlexander Shishkin * 44e443b333SAlexander Shishkin * TODO List 45e443b333SAlexander Shishkin * - OTG 46e443b333SAlexander Shishkin * - Isochronous & Interrupt Traffic 47e443b333SAlexander Shishkin * - Handle requests which spawns into several TDs 48e443b333SAlexander Shishkin * - GET_STATUS(device) - always reports 0 49e443b333SAlexander Shishkin * - Gadget API (majority of optional features) 50e443b333SAlexander Shishkin * - Suspend & Remote Wakeup 51e443b333SAlexander Shishkin */ 52e443b333SAlexander Shishkin #include <linux/delay.h> 53e443b333SAlexander Shishkin #include <linux/device.h> 54e443b333SAlexander Shishkin #include <linux/dma-mapping.h> 55e443b333SAlexander Shishkin #include <linux/platform_device.h> 56e443b333SAlexander Shishkin #include <linux/module.h> 57fe6e125eSRichard Zhao #include <linux/idr.h> 58e443b333SAlexander Shishkin #include <linux/interrupt.h> 59e443b333SAlexander Shishkin #include <linux/io.h> 60e443b333SAlexander Shishkin #include <linux/kernel.h> 61e443b333SAlexander Shishkin #include <linux/slab.h> 62e443b333SAlexander Shishkin #include <linux/pm_runtime.h> 63e443b333SAlexander Shishkin #include <linux/usb/ch9.h> 64e443b333SAlexander Shishkin #include <linux/usb/gadget.h> 65e443b333SAlexander Shishkin #include <linux/usb/otg.h> 66e443b333SAlexander Shishkin #include <linux/usb/chipidea.h> 67e443b333SAlexander Shishkin 68e443b333SAlexander Shishkin #include "ci.h" 69e443b333SAlexander Shishkin #include "udc.h" 70e443b333SAlexander Shishkin #include "bits.h" 71eb70e5abSAlexander Shishkin #include "host.h" 72e443b333SAlexander Shishkin #include "debug.h" 73e443b333SAlexander Shishkin 745f36e231SAlexander Shishkin /* Controller register map */ 75e443b333SAlexander Shishkin static uintptr_t ci_regs_nolpm[] = { 76e443b333SAlexander Shishkin [CAP_CAPLENGTH] = 0x000UL, 77e443b333SAlexander Shishkin [CAP_HCCPARAMS] = 0x008UL, 78e443b333SAlexander Shishkin [CAP_DCCPARAMS] = 0x024UL, 79e443b333SAlexander Shishkin [CAP_TESTMODE] = 0x038UL, 80e443b333SAlexander Shishkin [OP_USBCMD] = 0x000UL, 81e443b333SAlexander Shishkin [OP_USBSTS] = 0x004UL, 82e443b333SAlexander Shishkin [OP_USBINTR] = 0x008UL, 83e443b333SAlexander Shishkin [OP_DEVICEADDR] = 0x014UL, 84e443b333SAlexander Shishkin [OP_ENDPTLISTADDR] = 0x018UL, 85e443b333SAlexander Shishkin [OP_PORTSC] = 0x044UL, 86e443b333SAlexander Shishkin [OP_DEVLC] = 0x084UL, 875f36e231SAlexander Shishkin [OP_OTGSC] = 0x064UL, 88e443b333SAlexander Shishkin [OP_USBMODE] = 0x068UL, 89e443b333SAlexander Shishkin [OP_ENDPTSETUPSTAT] = 0x06CUL, 90e443b333SAlexander Shishkin [OP_ENDPTPRIME] = 0x070UL, 91e443b333SAlexander Shishkin [OP_ENDPTFLUSH] = 0x074UL, 92e443b333SAlexander Shishkin [OP_ENDPTSTAT] = 0x078UL, 93e443b333SAlexander Shishkin [OP_ENDPTCOMPLETE] = 0x07CUL, 94e443b333SAlexander Shishkin [OP_ENDPTCTRL] = 0x080UL, 95e443b333SAlexander Shishkin }; 96e443b333SAlexander Shishkin 97e443b333SAlexander Shishkin static uintptr_t ci_regs_lpm[] = { 98e443b333SAlexander Shishkin [CAP_CAPLENGTH] = 0x000UL, 99e443b333SAlexander Shishkin [CAP_HCCPARAMS] = 0x008UL, 100e443b333SAlexander Shishkin [CAP_DCCPARAMS] = 0x024UL, 101e443b333SAlexander Shishkin [CAP_TESTMODE] = 0x0FCUL, 102e443b333SAlexander Shishkin [OP_USBCMD] = 0x000UL, 103e443b333SAlexander Shishkin [OP_USBSTS] = 0x004UL, 104e443b333SAlexander Shishkin [OP_USBINTR] = 0x008UL, 105e443b333SAlexander Shishkin [OP_DEVICEADDR] = 0x014UL, 106e443b333SAlexander Shishkin [OP_ENDPTLISTADDR] = 0x018UL, 107e443b333SAlexander Shishkin [OP_PORTSC] = 0x044UL, 108e443b333SAlexander Shishkin [OP_DEVLC] = 0x084UL, 1095f36e231SAlexander Shishkin [OP_OTGSC] = 0x0C4UL, 110e443b333SAlexander Shishkin [OP_USBMODE] = 0x0C8UL, 111e443b333SAlexander Shishkin [OP_ENDPTSETUPSTAT] = 0x0D8UL, 112e443b333SAlexander Shishkin [OP_ENDPTPRIME] = 0x0DCUL, 113e443b333SAlexander Shishkin [OP_ENDPTFLUSH] = 0x0E0UL, 114e443b333SAlexander Shishkin [OP_ENDPTSTAT] = 0x0E4UL, 115e443b333SAlexander Shishkin [OP_ENDPTCOMPLETE] = 0x0E8UL, 116e443b333SAlexander Shishkin [OP_ENDPTCTRL] = 0x0ECUL, 117e443b333SAlexander Shishkin }; 118e443b333SAlexander Shishkin 1195f36e231SAlexander Shishkin static int hw_alloc_regmap(struct ci13xxx *ci, bool is_lpm) 120e443b333SAlexander Shishkin { 121e443b333SAlexander Shishkin int i; 122e443b333SAlexander Shishkin 1235f36e231SAlexander Shishkin kfree(ci->hw_bank.regmap); 124e443b333SAlexander Shishkin 1255f36e231SAlexander Shishkin ci->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *), 126e443b333SAlexander Shishkin GFP_KERNEL); 1275f36e231SAlexander Shishkin if (!ci->hw_bank.regmap) 128e443b333SAlexander Shishkin return -ENOMEM; 129e443b333SAlexander Shishkin 130e443b333SAlexander Shishkin for (i = 0; i < OP_ENDPTCTRL; i++) 1315f36e231SAlexander Shishkin ci->hw_bank.regmap[i] = 1325f36e231SAlexander Shishkin (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) + 133e443b333SAlexander Shishkin (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]); 134e443b333SAlexander Shishkin 135e443b333SAlexander Shishkin for (; i <= OP_LAST; i++) 1365f36e231SAlexander Shishkin ci->hw_bank.regmap[i] = ci->hw_bank.op + 137e443b333SAlexander Shishkin 4 * (i - OP_ENDPTCTRL) + 138e443b333SAlexander Shishkin (is_lpm 139e443b333SAlexander Shishkin ? ci_regs_lpm[OP_ENDPTCTRL] 140e443b333SAlexander Shishkin : ci_regs_nolpm[OP_ENDPTCTRL]); 141e443b333SAlexander Shishkin 142e443b333SAlexander Shishkin return 0; 143e443b333SAlexander Shishkin } 144e443b333SAlexander Shishkin 145e443b333SAlexander Shishkin /** 146e443b333SAlexander Shishkin * hw_port_test_set: writes port test mode (execute without interruption) 147e443b333SAlexander Shishkin * @mode: new value 148e443b333SAlexander Shishkin * 149e443b333SAlexander Shishkin * This function returns an error code 150e443b333SAlexander Shishkin */ 151e443b333SAlexander Shishkin int hw_port_test_set(struct ci13xxx *ci, u8 mode) 152e443b333SAlexander Shishkin { 153e443b333SAlexander Shishkin const u8 TEST_MODE_MAX = 7; 154e443b333SAlexander Shishkin 155e443b333SAlexander Shishkin if (mode > TEST_MODE_MAX) 156e443b333SAlexander Shishkin return -EINVAL; 157e443b333SAlexander Shishkin 158727b4ddbSFelipe Balbi hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC)); 159e443b333SAlexander Shishkin return 0; 160e443b333SAlexander Shishkin } 161e443b333SAlexander Shishkin 162e443b333SAlexander Shishkin /** 163e443b333SAlexander Shishkin * hw_port_test_get: reads port test mode value 164e443b333SAlexander Shishkin * 165e443b333SAlexander Shishkin * This function returns port test mode value 166e443b333SAlexander Shishkin */ 167e443b333SAlexander Shishkin u8 hw_port_test_get(struct ci13xxx *ci) 168e443b333SAlexander Shishkin { 169727b4ddbSFelipe Balbi return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC); 170e443b333SAlexander Shishkin } 171e443b333SAlexander Shishkin 1725f36e231SAlexander Shishkin static int hw_device_init(struct ci13xxx *ci, void __iomem *base) 173e443b333SAlexander Shishkin { 174e443b333SAlexander Shishkin u32 reg; 175e443b333SAlexander Shishkin 176e443b333SAlexander Shishkin /* bank is a module variable */ 1775f36e231SAlexander Shishkin ci->hw_bank.abs = base; 178e443b333SAlexander Shishkin 1795f36e231SAlexander Shishkin ci->hw_bank.cap = ci->hw_bank.abs; 18077c4400fSRichard Zhao ci->hw_bank.cap += ci->platdata->capoffset; 181938d323fSSvetoslav Neykov ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff); 182e443b333SAlexander Shishkin 1835f36e231SAlexander Shishkin hw_alloc_regmap(ci, false); 1845f36e231SAlexander Shishkin reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >> 185727b4ddbSFelipe Balbi __ffs(HCCPARAMS_LEN); 1865f36e231SAlexander Shishkin ci->hw_bank.lpm = reg; 1875f36e231SAlexander Shishkin hw_alloc_regmap(ci, !!reg); 1885f36e231SAlexander Shishkin ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs; 1895f36e231SAlexander Shishkin ci->hw_bank.size += OP_LAST; 1905f36e231SAlexander Shishkin ci->hw_bank.size /= sizeof(u32); 191e443b333SAlexander Shishkin 1925f36e231SAlexander Shishkin reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >> 193727b4ddbSFelipe Balbi __ffs(DCCPARAMS_DEN); 1945f36e231SAlexander Shishkin ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */ 195e443b333SAlexander Shishkin 19609c94e62SRichard Zhao if (ci->hw_ep_max > ENDPT_MAX) 197e443b333SAlexander Shishkin return -ENODEV; 198e443b333SAlexander Shishkin 1995f36e231SAlexander Shishkin dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n", 2005f36e231SAlexander Shishkin ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op); 201e443b333SAlexander Shishkin 202e443b333SAlexander Shishkin /* setup lock mode ? */ 203e443b333SAlexander Shishkin 204e443b333SAlexander Shishkin /* ENDPTSETUPSTAT is '0' by default */ 205e443b333SAlexander Shishkin 206e443b333SAlexander Shishkin /* HCSPARAMS.bf.ppc SHOULD BE zero for device */ 207e443b333SAlexander Shishkin 208e443b333SAlexander Shishkin return 0; 209e443b333SAlexander Shishkin } 210e443b333SAlexander Shishkin 211e443b333SAlexander Shishkin /** 212e443b333SAlexander Shishkin * hw_device_reset: resets chip (execute without interruption) 213e443b333SAlexander Shishkin * @ci: the controller 214e443b333SAlexander Shishkin * 215e443b333SAlexander Shishkin * This function returns an error code 216e443b333SAlexander Shishkin */ 217eb70e5abSAlexander Shishkin int hw_device_reset(struct ci13xxx *ci, u32 mode) 218e443b333SAlexander Shishkin { 219e443b333SAlexander Shishkin /* should flush & stop before reset */ 220e443b333SAlexander Shishkin hw_write(ci, OP_ENDPTFLUSH, ~0, ~0); 221e443b333SAlexander Shishkin hw_write(ci, OP_USBCMD, USBCMD_RS, 0); 222e443b333SAlexander Shishkin 223e443b333SAlexander Shishkin hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST); 224e443b333SAlexander Shishkin while (hw_read(ci, OP_USBCMD, USBCMD_RST)) 225e443b333SAlexander Shishkin udelay(10); /* not RTOS friendly */ 226e443b333SAlexander Shishkin 227e443b333SAlexander Shishkin 22877c4400fSRichard Zhao if (ci->platdata->notify_event) 22977c4400fSRichard Zhao ci->platdata->notify_event(ci, 230e443b333SAlexander Shishkin CI13XXX_CONTROLLER_RESET_EVENT); 231e443b333SAlexander Shishkin 23277c4400fSRichard Zhao if (ci->platdata->flags & CI13XXX_DISABLE_STREAMING) 233758fc986SAlexander Shishkin hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS); 234e443b333SAlexander Shishkin 235e443b333SAlexander Shishkin /* USBMODE should be configured step by step */ 236e443b333SAlexander Shishkin hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE); 237eb70e5abSAlexander Shishkin hw_write(ci, OP_USBMODE, USBMODE_CM, mode); 238e443b333SAlexander Shishkin /* HW >= 2.3 */ 239e443b333SAlexander Shishkin hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); 240e443b333SAlexander Shishkin 241eb70e5abSAlexander Shishkin if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) { 242eb70e5abSAlexander Shishkin pr_err("cannot enter in %s mode", ci_role(ci)->name); 243e443b333SAlexander Shishkin pr_err("lpm = %i", ci->hw_bank.lpm); 244e443b333SAlexander Shishkin return -ENODEV; 245e443b333SAlexander Shishkin } 246e443b333SAlexander Shishkin 247e443b333SAlexander Shishkin return 0; 248e443b333SAlexander Shishkin } 249e443b333SAlexander Shishkin 2505f36e231SAlexander Shishkin /** 2515f36e231SAlexander Shishkin * ci_otg_role - pick role based on ID pin state 2525f36e231SAlexander Shishkin * @ci: the controller 2535f36e231SAlexander Shishkin */ 2545f36e231SAlexander Shishkin static enum ci_role ci_otg_role(struct ci13xxx *ci) 2555f36e231SAlexander Shishkin { 2565f36e231SAlexander Shishkin u32 sts = hw_read(ci, OP_OTGSC, ~0); 2575f36e231SAlexander Shishkin enum ci_role role = sts & OTGSC_ID 2585f36e231SAlexander Shishkin ? CI_ROLE_GADGET 2595f36e231SAlexander Shishkin : CI_ROLE_HOST; 2605f36e231SAlexander Shishkin 2615f36e231SAlexander Shishkin return role; 2625f36e231SAlexander Shishkin } 2635f36e231SAlexander Shishkin 2645f36e231SAlexander Shishkin /** 2655f36e231SAlexander Shishkin * ci_role_work - perform role changing based on ID pin 2665f36e231SAlexander Shishkin * @work: work struct 2675f36e231SAlexander Shishkin */ 2685f36e231SAlexander Shishkin static void ci_role_work(struct work_struct *work) 2695f36e231SAlexander Shishkin { 2705f36e231SAlexander Shishkin struct ci13xxx *ci = container_of(work, struct ci13xxx, work); 2715f36e231SAlexander Shishkin enum ci_role role = ci_otg_role(ci); 2725f36e231SAlexander Shishkin 2735f36e231SAlexander Shishkin if (role != ci->role) { 2745f36e231SAlexander Shishkin dev_dbg(ci->dev, "switching from %s to %s\n", 2755f36e231SAlexander Shishkin ci_role(ci)->name, ci->roles[role]->name); 2765f36e231SAlexander Shishkin 2775f36e231SAlexander Shishkin ci_role_stop(ci); 2785f36e231SAlexander Shishkin ci_role_start(ci, role); 279b183c19fSRichard Zhao enable_irq(ci->irq); 2805f36e231SAlexander Shishkin } 2815f36e231SAlexander Shishkin } 2825f36e231SAlexander Shishkin 2835f36e231SAlexander Shishkin static irqreturn_t ci_irq(int irq, void *data) 2845f36e231SAlexander Shishkin { 2855f36e231SAlexander Shishkin struct ci13xxx *ci = data; 2865f36e231SAlexander Shishkin irqreturn_t ret = IRQ_NONE; 287b183c19fSRichard Zhao u32 otgsc = 0; 2885f36e231SAlexander Shishkin 289b183c19fSRichard Zhao if (ci->is_otg) 290b183c19fSRichard Zhao otgsc = hw_read(ci, OP_OTGSC, ~0); 2915f36e231SAlexander Shishkin 292b183c19fSRichard Zhao if (ci->role != CI_ROLE_END) 293b183c19fSRichard Zhao ret = ci_role(ci)->irq(ci); 294b183c19fSRichard Zhao 295b183c19fSRichard Zhao if (ci->is_otg && (otgsc & OTGSC_IDIS)) { 296984f753cSRichard Zhao hw_write(ci, OP_OTGSC, OTGSC_IDIS, OTGSC_IDIS); 297b183c19fSRichard Zhao disable_irq_nosync(ci->irq); 2985f36e231SAlexander Shishkin queue_work(ci->wq, &ci->work); 2995f36e231SAlexander Shishkin ret = IRQ_HANDLED; 3005f36e231SAlexander Shishkin } 3015f36e231SAlexander Shishkin 302b183c19fSRichard Zhao return ret; 3035f36e231SAlexander Shishkin } 3045f36e231SAlexander Shishkin 305fe6e125eSRichard Zhao static DEFINE_IDA(ci_ida); 306fe6e125eSRichard Zhao 307cbc6dc2aSRichard Zhao struct platform_device *ci13xxx_add_device(struct device *dev, 308cbc6dc2aSRichard Zhao struct resource *res, int nres, 309cbc6dc2aSRichard Zhao struct ci13xxx_platform_data *platdata) 310cbc6dc2aSRichard Zhao { 311cbc6dc2aSRichard Zhao struct platform_device *pdev; 312fe6e125eSRichard Zhao int id, ret; 313cbc6dc2aSRichard Zhao 314fe6e125eSRichard Zhao id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL); 315fe6e125eSRichard Zhao if (id < 0) 316fe6e125eSRichard Zhao return ERR_PTR(id); 317fe6e125eSRichard Zhao 318fe6e125eSRichard Zhao pdev = platform_device_alloc("ci_hdrc", id); 319fe6e125eSRichard Zhao if (!pdev) { 320fe6e125eSRichard Zhao ret = -ENOMEM; 321fe6e125eSRichard Zhao goto put_id; 322fe6e125eSRichard Zhao } 323cbc6dc2aSRichard Zhao 324cbc6dc2aSRichard Zhao pdev->dev.parent = dev; 325cbc6dc2aSRichard Zhao pdev->dev.dma_mask = dev->dma_mask; 326cbc6dc2aSRichard Zhao pdev->dev.dma_parms = dev->dma_parms; 327cbc6dc2aSRichard Zhao dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask); 328cbc6dc2aSRichard Zhao 329cbc6dc2aSRichard Zhao ret = platform_device_add_resources(pdev, res, nres); 330cbc6dc2aSRichard Zhao if (ret) 331cbc6dc2aSRichard Zhao goto err; 332cbc6dc2aSRichard Zhao 333cbc6dc2aSRichard Zhao ret = platform_device_add_data(pdev, platdata, sizeof(*platdata)); 334cbc6dc2aSRichard Zhao if (ret) 335cbc6dc2aSRichard Zhao goto err; 336cbc6dc2aSRichard Zhao 337cbc6dc2aSRichard Zhao ret = platform_device_add(pdev); 338cbc6dc2aSRichard Zhao if (ret) 339cbc6dc2aSRichard Zhao goto err; 340cbc6dc2aSRichard Zhao 341cbc6dc2aSRichard Zhao return pdev; 342cbc6dc2aSRichard Zhao 343cbc6dc2aSRichard Zhao err: 344cbc6dc2aSRichard Zhao platform_device_put(pdev); 345fe6e125eSRichard Zhao put_id: 346fe6e125eSRichard Zhao ida_simple_remove(&ci_ida, id); 347cbc6dc2aSRichard Zhao return ERR_PTR(ret); 348cbc6dc2aSRichard Zhao } 349cbc6dc2aSRichard Zhao EXPORT_SYMBOL_GPL(ci13xxx_add_device); 350cbc6dc2aSRichard Zhao 351cbc6dc2aSRichard Zhao void ci13xxx_remove_device(struct platform_device *pdev) 352cbc6dc2aSRichard Zhao { 35398c35534SLothar Waßmann int id = pdev->id; 354cbc6dc2aSRichard Zhao platform_device_unregister(pdev); 35598c35534SLothar Waßmann ida_simple_remove(&ci_ida, id); 356cbc6dc2aSRichard Zhao } 357cbc6dc2aSRichard Zhao EXPORT_SYMBOL_GPL(ci13xxx_remove_device); 358cbc6dc2aSRichard Zhao 35941ac7b3aSBill Pemberton static int ci_hdrc_probe(struct platform_device *pdev) 360e443b333SAlexander Shishkin { 361e443b333SAlexander Shishkin struct device *dev = &pdev->dev; 3625f36e231SAlexander Shishkin struct ci13xxx *ci; 363e443b333SAlexander Shishkin struct resource *res; 364e443b333SAlexander Shishkin void __iomem *base; 365e443b333SAlexander Shishkin int ret; 366e443b333SAlexander Shishkin 3675f36e231SAlexander Shishkin if (!dev->platform_data) { 368e443b333SAlexander Shishkin dev_err(dev, "platform data missing\n"); 369e443b333SAlexander Shishkin return -ENODEV; 370e443b333SAlexander Shishkin } 371e443b333SAlexander Shishkin 372e443b333SAlexander Shishkin res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 373e443b333SAlexander Shishkin if (!res) { 374e443b333SAlexander Shishkin dev_err(dev, "missing resource\n"); 375e443b333SAlexander Shishkin return -ENODEV; 376e443b333SAlexander Shishkin } 377e443b333SAlexander Shishkin 37819290816SFelipe Balbi base = devm_ioremap_resource(dev, res); 37919290816SFelipe Balbi if (IS_ERR(base)) 38019290816SFelipe Balbi return PTR_ERR(base); 381e443b333SAlexander Shishkin 3825f36e231SAlexander Shishkin ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL); 3835f36e231SAlexander Shishkin if (!ci) { 3845f36e231SAlexander Shishkin dev_err(dev, "can't allocate device\n"); 3855f36e231SAlexander Shishkin return -ENOMEM; 3865f36e231SAlexander Shishkin } 387e443b333SAlexander Shishkin 3885f36e231SAlexander Shishkin ci->dev = dev; 38977c4400fSRichard Zhao ci->platdata = dev->platform_data; 390a2c3d690SRichard Zhao if (ci->platdata->phy) 391a2c3d690SRichard Zhao ci->transceiver = ci->platdata->phy; 392a2c3d690SRichard Zhao else 393a2c3d690SRichard Zhao ci->global_phy = true; 3945f36e231SAlexander Shishkin 3955f36e231SAlexander Shishkin ret = hw_device_init(ci, base); 3965f36e231SAlexander Shishkin if (ret < 0) { 3975f36e231SAlexander Shishkin dev_err(dev, "can't initialize hardware\n"); 3985f36e231SAlexander Shishkin return -ENODEV; 3995f36e231SAlexander Shishkin } 4005f36e231SAlexander Shishkin 401eb70e5abSAlexander Shishkin ci->hw_bank.phys = res->start; 402eb70e5abSAlexander Shishkin 4035f36e231SAlexander Shishkin ci->irq = platform_get_irq(pdev, 0); 4045f36e231SAlexander Shishkin if (ci->irq < 0) { 405e443b333SAlexander Shishkin dev_err(dev, "missing IRQ\n"); 4065f36e231SAlexander Shishkin return -ENODEV; 407e443b333SAlexander Shishkin } 408e443b333SAlexander Shishkin 4095f36e231SAlexander Shishkin INIT_WORK(&ci->work, ci_role_work); 4105f36e231SAlexander Shishkin ci->wq = create_singlethread_workqueue("ci_otg"); 4115f36e231SAlexander Shishkin if (!ci->wq) { 4125f36e231SAlexander Shishkin dev_err(dev, "can't create workqueue\n"); 4135f36e231SAlexander Shishkin return -ENODEV; 4145f36e231SAlexander Shishkin } 415e443b333SAlexander Shishkin 4165f36e231SAlexander Shishkin /* initialize role(s) before the interrupt is requested */ 417eb70e5abSAlexander Shishkin ret = ci_hdrc_host_init(ci); 418eb70e5abSAlexander Shishkin if (ret) 419eb70e5abSAlexander Shishkin dev_info(dev, "doesn't support host\n"); 420eb70e5abSAlexander Shishkin 4215f36e231SAlexander Shishkin ret = ci_hdrc_gadget_init(ci); 422e443b333SAlexander Shishkin if (ret) 4235f36e231SAlexander Shishkin dev_info(dev, "doesn't support gadget\n"); 4245f36e231SAlexander Shishkin 4255f36e231SAlexander Shishkin if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) { 4265f36e231SAlexander Shishkin dev_err(dev, "no supported roles\n"); 4275f36e231SAlexander Shishkin ret = -ENODEV; 4285f36e231SAlexander Shishkin goto rm_wq; 4295f36e231SAlexander Shishkin } 4305f36e231SAlexander Shishkin 4315f36e231SAlexander Shishkin if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) { 4325f36e231SAlexander Shishkin ci->is_otg = true; 43386ad01a9SRichard Zhao /* ID pin needs 1ms debouce time, we delay 2ms for safe */ 43486ad01a9SRichard Zhao mdelay(2); 4355f36e231SAlexander Shishkin ci->role = ci_otg_role(ci); 4365f36e231SAlexander Shishkin } else { 4375f36e231SAlexander Shishkin ci->role = ci->roles[CI_ROLE_HOST] 4385f36e231SAlexander Shishkin ? CI_ROLE_HOST 4395f36e231SAlexander Shishkin : CI_ROLE_GADGET; 4405f36e231SAlexander Shishkin } 4415f36e231SAlexander Shishkin 4425f36e231SAlexander Shishkin ret = ci_role_start(ci, ci->role); 4435f36e231SAlexander Shishkin if (ret) { 4445f36e231SAlexander Shishkin dev_err(dev, "can't start %s role\n", ci_role(ci)->name); 4455f36e231SAlexander Shishkin ret = -ENODEV; 4465f36e231SAlexander Shishkin goto rm_wq; 4475f36e231SAlexander Shishkin } 4485f36e231SAlexander Shishkin 4495f36e231SAlexander Shishkin platform_set_drvdata(pdev, ci); 45077c4400fSRichard Zhao ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name, 4515f36e231SAlexander Shishkin ci); 4525f36e231SAlexander Shishkin if (ret) 4535f36e231SAlexander Shishkin goto stop; 4545f36e231SAlexander Shishkin 4555f36e231SAlexander Shishkin if (ci->is_otg) 4565f36e231SAlexander Shishkin hw_write(ci, OP_OTGSC, OTGSC_IDIE, OTGSC_IDIE); 4575f36e231SAlexander Shishkin 458adf0f735SAlexander Shishkin ret = dbg_create_files(ci); 459adf0f735SAlexander Shishkin if (!ret) 460adf0f735SAlexander Shishkin return 0; 4615f36e231SAlexander Shishkin 462adf0f735SAlexander Shishkin free_irq(ci->irq, ci); 4635f36e231SAlexander Shishkin stop: 4645f36e231SAlexander Shishkin ci_role_stop(ci); 4655f36e231SAlexander Shishkin rm_wq: 4665f36e231SAlexander Shishkin flush_workqueue(ci->wq); 4675f36e231SAlexander Shishkin destroy_workqueue(ci->wq); 468e443b333SAlexander Shishkin 469e443b333SAlexander Shishkin return ret; 470e443b333SAlexander Shishkin } 471e443b333SAlexander Shishkin 472fb4e98abSBill Pemberton static int ci_hdrc_remove(struct platform_device *pdev) 473e443b333SAlexander Shishkin { 4745f36e231SAlexander Shishkin struct ci13xxx *ci = platform_get_drvdata(pdev); 475e443b333SAlexander Shishkin 476adf0f735SAlexander Shishkin dbg_remove_files(ci); 4775f36e231SAlexander Shishkin flush_workqueue(ci->wq); 4785f36e231SAlexander Shishkin destroy_workqueue(ci->wq); 4795f36e231SAlexander Shishkin free_irq(ci->irq, ci); 4805f36e231SAlexander Shishkin ci_role_stop(ci); 481e443b333SAlexander Shishkin 482e443b333SAlexander Shishkin return 0; 483e443b333SAlexander Shishkin } 484e443b333SAlexander Shishkin 4855f36e231SAlexander Shishkin static struct platform_driver ci_hdrc_driver = { 4865f36e231SAlexander Shishkin .probe = ci_hdrc_probe, 4877690417dSBill Pemberton .remove = ci_hdrc_remove, 488e443b333SAlexander Shishkin .driver = { 4895f36e231SAlexander Shishkin .name = "ci_hdrc", 490e443b333SAlexander Shishkin }, 491e443b333SAlexander Shishkin }; 492e443b333SAlexander Shishkin 4935f36e231SAlexander Shishkin module_platform_driver(ci_hdrc_driver); 494e443b333SAlexander Shishkin 4955f36e231SAlexander Shishkin MODULE_ALIAS("platform:ci_hdrc"); 496e443b333SAlexander Shishkin MODULE_ALIAS("platform:ci13xxx"); 497e443b333SAlexander Shishkin MODULE_LICENSE("GPL v2"); 498e443b333SAlexander Shishkin MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>"); 4995f36e231SAlexander Shishkin MODULE_DESCRIPTION("ChipIdea HDRC Driver"); 500