1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2016, NVIDIA Corporation
4  */
5 
6 #include <linux/clk.h>
7 #include <linux/io.h>
8 #include <linux/module.h>
9 #include <linux/of_device.h>
10 #include <linux/pm_runtime.h>
11 #include <linux/reset.h>
12 
13 #include <linux/usb.h>
14 #include <linux/usb/chipidea.h>
15 #include <linux/usb/hcd.h>
16 #include <linux/usb/of.h>
17 #include <linux/usb/phy.h>
18 
19 #include <soc/tegra/common.h>
20 
21 #include "../host/ehci.h"
22 
23 #include "ci.h"
24 
25 struct tegra_usb {
26 	struct ci_hdrc_platform_data data;
27 	struct platform_device *dev;
28 
29 	const struct tegra_usb_soc_info *soc;
30 	struct usb_phy *phy;
31 	struct clk *clk;
32 
33 	bool needs_double_reset;
34 };
35 
36 struct tegra_usb_soc_info {
37 	unsigned long flags;
38 	unsigned int txfifothresh;
39 	enum usb_dr_mode dr_mode;
40 };
41 
42 static const struct tegra_usb_soc_info tegra20_ehci_soc_info = {
43 	.flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
44 		 CI_HDRC_OVERRIDE_PHY_CONTROL |
45 		 CI_HDRC_SUPPORTS_RUNTIME_PM,
46 	.dr_mode = USB_DR_MODE_HOST,
47 	.txfifothresh = 10,
48 };
49 
50 static const struct tegra_usb_soc_info tegra30_ehci_soc_info = {
51 	.flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
52 		 CI_HDRC_OVERRIDE_PHY_CONTROL |
53 		 CI_HDRC_SUPPORTS_RUNTIME_PM,
54 	.dr_mode = USB_DR_MODE_HOST,
55 	.txfifothresh = 16,
56 };
57 
58 static const struct tegra_usb_soc_info tegra20_udc_soc_info = {
59 	.flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
60 		 CI_HDRC_OVERRIDE_PHY_CONTROL |
61 		 CI_HDRC_SUPPORTS_RUNTIME_PM,
62 	.dr_mode = USB_DR_MODE_UNKNOWN,
63 	.txfifothresh = 10,
64 };
65 
66 static const struct tegra_usb_soc_info tegra30_udc_soc_info = {
67 	.flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
68 		 CI_HDRC_OVERRIDE_PHY_CONTROL |
69 		 CI_HDRC_SUPPORTS_RUNTIME_PM,
70 	.dr_mode = USB_DR_MODE_UNKNOWN,
71 	.txfifothresh = 16,
72 };
73 
74 static const struct of_device_id tegra_usb_of_match[] = {
75 	{
76 		.compatible = "nvidia,tegra20-ehci",
77 		.data = &tegra20_ehci_soc_info,
78 	}, {
79 		.compatible = "nvidia,tegra30-ehci",
80 		.data = &tegra30_ehci_soc_info,
81 	}, {
82 		.compatible = "nvidia,tegra20-udc",
83 		.data = &tegra20_udc_soc_info,
84 	}, {
85 		.compatible = "nvidia,tegra30-udc",
86 		.data = &tegra30_udc_soc_info,
87 	}, {
88 		.compatible = "nvidia,tegra114-udc",
89 		.data = &tegra30_udc_soc_info,
90 	}, {
91 		.compatible = "nvidia,tegra124-udc",
92 		.data = &tegra30_udc_soc_info,
93 	}, {
94 		/* sentinel */
95 	}
96 };
97 MODULE_DEVICE_TABLE(of, tegra_usb_of_match);
98 
99 static int tegra_usb_reset_controller(struct device *dev)
100 {
101 	struct reset_control *rst, *rst_utmi;
102 	struct device_node *phy_np;
103 	int err;
104 
105 	rst = devm_reset_control_get_shared(dev, "usb");
106 	if (IS_ERR(rst)) {
107 		dev_err(dev, "can't get ehci reset: %pe\n", rst);
108 		return PTR_ERR(rst);
109 	}
110 
111 	phy_np = of_parse_phandle(dev->of_node, "nvidia,phy", 0);
112 	if (!phy_np)
113 		return -ENOENT;
114 
115 	/*
116 	 * The 1st USB controller contains some UTMI pad registers that are
117 	 * global for all the controllers on the chip. Those registers are
118 	 * also cleared when reset is asserted to the 1st controller.
119 	 */
120 	rst_utmi = of_reset_control_get_shared(phy_np, "utmi-pads");
121 	if (IS_ERR(rst_utmi)) {
122 		dev_warn(dev, "can't get utmi-pads reset from the PHY\n");
123 		dev_warn(dev, "continuing, but please update your DT\n");
124 	} else {
125 		/*
126 		 * PHY driver performs UTMI-pads reset in a case of a
127 		 * non-legacy DT.
128 		 */
129 		reset_control_put(rst_utmi);
130 	}
131 
132 	of_node_put(phy_np);
133 
134 	/* reset control is shared, hence initialize it first */
135 	err = reset_control_deassert(rst);
136 	if (err)
137 		return err;
138 
139 	err = reset_control_assert(rst);
140 	if (err)
141 		return err;
142 
143 	udelay(1);
144 
145 	err = reset_control_deassert(rst);
146 	if (err)
147 		return err;
148 
149 	return 0;
150 }
151 
152 static int tegra_usb_notify_event(struct ci_hdrc *ci, unsigned int event)
153 {
154 	struct tegra_usb *usb = dev_get_drvdata(ci->dev->parent);
155 	struct ehci_hcd *ehci;
156 
157 	switch (event) {
158 	case CI_HDRC_CONTROLLER_RESET_EVENT:
159 		if (ci->hcd) {
160 			ehci = hcd_to_ehci(ci->hcd);
161 			ehci->has_tdi_phy_lpm = false;
162 			ehci_writel(ehci, usb->soc->txfifothresh << 16,
163 				    &ehci->regs->txfill_tuning);
164 		}
165 		break;
166 	}
167 
168 	return 0;
169 }
170 
171 static int tegra_usb_internal_port_reset(struct ehci_hcd *ehci,
172 					 u32 __iomem *portsc_reg,
173 					 unsigned long *flags)
174 {
175 	u32 saved_usbintr, temp;
176 	unsigned int i, tries;
177 	int retval = 0;
178 
179 	saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
180 	/* disable USB interrupt */
181 	ehci_writel(ehci, 0, &ehci->regs->intr_enable);
182 	spin_unlock_irqrestore(&ehci->lock, *flags);
183 
184 	/*
185 	 * Here we have to do Port Reset at most twice for
186 	 * Port Enable bit to be set.
187 	 */
188 	for (i = 0; i < 2; i++) {
189 		temp = ehci_readl(ehci, portsc_reg);
190 		temp |= PORT_RESET;
191 		ehci_writel(ehci, temp, portsc_reg);
192 		fsleep(10000);
193 		temp &= ~PORT_RESET;
194 		ehci_writel(ehci, temp, portsc_reg);
195 		fsleep(1000);
196 		tries = 100;
197 		do {
198 			fsleep(1000);
199 			/*
200 			 * Up to this point, Port Enable bit is
201 			 * expected to be set after 2 ms waiting.
202 			 * USB1 usually takes extra 45 ms, for safety,
203 			 * we take 100 ms as timeout.
204 			 */
205 			temp = ehci_readl(ehci, portsc_reg);
206 		} while (!(temp & PORT_PE) && tries--);
207 		if (temp & PORT_PE)
208 			break;
209 	}
210 	if (i == 2)
211 		retval = -ETIMEDOUT;
212 
213 	/*
214 	 * Clear Connect Status Change bit if it's set.
215 	 * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
216 	 */
217 	if (temp & PORT_CSC)
218 		ehci_writel(ehci, PORT_CSC, portsc_reg);
219 
220 	/*
221 	 * Write to clear any interrupt status bits that might be set
222 	 * during port reset.
223 	 */
224 	temp = ehci_readl(ehci, &ehci->regs->status);
225 	ehci_writel(ehci, temp, &ehci->regs->status);
226 
227 	/* restore original interrupt-enable bits */
228 	spin_lock_irqsave(&ehci->lock, *flags);
229 	ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
230 
231 	return retval;
232 }
233 
234 static int tegra_ehci_hub_control(struct ci_hdrc *ci, u16 typeReq, u16 wValue,
235 				  u16 wIndex, char *buf, u16 wLength,
236 				  bool *done, unsigned long *flags)
237 {
238 	struct tegra_usb *usb = dev_get_drvdata(ci->dev->parent);
239 	struct ehci_hcd *ehci = hcd_to_ehci(ci->hcd);
240 	u32 __iomem *status_reg;
241 	int retval = 0;
242 
243 	status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
244 
245 	switch (typeReq) {
246 	case SetPortFeature:
247 		if (wValue != USB_PORT_FEAT_RESET || !usb->needs_double_reset)
248 			break;
249 
250 		/* for USB1 port we need to issue Port Reset twice internally */
251 		retval = tegra_usb_internal_port_reset(ehci, status_reg, flags);
252 		*done  = true;
253 		break;
254 	}
255 
256 	return retval;
257 }
258 
259 static void tegra_usb_enter_lpm(struct ci_hdrc *ci, bool enable)
260 {
261 	/*
262 	 * Touching any register which belongs to AHB clock domain will
263 	 * hang CPU if USB controller is put into low power mode because
264 	 * AHB USB clock is gated on Tegra in the LPM.
265 	 *
266 	 * Tegra PHY has a separate register for checking the clock status
267 	 * and usb_phy_set_suspend() takes care of gating/ungating the clocks
268 	 * and restoring the PHY state on Tegra. Hence DEVLC/PORTSC registers
269 	 * shouldn't be touched directly by the CI driver.
270 	 */
271 	usb_phy_set_suspend(ci->usb_phy, enable);
272 }
273 
274 static int tegra_usb_probe(struct platform_device *pdev)
275 {
276 	const struct tegra_usb_soc_info *soc;
277 	struct tegra_usb *usb;
278 	int err;
279 
280 	usb = devm_kzalloc(&pdev->dev, sizeof(*usb), GFP_KERNEL);
281 	if (!usb)
282 		return -ENOMEM;
283 
284 	platform_set_drvdata(pdev, usb);
285 
286 	soc = of_device_get_match_data(&pdev->dev);
287 	if (!soc) {
288 		dev_err(&pdev->dev, "failed to match OF data\n");
289 		return -EINVAL;
290 	}
291 
292 	usb->phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0);
293 	if (IS_ERR(usb->phy))
294 		return dev_err_probe(&pdev->dev, PTR_ERR(usb->phy),
295 				     "failed to get PHY\n");
296 
297 	usb->clk = devm_clk_get(&pdev->dev, NULL);
298 	if (IS_ERR(usb->clk)) {
299 		err = PTR_ERR(usb->clk);
300 		dev_err(&pdev->dev, "failed to get clock: %d\n", err);
301 		return err;
302 	}
303 
304 	err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
305 	if (err)
306 		return err;
307 
308 	pm_runtime_enable(&pdev->dev);
309 	err = pm_runtime_resume_and_get(&pdev->dev);
310 	if (err)
311 		return err;
312 
313 	if (device_property_present(&pdev->dev, "nvidia,needs-double-reset"))
314 		usb->needs_double_reset = true;
315 
316 	err = tegra_usb_reset_controller(&pdev->dev);
317 	if (err) {
318 		dev_err(&pdev->dev, "failed to reset controller: %d\n", err);
319 		goto fail_power_off;
320 	}
321 
322 	/*
323 	 * USB controller registers shouldn't be touched before PHY is
324 	 * initialized, otherwise CPU will hang because clocks are gated.
325 	 * PHY driver controls gating of internal USB clocks on Tegra.
326 	 */
327 	err = usb_phy_init(usb->phy);
328 	if (err)
329 		goto fail_power_off;
330 
331 	/* setup and register ChipIdea HDRC device */
332 	usb->soc = soc;
333 	usb->data.name = "tegra-usb";
334 	usb->data.flags = soc->flags;
335 	usb->data.usb_phy = usb->phy;
336 	usb->data.dr_mode = soc->dr_mode;
337 	usb->data.capoffset = DEF_CAPOFFSET;
338 	usb->data.enter_lpm = tegra_usb_enter_lpm;
339 	usb->data.hub_control = tegra_ehci_hub_control;
340 	usb->data.notify_event = tegra_usb_notify_event;
341 
342 	/* Tegra PHY driver currently doesn't support LPM for ULPI */
343 	if (of_usb_get_phy_mode(pdev->dev.of_node) == USBPHY_INTERFACE_MODE_ULPI)
344 		usb->data.flags &= ~CI_HDRC_SUPPORTS_RUNTIME_PM;
345 
346 	usb->dev = ci_hdrc_add_device(&pdev->dev, pdev->resource,
347 				      pdev->num_resources, &usb->data);
348 	if (IS_ERR(usb->dev)) {
349 		err = PTR_ERR(usb->dev);
350 		dev_err(&pdev->dev, "failed to add HDRC device: %d\n", err);
351 		goto phy_shutdown;
352 	}
353 
354 	return 0;
355 
356 phy_shutdown:
357 	usb_phy_shutdown(usb->phy);
358 fail_power_off:
359 	pm_runtime_put_sync_suspend(&pdev->dev);
360 	pm_runtime_force_suspend(&pdev->dev);
361 
362 	return err;
363 }
364 
365 static int tegra_usb_remove(struct platform_device *pdev)
366 {
367 	struct tegra_usb *usb = platform_get_drvdata(pdev);
368 
369 	ci_hdrc_remove_device(usb->dev);
370 	usb_phy_shutdown(usb->phy);
371 
372 	pm_runtime_put_sync_suspend(&pdev->dev);
373 	pm_runtime_force_suspend(&pdev->dev);
374 
375 	return 0;
376 }
377 
378 static int __maybe_unused tegra_usb_runtime_resume(struct device *dev)
379 {
380 	struct tegra_usb *usb = dev_get_drvdata(dev);
381 	int err;
382 
383 	err = clk_prepare_enable(usb->clk);
384 	if (err < 0) {
385 		dev_err(dev, "failed to enable clock: %d\n", err);
386 		return err;
387 	}
388 
389 	return 0;
390 }
391 
392 static int __maybe_unused tegra_usb_runtime_suspend(struct device *dev)
393 {
394 	struct tegra_usb *usb = dev_get_drvdata(dev);
395 
396 	clk_disable_unprepare(usb->clk);
397 
398 	return 0;
399 }
400 
401 static const struct dev_pm_ops tegra_usb_pm = {
402 	SET_RUNTIME_PM_OPS(tegra_usb_runtime_suspend, tegra_usb_runtime_resume,
403 			   NULL)
404 };
405 
406 static struct platform_driver tegra_usb_driver = {
407 	.driver = {
408 		.name = "tegra-usb",
409 		.of_match_table = tegra_usb_of_match,
410 		.pm = &tegra_usb_pm,
411 	},
412 	.probe = tegra_usb_probe,
413 	.remove = tegra_usb_remove,
414 };
415 module_platform_driver(tegra_usb_driver);
416 
417 MODULE_DESCRIPTION("NVIDIA Tegra USB driver");
418 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
419 MODULE_LICENSE("GPL v2");
420