xref: /openbmc/linux/drivers/usb/chipidea/ci.h (revision dd1fc3c5) 
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * ci.h - common structures, functions, and macros of the ChipIdea driver
4  *
5  * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
6  *
7  * Author: David Lopo
8  */
9 
10 #ifndef __DRIVERS_USB_CHIPIDEA_CI_H
11 #define __DRIVERS_USB_CHIPIDEA_CI_H
12 
13 #include <linux/list.h>
14 #include <linux/irqreturn.h>
15 #include <linux/usb.h>
16 #include <linux/usb/gadget.h>
17 #include <linux/usb/otg-fsm.h>
18 #include <linux/usb/otg.h>
19 #include <linux/usb/role.h>
20 #include <linux/ulpi/interface.h>
21 
22 /******************************************************************************
23  * DEFINE
24  *****************************************************************************/
25 #define TD_PAGE_COUNT      5
26 #define CI_HDRC_PAGE_SIZE  4096ul /* page size for TD's */
27 #define ENDPT_MAX          32
28 #define CI_MAX_BUF_SIZE	(TD_PAGE_COUNT * CI_HDRC_PAGE_SIZE)
29 
30 /******************************************************************************
31  * REGISTERS
32  *****************************************************************************/
33 /* Identification Registers */
34 #define ID_ID				0x0
35 #define ID_HWGENERAL			0x4
36 #define ID_HWHOST			0x8
37 #define ID_HWDEVICE			0xc
38 #define ID_HWTXBUF			0x10
39 #define ID_HWRXBUF			0x14
40 #define ID_SBUSCFG			0x90
41 
42 /* register indices */
43 enum ci_hw_regs {
44 	CAP_CAPLENGTH,
45 	CAP_HCCPARAMS,
46 	CAP_DCCPARAMS,
47 	CAP_TESTMODE,
48 	CAP_LAST = CAP_TESTMODE,
49 	OP_USBCMD,
50 	OP_USBSTS,
51 	OP_USBINTR,
52 	OP_DEVICEADDR,
53 	OP_ENDPTLISTADDR,
54 	OP_TTCTRL,
55 	OP_BURSTSIZE,
56 	OP_ULPI_VIEWPORT,
57 	OP_PORTSC,
58 	OP_DEVLC,
59 	OP_OTGSC,
60 	OP_USBMODE,
61 	OP_ENDPTSETUPSTAT,
62 	OP_ENDPTPRIME,
63 	OP_ENDPTFLUSH,
64 	OP_ENDPTSTAT,
65 	OP_ENDPTCOMPLETE,
66 	OP_ENDPTCTRL,
67 	/* endptctrl1..15 follow */
68 	OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
69 };
70 
71 /******************************************************************************
72  * STRUCTURES
73  *****************************************************************************/
74 /**
75  * struct ci_hw_ep - endpoint representation
76  * @ep: endpoint structure for gadget drivers
77  * @dir: endpoint direction (TX/RX)
78  * @num: endpoint number
79  * @type: endpoint type
80  * @name: string description of the endpoint
81  * @qh: queue head for this endpoint
82  * @wedge: is the endpoint wedged
83  * @ci: pointer to the controller
84  * @lock: pointer to controller's spinlock
85  * @td_pool: pointer to controller's TD pool
86  */
87 struct ci_hw_ep {
88 	struct usb_ep				ep;
89 	u8					dir;
90 	u8					num;
91 	u8					type;
92 	char					name[16];
93 	struct {
94 		struct list_head	queue;
95 		struct ci_hw_qh		*ptr;
96 		dma_addr_t		dma;
97 	}					qh;
98 	int					wedge;
99 
100 	/* global resources */
101 	struct ci_hdrc				*ci;
102 	spinlock_t				*lock;
103 	struct dma_pool				*td_pool;
104 	struct td_node				*pending_td;
105 };
106 
107 enum ci_role {
108 	CI_ROLE_HOST = 0,
109 	CI_ROLE_GADGET,
110 	CI_ROLE_END,
111 };
112 
113 enum ci_revision {
114 	CI_REVISION_1X = 10,	/* Revision 1.x */
115 	CI_REVISION_20 = 20, /* Revision 2.0 */
116 	CI_REVISION_21, /* Revision 2.1 */
117 	CI_REVISION_22, /* Revision 2.2 */
118 	CI_REVISION_23, /* Revision 2.3 */
119 	CI_REVISION_24, /* Revision 2.4 */
120 	CI_REVISION_25, /* Revision 2.5 */
121 	CI_REVISION_25_PLUS, /* Revision above than 2.5 */
122 	CI_REVISION_UNKNOWN = 99, /* Unknown Revision */
123 };
124 
125 /**
126  * struct ci_role_driver - host/gadget role driver
127  * @start: start this role
128  * @stop: stop this role
129  * @irq: irq handler for this role
130  * @name: role name string (host/gadget)
131  */
132 struct ci_role_driver {
133 	int		(*start)(struct ci_hdrc *);
134 	void		(*stop)(struct ci_hdrc *);
135 	irqreturn_t	(*irq)(struct ci_hdrc *);
136 	const char	*name;
137 };
138 
139 /**
140  * struct hw_bank - hardware register mapping representation
141  * @lpm: set if the device is LPM capable
142  * @phys: physical address of the controller's registers
143  * @abs: absolute address of the beginning of register window
144  * @cap: capability registers
145  * @op: operational registers
146  * @size: size of the register window
147  * @regmap: register lookup table
148  */
149 struct hw_bank {
150 	unsigned	lpm;
151 	resource_size_t	phys;
152 	void __iomem	*abs;
153 	void __iomem	*cap;
154 	void __iomem	*op;
155 	size_t		size;
156 	void __iomem	*regmap[OP_LAST + 1];
157 };
158 
159 /**
160  * struct ci_hdrc - chipidea device representation
161  * @dev: pointer to parent device
162  * @lock: access synchronization
163  * @hw_bank: hardware register mapping
164  * @irq: IRQ number
165  * @roles: array of supported roles for this controller
166  * @role: current role
167  * @is_otg: if the device is otg-capable
168  * @fsm: otg finite state machine
169  * @otg_fsm_hrtimer: hrtimer for otg fsm timers
170  * @hr_timeouts: time out list for active otg fsm timers
171  * @enabled_otg_timer_bits: bits of enabled otg timers
172  * @next_otg_timer: next nearest enabled timer to be expired
173  * @work: work for role changing
174  * @wq: workqueue thread
175  * @qh_pool: allocation pool for queue heads
176  * @td_pool: allocation pool for transfer descriptors
177  * @gadget: device side representation for peripheral controller
178  * @driver: gadget driver
179  * @resume_state: save the state of gadget suspend from
180  * @hw_ep_max: total number of endpoints supported by hardware
181  * @ci_hw_ep: array of endpoints
182  * @ep0_dir: ep0 direction
183  * @ep0out: pointer to ep0 OUT endpoint
184  * @ep0in: pointer to ep0 IN endpoint
185  * @status: ep0 status request
186  * @setaddr: if we should set the address on status completion
187  * @address: usb address received from the host
188  * @remote_wakeup: host-enabled remote wakeup
189  * @suspended: suspended by host
190  * @test_mode: the selected test mode
191  * @platdata: platform specific information supplied by parent device
192  * @vbus_active: is VBUS active
193  * @ulpi: pointer to ULPI device, if any
194  * @ulpi_ops: ULPI read/write ops for this device
195  * @phy: pointer to PHY, if any
196  * @usb_phy: pointer to USB PHY, if any and if using the USB PHY framework
197  * @hcd: pointer to usb_hcd for ehci host driver
198  * @debugfs: root dentry for this controller in debugfs
199  * @id_event: indicates there is an id event, and handled at ci_otg_work
200  * @b_sess_valid_event: indicates there is a vbus event, and handled
201  * at ci_otg_work
202  * @imx28_write_fix: Freescale imx28 needs swp instruction for writing
203  * @supports_runtime_pm: if runtime pm is supported
204  * @in_lpm: if the core in low power mode
205  * @wakeup_int: if wakeup interrupt occur
206  * @rev: The revision number for controller
207  */
208 struct ci_hdrc {
209 	struct device			*dev;
210 	spinlock_t			lock;
211 	struct hw_bank			hw_bank;
212 	int				irq;
213 	struct ci_role_driver		*roles[CI_ROLE_END];
214 	enum ci_role			role;
215 	bool				is_otg;
216 	struct usb_otg			otg;
217 	struct otg_fsm			fsm;
218 	struct hrtimer			otg_fsm_hrtimer;
219 	ktime_t				hr_timeouts[NUM_OTG_FSM_TIMERS];
220 	unsigned			enabled_otg_timer_bits;
221 	enum otg_fsm_timer		next_otg_timer;
222 	struct usb_role_switch		*role_switch;
223 	struct work_struct		work;
224 	struct workqueue_struct		*wq;
225 
226 	struct dma_pool			*qh_pool;
227 	struct dma_pool			*td_pool;
228 
229 	struct usb_gadget		gadget;
230 	struct usb_gadget_driver	*driver;
231 	enum usb_device_state		resume_state;
232 	unsigned			hw_ep_max;
233 	struct ci_hw_ep			ci_hw_ep[ENDPT_MAX];
234 	u32				ep0_dir;
235 	struct ci_hw_ep			*ep0out, *ep0in;
236 
237 	struct usb_request		*status;
238 	bool				setaddr;
239 	u8				address;
240 	u8				remote_wakeup;
241 	u8				suspended;
242 	u8				test_mode;
243 
244 	struct ci_hdrc_platform_data	*platdata;
245 	int				vbus_active;
246 	struct ulpi			*ulpi;
247 	struct ulpi_ops 		ulpi_ops;
248 	struct phy			*phy;
249 	/* old usb_phy interface */
250 	struct usb_phy			*usb_phy;
251 	struct usb_hcd			*hcd;
252 	struct dentry			*debugfs;
253 	bool				id_event;
254 	bool				b_sess_valid_event;
255 	bool				imx28_write_fix;
256 	bool				supports_runtime_pm;
257 	bool				in_lpm;
258 	bool				wakeup_int;
259 	enum ci_revision		rev;
260 };
261 
262 static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
263 {
264 	BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
265 	return ci->roles[ci->role];
266 }
267 
268 static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
269 {
270 	int ret;
271 
272 	if (role >= CI_ROLE_END)
273 		return -EINVAL;
274 
275 	if (!ci->roles[role])
276 		return -ENXIO;
277 
278 	ret = ci->roles[role]->start(ci);
279 	if (!ret)
280 		ci->role = role;
281 	return ret;
282 }
283 
284 static inline void ci_role_stop(struct ci_hdrc *ci)
285 {
286 	enum ci_role role = ci->role;
287 
288 	if (role == CI_ROLE_END)
289 		return;
290 
291 	ci->role = CI_ROLE_END;
292 
293 	ci->roles[role]->stop(ci);
294 }
295 
296 static inline enum usb_role ci_role_to_usb_role(struct ci_hdrc *ci)
297 {
298 	if (ci->role == CI_ROLE_HOST)
299 		return USB_ROLE_HOST;
300 	else if (ci->role == CI_ROLE_GADGET && ci->vbus_active)
301 		return USB_ROLE_DEVICE;
302 	else
303 		return USB_ROLE_NONE;
304 }
305 
306 static inline enum ci_role usb_role_to_ci_role(enum usb_role role)
307 {
308 	if (role == USB_ROLE_HOST)
309 		return CI_ROLE_HOST;
310 	else if (role == USB_ROLE_DEVICE)
311 		return CI_ROLE_GADGET;
312 	else
313 		return CI_ROLE_END;
314 }
315 
316 /**
317  * hw_read_id_reg: reads from a identification register
318  * @ci: the controller
319  * @offset: offset from the beginning of identification registers region
320  * @mask: bitfield mask
321  *
322  * This function returns register contents
323  */
324 static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask)
325 {
326 	return ioread32(ci->hw_bank.abs + offset) & mask;
327 }
328 
329 /**
330  * hw_write_id_reg: writes to a identification register
331  * @ci: the controller
332  * @offset: offset from the beginning of identification registers region
333  * @mask: bitfield mask
334  * @data: new value
335  */
336 static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset,
337 			    u32 mask, u32 data)
338 {
339 	if (~mask)
340 		data = (ioread32(ci->hw_bank.abs + offset) & ~mask)
341 			| (data & mask);
342 
343 	iowrite32(data, ci->hw_bank.abs + offset);
344 }
345 
346 /**
347  * hw_read: reads from a hw register
348  * @ci: the controller
349  * @reg:  register index
350  * @mask: bitfield mask
351  *
352  * This function returns register contents
353  */
354 static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
355 {
356 	return ioread32(ci->hw_bank.regmap[reg]) & mask;
357 }
358 
359 #ifdef CONFIG_SOC_IMX28
360 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
361 {
362 	__asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
363 }
364 #else
365 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
366 {
367 }
368 #endif
369 
370 static inline void __hw_write(struct ci_hdrc *ci, u32 val,
371 		void __iomem *addr)
372 {
373 	if (ci->imx28_write_fix)
374 		imx28_ci_writel(val, addr);
375 	else
376 		iowrite32(val, addr);
377 }
378 
379 /**
380  * hw_write: writes to a hw register
381  * @ci: the controller
382  * @reg:  register index
383  * @mask: bitfield mask
384  * @data: new value
385  */
386 static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
387 			    u32 mask, u32 data)
388 {
389 	if (~mask)
390 		data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
391 			| (data & mask);
392 
393 	__hw_write(ci, data, ci->hw_bank.regmap[reg]);
394 }
395 
396 /**
397  * hw_test_and_clear: tests & clears a hw register
398  * @ci: the controller
399  * @reg:  register index
400  * @mask: bitfield mask
401  *
402  * This function returns register contents
403  */
404 static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
405 				    u32 mask)
406 {
407 	u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
408 
409 	__hw_write(ci, val, ci->hw_bank.regmap[reg]);
410 	return val;
411 }
412 
413 /**
414  * hw_test_and_write: tests & writes a hw register
415  * @ci: the controller
416  * @reg:  register index
417  * @mask: bitfield mask
418  * @data: new value
419  *
420  * This function returns register contents
421  */
422 static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
423 				    u32 mask, u32 data)
424 {
425 	u32 val = hw_read(ci, reg, ~0);
426 
427 	hw_write(ci, reg, mask, data);
428 	return (val & mask) >> __ffs(mask);
429 }
430 
431 /**
432  * ci_otg_is_fsm_mode: runtime check if otg controller
433  * is in otg fsm mode.
434  *
435  * @ci: chipidea device
436  */
437 static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci)
438 {
439 #ifdef CONFIG_USB_OTG_FSM
440 	struct usb_otg_caps *otg_caps = &ci->platdata->ci_otg_caps;
441 
442 	return ci->is_otg && ci->roles[CI_ROLE_HOST] &&
443 		ci->roles[CI_ROLE_GADGET] && (otg_caps->srp_support ||
444 		otg_caps->hnp_support || otg_caps->adp_support);
445 #else
446 	return false;
447 #endif
448 }
449 
450 int ci_ulpi_init(struct ci_hdrc *ci);
451 void ci_ulpi_exit(struct ci_hdrc *ci);
452 int ci_ulpi_resume(struct ci_hdrc *ci);
453 
454 u32 hw_read_intr_enable(struct ci_hdrc *ci);
455 
456 u32 hw_read_intr_status(struct ci_hdrc *ci);
457 
458 int hw_device_reset(struct ci_hdrc *ci);
459 
460 int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
461 
462 u8 hw_port_test_get(struct ci_hdrc *ci);
463 
464 void hw_phymode_configure(struct ci_hdrc *ci);
465 
466 void ci_platform_configure(struct ci_hdrc *ci);
467 
468 void dbg_create_files(struct ci_hdrc *ci);
469 
470 void dbg_remove_files(struct ci_hdrc *ci);
471 #endif	/* __DRIVERS_USB_CHIPIDEA_CI_H */
472