1 /* 2 * ci.h - common structures, functions, and macros of the ChipIdea driver 3 * 4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. 5 * 6 * Author: David Lopo 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #ifndef __DRIVERS_USB_CHIPIDEA_CI_H 14 #define __DRIVERS_USB_CHIPIDEA_CI_H 15 16 #include <linux/list.h> 17 #include <linux/irqreturn.h> 18 #include <linux/usb.h> 19 #include <linux/usb/gadget.h> 20 21 /****************************************************************************** 22 * DEFINE 23 *****************************************************************************/ 24 #define TD_PAGE_COUNT 5 25 #define CI_HDRC_PAGE_SIZE 4096ul /* page size for TD's */ 26 #define ENDPT_MAX 32 27 28 /****************************************************************************** 29 * REGISTERS 30 *****************************************************************************/ 31 /* register indices */ 32 enum ci_hw_regs { 33 CAP_CAPLENGTH, 34 CAP_HCCPARAMS, 35 CAP_DCCPARAMS, 36 CAP_TESTMODE, 37 CAP_LAST = CAP_TESTMODE, 38 OP_USBCMD, 39 OP_USBSTS, 40 OP_USBINTR, 41 OP_DEVICEADDR, 42 OP_ENDPTLISTADDR, 43 OP_PORTSC, 44 OP_DEVLC, 45 OP_OTGSC, 46 OP_USBMODE, 47 OP_ENDPTSETUPSTAT, 48 OP_ENDPTPRIME, 49 OP_ENDPTFLUSH, 50 OP_ENDPTSTAT, 51 OP_ENDPTCOMPLETE, 52 OP_ENDPTCTRL, 53 /* endptctrl1..15 follow */ 54 OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2, 55 }; 56 57 /****************************************************************************** 58 * STRUCTURES 59 *****************************************************************************/ 60 /** 61 * struct ci_hw_ep - endpoint representation 62 * @ep: endpoint structure for gadget drivers 63 * @dir: endpoint direction (TX/RX) 64 * @num: endpoint number 65 * @type: endpoint type 66 * @name: string description of the endpoint 67 * @qh: queue head for this endpoint 68 * @wedge: is the endpoint wedged 69 * @ci: pointer to the controller 70 * @lock: pointer to controller's spinlock 71 * @td_pool: pointer to controller's TD pool 72 */ 73 struct ci_hw_ep { 74 struct usb_ep ep; 75 u8 dir; 76 u8 num; 77 u8 type; 78 char name[16]; 79 struct { 80 struct list_head queue; 81 struct ci_hw_qh *ptr; 82 dma_addr_t dma; 83 } qh; 84 int wedge; 85 86 /* global resources */ 87 struct ci_hdrc *ci; 88 spinlock_t *lock; 89 struct dma_pool *td_pool; 90 struct td_node *pending_td; 91 }; 92 93 enum ci_role { 94 CI_ROLE_HOST = 0, 95 CI_ROLE_GADGET, 96 CI_ROLE_END, 97 }; 98 99 /** 100 * struct ci_role_driver - host/gadget role driver 101 * start: start this role 102 * stop: stop this role 103 * irq: irq handler for this role 104 * name: role name string (host/gadget) 105 */ 106 struct ci_role_driver { 107 int (*start)(struct ci_hdrc *); 108 void (*stop)(struct ci_hdrc *); 109 irqreturn_t (*irq)(struct ci_hdrc *); 110 const char *name; 111 }; 112 113 /** 114 * struct hw_bank - hardware register mapping representation 115 * @lpm: set if the device is LPM capable 116 * @phys: physical address of the controller's registers 117 * @abs: absolute address of the beginning of register window 118 * @cap: capability registers 119 * @op: operational registers 120 * @size: size of the register window 121 * @regmap: register lookup table 122 */ 123 struct hw_bank { 124 unsigned lpm; 125 resource_size_t phys; 126 void __iomem *abs; 127 void __iomem *cap; 128 void __iomem *op; 129 size_t size; 130 void __iomem *regmap[OP_LAST + 1]; 131 }; 132 133 /** 134 * struct ci_hdrc - chipidea device representation 135 * @dev: pointer to parent device 136 * @lock: access synchronization 137 * @hw_bank: hardware register mapping 138 * @irq: IRQ number 139 * @roles: array of supported roles for this controller 140 * @role: current role 141 * @is_otg: if the device is otg-capable 142 * @work: work for role changing 143 * @wq: workqueue thread 144 * @qh_pool: allocation pool for queue heads 145 * @td_pool: allocation pool for transfer descriptors 146 * @gadget: device side representation for peripheral controller 147 * @driver: gadget driver 148 * @hw_ep_max: total number of endpoints supported by hardware 149 * @ci_hw_ep: array of endpoints 150 * @ep0_dir: ep0 direction 151 * @ep0out: pointer to ep0 OUT endpoint 152 * @ep0in: pointer to ep0 IN endpoint 153 * @status: ep0 status request 154 * @setaddr: if we should set the address on status completion 155 * @address: usb address received from the host 156 * @remote_wakeup: host-enabled remote wakeup 157 * @suspended: suspended by host 158 * @test_mode: the selected test mode 159 * @platdata: platform specific information supplied by parent device 160 * @vbus_active: is VBUS active 161 * @transceiver: pointer to USB PHY, if any 162 * @hcd: pointer to usb_hcd for ehci host driver 163 * @debugfs: root dentry for this controller in debugfs 164 * @id_event: indicates there is an id event, and handled at ci_otg_work 165 * @b_sess_valid_event: indicates there is a vbus event, and handled 166 * at ci_otg_work 167 * @imx28_write_fix: Freescale imx28 needs swp instruction for writing 168 */ 169 struct ci_hdrc { 170 struct device *dev; 171 spinlock_t lock; 172 struct hw_bank hw_bank; 173 int irq; 174 struct ci_role_driver *roles[CI_ROLE_END]; 175 enum ci_role role; 176 bool is_otg; 177 struct work_struct work; 178 struct workqueue_struct *wq; 179 180 struct dma_pool *qh_pool; 181 struct dma_pool *td_pool; 182 183 struct usb_gadget gadget; 184 struct usb_gadget_driver *driver; 185 unsigned hw_ep_max; 186 struct ci_hw_ep ci_hw_ep[ENDPT_MAX]; 187 u32 ep0_dir; 188 struct ci_hw_ep *ep0out, *ep0in; 189 190 struct usb_request *status; 191 bool setaddr; 192 u8 address; 193 u8 remote_wakeup; 194 u8 suspended; 195 u8 test_mode; 196 197 struct ci_hdrc_platform_data *platdata; 198 int vbus_active; 199 struct usb_phy *transceiver; 200 struct usb_hcd *hcd; 201 struct dentry *debugfs; 202 bool id_event; 203 bool b_sess_valid_event; 204 bool imx28_write_fix; 205 }; 206 207 static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci) 208 { 209 BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]); 210 return ci->roles[ci->role]; 211 } 212 213 static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role) 214 { 215 int ret; 216 217 if (role >= CI_ROLE_END) 218 return -EINVAL; 219 220 if (!ci->roles[role]) 221 return -ENXIO; 222 223 ret = ci->roles[role]->start(ci); 224 if (!ret) 225 ci->role = role; 226 return ret; 227 } 228 229 static inline void ci_role_stop(struct ci_hdrc *ci) 230 { 231 enum ci_role role = ci->role; 232 233 if (role == CI_ROLE_END) 234 return; 235 236 ci->role = CI_ROLE_END; 237 238 ci->roles[role]->stop(ci); 239 } 240 241 /** 242 * hw_read: reads from a hw register 243 * @reg: register index 244 * @mask: bitfield mask 245 * 246 * This function returns register contents 247 */ 248 static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask) 249 { 250 return ioread32(ci->hw_bank.regmap[reg]) & mask; 251 } 252 253 #ifdef CONFIG_SOC_IMX28 254 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr) 255 { 256 __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr)); 257 } 258 #else 259 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr) 260 { 261 } 262 #endif 263 264 static inline void __hw_write(struct ci_hdrc *ci, u32 val, 265 void __iomem *addr) 266 { 267 if (ci->imx28_write_fix) 268 imx28_ci_writel(val, addr); 269 else 270 iowrite32(val, addr); 271 } 272 273 /** 274 * hw_write: writes to a hw register 275 * @reg: register index 276 * @mask: bitfield mask 277 * @data: new value 278 */ 279 static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg, 280 u32 mask, u32 data) 281 { 282 if (~mask) 283 data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask) 284 | (data & mask); 285 286 __hw_write(ci, data, ci->hw_bank.regmap[reg]); 287 } 288 289 /** 290 * hw_test_and_clear: tests & clears a hw register 291 * @reg: register index 292 * @mask: bitfield mask 293 * 294 * This function returns register contents 295 */ 296 static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg, 297 u32 mask) 298 { 299 u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask; 300 301 __hw_write(ci, val, ci->hw_bank.regmap[reg]); 302 return val; 303 } 304 305 /** 306 * hw_test_and_write: tests & writes a hw register 307 * @reg: register index 308 * @mask: bitfield mask 309 * @data: new value 310 * 311 * This function returns register contents 312 */ 313 static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg, 314 u32 mask, u32 data) 315 { 316 u32 val = hw_read(ci, reg, ~0); 317 318 hw_write(ci, reg, mask, data); 319 return (val & mask) >> __ffs(mask); 320 } 321 322 int hw_device_reset(struct ci_hdrc *ci, u32 mode); 323 324 int hw_port_test_set(struct ci_hdrc *ci, u8 mode); 325 326 u8 hw_port_test_get(struct ci_hdrc *ci); 327 328 int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask, 329 u32 value, unsigned int timeout_ms); 330 331 #endif /* __DRIVERS_USB_CHIPIDEA_CI_H */ 332