xref: /openbmc/linux/drivers/usb/chipidea/ci.h (revision 7aacf86b) 
1 /*
2  * ci.h - common structures, functions, and macros of the ChipIdea driver
3  *
4  * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
5  *
6  * Author: David Lopo
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12 
13 #ifndef __DRIVERS_USB_CHIPIDEA_CI_H
14 #define __DRIVERS_USB_CHIPIDEA_CI_H
15 
16 #include <linux/list.h>
17 #include <linux/irqreturn.h>
18 #include <linux/usb.h>
19 #include <linux/usb/gadget.h>
20 #include <linux/usb/otg-fsm.h>
21 #include <linux/usb/otg.h>
22 #include <linux/ulpi/interface.h>
23 
24 /******************************************************************************
25  * DEFINE
26  *****************************************************************************/
27 #define TD_PAGE_COUNT      5
28 #define CI_HDRC_PAGE_SIZE  4096ul /* page size for TD's */
29 #define ENDPT_MAX          32
30 
31 /******************************************************************************
32  * REGISTERS
33  *****************************************************************************/
34 /* Identification Registers */
35 #define ID_ID				0x0
36 #define ID_HWGENERAL			0x4
37 #define ID_HWHOST			0x8
38 #define ID_HWDEVICE			0xc
39 #define ID_HWTXBUF			0x10
40 #define ID_HWRXBUF			0x14
41 #define ID_SBUSCFG			0x90
42 
43 /* register indices */
44 enum ci_hw_regs {
45 	CAP_CAPLENGTH,
46 	CAP_HCCPARAMS,
47 	CAP_DCCPARAMS,
48 	CAP_TESTMODE,
49 	CAP_LAST = CAP_TESTMODE,
50 	OP_USBCMD,
51 	OP_USBSTS,
52 	OP_USBINTR,
53 	OP_DEVICEADDR,
54 	OP_ENDPTLISTADDR,
55 	OP_TTCTRL,
56 	OP_BURSTSIZE,
57 	OP_ULPI_VIEWPORT,
58 	OP_PORTSC,
59 	OP_DEVLC,
60 	OP_OTGSC,
61 	OP_USBMODE,
62 	OP_ENDPTSETUPSTAT,
63 	OP_ENDPTPRIME,
64 	OP_ENDPTFLUSH,
65 	OP_ENDPTSTAT,
66 	OP_ENDPTCOMPLETE,
67 	OP_ENDPTCTRL,
68 	/* endptctrl1..15 follow */
69 	OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
70 };
71 
72 /******************************************************************************
73  * STRUCTURES
74  *****************************************************************************/
75 /**
76  * struct ci_hw_ep - endpoint representation
77  * @ep: endpoint structure for gadget drivers
78  * @dir: endpoint direction (TX/RX)
79  * @num: endpoint number
80  * @type: endpoint type
81  * @name: string description of the endpoint
82  * @qh: queue head for this endpoint
83  * @wedge: is the endpoint wedged
84  * @ci: pointer to the controller
85  * @lock: pointer to controller's spinlock
86  * @td_pool: pointer to controller's TD pool
87  */
88 struct ci_hw_ep {
89 	struct usb_ep				ep;
90 	u8					dir;
91 	u8					num;
92 	u8					type;
93 	char					name[16];
94 	struct {
95 		struct list_head	queue;
96 		struct ci_hw_qh		*ptr;
97 		dma_addr_t		dma;
98 	}					qh;
99 	int					wedge;
100 
101 	/* global resources */
102 	struct ci_hdrc				*ci;
103 	spinlock_t				*lock;
104 	struct dma_pool				*td_pool;
105 	struct td_node				*pending_td;
106 };
107 
108 enum ci_role {
109 	CI_ROLE_HOST = 0,
110 	CI_ROLE_GADGET,
111 	CI_ROLE_END,
112 };
113 
114 enum ci_revision {
115 	CI_REVISION_1X = 10,	/* Revision 1.x */
116 	CI_REVISION_20 = 20, /* Revision 2.0 */
117 	CI_REVISION_21, /* Revision 2.1 */
118 	CI_REVISION_22, /* Revision 2.2 */
119 	CI_REVISION_23, /* Revision 2.3 */
120 	CI_REVISION_24, /* Revision 2.4 */
121 	CI_REVISION_25, /* Revision 2.5 */
122 	CI_REVISION_25_PLUS, /* Revision above than 2.5 */
123 	CI_REVISION_UNKNOWN = 99, /* Unknown Revision */
124 };
125 
126 /**
127  * struct ci_role_driver - host/gadget role driver
128  * @start: start this role
129  * @stop: stop this role
130  * @irq: irq handler for this role
131  * @name: role name string (host/gadget)
132  */
133 struct ci_role_driver {
134 	int		(*start)(struct ci_hdrc *);
135 	void		(*stop)(struct ci_hdrc *);
136 	irqreturn_t	(*irq)(struct ci_hdrc *);
137 	const char	*name;
138 };
139 
140 /**
141  * struct hw_bank - hardware register mapping representation
142  * @lpm: set if the device is LPM capable
143  * @phys: physical address of the controller's registers
144  * @abs: absolute address of the beginning of register window
145  * @cap: capability registers
146  * @op: operational registers
147  * @size: size of the register window
148  * @regmap: register lookup table
149  */
150 struct hw_bank {
151 	unsigned	lpm;
152 	resource_size_t	phys;
153 	void __iomem	*abs;
154 	void __iomem	*cap;
155 	void __iomem	*op;
156 	size_t		size;
157 	void __iomem	*regmap[OP_LAST + 1];
158 };
159 
160 /**
161  * struct ci_hdrc - chipidea device representation
162  * @dev: pointer to parent device
163  * @lock: access synchronization
164  * @hw_bank: hardware register mapping
165  * @irq: IRQ number
166  * @roles: array of supported roles for this controller
167  * @role: current role
168  * @is_otg: if the device is otg-capable
169  * @fsm: otg finite state machine
170  * @otg_fsm_hrtimer: hrtimer for otg fsm timers
171  * @hr_timeouts: time out list for active otg fsm timers
172  * @enabled_otg_timer_bits: bits of enabled otg timers
173  * @next_otg_timer: next nearest enabled timer to be expired
174  * @work: work for role changing
175  * @wq: workqueue thread
176  * @qh_pool: allocation pool for queue heads
177  * @td_pool: allocation pool for transfer descriptors
178  * @gadget: device side representation for peripheral controller
179  * @driver: gadget driver
180  * @resume_state: save the state of gadget suspend from
181  * @hw_ep_max: total number of endpoints supported by hardware
182  * @ci_hw_ep: array of endpoints
183  * @ep0_dir: ep0 direction
184  * @ep0out: pointer to ep0 OUT endpoint
185  * @ep0in: pointer to ep0 IN endpoint
186  * @status: ep0 status request
187  * @setaddr: if we should set the address on status completion
188  * @address: usb address received from the host
189  * @remote_wakeup: host-enabled remote wakeup
190  * @suspended: suspended by host
191  * @test_mode: the selected test mode
192  * @platdata: platform specific information supplied by parent device
193  * @vbus_active: is VBUS active
194  * @ulpi: pointer to ULPI device, if any
195  * @ulpi_ops: ULPI read/write ops for this device
196  * @phy: pointer to PHY, if any
197  * @usb_phy: pointer to USB PHY, if any and if using the USB PHY framework
198  * @hcd: pointer to usb_hcd for ehci host driver
199  * @debugfs: root dentry for this controller in debugfs
200  * @id_event: indicates there is an id event, and handled at ci_otg_work
201  * @b_sess_valid_event: indicates there is a vbus event, and handled
202  * at ci_otg_work
203  * @imx28_write_fix: Freescale imx28 needs swp instruction for writing
204  * @supports_runtime_pm: if runtime pm is supported
205  * @in_lpm: if the core in low power mode
206  * @wakeup_int: if wakeup interrupt occur
207  * @rev: The revision number for controller
208  */
209 struct ci_hdrc {
210 	struct device			*dev;
211 	spinlock_t			lock;
212 	struct hw_bank			hw_bank;
213 	int				irq;
214 	struct ci_role_driver		*roles[CI_ROLE_END];
215 	enum ci_role			role;
216 	bool				is_otg;
217 	struct usb_otg			otg;
218 	struct otg_fsm			fsm;
219 	struct hrtimer			otg_fsm_hrtimer;
220 	ktime_t				hr_timeouts[NUM_OTG_FSM_TIMERS];
221 	unsigned			enabled_otg_timer_bits;
222 	enum otg_fsm_timer		next_otg_timer;
223 	struct work_struct		work;
224 	struct workqueue_struct		*wq;
225 
226 	struct dma_pool			*qh_pool;
227 	struct dma_pool			*td_pool;
228 
229 	struct usb_gadget		gadget;
230 	struct usb_gadget_driver	*driver;
231 	enum usb_device_state		resume_state;
232 	unsigned			hw_ep_max;
233 	struct ci_hw_ep			ci_hw_ep[ENDPT_MAX];
234 	u32				ep0_dir;
235 	struct ci_hw_ep			*ep0out, *ep0in;
236 
237 	struct usb_request		*status;
238 	bool				setaddr;
239 	u8				address;
240 	u8				remote_wakeup;
241 	u8				suspended;
242 	u8				test_mode;
243 
244 	struct ci_hdrc_platform_data	*platdata;
245 	int				vbus_active;
246 #ifdef CONFIG_USB_CHIPIDEA_ULPI
247 	struct ulpi			*ulpi;
248 	struct ulpi_ops 		ulpi_ops;
249 #endif
250 	struct phy			*phy;
251 	/* old usb_phy interface */
252 	struct usb_phy			*usb_phy;
253 	struct usb_hcd			*hcd;
254 	struct dentry			*debugfs;
255 	bool				id_event;
256 	bool				b_sess_valid_event;
257 	bool				imx28_write_fix;
258 	bool				supports_runtime_pm;
259 	bool				in_lpm;
260 	bool				wakeup_int;
261 	enum ci_revision		rev;
262 };
263 
264 static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
265 {
266 	BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
267 	return ci->roles[ci->role];
268 }
269 
270 static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
271 {
272 	int ret;
273 
274 	if (role >= CI_ROLE_END)
275 		return -EINVAL;
276 
277 	if (!ci->roles[role])
278 		return -ENXIO;
279 
280 	ret = ci->roles[role]->start(ci);
281 	if (!ret)
282 		ci->role = role;
283 	return ret;
284 }
285 
286 static inline void ci_role_stop(struct ci_hdrc *ci)
287 {
288 	enum ci_role role = ci->role;
289 
290 	if (role == CI_ROLE_END)
291 		return;
292 
293 	ci->role = CI_ROLE_END;
294 
295 	ci->roles[role]->stop(ci);
296 }
297 
298 /**
299  * hw_read_id_reg: reads from a identification register
300  * @ci: the controller
301  * @offset: offset from the beginning of identification registers region
302  * @mask: bitfield mask
303  *
304  * This function returns register contents
305  */
306 static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask)
307 {
308 	return ioread32(ci->hw_bank.abs + offset) & mask;
309 }
310 
311 /**
312  * hw_write_id_reg: writes to a identification register
313  * @ci: the controller
314  * @offset: offset from the beginning of identification registers region
315  * @mask: bitfield mask
316  * @data: new value
317  */
318 static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset,
319 			    u32 mask, u32 data)
320 {
321 	if (~mask)
322 		data = (ioread32(ci->hw_bank.abs + offset) & ~mask)
323 			| (data & mask);
324 
325 	iowrite32(data, ci->hw_bank.abs + offset);
326 }
327 
328 /**
329  * hw_read: reads from a hw register
330  * @ci: the controller
331  * @reg:  register index
332  * @mask: bitfield mask
333  *
334  * This function returns register contents
335  */
336 static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
337 {
338 	return ioread32(ci->hw_bank.regmap[reg]) & mask;
339 }
340 
341 #ifdef CONFIG_SOC_IMX28
342 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
343 {
344 	__asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
345 }
346 #else
347 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
348 {
349 }
350 #endif
351 
352 static inline void __hw_write(struct ci_hdrc *ci, u32 val,
353 		void __iomem *addr)
354 {
355 	if (ci->imx28_write_fix)
356 		imx28_ci_writel(val, addr);
357 	else
358 		iowrite32(val, addr);
359 }
360 
361 /**
362  * hw_write: writes to a hw register
363  * @ci: the controller
364  * @reg:  register index
365  * @mask: bitfield mask
366  * @data: new value
367  */
368 static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
369 			    u32 mask, u32 data)
370 {
371 	if (~mask)
372 		data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
373 			| (data & mask);
374 
375 	__hw_write(ci, data, ci->hw_bank.regmap[reg]);
376 }
377 
378 /**
379  * hw_test_and_clear: tests & clears a hw register
380  * @ci: the controller
381  * @reg:  register index
382  * @mask: bitfield mask
383  *
384  * This function returns register contents
385  */
386 static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
387 				    u32 mask)
388 {
389 	u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
390 
391 	__hw_write(ci, val, ci->hw_bank.regmap[reg]);
392 	return val;
393 }
394 
395 /**
396  * hw_test_and_write: tests & writes a hw register
397  * @ci: the controller
398  * @reg:  register index
399  * @mask: bitfield mask
400  * @data: new value
401  *
402  * This function returns register contents
403  */
404 static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
405 				    u32 mask, u32 data)
406 {
407 	u32 val = hw_read(ci, reg, ~0);
408 
409 	hw_write(ci, reg, mask, data);
410 	return (val & mask) >> __ffs(mask);
411 }
412 
413 /**
414  * ci_otg_is_fsm_mode: runtime check if otg controller
415  * is in otg fsm mode.
416  *
417  * @ci: chipidea device
418  */
419 static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci)
420 {
421 #ifdef CONFIG_USB_OTG_FSM
422 	struct usb_otg_caps *otg_caps = &ci->platdata->ci_otg_caps;
423 
424 	return ci->is_otg && ci->roles[CI_ROLE_HOST] &&
425 		ci->roles[CI_ROLE_GADGET] && (otg_caps->srp_support ||
426 		otg_caps->hnp_support || otg_caps->adp_support);
427 #else
428 	return false;
429 #endif
430 }
431 
432 #if IS_ENABLED(CONFIG_USB_CHIPIDEA_ULPI)
433 int ci_ulpi_init(struct ci_hdrc *ci);
434 void ci_ulpi_exit(struct ci_hdrc *ci);
435 int ci_ulpi_resume(struct ci_hdrc *ci);
436 #else
437 static inline int ci_ulpi_init(struct ci_hdrc *ci) { return 0; }
438 static inline void ci_ulpi_exit(struct ci_hdrc *ci) { }
439 static inline int ci_ulpi_resume(struct ci_hdrc *ci) { return 0; }
440 #endif
441 
442 u32 hw_read_intr_enable(struct ci_hdrc *ci);
443 
444 u32 hw_read_intr_status(struct ci_hdrc *ci);
445 
446 int hw_device_reset(struct ci_hdrc *ci);
447 
448 int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
449 
450 u8 hw_port_test_get(struct ci_hdrc *ci);
451 
452 void hw_phymode_configure(struct ci_hdrc *ci);
453 
454 void ci_platform_configure(struct ci_hdrc *ci);
455 
456 int dbg_create_files(struct ci_hdrc *ci);
457 
458 void dbg_remove_files(struct ci_hdrc *ci);
459 #endif	/* __DRIVERS_USB_CHIPIDEA_CI_H */
460