1 /* 2 * ci.h - common structures, functions, and macros of the ChipIdea driver 3 * 4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. 5 * 6 * Author: David Lopo 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #ifndef __DRIVERS_USB_CHIPIDEA_CI_H 14 #define __DRIVERS_USB_CHIPIDEA_CI_H 15 16 #include <linux/list.h> 17 #include <linux/irqreturn.h> 18 #include <linux/usb.h> 19 #include <linux/usb/gadget.h> 20 21 /****************************************************************************** 22 * DEFINE 23 *****************************************************************************/ 24 #define TD_PAGE_COUNT 5 25 #define CI_HDRC_PAGE_SIZE 4096ul /* page size for TD's */ 26 #define ENDPT_MAX 32 27 28 /****************************************************************************** 29 * STRUCTURES 30 *****************************************************************************/ 31 /** 32 * struct ci_hw_ep - endpoint representation 33 * @ep: endpoint structure for gadget drivers 34 * @dir: endpoint direction (TX/RX) 35 * @num: endpoint number 36 * @type: endpoint type 37 * @name: string description of the endpoint 38 * @qh: queue head for this endpoint 39 * @wedge: is the endpoint wedged 40 * @ci: pointer to the controller 41 * @lock: pointer to controller's spinlock 42 * @td_pool: pointer to controller's TD pool 43 */ 44 struct ci_hw_ep { 45 struct usb_ep ep; 46 u8 dir; 47 u8 num; 48 u8 type; 49 char name[16]; 50 struct { 51 struct list_head queue; 52 struct ci_hw_qh *ptr; 53 dma_addr_t dma; 54 } qh; 55 int wedge; 56 57 /* global resources */ 58 struct ci_hdrc *ci; 59 spinlock_t *lock; 60 struct dma_pool *td_pool; 61 struct td_node *pending_td; 62 }; 63 64 enum ci_role { 65 CI_ROLE_HOST = 0, 66 CI_ROLE_GADGET, 67 CI_ROLE_END, 68 }; 69 70 /** 71 * struct ci_role_driver - host/gadget role driver 72 * start: start this role 73 * stop: stop this role 74 * irq: irq handler for this role 75 * name: role name string (host/gadget) 76 */ 77 struct ci_role_driver { 78 int (*start)(struct ci_hdrc *); 79 void (*stop)(struct ci_hdrc *); 80 irqreturn_t (*irq)(struct ci_hdrc *); 81 const char *name; 82 }; 83 84 /** 85 * struct hw_bank - hardware register mapping representation 86 * @lpm: set if the device is LPM capable 87 * @phys: physical address of the controller's registers 88 * @abs: absolute address of the beginning of register window 89 * @cap: capability registers 90 * @op: operational registers 91 * @size: size of the register window 92 * @regmap: register lookup table 93 */ 94 struct hw_bank { 95 unsigned lpm; 96 resource_size_t phys; 97 void __iomem *abs; 98 void __iomem *cap; 99 void __iomem *op; 100 size_t size; 101 void __iomem **regmap; 102 }; 103 104 /** 105 * struct ci_hdrc - chipidea device representation 106 * @dev: pointer to parent device 107 * @lock: access synchronization 108 * @hw_bank: hardware register mapping 109 * @irq: IRQ number 110 * @roles: array of supported roles for this controller 111 * @role: current role 112 * @is_otg: if the device is otg-capable 113 * @work: work for role changing 114 * @wq: workqueue thread 115 * @qh_pool: allocation pool for queue heads 116 * @td_pool: allocation pool for transfer descriptors 117 * @gadget: device side representation for peripheral controller 118 * @driver: gadget driver 119 * @hw_ep_max: total number of endpoints supported by hardware 120 * @ci_hw_ep: array of endpoints 121 * @ep0_dir: ep0 direction 122 * @ep0out: pointer to ep0 OUT endpoint 123 * @ep0in: pointer to ep0 IN endpoint 124 * @status: ep0 status request 125 * @setaddr: if we should set the address on status completion 126 * @address: usb address received from the host 127 * @remote_wakeup: host-enabled remote wakeup 128 * @suspended: suspended by host 129 * @test_mode: the selected test mode 130 * @platdata: platform specific information supplied by parent device 131 * @vbus_active: is VBUS active 132 * @transceiver: pointer to USB PHY, if any 133 * @hcd: pointer to usb_hcd for ehci host driver 134 * @debugfs: root dentry for this controller in debugfs 135 * @id_event: indicates there is an id event, and handled at ci_otg_work 136 * @b_sess_valid_event: indicates there is a vbus event, and handled 137 * at ci_otg_work 138 */ 139 struct ci_hdrc { 140 struct device *dev; 141 spinlock_t lock; 142 struct hw_bank hw_bank; 143 int irq; 144 struct ci_role_driver *roles[CI_ROLE_END]; 145 enum ci_role role; 146 bool is_otg; 147 struct work_struct work; 148 struct workqueue_struct *wq; 149 150 struct dma_pool *qh_pool; 151 struct dma_pool *td_pool; 152 153 struct usb_gadget gadget; 154 struct usb_gadget_driver *driver; 155 unsigned hw_ep_max; 156 struct ci_hw_ep ci_hw_ep[ENDPT_MAX]; 157 u32 ep0_dir; 158 struct ci_hw_ep *ep0out, *ep0in; 159 160 struct usb_request *status; 161 bool setaddr; 162 u8 address; 163 u8 remote_wakeup; 164 u8 suspended; 165 u8 test_mode; 166 167 struct ci_hdrc_platform_data *platdata; 168 int vbus_active; 169 /* FIXME: some day, we'll not use global phy */ 170 bool global_phy; 171 struct usb_phy *transceiver; 172 struct usb_hcd *hcd; 173 struct dentry *debugfs; 174 bool id_event; 175 bool b_sess_valid_event; 176 }; 177 178 static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci) 179 { 180 BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]); 181 return ci->roles[ci->role]; 182 } 183 184 static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role) 185 { 186 int ret; 187 188 if (role >= CI_ROLE_END) 189 return -EINVAL; 190 191 if (!ci->roles[role]) 192 return -ENXIO; 193 194 ret = ci->roles[role]->start(ci); 195 if (!ret) 196 ci->role = role; 197 return ret; 198 } 199 200 static inline void ci_role_stop(struct ci_hdrc *ci) 201 { 202 enum ci_role role = ci->role; 203 204 if (role == CI_ROLE_END) 205 return; 206 207 ci->role = CI_ROLE_END; 208 209 ci->roles[role]->stop(ci); 210 } 211 212 /****************************************************************************** 213 * REGISTERS 214 *****************************************************************************/ 215 /* register size */ 216 #define REG_BITS (32) 217 218 /* register indices */ 219 enum ci_hw_regs { 220 CAP_CAPLENGTH, 221 CAP_HCCPARAMS, 222 CAP_DCCPARAMS, 223 CAP_TESTMODE, 224 CAP_LAST = CAP_TESTMODE, 225 OP_USBCMD, 226 OP_USBSTS, 227 OP_USBINTR, 228 OP_DEVICEADDR, 229 OP_ENDPTLISTADDR, 230 OP_PORTSC, 231 OP_DEVLC, 232 OP_OTGSC, 233 OP_USBMODE, 234 OP_ENDPTSETUPSTAT, 235 OP_ENDPTPRIME, 236 OP_ENDPTFLUSH, 237 OP_ENDPTSTAT, 238 OP_ENDPTCOMPLETE, 239 OP_ENDPTCTRL, 240 /* endptctrl1..15 follow */ 241 OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2, 242 }; 243 244 /** 245 * hw_read: reads from a hw register 246 * @reg: register index 247 * @mask: bitfield mask 248 * 249 * This function returns register contents 250 */ 251 static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask) 252 { 253 return ioread32(ci->hw_bank.regmap[reg]) & mask; 254 } 255 256 /** 257 * hw_write: writes to a hw register 258 * @reg: register index 259 * @mask: bitfield mask 260 * @data: new value 261 */ 262 static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg, 263 u32 mask, u32 data) 264 { 265 if (~mask) 266 data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask) 267 | (data & mask); 268 269 iowrite32(data, ci->hw_bank.regmap[reg]); 270 } 271 272 /** 273 * hw_test_and_clear: tests & clears a hw register 274 * @reg: register index 275 * @mask: bitfield mask 276 * 277 * This function returns register contents 278 */ 279 static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg, 280 u32 mask) 281 { 282 u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask; 283 284 iowrite32(val, ci->hw_bank.regmap[reg]); 285 return val; 286 } 287 288 /** 289 * hw_test_and_write: tests & writes a hw register 290 * @reg: register index 291 * @mask: bitfield mask 292 * @data: new value 293 * 294 * This function returns register contents 295 */ 296 static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg, 297 u32 mask, u32 data) 298 { 299 u32 val = hw_read(ci, reg, ~0); 300 301 hw_write(ci, reg, mask, data); 302 return (val & mask) >> __ffs(mask); 303 } 304 305 int hw_device_reset(struct ci_hdrc *ci, u32 mode); 306 307 int hw_port_test_set(struct ci_hdrc *ci, u8 mode); 308 309 u8 hw_port_test_get(struct ci_hdrc *ci); 310 311 int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask, 312 u32 value, unsigned int timeout_ms); 313 314 #endif /* __DRIVERS_USB_CHIPIDEA_CI_H */ 315