1 /* 2 * bits.h - register bits of the ChipIdea USB IP core 3 * 4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. 5 * 6 * Author: David Lopo 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #ifndef __DRIVERS_USB_CHIPIDEA_BITS_H 14 #define __DRIVERS_USB_CHIPIDEA_BITS_H 15 16 #include <linux/usb/ehci_def.h> 17 18 /* HCCPARAMS */ 19 #define HCCPARAMS_LEN BIT(17) 20 21 /* DCCPARAMS */ 22 #define DCCPARAMS_DEN (0x1F << 0) 23 #define DCCPARAMS_DC BIT(7) 24 #define DCCPARAMS_HC BIT(8) 25 26 /* TESTMODE */ 27 #define TESTMODE_FORCE BIT(0) 28 29 /* USBCMD */ 30 #define USBCMD_RS BIT(0) 31 #define USBCMD_RST BIT(1) 32 #define USBCMD_SUTW BIT(13) 33 #define USBCMD_ATDTW BIT(14) 34 35 /* USBSTS & USBINTR */ 36 #define USBi_UI BIT(0) 37 #define USBi_UEI BIT(1) 38 #define USBi_PCI BIT(2) 39 #define USBi_URI BIT(6) 40 #define USBi_SLI BIT(8) 41 42 /* DEVICEADDR */ 43 #define DEVICEADDR_USBADRA BIT(24) 44 #define DEVICEADDR_USBADR (0x7FUL << 25) 45 46 /* PORTSC */ 47 #define PORTSC_FPR BIT(6) 48 #define PORTSC_SUSP BIT(7) 49 #define PORTSC_HSP BIT(9) 50 #define PORTSC_PTC (0x0FUL << 16) 51 52 /* DEVLC */ 53 #define DEVLC_PSPD (0x03UL << 25) 54 #define DEVLC_PSPD_HS (0x02UL << 25) 55 56 /* OTGSC */ 57 #define OTGSC_IDPU BIT(5) 58 #define OTGSC_ID BIT(8) 59 #define OTGSC_AVV BIT(9) 60 #define OTGSC_ASV BIT(10) 61 #define OTGSC_BSV BIT(11) 62 #define OTGSC_BSE BIT(12) 63 #define OTGSC_IDIS BIT(16) 64 #define OTGSC_AVVIS BIT(17) 65 #define OTGSC_ASVIS BIT(18) 66 #define OTGSC_BSVIS BIT(19) 67 #define OTGSC_BSEIS BIT(20) 68 #define OTGSC_IDIE BIT(24) 69 #define OTGSC_AVVIE BIT(25) 70 #define OTGSC_ASVIE BIT(26) 71 #define OTGSC_BSVIE BIT(27) 72 #define OTGSC_BSEIE BIT(28) 73 74 /* USBMODE */ 75 #define USBMODE_CM (0x03UL << 0) 76 #define USBMODE_CM_DC (0x02UL << 0) 77 #define USBMODE_SLOM BIT(3) 78 #define USBMODE_CI_SDIS BIT(4) 79 80 /* ENDPTCTRL */ 81 #define ENDPTCTRL_RXS BIT(0) 82 #define ENDPTCTRL_RXT (0x03UL << 2) 83 #define ENDPTCTRL_RXR BIT(6) /* reserved for port 0 */ 84 #define ENDPTCTRL_RXE BIT(7) 85 #define ENDPTCTRL_TXS BIT(16) 86 #define ENDPTCTRL_TXT (0x03UL << 18) 87 #define ENDPTCTRL_TXR BIT(22) /* reserved for port 0 */ 88 #define ENDPTCTRL_TXE BIT(23) 89 90 #endif /* __DRIVERS_USB_CHIPIDEA_BITS_H */ 91