1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/acpi.h> 7 #include <linux/time.h> 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/interconnect.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/platform_device.h> 14 #include <linux/phy/phy.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/reset-controller.h> 17 #include <linux/devfreq.h> 18 19 #include <soc/qcom/ice.h> 20 21 #include <ufs/ufshcd.h> 22 #include "ufshcd-pltfrm.h" 23 #include <ufs/unipro.h> 24 #include "ufs-qcom.h" 25 #include <ufs/ufshci.h> 26 #include <ufs/ufs_quirks.h> 27 28 #define MCQ_QCFGPTR_MASK GENMASK(7, 0) 29 #define MCQ_QCFGPTR_UNIT 0x200 30 #define MCQ_SQATTR_OFFSET(c) \ 31 ((((c) >> 16) & MCQ_QCFGPTR_MASK) * MCQ_QCFGPTR_UNIT) 32 #define MCQ_QCFG_SIZE 0x40 33 34 enum { 35 TSTBUS_UAWM, 36 TSTBUS_UARM, 37 TSTBUS_TXUC, 38 TSTBUS_RXUC, 39 TSTBUS_DFC, 40 TSTBUS_TRLUT, 41 TSTBUS_TMRLUT, 42 TSTBUS_OCSC, 43 TSTBUS_UTP_HCI, 44 TSTBUS_COMBINED, 45 TSTBUS_WRAPPER, 46 TSTBUS_UNIPRO, 47 TSTBUS_MAX, 48 }; 49 50 #define QCOM_UFS_MAX_GEAR 5 51 #define QCOM_UFS_MAX_LANE 2 52 53 enum { 54 MODE_MIN, 55 MODE_PWM, 56 MODE_HS_RA, 57 MODE_HS_RB, 58 MODE_MAX, 59 }; 60 61 static const struct __ufs_qcom_bw_table { 62 u32 mem_bw; 63 u32 cfg_bw; 64 } ufs_qcom_bw_table[MODE_MAX + 1][QCOM_UFS_MAX_GEAR + 1][QCOM_UFS_MAX_LANE + 1] = { 65 [MODE_MIN][0][0] = { 0, 0 }, /* Bandwidth values in KB/s */ 66 [MODE_PWM][UFS_PWM_G1][UFS_LANE_1] = { 922, 1000 }, 67 [MODE_PWM][UFS_PWM_G2][UFS_LANE_1] = { 1844, 1000 }, 68 [MODE_PWM][UFS_PWM_G3][UFS_LANE_1] = { 3688, 1000 }, 69 [MODE_PWM][UFS_PWM_G4][UFS_LANE_1] = { 7376, 1000 }, 70 [MODE_PWM][UFS_PWM_G5][UFS_LANE_1] = { 14752, 1000 }, 71 [MODE_PWM][UFS_PWM_G1][UFS_LANE_2] = { 1844, 1000 }, 72 [MODE_PWM][UFS_PWM_G2][UFS_LANE_2] = { 3688, 1000 }, 73 [MODE_PWM][UFS_PWM_G3][UFS_LANE_2] = { 7376, 1000 }, 74 [MODE_PWM][UFS_PWM_G4][UFS_LANE_2] = { 14752, 1000 }, 75 [MODE_PWM][UFS_PWM_G5][UFS_LANE_2] = { 29504, 1000 }, 76 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_1] = { 127796, 1000 }, 77 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_1] = { 255591, 1000 }, 78 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 }, 79 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 }, 80 [MODE_HS_RA][UFS_HS_G5][UFS_LANE_1] = { 5836800, 409600 }, 81 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_2] = { 255591, 1000 }, 82 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_2] = { 511181, 1000 }, 83 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 }, 84 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 }, 85 [MODE_HS_RA][UFS_HS_G5][UFS_LANE_2] = { 5836800, 819200 }, 86 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_1] = { 149422, 1000 }, 87 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_1] = { 298189, 1000 }, 88 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 }, 89 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 }, 90 [MODE_HS_RB][UFS_HS_G5][UFS_LANE_1] = { 5836800, 409600 }, 91 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_2] = { 298189, 1000 }, 92 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_2] = { 596378, 1000 }, 93 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 }, 94 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 }, 95 [MODE_HS_RB][UFS_HS_G5][UFS_LANE_2] = { 5836800, 819200 }, 96 [MODE_MAX][0][0] = { 7643136, 307200 }, 97 }; 98 99 static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS]; 100 101 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host); 102 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba, 103 u32 clk_cycles); 104 105 static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd) 106 { 107 return container_of(rcd, struct ufs_qcom_host, rcdev); 108 } 109 110 #ifdef CONFIG_SCSI_UFS_CRYPTO 111 112 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host) 113 { 114 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 115 qcom_ice_enable(host->ice); 116 } 117 118 static int ufs_qcom_ice_init(struct ufs_qcom_host *host) 119 { 120 struct ufs_hba *hba = host->hba; 121 struct device *dev = hba->dev; 122 struct qcom_ice *ice; 123 124 ice = of_qcom_ice_get(dev); 125 if (ice == ERR_PTR(-EOPNOTSUPP)) { 126 dev_warn(dev, "Disabling inline encryption support\n"); 127 ice = NULL; 128 } 129 130 if (IS_ERR_OR_NULL(ice)) 131 return PTR_ERR_OR_ZERO(ice); 132 133 host->ice = ice; 134 hba->caps |= UFSHCD_CAP_CRYPTO; 135 136 return 0; 137 } 138 139 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host) 140 { 141 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 142 return qcom_ice_resume(host->ice); 143 144 return 0; 145 } 146 147 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host) 148 { 149 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 150 return qcom_ice_suspend(host->ice); 151 152 return 0; 153 } 154 155 static int ufs_qcom_ice_program_key(struct ufs_hba *hba, 156 const union ufs_crypto_cfg_entry *cfg, 157 int slot) 158 { 159 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 160 union ufs_crypto_cap_entry cap; 161 bool config_enable = 162 cfg->config_enable & UFS_CRYPTO_CONFIGURATION_ENABLE; 163 164 /* Only AES-256-XTS has been tested so far. */ 165 cap = hba->crypto_cap_array[cfg->crypto_cap_idx]; 166 if (cap.algorithm_id != UFS_CRYPTO_ALG_AES_XTS || 167 cap.key_size != UFS_CRYPTO_KEY_SIZE_256) 168 return -EOPNOTSUPP; 169 170 if (config_enable) 171 return qcom_ice_program_key(host->ice, 172 QCOM_ICE_CRYPTO_ALG_AES_XTS, 173 QCOM_ICE_CRYPTO_KEY_SIZE_256, 174 cfg->crypto_key, 175 cfg->data_unit_size, slot); 176 else 177 return qcom_ice_evict_key(host->ice, slot); 178 } 179 180 #else 181 182 #define ufs_qcom_ice_program_key NULL 183 184 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host) 185 { 186 } 187 188 static int ufs_qcom_ice_init(struct ufs_qcom_host *host) 189 { 190 return 0; 191 } 192 193 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host) 194 { 195 return 0; 196 } 197 198 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host) 199 { 200 return 0; 201 } 202 #endif 203 204 static int ufs_qcom_host_clk_get(struct device *dev, 205 const char *name, struct clk **clk_out, bool optional) 206 { 207 struct clk *clk; 208 int err = 0; 209 210 clk = devm_clk_get(dev, name); 211 if (!IS_ERR(clk)) { 212 *clk_out = clk; 213 return 0; 214 } 215 216 err = PTR_ERR(clk); 217 218 if (optional && err == -ENOENT) { 219 *clk_out = NULL; 220 return 0; 221 } 222 223 if (err != -EPROBE_DEFER) 224 dev_err(dev, "failed to get %s err %d\n", name, err); 225 226 return err; 227 } 228 229 static int ufs_qcom_host_clk_enable(struct device *dev, 230 const char *name, struct clk *clk) 231 { 232 int err = 0; 233 234 err = clk_prepare_enable(clk); 235 if (err) 236 dev_err(dev, "%s: %s enable failed %d\n", __func__, name, err); 237 238 return err; 239 } 240 241 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host) 242 { 243 if (!host->is_lane_clks_enabled) 244 return; 245 246 clk_disable_unprepare(host->tx_l1_sync_clk); 247 clk_disable_unprepare(host->tx_l0_sync_clk); 248 clk_disable_unprepare(host->rx_l1_sync_clk); 249 clk_disable_unprepare(host->rx_l0_sync_clk); 250 251 host->is_lane_clks_enabled = false; 252 } 253 254 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host) 255 { 256 int err; 257 struct device *dev = host->hba->dev; 258 259 if (host->is_lane_clks_enabled) 260 return 0; 261 262 err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk", 263 host->rx_l0_sync_clk); 264 if (err) 265 return err; 266 267 err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk", 268 host->tx_l0_sync_clk); 269 if (err) 270 goto disable_rx_l0; 271 272 err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk", 273 host->rx_l1_sync_clk); 274 if (err) 275 goto disable_tx_l0; 276 277 err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk", 278 host->tx_l1_sync_clk); 279 if (err) 280 goto disable_rx_l1; 281 282 host->is_lane_clks_enabled = true; 283 284 return 0; 285 286 disable_rx_l1: 287 clk_disable_unprepare(host->rx_l1_sync_clk); 288 disable_tx_l0: 289 clk_disable_unprepare(host->tx_l0_sync_clk); 290 disable_rx_l0: 291 clk_disable_unprepare(host->rx_l0_sync_clk); 292 293 return err; 294 } 295 296 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host) 297 { 298 int err = 0; 299 struct device *dev = host->hba->dev; 300 301 if (has_acpi_companion(dev)) 302 return 0; 303 304 err = ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk", 305 &host->rx_l0_sync_clk, false); 306 if (err) 307 return err; 308 309 err = ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk", 310 &host->tx_l0_sync_clk, false); 311 if (err) 312 return err; 313 314 /* In case of single lane per direction, don't read lane1 clocks */ 315 if (host->hba->lanes_per_direction > 1) { 316 err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk", 317 &host->rx_l1_sync_clk, false); 318 if (err) 319 return err; 320 321 err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk", 322 &host->tx_l1_sync_clk, true); 323 } 324 325 return 0; 326 } 327 328 static int ufs_qcom_check_hibern8(struct ufs_hba *hba) 329 { 330 int err; 331 u32 tx_fsm_val = 0; 332 unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS); 333 334 do { 335 err = ufshcd_dme_get(hba, 336 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 337 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 338 &tx_fsm_val); 339 if (err || tx_fsm_val == TX_FSM_HIBERN8) 340 break; 341 342 /* sleep for max. 200us */ 343 usleep_range(100, 200); 344 } while (time_before(jiffies, timeout)); 345 346 /* 347 * we might have scheduled out for long during polling so 348 * check the state again. 349 */ 350 if (time_after(jiffies, timeout)) 351 err = ufshcd_dme_get(hba, 352 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 353 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 354 &tx_fsm_val); 355 356 if (err) { 357 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n", 358 __func__, err); 359 } else if (tx_fsm_val != TX_FSM_HIBERN8) { 360 err = tx_fsm_val; 361 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n", 362 __func__, err); 363 } 364 365 return err; 366 } 367 368 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host) 369 { 370 ufshcd_rmwl(host->hba, QUNIPRO_SEL, 371 ufs_qcom_cap_qunipro(host) ? QUNIPRO_SEL : 0, 372 REG_UFS_CFG1); 373 374 if (host->hw_ver.major >= 0x05) 375 ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0); 376 377 /* make sure above configuration is applied before we return */ 378 mb(); 379 } 380 381 /* 382 * ufs_qcom_host_reset - reset host controller and PHY 383 */ 384 static int ufs_qcom_host_reset(struct ufs_hba *hba) 385 { 386 int ret = 0; 387 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 388 bool reenable_intr = false; 389 390 if (!host->core_reset) { 391 dev_warn(hba->dev, "%s: reset control not set\n", __func__); 392 return 0; 393 } 394 395 reenable_intr = hba->is_irq_enabled; 396 disable_irq(hba->irq); 397 hba->is_irq_enabled = false; 398 399 ret = reset_control_assert(host->core_reset); 400 if (ret) { 401 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n", 402 __func__, ret); 403 return ret; 404 } 405 406 /* 407 * The hardware requirement for delay between assert/deassert 408 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to 409 * ~125us (4/32768). To be on the safe side add 200us delay. 410 */ 411 usleep_range(200, 210); 412 413 ret = reset_control_deassert(host->core_reset); 414 if (ret) 415 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n", 416 __func__, ret); 417 418 usleep_range(1000, 1100); 419 420 if (reenable_intr) { 421 enable_irq(hba->irq); 422 hba->is_irq_enabled = true; 423 } 424 425 return 0; 426 } 427 428 static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) 429 { 430 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 431 432 if (host->hw_ver.major == 0x1) { 433 /* 434 * HS-G3 operations may not reliably work on legacy QCOM 435 * UFS host controller hardware even though capability 436 * exchange during link startup phase may end up 437 * negotiating maximum supported gear as G3. 438 * Hence downgrade the maximum supported gear to HS-G2. 439 */ 440 return UFS_HS_G2; 441 } else if (host->hw_ver.major >= 0x4) { 442 return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0)); 443 } 444 445 /* Default is HS-G3 */ 446 return UFS_HS_G3; 447 } 448 449 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) 450 { 451 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 452 struct phy *phy = host->generic_phy; 453 int ret; 454 455 /* Reset UFS Host Controller and PHY */ 456 ret = ufs_qcom_host_reset(hba); 457 if (ret) 458 dev_warn(hba->dev, "%s: host reset returned %d\n", 459 __func__, ret); 460 461 /* phy initialization - calibrate the phy */ 462 ret = phy_init(phy); 463 if (ret) { 464 dev_err(hba->dev, "%s: phy init failed, ret = %d\n", 465 __func__, ret); 466 return ret; 467 } 468 469 phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->hs_gear); 470 471 /* power on phy - start serdes and phy's power and clocks */ 472 ret = phy_power_on(phy); 473 if (ret) { 474 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n", 475 __func__, ret); 476 goto out_disable_phy; 477 } 478 479 ufs_qcom_select_unipro_mode(host); 480 481 return 0; 482 483 out_disable_phy: 484 phy_exit(phy); 485 486 return ret; 487 } 488 489 /* 490 * The UTP controller has a number of internal clock gating cells (CGCs). 491 * Internal hardware sub-modules within the UTP controller control the CGCs. 492 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved 493 * in a specific operation, UTP controller CGCs are by default disabled and 494 * this function enables them (after every UFS link startup) to save some power 495 * leakage. 496 */ 497 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba) 498 { 499 ufshcd_writel(hba, 500 ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL, 501 REG_UFS_CFG2); 502 503 /* Ensure that HW clock gating is enabled before next operations */ 504 mb(); 505 } 506 507 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba, 508 enum ufs_notify_change_status status) 509 { 510 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 511 int err = 0; 512 513 switch (status) { 514 case PRE_CHANGE: 515 ufs_qcom_power_up_sequence(hba); 516 /* 517 * The PHY PLL output is the source of tx/rx lane symbol 518 * clocks, hence, enable the lane clocks only after PHY 519 * is initialized. 520 */ 521 err = ufs_qcom_enable_lane_clks(host); 522 break; 523 case POST_CHANGE: 524 /* check if UFS PHY moved from DISABLED to HIBERN8 */ 525 err = ufs_qcom_check_hibern8(hba); 526 ufs_qcom_enable_hw_clk_gating(hba); 527 ufs_qcom_ice_enable(host); 528 break; 529 default: 530 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status); 531 err = -EINVAL; 532 break; 533 } 534 return err; 535 } 536 537 /* 538 * Return: zero for success and non-zero in case of a failure. 539 */ 540 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, 541 u32 hs, u32 rate, bool update_link_startup_timer) 542 { 543 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 544 struct ufs_clk_info *clki; 545 u32 core_clk_period_in_ns; 546 u32 tx_clk_cycles_per_us = 0; 547 unsigned long core_clk_rate = 0; 548 u32 core_clk_cycles_per_us = 0; 549 550 static u32 pwm_fr_table[][2] = { 551 {UFS_PWM_G1, 0x1}, 552 {UFS_PWM_G2, 0x1}, 553 {UFS_PWM_G3, 0x1}, 554 {UFS_PWM_G4, 0x1}, 555 }; 556 557 static u32 hs_fr_table_rA[][2] = { 558 {UFS_HS_G1, 0x1F}, 559 {UFS_HS_G2, 0x3e}, 560 {UFS_HS_G3, 0x7D}, 561 }; 562 563 static u32 hs_fr_table_rB[][2] = { 564 {UFS_HS_G1, 0x24}, 565 {UFS_HS_G2, 0x49}, 566 {UFS_HS_G3, 0x92}, 567 }; 568 569 /* 570 * The Qunipro controller does not use following registers: 571 * SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG & 572 * UFS_REG_PA_LINK_STARTUP_TIMER 573 * But UTP controller uses SYS1CLK_1US_REG register for Interrupt 574 * Aggregation logic. 575 */ 576 if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba)) 577 return 0; 578 579 if (gear == 0) { 580 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear); 581 return -EINVAL; 582 } 583 584 list_for_each_entry(clki, &hba->clk_list_head, list) { 585 if (!strcmp(clki->name, "core_clk")) 586 core_clk_rate = clk_get_rate(clki->clk); 587 } 588 589 /* If frequency is smaller than 1MHz, set to 1MHz */ 590 if (core_clk_rate < DEFAULT_CLK_RATE_HZ) 591 core_clk_rate = DEFAULT_CLK_RATE_HZ; 592 593 core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC; 594 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) { 595 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US); 596 /* 597 * make sure above write gets applied before we return from 598 * this function. 599 */ 600 mb(); 601 } 602 603 if (ufs_qcom_cap_qunipro(host)) 604 return 0; 605 606 core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate; 607 core_clk_period_in_ns <<= OFFSET_CLK_NS_REG; 608 core_clk_period_in_ns &= MASK_CLK_NS_REG; 609 610 switch (hs) { 611 case FASTAUTO_MODE: 612 case FAST_MODE: 613 if (rate == PA_HS_MODE_A) { 614 if (gear > ARRAY_SIZE(hs_fr_table_rA)) { 615 dev_err(hba->dev, 616 "%s: index %d exceeds table size %zu\n", 617 __func__, gear, 618 ARRAY_SIZE(hs_fr_table_rA)); 619 return -EINVAL; 620 } 621 tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1]; 622 } else if (rate == PA_HS_MODE_B) { 623 if (gear > ARRAY_SIZE(hs_fr_table_rB)) { 624 dev_err(hba->dev, 625 "%s: index %d exceeds table size %zu\n", 626 __func__, gear, 627 ARRAY_SIZE(hs_fr_table_rB)); 628 return -EINVAL; 629 } 630 tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1]; 631 } else { 632 dev_err(hba->dev, "%s: invalid rate = %d\n", 633 __func__, rate); 634 return -EINVAL; 635 } 636 break; 637 case SLOWAUTO_MODE: 638 case SLOW_MODE: 639 if (gear > ARRAY_SIZE(pwm_fr_table)) { 640 dev_err(hba->dev, 641 "%s: index %d exceeds table size %zu\n", 642 __func__, gear, 643 ARRAY_SIZE(pwm_fr_table)); 644 return -EINVAL; 645 } 646 tx_clk_cycles_per_us = pwm_fr_table[gear-1][1]; 647 break; 648 case UNCHANGED: 649 default: 650 dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs); 651 return -EINVAL; 652 } 653 654 if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) != 655 (core_clk_period_in_ns | tx_clk_cycles_per_us)) { 656 /* this register 2 fields shall be written at once */ 657 ufshcd_writel(hba, core_clk_period_in_ns | tx_clk_cycles_per_us, 658 REG_UFS_TX_SYMBOL_CLK_NS_US); 659 /* 660 * make sure above write gets applied before we return from 661 * this function. 662 */ 663 mb(); 664 } 665 666 if (update_link_startup_timer && host->hw_ver.major != 0x5) { 667 ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100), 668 REG_UFS_CFG0); 669 /* 670 * make sure that this configuration is applied before 671 * we return 672 */ 673 mb(); 674 } 675 676 return 0; 677 } 678 679 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, 680 enum ufs_notify_change_status status) 681 { 682 int err = 0; 683 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 684 685 switch (status) { 686 case PRE_CHANGE: 687 if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE, 688 0, true)) { 689 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", 690 __func__); 691 return -EINVAL; 692 } 693 694 if (ufs_qcom_cap_qunipro(host)) 695 /* 696 * set unipro core clock cycles to 150 & clear clock 697 * divider 698 */ 699 err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 700 150); 701 702 /* 703 * Some UFS devices (and may be host) have issues if LCC is 704 * enabled. So we are setting PA_Local_TX_LCC_Enable to 0 705 * before link startup which will make sure that both host 706 * and device TX LCC are disabled once link startup is 707 * completed. 708 */ 709 if (ufshcd_get_local_unipro_ver(hba) != UFS_UNIPRO_VER_1_41) 710 err = ufshcd_disable_host_tx_lcc(hba); 711 712 break; 713 default: 714 break; 715 } 716 717 return err; 718 } 719 720 static void ufs_qcom_device_reset_ctrl(struct ufs_hba *hba, bool asserted) 721 { 722 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 723 724 /* reset gpio is optional */ 725 if (!host->device_reset) 726 return; 727 728 gpiod_set_value_cansleep(host->device_reset, asserted); 729 } 730 731 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, 732 enum ufs_notify_change_status status) 733 { 734 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 735 struct phy *phy = host->generic_phy; 736 737 if (status == PRE_CHANGE) 738 return 0; 739 740 if (ufs_qcom_is_link_off(hba)) { 741 /* 742 * Disable the tx/rx lane symbol clocks before PHY is 743 * powered down as the PLL source should be disabled 744 * after downstream clocks are disabled. 745 */ 746 ufs_qcom_disable_lane_clks(host); 747 phy_power_off(phy); 748 749 /* reset the connected UFS device during power down */ 750 ufs_qcom_device_reset_ctrl(hba, true); 751 752 } else if (!ufs_qcom_is_link_active(hba)) { 753 ufs_qcom_disable_lane_clks(host); 754 } 755 756 return ufs_qcom_ice_suspend(host); 757 } 758 759 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) 760 { 761 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 762 struct phy *phy = host->generic_phy; 763 int err; 764 765 if (ufs_qcom_is_link_off(hba)) { 766 err = phy_power_on(phy); 767 if (err) { 768 dev_err(hba->dev, "%s: failed PHY power on: %d\n", 769 __func__, err); 770 return err; 771 } 772 773 err = ufs_qcom_enable_lane_clks(host); 774 if (err) 775 return err; 776 777 } else if (!ufs_qcom_is_link_active(hba)) { 778 err = ufs_qcom_enable_lane_clks(host); 779 if (err) 780 return err; 781 } 782 783 return ufs_qcom_ice_resume(host); 784 } 785 786 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable) 787 { 788 if (host->dev_ref_clk_ctrl_mmio && 789 (enable ^ host->is_dev_ref_clk_enabled)) { 790 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio); 791 792 if (enable) 793 temp |= host->dev_ref_clk_en_mask; 794 else 795 temp &= ~host->dev_ref_clk_en_mask; 796 797 /* 798 * If we are here to disable this clock it might be immediately 799 * after entering into hibern8 in which case we need to make 800 * sure that device ref_clk is active for specific time after 801 * hibern8 enter. 802 */ 803 if (!enable) { 804 unsigned long gating_wait; 805 806 gating_wait = host->hba->dev_info.clk_gating_wait_us; 807 if (!gating_wait) { 808 udelay(1); 809 } else { 810 /* 811 * bRefClkGatingWaitTime defines the minimum 812 * time for which the reference clock is 813 * required by device during transition from 814 * HS-MODE to LS-MODE or HIBERN8 state. Give it 815 * more delay to be on the safe side. 816 */ 817 gating_wait += 10; 818 usleep_range(gating_wait, gating_wait + 10); 819 } 820 } 821 822 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio); 823 824 /* 825 * Make sure the write to ref_clk reaches the destination and 826 * not stored in a Write Buffer (WB). 827 */ 828 readl(host->dev_ref_clk_ctrl_mmio); 829 830 /* 831 * If we call hibern8 exit after this, we need to make sure that 832 * device ref_clk is stable for at least 1us before the hibern8 833 * exit command. 834 */ 835 if (enable) 836 udelay(1); 837 838 host->is_dev_ref_clk_enabled = enable; 839 } 840 } 841 842 static int ufs_qcom_icc_set_bw(struct ufs_qcom_host *host, u32 mem_bw, u32 cfg_bw) 843 { 844 struct device *dev = host->hba->dev; 845 int ret; 846 847 ret = icc_set_bw(host->icc_ddr, 0, mem_bw); 848 if (ret < 0) { 849 dev_err(dev, "failed to set bandwidth request: %d\n", ret); 850 return ret; 851 } 852 853 ret = icc_set_bw(host->icc_cpu, 0, cfg_bw); 854 if (ret < 0) { 855 dev_err(dev, "failed to set bandwidth request: %d\n", ret); 856 return ret; 857 } 858 859 return 0; 860 } 861 862 static struct __ufs_qcom_bw_table ufs_qcom_get_bw_table(struct ufs_qcom_host *host) 863 { 864 struct ufs_pa_layer_attr *p = &host->dev_req_params; 865 int gear = max_t(u32, p->gear_rx, p->gear_tx); 866 int lane = max_t(u32, p->lane_rx, p->lane_tx); 867 868 if (ufshcd_is_hs_mode(p)) { 869 if (p->hs_rate == PA_HS_MODE_B) 870 return ufs_qcom_bw_table[MODE_HS_RB][gear][lane]; 871 else 872 return ufs_qcom_bw_table[MODE_HS_RA][gear][lane]; 873 } else { 874 return ufs_qcom_bw_table[MODE_PWM][gear][lane]; 875 } 876 } 877 878 static int ufs_qcom_icc_update_bw(struct ufs_qcom_host *host) 879 { 880 struct __ufs_qcom_bw_table bw_table; 881 882 bw_table = ufs_qcom_get_bw_table(host); 883 884 return ufs_qcom_icc_set_bw(host, bw_table.mem_bw, bw_table.cfg_bw); 885 } 886 887 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, 888 enum ufs_notify_change_status status, 889 struct ufs_pa_layer_attr *dev_max_params, 890 struct ufs_pa_layer_attr *dev_req_params) 891 { 892 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 893 struct ufs_dev_params ufs_qcom_cap; 894 int ret = 0; 895 896 if (!dev_req_params) { 897 pr_err("%s: incoming dev_req_params is NULL\n", __func__); 898 return -EINVAL; 899 } 900 901 switch (status) { 902 case PRE_CHANGE: 903 ufshcd_init_pwr_dev_param(&ufs_qcom_cap); 904 ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE; 905 906 /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */ 907 ufs_qcom_cap.hs_tx_gear = ufs_qcom_cap.hs_rx_gear = ufs_qcom_get_hs_gear(hba); 908 909 ret = ufshcd_get_pwr_dev_param(&ufs_qcom_cap, 910 dev_max_params, 911 dev_req_params); 912 if (ret) { 913 dev_err(hba->dev, "%s: failed to determine capabilities\n", 914 __func__); 915 return ret; 916 } 917 918 /* 919 * Update hs_gear only when the gears are scaled to a higher value. This is because, 920 * the PHY gear settings are backwards compatible and we only need to change the PHY 921 * settings while scaling to higher gears. 922 */ 923 if (dev_req_params->gear_tx > host->hs_gear) 924 host->hs_gear = dev_req_params->gear_tx; 925 926 /* enable the device ref clock before changing to HS mode */ 927 if (!ufshcd_is_hs_mode(&hba->pwr_info) && 928 ufshcd_is_hs_mode(dev_req_params)) 929 ufs_qcom_dev_ref_clk_ctrl(host, true); 930 931 if (host->hw_ver.major >= 0x4) { 932 ufshcd_dme_configure_adapt(hba, 933 dev_req_params->gear_tx, 934 PA_INITIAL_ADAPT); 935 } 936 break; 937 case POST_CHANGE: 938 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx, 939 dev_req_params->pwr_rx, 940 dev_req_params->hs_rate, false)) { 941 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", 942 __func__); 943 /* 944 * we return error code at the end of the routine, 945 * but continue to configure UFS_PHY_TX_LANE_ENABLE 946 * and bus voting as usual 947 */ 948 ret = -EINVAL; 949 } 950 951 /* cache the power mode parameters to use internally */ 952 memcpy(&host->dev_req_params, 953 dev_req_params, sizeof(*dev_req_params)); 954 955 ufs_qcom_icc_update_bw(host); 956 957 /* disable the device ref clock if entered PWM mode */ 958 if (ufshcd_is_hs_mode(&hba->pwr_info) && 959 !ufshcd_is_hs_mode(dev_req_params)) 960 ufs_qcom_dev_ref_clk_ctrl(host, false); 961 break; 962 default: 963 ret = -EINVAL; 964 break; 965 } 966 967 return ret; 968 } 969 970 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba) 971 { 972 int err; 973 u32 pa_vs_config_reg1; 974 975 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), 976 &pa_vs_config_reg1); 977 if (err) 978 return err; 979 980 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */ 981 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), 982 (pa_vs_config_reg1 | (1 << 12))); 983 } 984 985 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba) 986 { 987 int err = 0; 988 989 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME) 990 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba); 991 992 if (hba->dev_info.wmanufacturerid == UFS_VENDOR_WDC) 993 hba->dev_quirks |= UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE; 994 995 return err; 996 } 997 998 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba) 999 { 1000 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1001 1002 if (host->hw_ver.major == 0x1) 1003 return ufshci_version(1, 1); 1004 else 1005 return ufshci_version(2, 0); 1006 } 1007 1008 /** 1009 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks 1010 * @hba: host controller instance 1011 * 1012 * QCOM UFS host controller might have some non standard behaviours (quirks) 1013 * than what is specified by UFSHCI specification. Advertise all such 1014 * quirks to standard UFS host controller driver so standard takes them into 1015 * account. 1016 */ 1017 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba) 1018 { 1019 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1020 1021 if (host->hw_ver.major == 0x01) { 1022 hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS 1023 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP 1024 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE; 1025 1026 if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001) 1027 hba->quirks |= UFSHCD_QUIRK_BROKEN_INTR_AGGR; 1028 1029 hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC; 1030 } 1031 1032 if (host->hw_ver.major == 0x2) { 1033 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION; 1034 1035 if (!ufs_qcom_cap_qunipro(host)) 1036 /* Legacy UniPro mode still need following quirks */ 1037 hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS 1038 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE 1039 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP); 1040 } 1041 1042 if (host->hw_ver.major > 0x3) 1043 hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; 1044 } 1045 1046 static void ufs_qcom_set_caps(struct ufs_hba *hba) 1047 { 1048 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1049 1050 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; 1051 hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING; 1052 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND; 1053 hba->caps |= UFSHCD_CAP_WB_EN; 1054 hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE; 1055 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND; 1056 1057 if (host->hw_ver.major >= 0x2) { 1058 host->caps = UFS_QCOM_CAP_QUNIPRO | 1059 UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE; 1060 } 1061 } 1062 1063 /** 1064 * ufs_qcom_setup_clocks - enables/disable clocks 1065 * @hba: host controller instance 1066 * @on: If true, enable clocks else disable them. 1067 * @status: PRE_CHANGE or POST_CHANGE notify 1068 * 1069 * Return: 0 on success, non-zero on failure. 1070 */ 1071 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, 1072 enum ufs_notify_change_status status) 1073 { 1074 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1075 1076 /* 1077 * In case ufs_qcom_init() is not yet done, simply ignore. 1078 * This ufs_qcom_setup_clocks() shall be called from 1079 * ufs_qcom_init() after init is done. 1080 */ 1081 if (!host) 1082 return 0; 1083 1084 switch (status) { 1085 case PRE_CHANGE: 1086 if (on) { 1087 ufs_qcom_icc_update_bw(host); 1088 } else { 1089 if (!ufs_qcom_is_link_active(hba)) { 1090 /* disable device ref_clk */ 1091 ufs_qcom_dev_ref_clk_ctrl(host, false); 1092 } 1093 } 1094 break; 1095 case POST_CHANGE: 1096 if (on) { 1097 /* enable the device ref clock for HS mode*/ 1098 if (ufshcd_is_hs_mode(&hba->pwr_info)) 1099 ufs_qcom_dev_ref_clk_ctrl(host, true); 1100 } else { 1101 ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MIN][0][0].mem_bw, 1102 ufs_qcom_bw_table[MODE_MIN][0][0].cfg_bw); 1103 } 1104 break; 1105 } 1106 1107 return 0; 1108 } 1109 1110 static int 1111 ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) 1112 { 1113 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); 1114 1115 ufs_qcom_assert_reset(host->hba); 1116 /* provide 1ms delay to let the reset pulse propagate. */ 1117 usleep_range(1000, 1100); 1118 return 0; 1119 } 1120 1121 static int 1122 ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) 1123 { 1124 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); 1125 1126 ufs_qcom_deassert_reset(host->hba); 1127 1128 /* 1129 * after reset deassertion, phy will need all ref clocks, 1130 * voltage, current to settle down before starting serdes. 1131 */ 1132 usleep_range(1000, 1100); 1133 return 0; 1134 } 1135 1136 static const struct reset_control_ops ufs_qcom_reset_ops = { 1137 .assert = ufs_qcom_reset_assert, 1138 .deassert = ufs_qcom_reset_deassert, 1139 }; 1140 1141 static int ufs_qcom_icc_init(struct ufs_qcom_host *host) 1142 { 1143 struct device *dev = host->hba->dev; 1144 int ret; 1145 1146 host->icc_ddr = devm_of_icc_get(dev, "ufs-ddr"); 1147 if (IS_ERR(host->icc_ddr)) 1148 return dev_err_probe(dev, PTR_ERR(host->icc_ddr), 1149 "failed to acquire interconnect path\n"); 1150 1151 host->icc_cpu = devm_of_icc_get(dev, "cpu-ufs"); 1152 if (IS_ERR(host->icc_cpu)) 1153 return dev_err_probe(dev, PTR_ERR(host->icc_cpu), 1154 "failed to acquire interconnect path\n"); 1155 1156 /* 1157 * Set Maximum bandwidth vote before initializing the UFS controller and 1158 * device. Ideally, a minimal interconnect vote would suffice for the 1159 * initialization, but a max vote would allow faster initialization. 1160 */ 1161 ret = ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MAX][0][0].mem_bw, 1162 ufs_qcom_bw_table[MODE_MAX][0][0].cfg_bw); 1163 if (ret < 0) 1164 return dev_err_probe(dev, ret, "failed to set bandwidth request\n"); 1165 1166 return 0; 1167 } 1168 1169 /** 1170 * ufs_qcom_init - bind phy with controller 1171 * @hba: host controller instance 1172 * 1173 * Binds PHY with controller and powers up PHY enabling clocks 1174 * and regulators. 1175 * 1176 * Return: -EPROBE_DEFER if binding fails, returns negative error 1177 * on phy power up failure and returns zero on success. 1178 */ 1179 static int ufs_qcom_init(struct ufs_hba *hba) 1180 { 1181 int err; 1182 struct device *dev = hba->dev; 1183 struct platform_device *pdev = to_platform_device(dev); 1184 struct ufs_qcom_host *host; 1185 struct resource *res; 1186 struct ufs_clk_info *clki; 1187 1188 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); 1189 if (!host) { 1190 dev_err(dev, "%s: no memory for qcom ufs host\n", __func__); 1191 return -ENOMEM; 1192 } 1193 1194 /* Make a two way bind between the qcom host and the hba */ 1195 host->hba = hba; 1196 ufshcd_set_variant(hba, host); 1197 1198 /* Setup the optional reset control of HCI */ 1199 host->core_reset = devm_reset_control_get_optional(hba->dev, "rst"); 1200 if (IS_ERR(host->core_reset)) { 1201 err = dev_err_probe(dev, PTR_ERR(host->core_reset), 1202 "Failed to get reset control\n"); 1203 goto out_variant_clear; 1204 } 1205 1206 /* Fire up the reset controller. Failure here is non-fatal. */ 1207 host->rcdev.of_node = dev->of_node; 1208 host->rcdev.ops = &ufs_qcom_reset_ops; 1209 host->rcdev.owner = dev->driver->owner; 1210 host->rcdev.nr_resets = 1; 1211 err = devm_reset_controller_register(dev, &host->rcdev); 1212 if (err) 1213 dev_warn(dev, "Failed to register reset controller\n"); 1214 1215 if (!has_acpi_companion(dev)) { 1216 host->generic_phy = devm_phy_get(dev, "ufsphy"); 1217 if (IS_ERR(host->generic_phy)) { 1218 err = dev_err_probe(dev, PTR_ERR(host->generic_phy), "Failed to get PHY\n"); 1219 goto out_variant_clear; 1220 } 1221 } 1222 1223 err = ufs_qcom_icc_init(host); 1224 if (err) 1225 goto out_variant_clear; 1226 1227 host->device_reset = devm_gpiod_get_optional(dev, "reset", 1228 GPIOD_OUT_HIGH); 1229 if (IS_ERR(host->device_reset)) { 1230 err = PTR_ERR(host->device_reset); 1231 if (err != -EPROBE_DEFER) 1232 dev_err(dev, "failed to acquire reset gpio: %d\n", err); 1233 goto out_variant_clear; 1234 } 1235 1236 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major, 1237 &host->hw_ver.minor, &host->hw_ver.step); 1238 1239 /* 1240 * for newer controllers, device reference clock control bit has 1241 * moved inside UFS controller register address space itself. 1242 */ 1243 if (host->hw_ver.major >= 0x02) { 1244 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1; 1245 host->dev_ref_clk_en_mask = BIT(26); 1246 } else { 1247 /* "dev_ref_clk_ctrl_mem" is optional resource */ 1248 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1249 "dev_ref_clk_ctrl_mem"); 1250 if (res) { 1251 host->dev_ref_clk_ctrl_mmio = 1252 devm_ioremap_resource(dev, res); 1253 if (IS_ERR(host->dev_ref_clk_ctrl_mmio)) 1254 host->dev_ref_clk_ctrl_mmio = NULL; 1255 host->dev_ref_clk_en_mask = BIT(5); 1256 } 1257 } 1258 1259 list_for_each_entry(clki, &hba->clk_list_head, list) { 1260 if (!strcmp(clki->name, "core_clk_unipro")) 1261 clki->keep_link_active = true; 1262 } 1263 1264 err = ufs_qcom_init_lane_clks(host); 1265 if (err) 1266 goto out_variant_clear; 1267 1268 ufs_qcom_set_caps(hba); 1269 ufs_qcom_advertise_quirks(hba); 1270 1271 err = ufs_qcom_ice_init(host); 1272 if (err) 1273 goto out_variant_clear; 1274 1275 ufs_qcom_setup_clocks(hba, true, POST_CHANGE); 1276 1277 if (hba->dev->id < MAX_UFS_QCOM_HOSTS) 1278 ufs_qcom_hosts[hba->dev->id] = host; 1279 1280 ufs_qcom_get_default_testbus_cfg(host); 1281 err = ufs_qcom_testbus_config(host); 1282 if (err) 1283 /* Failure is non-fatal */ 1284 dev_warn(dev, "%s: failed to configure the testbus %d\n", 1285 __func__, err); 1286 1287 /* 1288 * Power up the PHY using the minimum supported gear (UFS_HS_G2). 1289 * Switching to max gear will be performed during reinit if supported. 1290 */ 1291 host->hs_gear = UFS_HS_G2; 1292 1293 return 0; 1294 1295 out_variant_clear: 1296 ufshcd_set_variant(hba, NULL); 1297 1298 return err; 1299 } 1300 1301 static void ufs_qcom_exit(struct ufs_hba *hba) 1302 { 1303 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1304 1305 ufs_qcom_disable_lane_clks(host); 1306 phy_power_off(host->generic_phy); 1307 phy_exit(host->generic_phy); 1308 } 1309 1310 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba, 1311 u32 clk_cycles) 1312 { 1313 int err; 1314 u32 core_clk_ctrl_reg; 1315 1316 if (clk_cycles > DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK) 1317 return -EINVAL; 1318 1319 err = ufshcd_dme_get(hba, 1320 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1321 &core_clk_ctrl_reg); 1322 if (err) 1323 return err; 1324 1325 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK; 1326 core_clk_ctrl_reg |= clk_cycles; 1327 1328 /* Clear CORE_CLK_DIV_EN */ 1329 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; 1330 1331 return ufshcd_dme_set(hba, 1332 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1333 core_clk_ctrl_reg); 1334 } 1335 1336 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba) 1337 { 1338 /* nothing to do as of now */ 1339 return 0; 1340 } 1341 1342 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba) 1343 { 1344 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1345 1346 if (!ufs_qcom_cap_qunipro(host)) 1347 return 0; 1348 1349 /* set unipro core clock cycles to 150 and clear clock divider */ 1350 return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150); 1351 } 1352 1353 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba) 1354 { 1355 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1356 int err; 1357 u32 core_clk_ctrl_reg; 1358 1359 if (!ufs_qcom_cap_qunipro(host)) 1360 return 0; 1361 1362 err = ufshcd_dme_get(hba, 1363 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1364 &core_clk_ctrl_reg); 1365 1366 /* make sure CORE_CLK_DIV_EN is cleared */ 1367 if (!err && 1368 (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) { 1369 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; 1370 err = ufshcd_dme_set(hba, 1371 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1372 core_clk_ctrl_reg); 1373 } 1374 1375 return err; 1376 } 1377 1378 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba) 1379 { 1380 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1381 1382 if (!ufs_qcom_cap_qunipro(host)) 1383 return 0; 1384 1385 /* set unipro core clock cycles to 75 and clear clock divider */ 1386 return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 75); 1387 } 1388 1389 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, 1390 bool scale_up, enum ufs_notify_change_status status) 1391 { 1392 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1393 struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params; 1394 int err = 0; 1395 1396 /* check the host controller state before sending hibern8 cmd */ 1397 if (!ufshcd_is_hba_active(hba)) 1398 return 0; 1399 1400 if (status == PRE_CHANGE) { 1401 err = ufshcd_uic_hibern8_enter(hba); 1402 if (err) 1403 return err; 1404 if (scale_up) 1405 err = ufs_qcom_clk_scale_up_pre_change(hba); 1406 else 1407 err = ufs_qcom_clk_scale_down_pre_change(hba); 1408 1409 if (err) { 1410 ufshcd_uic_hibern8_exit(hba); 1411 return err; 1412 } 1413 } else { 1414 if (scale_up) 1415 err = ufs_qcom_clk_scale_up_post_change(hba); 1416 else 1417 err = ufs_qcom_clk_scale_down_post_change(hba); 1418 1419 1420 if (err) { 1421 ufshcd_uic_hibern8_exit(hba); 1422 return err; 1423 } 1424 1425 ufs_qcom_cfg_timers(hba, 1426 dev_req_params->gear_rx, 1427 dev_req_params->pwr_rx, 1428 dev_req_params->hs_rate, 1429 false); 1430 ufs_qcom_icc_update_bw(host); 1431 ufshcd_uic_hibern8_exit(hba); 1432 } 1433 1434 return 0; 1435 } 1436 1437 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host) 1438 { 1439 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 1440 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1); 1441 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1); 1442 } 1443 1444 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host) 1445 { 1446 /* provide a legal default configuration */ 1447 host->testbus.select_major = TSTBUS_UNIPRO; 1448 host->testbus.select_minor = 37; 1449 } 1450 1451 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host) 1452 { 1453 if (host->testbus.select_major >= TSTBUS_MAX) { 1454 dev_err(host->hba->dev, 1455 "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n", 1456 __func__, host->testbus.select_major); 1457 return false; 1458 } 1459 1460 return true; 1461 } 1462 1463 int ufs_qcom_testbus_config(struct ufs_qcom_host *host) 1464 { 1465 int reg; 1466 int offset; 1467 u32 mask = TEST_BUS_SUB_SEL_MASK; 1468 1469 if (!host) 1470 return -EINVAL; 1471 1472 if (!ufs_qcom_testbus_cfg_is_ok(host)) 1473 return -EPERM; 1474 1475 switch (host->testbus.select_major) { 1476 case TSTBUS_UAWM: 1477 reg = UFS_TEST_BUS_CTRL_0; 1478 offset = 24; 1479 break; 1480 case TSTBUS_UARM: 1481 reg = UFS_TEST_BUS_CTRL_0; 1482 offset = 16; 1483 break; 1484 case TSTBUS_TXUC: 1485 reg = UFS_TEST_BUS_CTRL_0; 1486 offset = 8; 1487 break; 1488 case TSTBUS_RXUC: 1489 reg = UFS_TEST_BUS_CTRL_0; 1490 offset = 0; 1491 break; 1492 case TSTBUS_DFC: 1493 reg = UFS_TEST_BUS_CTRL_1; 1494 offset = 24; 1495 break; 1496 case TSTBUS_TRLUT: 1497 reg = UFS_TEST_BUS_CTRL_1; 1498 offset = 16; 1499 break; 1500 case TSTBUS_TMRLUT: 1501 reg = UFS_TEST_BUS_CTRL_1; 1502 offset = 8; 1503 break; 1504 case TSTBUS_OCSC: 1505 reg = UFS_TEST_BUS_CTRL_1; 1506 offset = 0; 1507 break; 1508 case TSTBUS_WRAPPER: 1509 reg = UFS_TEST_BUS_CTRL_2; 1510 offset = 16; 1511 break; 1512 case TSTBUS_COMBINED: 1513 reg = UFS_TEST_BUS_CTRL_2; 1514 offset = 8; 1515 break; 1516 case TSTBUS_UTP_HCI: 1517 reg = UFS_TEST_BUS_CTRL_2; 1518 offset = 0; 1519 break; 1520 case TSTBUS_UNIPRO: 1521 reg = UFS_UNIPRO_CFG; 1522 offset = 20; 1523 mask = 0xFFF; 1524 break; 1525 /* 1526 * No need for a default case, since 1527 * ufs_qcom_testbus_cfg_is_ok() checks that the configuration 1528 * is legal 1529 */ 1530 } 1531 mask <<= offset; 1532 ufshcd_rmwl(host->hba, TEST_BUS_SEL, 1533 (u32)host->testbus.select_major << 19, 1534 REG_UFS_CFG1); 1535 ufshcd_rmwl(host->hba, mask, 1536 (u32)host->testbus.select_minor << offset, 1537 reg); 1538 ufs_qcom_enable_test_bus(host); 1539 /* 1540 * Make sure the test bus configuration is 1541 * committed before returning. 1542 */ 1543 mb(); 1544 1545 return 0; 1546 } 1547 1548 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba) 1549 { 1550 u32 reg; 1551 struct ufs_qcom_host *host; 1552 1553 host = ufshcd_get_variant(hba); 1554 1555 ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4, 1556 "HCI Vendor Specific Registers "); 1557 1558 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC); 1559 ufshcd_dump_regs(hba, reg, 44 * 4, "UFS_UFS_DBG_RD_REG_OCSC "); 1560 1561 reg = ufshcd_readl(hba, REG_UFS_CFG1); 1562 reg |= UTP_DBG_RAMS_EN; 1563 ufshcd_writel(hba, reg, REG_UFS_CFG1); 1564 1565 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM); 1566 ufshcd_dump_regs(hba, reg, 32 * 4, "UFS_UFS_DBG_RD_EDTL_RAM "); 1567 1568 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM); 1569 ufshcd_dump_regs(hba, reg, 128 * 4, "UFS_UFS_DBG_RD_DESC_RAM "); 1570 1571 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM); 1572 ufshcd_dump_regs(hba, reg, 64 * 4, "UFS_UFS_DBG_RD_PRDT_RAM "); 1573 1574 /* clear bit 17 - UTP_DBG_RAMS_EN */ 1575 ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1); 1576 1577 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM); 1578 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UAWM "); 1579 1580 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM); 1581 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UARM "); 1582 1583 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC); 1584 ufshcd_dump_regs(hba, reg, 48 * 4, "UFS_DBG_RD_REG_TXUC "); 1585 1586 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC); 1587 ufshcd_dump_regs(hba, reg, 27 * 4, "UFS_DBG_RD_REG_RXUC "); 1588 1589 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC); 1590 ufshcd_dump_regs(hba, reg, 19 * 4, "UFS_DBG_RD_REG_DFC "); 1591 1592 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT); 1593 ufshcd_dump_regs(hba, reg, 34 * 4, "UFS_DBG_RD_REG_TRLUT "); 1594 1595 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT); 1596 ufshcd_dump_regs(hba, reg, 9 * 4, "UFS_DBG_RD_REG_TMRLUT "); 1597 } 1598 1599 /** 1600 * ufs_qcom_device_reset() - toggle the (optional) device reset line 1601 * @hba: per-adapter instance 1602 * 1603 * Toggles the (optional) reset line to reset the attached device. 1604 */ 1605 static int ufs_qcom_device_reset(struct ufs_hba *hba) 1606 { 1607 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1608 1609 /* reset gpio is optional */ 1610 if (!host->device_reset) 1611 return -EOPNOTSUPP; 1612 1613 /* 1614 * The UFS device shall detect reset pulses of 1us, sleep for 10us to 1615 * be on the safe side. 1616 */ 1617 ufs_qcom_device_reset_ctrl(hba, true); 1618 usleep_range(10, 15); 1619 1620 ufs_qcom_device_reset_ctrl(hba, false); 1621 usleep_range(10, 15); 1622 1623 return 0; 1624 } 1625 1626 #if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND) 1627 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba, 1628 struct devfreq_dev_profile *p, 1629 struct devfreq_simple_ondemand_data *d) 1630 { 1631 p->polling_ms = 60; 1632 p->timer = DEVFREQ_TIMER_DELAYED; 1633 d->upthreshold = 70; 1634 d->downdifferential = 5; 1635 } 1636 #else 1637 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba, 1638 struct devfreq_dev_profile *p, 1639 struct devfreq_simple_ondemand_data *data) 1640 { 1641 } 1642 #endif 1643 1644 static void ufs_qcom_reinit_notify(struct ufs_hba *hba) 1645 { 1646 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1647 1648 phy_power_off(host->generic_phy); 1649 } 1650 1651 /* Resources */ 1652 static const struct ufshcd_res_info ufs_res_info[RES_MAX] = { 1653 {.name = "ufs_mem",}, 1654 {.name = "mcq",}, 1655 /* Submission Queue DAO */ 1656 {.name = "mcq_sqd",}, 1657 /* Submission Queue Interrupt Status */ 1658 {.name = "mcq_sqis",}, 1659 /* Completion Queue DAO */ 1660 {.name = "mcq_cqd",}, 1661 /* Completion Queue Interrupt Status */ 1662 {.name = "mcq_cqis",}, 1663 /* MCQ vendor specific */ 1664 {.name = "mcq_vs",}, 1665 }; 1666 1667 static int ufs_qcom_mcq_config_resource(struct ufs_hba *hba) 1668 { 1669 struct platform_device *pdev = to_platform_device(hba->dev); 1670 struct ufshcd_res_info *res; 1671 struct resource *res_mem, *res_mcq; 1672 int i, ret = 0; 1673 1674 memcpy(hba->res, ufs_res_info, sizeof(ufs_res_info)); 1675 1676 for (i = 0; i < RES_MAX; i++) { 1677 res = &hba->res[i]; 1678 res->resource = platform_get_resource_byname(pdev, 1679 IORESOURCE_MEM, 1680 res->name); 1681 if (!res->resource) { 1682 dev_info(hba->dev, "Resource %s not provided\n", res->name); 1683 if (i == RES_UFS) 1684 return -ENODEV; 1685 continue; 1686 } else if (i == RES_UFS) { 1687 res_mem = res->resource; 1688 res->base = hba->mmio_base; 1689 continue; 1690 } 1691 1692 res->base = devm_ioremap_resource(hba->dev, res->resource); 1693 if (IS_ERR(res->base)) { 1694 dev_err(hba->dev, "Failed to map res %s, err=%d\n", 1695 res->name, (int)PTR_ERR(res->base)); 1696 ret = PTR_ERR(res->base); 1697 res->base = NULL; 1698 return ret; 1699 } 1700 } 1701 1702 /* MCQ resource provided in DT */ 1703 res = &hba->res[RES_MCQ]; 1704 /* Bail if MCQ resource is provided */ 1705 if (res->base) 1706 goto out; 1707 1708 /* Explicitly allocate MCQ resource from ufs_mem */ 1709 res_mcq = devm_kzalloc(hba->dev, sizeof(*res_mcq), GFP_KERNEL); 1710 if (!res_mcq) 1711 return -ENOMEM; 1712 1713 res_mcq->start = res_mem->start + 1714 MCQ_SQATTR_OFFSET(hba->mcq_capabilities); 1715 res_mcq->end = res_mcq->start + hba->nr_hw_queues * MCQ_QCFG_SIZE - 1; 1716 res_mcq->flags = res_mem->flags; 1717 res_mcq->name = "mcq"; 1718 1719 ret = insert_resource(&iomem_resource, res_mcq); 1720 if (ret) { 1721 dev_err(hba->dev, "Failed to insert MCQ resource, err=%d\n", 1722 ret); 1723 return ret; 1724 } 1725 1726 res->base = devm_ioremap_resource(hba->dev, res_mcq); 1727 if (IS_ERR(res->base)) { 1728 dev_err(hba->dev, "MCQ registers mapping failed, err=%d\n", 1729 (int)PTR_ERR(res->base)); 1730 ret = PTR_ERR(res->base); 1731 goto ioremap_err; 1732 } 1733 1734 out: 1735 hba->mcq_base = res->base; 1736 return 0; 1737 ioremap_err: 1738 res->base = NULL; 1739 remove_resource(res_mcq); 1740 return ret; 1741 } 1742 1743 static int ufs_qcom_op_runtime_config(struct ufs_hba *hba) 1744 { 1745 struct ufshcd_res_info *mem_res, *sqdao_res; 1746 struct ufshcd_mcq_opr_info_t *opr; 1747 int i; 1748 1749 mem_res = &hba->res[RES_UFS]; 1750 sqdao_res = &hba->res[RES_MCQ_SQD]; 1751 1752 if (!mem_res->base || !sqdao_res->base) 1753 return -EINVAL; 1754 1755 for (i = 0; i < OPR_MAX; i++) { 1756 opr = &hba->mcq_opr[i]; 1757 opr->offset = sqdao_res->resource->start - 1758 mem_res->resource->start + 0x40 * i; 1759 opr->stride = 0x100; 1760 opr->base = sqdao_res->base + 0x40 * i; 1761 } 1762 1763 return 0; 1764 } 1765 1766 static int ufs_qcom_get_hba_mac(struct ufs_hba *hba) 1767 { 1768 /* Qualcomm HC supports up to 64 */ 1769 return MAX_SUPP_MAC; 1770 } 1771 1772 static int ufs_qcom_get_outstanding_cqs(struct ufs_hba *hba, 1773 unsigned long *ocqs) 1774 { 1775 struct ufshcd_res_info *mcq_vs_res = &hba->res[RES_MCQ_VS]; 1776 1777 if (!mcq_vs_res->base) 1778 return -EINVAL; 1779 1780 *ocqs = readl(mcq_vs_res->base + UFS_MEM_CQIS_VS); 1781 1782 return 0; 1783 } 1784 1785 static void ufs_qcom_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg) 1786 { 1787 struct device *dev = msi_desc_to_dev(desc); 1788 struct ufs_hba *hba = dev_get_drvdata(dev); 1789 1790 ufshcd_mcq_config_esi(hba, msg); 1791 } 1792 1793 static irqreturn_t ufs_qcom_mcq_esi_handler(int irq, void *data) 1794 { 1795 struct msi_desc *desc = data; 1796 struct device *dev = msi_desc_to_dev(desc); 1797 struct ufs_hba *hba = dev_get_drvdata(dev); 1798 u32 id = desc->msi_index; 1799 struct ufs_hw_queue *hwq = &hba->uhq[id]; 1800 1801 ufshcd_mcq_write_cqis(hba, 0x1, id); 1802 ufshcd_mcq_poll_cqe_lock(hba, hwq); 1803 1804 return IRQ_HANDLED; 1805 } 1806 1807 static int ufs_qcom_config_esi(struct ufs_hba *hba) 1808 { 1809 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1810 struct msi_desc *desc; 1811 struct msi_desc *failed_desc = NULL; 1812 int nr_irqs, ret; 1813 1814 if (host->esi_enabled) 1815 return 0; 1816 1817 /* 1818 * 1. We only handle CQs as of now. 1819 * 2. Poll queues do not need ESI. 1820 */ 1821 nr_irqs = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; 1822 ret = platform_msi_domain_alloc_irqs(hba->dev, nr_irqs, 1823 ufs_qcom_write_msi_msg); 1824 if (ret) { 1825 dev_err(hba->dev, "Failed to request Platform MSI %d\n", ret); 1826 goto out; 1827 } 1828 1829 msi_lock_descs(hba->dev); 1830 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { 1831 ret = devm_request_irq(hba->dev, desc->irq, 1832 ufs_qcom_mcq_esi_handler, 1833 IRQF_SHARED, "qcom-mcq-esi", desc); 1834 if (ret) { 1835 dev_err(hba->dev, "%s: Fail to request IRQ for %d, err = %d\n", 1836 __func__, desc->irq, ret); 1837 failed_desc = desc; 1838 break; 1839 } 1840 } 1841 msi_unlock_descs(hba->dev); 1842 1843 if (ret) { 1844 /* Rewind */ 1845 msi_lock_descs(hba->dev); 1846 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { 1847 if (desc == failed_desc) 1848 break; 1849 devm_free_irq(hba->dev, desc->irq, hba); 1850 } 1851 msi_unlock_descs(hba->dev); 1852 platform_msi_domain_free_irqs(hba->dev); 1853 } else { 1854 if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 && 1855 host->hw_ver.step == 0) { 1856 ufshcd_writel(hba, 1857 ufshcd_readl(hba, REG_UFS_CFG3) | 0x1F000, 1858 REG_UFS_CFG3); 1859 } 1860 ufshcd_mcq_enable_esi(hba); 1861 } 1862 1863 out: 1864 if (!ret) 1865 host->esi_enabled = true; 1866 1867 return ret; 1868 } 1869 1870 /* 1871 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations 1872 * 1873 * The variant operations configure the necessary controller and PHY 1874 * handshake during initialization. 1875 */ 1876 static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = { 1877 .name = "qcom", 1878 .init = ufs_qcom_init, 1879 .exit = ufs_qcom_exit, 1880 .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version, 1881 .clk_scale_notify = ufs_qcom_clk_scale_notify, 1882 .setup_clocks = ufs_qcom_setup_clocks, 1883 .hce_enable_notify = ufs_qcom_hce_enable_notify, 1884 .link_startup_notify = ufs_qcom_link_startup_notify, 1885 .pwr_change_notify = ufs_qcom_pwr_change_notify, 1886 .apply_dev_quirks = ufs_qcom_apply_dev_quirks, 1887 .suspend = ufs_qcom_suspend, 1888 .resume = ufs_qcom_resume, 1889 .dbg_register_dump = ufs_qcom_dump_dbg_regs, 1890 .device_reset = ufs_qcom_device_reset, 1891 .config_scaling_param = ufs_qcom_config_scaling_param, 1892 .program_key = ufs_qcom_ice_program_key, 1893 .reinit_notify = ufs_qcom_reinit_notify, 1894 .mcq_config_resource = ufs_qcom_mcq_config_resource, 1895 .get_hba_mac = ufs_qcom_get_hba_mac, 1896 .op_runtime_config = ufs_qcom_op_runtime_config, 1897 .get_outstanding_cqs = ufs_qcom_get_outstanding_cqs, 1898 .config_esi = ufs_qcom_config_esi, 1899 }; 1900 1901 /** 1902 * ufs_qcom_probe - probe routine of the driver 1903 * @pdev: pointer to Platform device handle 1904 * 1905 * Return: zero for success and non-zero for failure. 1906 */ 1907 static int ufs_qcom_probe(struct platform_device *pdev) 1908 { 1909 int err; 1910 struct device *dev = &pdev->dev; 1911 1912 /* Perform generic probe */ 1913 err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops); 1914 if (err) 1915 return dev_err_probe(dev, err, "ufshcd_pltfrm_init() failed\n"); 1916 1917 return 0; 1918 } 1919 1920 /** 1921 * ufs_qcom_remove - set driver_data of the device to NULL 1922 * @pdev: pointer to platform device handle 1923 * 1924 * Always returns 0 1925 */ 1926 static int ufs_qcom_remove(struct platform_device *pdev) 1927 { 1928 struct ufs_hba *hba = platform_get_drvdata(pdev); 1929 1930 pm_runtime_get_sync(&(pdev)->dev); 1931 ufshcd_remove(hba); 1932 platform_msi_domain_free_irqs(hba->dev); 1933 return 0; 1934 } 1935 1936 static const struct of_device_id ufs_qcom_of_match[] __maybe_unused = { 1937 { .compatible = "qcom,ufshc"}, 1938 {}, 1939 }; 1940 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match); 1941 1942 #ifdef CONFIG_ACPI 1943 static const struct acpi_device_id ufs_qcom_acpi_match[] = { 1944 { "QCOM24A5" }, 1945 { }, 1946 }; 1947 MODULE_DEVICE_TABLE(acpi, ufs_qcom_acpi_match); 1948 #endif 1949 1950 static const struct dev_pm_ops ufs_qcom_pm_ops = { 1951 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL) 1952 .prepare = ufshcd_suspend_prepare, 1953 .complete = ufshcd_resume_complete, 1954 #ifdef CONFIG_PM_SLEEP 1955 .suspend = ufshcd_system_suspend, 1956 .resume = ufshcd_system_resume, 1957 .freeze = ufshcd_system_freeze, 1958 .restore = ufshcd_system_restore, 1959 .thaw = ufshcd_system_thaw, 1960 #endif 1961 }; 1962 1963 static struct platform_driver ufs_qcom_pltform = { 1964 .probe = ufs_qcom_probe, 1965 .remove = ufs_qcom_remove, 1966 .driver = { 1967 .name = "ufshcd-qcom", 1968 .pm = &ufs_qcom_pm_ops, 1969 .of_match_table = of_match_ptr(ufs_qcom_of_match), 1970 .acpi_match_table = ACPI_PTR(ufs_qcom_acpi_match), 1971 }, 1972 }; 1973 module_platform_driver(ufs_qcom_pltform); 1974 1975 MODULE_LICENSE("GPL v2"); 1976