1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/acpi.h> 7 #include <linux/time.h> 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/interconnect.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/platform_device.h> 14 #include <linux/phy/phy.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/reset-controller.h> 17 #include <linux/devfreq.h> 18 19 #include <soc/qcom/ice.h> 20 21 #include <ufs/ufshcd.h> 22 #include "ufshcd-pltfrm.h" 23 #include <ufs/unipro.h> 24 #include "ufs-qcom.h" 25 #include <ufs/ufshci.h> 26 #include <ufs/ufs_quirks.h> 27 28 #define MCQ_QCFGPTR_MASK GENMASK(7, 0) 29 #define MCQ_QCFGPTR_UNIT 0x200 30 #define MCQ_SQATTR_OFFSET(c) \ 31 ((((c) >> 16) & MCQ_QCFGPTR_MASK) * MCQ_QCFGPTR_UNIT) 32 #define MCQ_QCFG_SIZE 0x40 33 34 enum { 35 TSTBUS_UAWM, 36 TSTBUS_UARM, 37 TSTBUS_TXUC, 38 TSTBUS_RXUC, 39 TSTBUS_DFC, 40 TSTBUS_TRLUT, 41 TSTBUS_TMRLUT, 42 TSTBUS_OCSC, 43 TSTBUS_UTP_HCI, 44 TSTBUS_COMBINED, 45 TSTBUS_WRAPPER, 46 TSTBUS_UNIPRO, 47 TSTBUS_MAX, 48 }; 49 50 #define QCOM_UFS_MAX_GEAR 5 51 #define QCOM_UFS_MAX_LANE 2 52 53 enum { 54 MODE_MIN, 55 MODE_PWM, 56 MODE_HS_RA, 57 MODE_HS_RB, 58 MODE_MAX, 59 }; 60 61 static const struct __ufs_qcom_bw_table { 62 u32 mem_bw; 63 u32 cfg_bw; 64 } ufs_qcom_bw_table[MODE_MAX + 1][QCOM_UFS_MAX_GEAR + 1][QCOM_UFS_MAX_LANE + 1] = { 65 [MODE_MIN][0][0] = { 0, 0 }, /* Bandwidth values in KB/s */ 66 [MODE_PWM][UFS_PWM_G1][UFS_LANE_1] = { 922, 1000 }, 67 [MODE_PWM][UFS_PWM_G2][UFS_LANE_1] = { 1844, 1000 }, 68 [MODE_PWM][UFS_PWM_G3][UFS_LANE_1] = { 3688, 1000 }, 69 [MODE_PWM][UFS_PWM_G4][UFS_LANE_1] = { 7376, 1000 }, 70 [MODE_PWM][UFS_PWM_G5][UFS_LANE_1] = { 14752, 1000 }, 71 [MODE_PWM][UFS_PWM_G1][UFS_LANE_2] = { 1844, 1000 }, 72 [MODE_PWM][UFS_PWM_G2][UFS_LANE_2] = { 3688, 1000 }, 73 [MODE_PWM][UFS_PWM_G3][UFS_LANE_2] = { 7376, 1000 }, 74 [MODE_PWM][UFS_PWM_G4][UFS_LANE_2] = { 14752, 1000 }, 75 [MODE_PWM][UFS_PWM_G5][UFS_LANE_2] = { 29504, 1000 }, 76 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_1] = { 127796, 1000 }, 77 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_1] = { 255591, 1000 }, 78 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 }, 79 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 }, 80 [MODE_HS_RA][UFS_HS_G5][UFS_LANE_1] = { 5836800, 409600 }, 81 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_2] = { 255591, 1000 }, 82 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_2] = { 511181, 1000 }, 83 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 }, 84 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 }, 85 [MODE_HS_RA][UFS_HS_G5][UFS_LANE_2] = { 5836800, 819200 }, 86 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_1] = { 149422, 1000 }, 87 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_1] = { 298189, 1000 }, 88 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 }, 89 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 }, 90 [MODE_HS_RB][UFS_HS_G5][UFS_LANE_1] = { 5836800, 409600 }, 91 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_2] = { 298189, 1000 }, 92 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_2] = { 596378, 1000 }, 93 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 }, 94 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 }, 95 [MODE_HS_RB][UFS_HS_G5][UFS_LANE_2] = { 5836800, 819200 }, 96 [MODE_MAX][0][0] = { 7643136, 819200 }, 97 }; 98 99 static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS]; 100 101 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host); 102 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba, 103 u32 clk_cycles); 104 105 static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd) 106 { 107 return container_of(rcd, struct ufs_qcom_host, rcdev); 108 } 109 110 #ifdef CONFIG_SCSI_UFS_CRYPTO 111 112 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host) 113 { 114 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 115 qcom_ice_enable(host->ice); 116 } 117 118 static int ufs_qcom_ice_init(struct ufs_qcom_host *host) 119 { 120 struct ufs_hba *hba = host->hba; 121 struct device *dev = hba->dev; 122 struct qcom_ice *ice; 123 124 ice = of_qcom_ice_get(dev); 125 if (ice == ERR_PTR(-EOPNOTSUPP)) { 126 dev_warn(dev, "Disabling inline encryption support\n"); 127 ice = NULL; 128 } 129 130 if (IS_ERR_OR_NULL(ice)) 131 return PTR_ERR_OR_ZERO(ice); 132 133 host->ice = ice; 134 hba->caps |= UFSHCD_CAP_CRYPTO; 135 136 return 0; 137 } 138 139 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host) 140 { 141 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 142 return qcom_ice_resume(host->ice); 143 144 return 0; 145 } 146 147 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host) 148 { 149 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 150 return qcom_ice_suspend(host->ice); 151 152 return 0; 153 } 154 155 static int ufs_qcom_ice_program_key(struct ufs_hba *hba, 156 const union ufs_crypto_cfg_entry *cfg, 157 int slot) 158 { 159 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 160 union ufs_crypto_cap_entry cap; 161 bool config_enable = 162 cfg->config_enable & UFS_CRYPTO_CONFIGURATION_ENABLE; 163 164 /* Only AES-256-XTS has been tested so far. */ 165 cap = hba->crypto_cap_array[cfg->crypto_cap_idx]; 166 if (cap.algorithm_id != UFS_CRYPTO_ALG_AES_XTS || 167 cap.key_size != UFS_CRYPTO_KEY_SIZE_256) 168 return -EOPNOTSUPP; 169 170 if (config_enable) 171 return qcom_ice_program_key(host->ice, 172 QCOM_ICE_CRYPTO_ALG_AES_XTS, 173 QCOM_ICE_CRYPTO_KEY_SIZE_256, 174 cfg->crypto_key, 175 cfg->data_unit_size, slot); 176 else 177 return qcom_ice_evict_key(host->ice, slot); 178 } 179 180 #else 181 182 #define ufs_qcom_ice_program_key NULL 183 184 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host) 185 { 186 } 187 188 static int ufs_qcom_ice_init(struct ufs_qcom_host *host) 189 { 190 return 0; 191 } 192 193 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host) 194 { 195 return 0; 196 } 197 198 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host) 199 { 200 return 0; 201 } 202 #endif 203 204 static int ufs_qcom_host_clk_get(struct device *dev, 205 const char *name, struct clk **clk_out, bool optional) 206 { 207 struct clk *clk; 208 int err = 0; 209 210 clk = devm_clk_get(dev, name); 211 if (!IS_ERR(clk)) { 212 *clk_out = clk; 213 return 0; 214 } 215 216 err = PTR_ERR(clk); 217 218 if (optional && err == -ENOENT) { 219 *clk_out = NULL; 220 return 0; 221 } 222 223 if (err != -EPROBE_DEFER) 224 dev_err(dev, "failed to get %s err %d\n", name, err); 225 226 return err; 227 } 228 229 static int ufs_qcom_host_clk_enable(struct device *dev, 230 const char *name, struct clk *clk) 231 { 232 int err = 0; 233 234 err = clk_prepare_enable(clk); 235 if (err) 236 dev_err(dev, "%s: %s enable failed %d\n", __func__, name, err); 237 238 return err; 239 } 240 241 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host) 242 { 243 if (!host->is_lane_clks_enabled) 244 return; 245 246 clk_disable_unprepare(host->tx_l1_sync_clk); 247 clk_disable_unprepare(host->tx_l0_sync_clk); 248 clk_disable_unprepare(host->rx_l1_sync_clk); 249 clk_disable_unprepare(host->rx_l0_sync_clk); 250 251 host->is_lane_clks_enabled = false; 252 } 253 254 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host) 255 { 256 int err; 257 struct device *dev = host->hba->dev; 258 259 if (host->is_lane_clks_enabled) 260 return 0; 261 262 err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk", 263 host->rx_l0_sync_clk); 264 if (err) 265 return err; 266 267 err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk", 268 host->tx_l0_sync_clk); 269 if (err) 270 goto disable_rx_l0; 271 272 err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk", 273 host->rx_l1_sync_clk); 274 if (err) 275 goto disable_tx_l0; 276 277 err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk", 278 host->tx_l1_sync_clk); 279 if (err) 280 goto disable_rx_l1; 281 282 host->is_lane_clks_enabled = true; 283 284 return 0; 285 286 disable_rx_l1: 287 clk_disable_unprepare(host->rx_l1_sync_clk); 288 disable_tx_l0: 289 clk_disable_unprepare(host->tx_l0_sync_clk); 290 disable_rx_l0: 291 clk_disable_unprepare(host->rx_l0_sync_clk); 292 293 return err; 294 } 295 296 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host) 297 { 298 int err = 0; 299 struct device *dev = host->hba->dev; 300 301 if (has_acpi_companion(dev)) 302 return 0; 303 304 err = ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk", 305 &host->rx_l0_sync_clk, false); 306 if (err) 307 return err; 308 309 err = ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk", 310 &host->tx_l0_sync_clk, false); 311 if (err) 312 return err; 313 314 /* In case of single lane per direction, don't read lane1 clocks */ 315 if (host->hba->lanes_per_direction > 1) { 316 err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk", 317 &host->rx_l1_sync_clk, false); 318 if (err) 319 return err; 320 321 err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk", 322 &host->tx_l1_sync_clk, true); 323 } 324 325 return 0; 326 } 327 328 static int ufs_qcom_check_hibern8(struct ufs_hba *hba) 329 { 330 int err; 331 u32 tx_fsm_val = 0; 332 unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS); 333 334 do { 335 err = ufshcd_dme_get(hba, 336 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 337 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 338 &tx_fsm_val); 339 if (err || tx_fsm_val == TX_FSM_HIBERN8) 340 break; 341 342 /* sleep for max. 200us */ 343 usleep_range(100, 200); 344 } while (time_before(jiffies, timeout)); 345 346 /* 347 * we might have scheduled out for long during polling so 348 * check the state again. 349 */ 350 if (time_after(jiffies, timeout)) 351 err = ufshcd_dme_get(hba, 352 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 353 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 354 &tx_fsm_val); 355 356 if (err) { 357 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n", 358 __func__, err); 359 } else if (tx_fsm_val != TX_FSM_HIBERN8) { 360 err = tx_fsm_val; 361 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n", 362 __func__, err); 363 } 364 365 return err; 366 } 367 368 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host) 369 { 370 ufshcd_rmwl(host->hba, QUNIPRO_SEL, 371 ufs_qcom_cap_qunipro(host) ? QUNIPRO_SEL : 0, 372 REG_UFS_CFG1); 373 374 if (host->hw_ver.major >= 0x05) 375 ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0); 376 } 377 378 /* 379 * ufs_qcom_host_reset - reset host controller and PHY 380 */ 381 static int ufs_qcom_host_reset(struct ufs_hba *hba) 382 { 383 int ret = 0; 384 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 385 bool reenable_intr = false; 386 387 if (!host->core_reset) { 388 dev_warn(hba->dev, "%s: reset control not set\n", __func__); 389 return 0; 390 } 391 392 reenable_intr = hba->is_irq_enabled; 393 disable_irq(hba->irq); 394 hba->is_irq_enabled = false; 395 396 ret = reset_control_assert(host->core_reset); 397 if (ret) { 398 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n", 399 __func__, ret); 400 return ret; 401 } 402 403 /* 404 * The hardware requirement for delay between assert/deassert 405 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to 406 * ~125us (4/32768). To be on the safe side add 200us delay. 407 */ 408 usleep_range(200, 210); 409 410 ret = reset_control_deassert(host->core_reset); 411 if (ret) 412 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n", 413 __func__, ret); 414 415 usleep_range(1000, 1100); 416 417 if (reenable_intr) { 418 enable_irq(hba->irq); 419 hba->is_irq_enabled = true; 420 } 421 422 return 0; 423 } 424 425 static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) 426 { 427 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 428 429 if (host->hw_ver.major == 0x1) { 430 /* 431 * HS-G3 operations may not reliably work on legacy QCOM 432 * UFS host controller hardware even though capability 433 * exchange during link startup phase may end up 434 * negotiating maximum supported gear as G3. 435 * Hence downgrade the maximum supported gear to HS-G2. 436 */ 437 return UFS_HS_G2; 438 } else if (host->hw_ver.major >= 0x4) { 439 return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0)); 440 } 441 442 /* Default is HS-G3 */ 443 return UFS_HS_G3; 444 } 445 446 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) 447 { 448 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 449 struct phy *phy = host->generic_phy; 450 int ret; 451 452 /* Reset UFS Host Controller and PHY */ 453 ret = ufs_qcom_host_reset(hba); 454 if (ret) 455 dev_warn(hba->dev, "%s: host reset returned %d\n", 456 __func__, ret); 457 458 /* phy initialization - calibrate the phy */ 459 ret = phy_init(phy); 460 if (ret) { 461 dev_err(hba->dev, "%s: phy init failed, ret = %d\n", 462 __func__, ret); 463 return ret; 464 } 465 466 phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->hs_gear); 467 468 /* power on phy - start serdes and phy's power and clocks */ 469 ret = phy_power_on(phy); 470 if (ret) { 471 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n", 472 __func__, ret); 473 goto out_disable_phy; 474 } 475 476 ufs_qcom_select_unipro_mode(host); 477 478 return 0; 479 480 out_disable_phy: 481 phy_exit(phy); 482 483 return ret; 484 } 485 486 /* 487 * The UTP controller has a number of internal clock gating cells (CGCs). 488 * Internal hardware sub-modules within the UTP controller control the CGCs. 489 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved 490 * in a specific operation, UTP controller CGCs are by default disabled and 491 * this function enables them (after every UFS link startup) to save some power 492 * leakage. 493 */ 494 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba) 495 { 496 ufshcd_writel(hba, 497 ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL, 498 REG_UFS_CFG2); 499 500 /* Ensure that HW clock gating is enabled before next operations */ 501 ufshcd_readl(hba, REG_UFS_CFG2); 502 } 503 504 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba, 505 enum ufs_notify_change_status status) 506 { 507 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 508 int err = 0; 509 510 switch (status) { 511 case PRE_CHANGE: 512 ufs_qcom_power_up_sequence(hba); 513 /* 514 * The PHY PLL output is the source of tx/rx lane symbol 515 * clocks, hence, enable the lane clocks only after PHY 516 * is initialized. 517 */ 518 err = ufs_qcom_enable_lane_clks(host); 519 break; 520 case POST_CHANGE: 521 /* check if UFS PHY moved from DISABLED to HIBERN8 */ 522 err = ufs_qcom_check_hibern8(hba); 523 ufs_qcom_enable_hw_clk_gating(hba); 524 ufs_qcom_ice_enable(host); 525 break; 526 default: 527 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status); 528 err = -EINVAL; 529 break; 530 } 531 return err; 532 } 533 534 /* 535 * Return: zero for success and non-zero in case of a failure. 536 */ 537 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, 538 u32 hs, u32 rate, bool update_link_startup_timer) 539 { 540 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 541 struct ufs_clk_info *clki; 542 u32 core_clk_period_in_ns; 543 u32 tx_clk_cycles_per_us = 0; 544 unsigned long core_clk_rate = 0; 545 u32 core_clk_cycles_per_us = 0; 546 547 static u32 pwm_fr_table[][2] = { 548 {UFS_PWM_G1, 0x1}, 549 {UFS_PWM_G2, 0x1}, 550 {UFS_PWM_G3, 0x1}, 551 {UFS_PWM_G4, 0x1}, 552 }; 553 554 static u32 hs_fr_table_rA[][2] = { 555 {UFS_HS_G1, 0x1F}, 556 {UFS_HS_G2, 0x3e}, 557 {UFS_HS_G3, 0x7D}, 558 }; 559 560 static u32 hs_fr_table_rB[][2] = { 561 {UFS_HS_G1, 0x24}, 562 {UFS_HS_G2, 0x49}, 563 {UFS_HS_G3, 0x92}, 564 }; 565 566 /* 567 * The Qunipro controller does not use following registers: 568 * SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG & 569 * UFS_REG_PA_LINK_STARTUP_TIMER 570 * But UTP controller uses SYS1CLK_1US_REG register for Interrupt 571 * Aggregation logic. 572 */ 573 if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba)) 574 return 0; 575 576 if (gear == 0) { 577 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear); 578 return -EINVAL; 579 } 580 581 list_for_each_entry(clki, &hba->clk_list_head, list) { 582 if (!strcmp(clki->name, "core_clk")) 583 core_clk_rate = clk_get_rate(clki->clk); 584 } 585 586 /* If frequency is smaller than 1MHz, set to 1MHz */ 587 if (core_clk_rate < DEFAULT_CLK_RATE_HZ) 588 core_clk_rate = DEFAULT_CLK_RATE_HZ; 589 590 core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC; 591 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) { 592 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US); 593 /* 594 * make sure above write gets applied before we return from 595 * this function. 596 */ 597 ufshcd_readl(hba, REG_UFS_SYS1CLK_1US); 598 } 599 600 if (ufs_qcom_cap_qunipro(host)) 601 return 0; 602 603 core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate; 604 core_clk_period_in_ns <<= OFFSET_CLK_NS_REG; 605 core_clk_period_in_ns &= MASK_CLK_NS_REG; 606 607 switch (hs) { 608 case FASTAUTO_MODE: 609 case FAST_MODE: 610 if (rate == PA_HS_MODE_A) { 611 if (gear > ARRAY_SIZE(hs_fr_table_rA)) { 612 dev_err(hba->dev, 613 "%s: index %d exceeds table size %zu\n", 614 __func__, gear, 615 ARRAY_SIZE(hs_fr_table_rA)); 616 return -EINVAL; 617 } 618 tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1]; 619 } else if (rate == PA_HS_MODE_B) { 620 if (gear > ARRAY_SIZE(hs_fr_table_rB)) { 621 dev_err(hba->dev, 622 "%s: index %d exceeds table size %zu\n", 623 __func__, gear, 624 ARRAY_SIZE(hs_fr_table_rB)); 625 return -EINVAL; 626 } 627 tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1]; 628 } else { 629 dev_err(hba->dev, "%s: invalid rate = %d\n", 630 __func__, rate); 631 return -EINVAL; 632 } 633 break; 634 case SLOWAUTO_MODE: 635 case SLOW_MODE: 636 if (gear > ARRAY_SIZE(pwm_fr_table)) { 637 dev_err(hba->dev, 638 "%s: index %d exceeds table size %zu\n", 639 __func__, gear, 640 ARRAY_SIZE(pwm_fr_table)); 641 return -EINVAL; 642 } 643 tx_clk_cycles_per_us = pwm_fr_table[gear-1][1]; 644 break; 645 case UNCHANGED: 646 default: 647 dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs); 648 return -EINVAL; 649 } 650 651 if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) != 652 (core_clk_period_in_ns | tx_clk_cycles_per_us)) { 653 /* this register 2 fields shall be written at once */ 654 ufshcd_writel(hba, core_clk_period_in_ns | tx_clk_cycles_per_us, 655 REG_UFS_TX_SYMBOL_CLK_NS_US); 656 /* 657 * make sure above write gets applied before we return from 658 * this function. 659 */ 660 mb(); 661 } 662 663 if (update_link_startup_timer && host->hw_ver.major != 0x5) { 664 ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100), 665 REG_UFS_CFG0); 666 /* 667 * make sure that this configuration is applied before 668 * we return 669 */ 670 mb(); 671 } 672 673 return 0; 674 } 675 676 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, 677 enum ufs_notify_change_status status) 678 { 679 int err = 0; 680 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 681 682 switch (status) { 683 case PRE_CHANGE: 684 if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE, 685 0, true)) { 686 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", 687 __func__); 688 return -EINVAL; 689 } 690 691 if (ufs_qcom_cap_qunipro(host)) 692 /* 693 * set unipro core clock cycles to 150 & clear clock 694 * divider 695 */ 696 err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 697 150); 698 699 /* 700 * Some UFS devices (and may be host) have issues if LCC is 701 * enabled. So we are setting PA_Local_TX_LCC_Enable to 0 702 * before link startup which will make sure that both host 703 * and device TX LCC are disabled once link startup is 704 * completed. 705 */ 706 if (ufshcd_get_local_unipro_ver(hba) != UFS_UNIPRO_VER_1_41) 707 err = ufshcd_disable_host_tx_lcc(hba); 708 709 break; 710 default: 711 break; 712 } 713 714 return err; 715 } 716 717 static void ufs_qcom_device_reset_ctrl(struct ufs_hba *hba, bool asserted) 718 { 719 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 720 721 /* reset gpio is optional */ 722 if (!host->device_reset) 723 return; 724 725 gpiod_set_value_cansleep(host->device_reset, asserted); 726 } 727 728 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, 729 enum ufs_notify_change_status status) 730 { 731 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 732 struct phy *phy = host->generic_phy; 733 734 if (status == PRE_CHANGE) 735 return 0; 736 737 if (ufs_qcom_is_link_off(hba)) { 738 /* 739 * Disable the tx/rx lane symbol clocks before PHY is 740 * powered down as the PLL source should be disabled 741 * after downstream clocks are disabled. 742 */ 743 ufs_qcom_disable_lane_clks(host); 744 phy_power_off(phy); 745 746 /* reset the connected UFS device during power down */ 747 ufs_qcom_device_reset_ctrl(hba, true); 748 749 } else if (!ufs_qcom_is_link_active(hba)) { 750 ufs_qcom_disable_lane_clks(host); 751 } 752 753 return ufs_qcom_ice_suspend(host); 754 } 755 756 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) 757 { 758 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 759 struct phy *phy = host->generic_phy; 760 int err; 761 762 if (ufs_qcom_is_link_off(hba)) { 763 err = phy_power_on(phy); 764 if (err) { 765 dev_err(hba->dev, "%s: failed PHY power on: %d\n", 766 __func__, err); 767 return err; 768 } 769 770 err = ufs_qcom_enable_lane_clks(host); 771 if (err) 772 return err; 773 774 } else if (!ufs_qcom_is_link_active(hba)) { 775 err = ufs_qcom_enable_lane_clks(host); 776 if (err) 777 return err; 778 } 779 780 return ufs_qcom_ice_resume(host); 781 } 782 783 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable) 784 { 785 if (host->dev_ref_clk_ctrl_mmio && 786 (enable ^ host->is_dev_ref_clk_enabled)) { 787 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio); 788 789 if (enable) 790 temp |= host->dev_ref_clk_en_mask; 791 else 792 temp &= ~host->dev_ref_clk_en_mask; 793 794 /* 795 * If we are here to disable this clock it might be immediately 796 * after entering into hibern8 in which case we need to make 797 * sure that device ref_clk is active for specific time after 798 * hibern8 enter. 799 */ 800 if (!enable) { 801 unsigned long gating_wait; 802 803 gating_wait = host->hba->dev_info.clk_gating_wait_us; 804 if (!gating_wait) { 805 udelay(1); 806 } else { 807 /* 808 * bRefClkGatingWaitTime defines the minimum 809 * time for which the reference clock is 810 * required by device during transition from 811 * HS-MODE to LS-MODE or HIBERN8 state. Give it 812 * more delay to be on the safe side. 813 */ 814 gating_wait += 10; 815 usleep_range(gating_wait, gating_wait + 10); 816 } 817 } 818 819 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio); 820 821 /* 822 * Make sure the write to ref_clk reaches the destination and 823 * not stored in a Write Buffer (WB). 824 */ 825 readl(host->dev_ref_clk_ctrl_mmio); 826 827 /* 828 * If we call hibern8 exit after this, we need to make sure that 829 * device ref_clk is stable for at least 1us before the hibern8 830 * exit command. 831 */ 832 if (enable) 833 udelay(1); 834 835 host->is_dev_ref_clk_enabled = enable; 836 } 837 } 838 839 static int ufs_qcom_icc_set_bw(struct ufs_qcom_host *host, u32 mem_bw, u32 cfg_bw) 840 { 841 struct device *dev = host->hba->dev; 842 int ret; 843 844 ret = icc_set_bw(host->icc_ddr, 0, mem_bw); 845 if (ret < 0) { 846 dev_err(dev, "failed to set bandwidth request: %d\n", ret); 847 return ret; 848 } 849 850 ret = icc_set_bw(host->icc_cpu, 0, cfg_bw); 851 if (ret < 0) { 852 dev_err(dev, "failed to set bandwidth request: %d\n", ret); 853 return ret; 854 } 855 856 return 0; 857 } 858 859 static struct __ufs_qcom_bw_table ufs_qcom_get_bw_table(struct ufs_qcom_host *host) 860 { 861 struct ufs_pa_layer_attr *p = &host->dev_req_params; 862 int gear = max_t(u32, p->gear_rx, p->gear_tx); 863 int lane = max_t(u32, p->lane_rx, p->lane_tx); 864 865 if (ufshcd_is_hs_mode(p)) { 866 if (p->hs_rate == PA_HS_MODE_B) 867 return ufs_qcom_bw_table[MODE_HS_RB][gear][lane]; 868 else 869 return ufs_qcom_bw_table[MODE_HS_RA][gear][lane]; 870 } else { 871 return ufs_qcom_bw_table[MODE_PWM][gear][lane]; 872 } 873 } 874 875 static int ufs_qcom_icc_update_bw(struct ufs_qcom_host *host) 876 { 877 struct __ufs_qcom_bw_table bw_table; 878 879 bw_table = ufs_qcom_get_bw_table(host); 880 881 return ufs_qcom_icc_set_bw(host, bw_table.mem_bw, bw_table.cfg_bw); 882 } 883 884 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, 885 enum ufs_notify_change_status status, 886 struct ufs_pa_layer_attr *dev_max_params, 887 struct ufs_pa_layer_attr *dev_req_params) 888 { 889 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 890 struct ufs_dev_params ufs_qcom_cap; 891 int ret = 0; 892 893 if (!dev_req_params) { 894 pr_err("%s: incoming dev_req_params is NULL\n", __func__); 895 return -EINVAL; 896 } 897 898 switch (status) { 899 case PRE_CHANGE: 900 ufshcd_init_pwr_dev_param(&ufs_qcom_cap); 901 ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE; 902 903 /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */ 904 ufs_qcom_cap.hs_tx_gear = ufs_qcom_cap.hs_rx_gear = ufs_qcom_get_hs_gear(hba); 905 906 ret = ufshcd_get_pwr_dev_param(&ufs_qcom_cap, 907 dev_max_params, 908 dev_req_params); 909 if (ret) { 910 dev_err(hba->dev, "%s: failed to determine capabilities\n", 911 __func__); 912 return ret; 913 } 914 915 /* 916 * Update hs_gear only when the gears are scaled to a higher value. This is because, 917 * the PHY gear settings are backwards compatible and we only need to change the PHY 918 * settings while scaling to higher gears. 919 */ 920 if (dev_req_params->gear_tx > host->hs_gear) 921 host->hs_gear = dev_req_params->gear_tx; 922 923 /* enable the device ref clock before changing to HS mode */ 924 if (!ufshcd_is_hs_mode(&hba->pwr_info) && 925 ufshcd_is_hs_mode(dev_req_params)) 926 ufs_qcom_dev_ref_clk_ctrl(host, true); 927 928 if (host->hw_ver.major >= 0x4) { 929 ufshcd_dme_configure_adapt(hba, 930 dev_req_params->gear_tx, 931 PA_INITIAL_ADAPT); 932 } 933 break; 934 case POST_CHANGE: 935 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx, 936 dev_req_params->pwr_rx, 937 dev_req_params->hs_rate, false)) { 938 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", 939 __func__); 940 /* 941 * we return error code at the end of the routine, 942 * but continue to configure UFS_PHY_TX_LANE_ENABLE 943 * and bus voting as usual 944 */ 945 ret = -EINVAL; 946 } 947 948 /* cache the power mode parameters to use internally */ 949 memcpy(&host->dev_req_params, 950 dev_req_params, sizeof(*dev_req_params)); 951 952 ufs_qcom_icc_update_bw(host); 953 954 /* disable the device ref clock if entered PWM mode */ 955 if (ufshcd_is_hs_mode(&hba->pwr_info) && 956 !ufshcd_is_hs_mode(dev_req_params)) 957 ufs_qcom_dev_ref_clk_ctrl(host, false); 958 break; 959 default: 960 ret = -EINVAL; 961 break; 962 } 963 964 return ret; 965 } 966 967 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba) 968 { 969 int err; 970 u32 pa_vs_config_reg1; 971 972 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), 973 &pa_vs_config_reg1); 974 if (err) 975 return err; 976 977 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */ 978 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), 979 (pa_vs_config_reg1 | (1 << 12))); 980 } 981 982 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba) 983 { 984 int err = 0; 985 986 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME) 987 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba); 988 989 if (hba->dev_info.wmanufacturerid == UFS_VENDOR_WDC) 990 hba->dev_quirks |= UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE; 991 992 return err; 993 } 994 995 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba) 996 { 997 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 998 999 if (host->hw_ver.major == 0x1) 1000 return ufshci_version(1, 1); 1001 else 1002 return ufshci_version(2, 0); 1003 } 1004 1005 /** 1006 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks 1007 * @hba: host controller instance 1008 * 1009 * QCOM UFS host controller might have some non standard behaviours (quirks) 1010 * than what is specified by UFSHCI specification. Advertise all such 1011 * quirks to standard UFS host controller driver so standard takes them into 1012 * account. 1013 */ 1014 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba) 1015 { 1016 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1017 1018 if (host->hw_ver.major == 0x01) { 1019 hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS 1020 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP 1021 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE; 1022 1023 if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001) 1024 hba->quirks |= UFSHCD_QUIRK_BROKEN_INTR_AGGR; 1025 1026 hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC; 1027 } 1028 1029 if (host->hw_ver.major == 0x2) { 1030 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION; 1031 1032 if (!ufs_qcom_cap_qunipro(host)) 1033 /* Legacy UniPro mode still need following quirks */ 1034 hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS 1035 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE 1036 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP); 1037 } 1038 1039 if (host->hw_ver.major > 0x3) 1040 hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; 1041 } 1042 1043 static void ufs_qcom_set_caps(struct ufs_hba *hba) 1044 { 1045 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1046 1047 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; 1048 hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING; 1049 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND; 1050 hba->caps |= UFSHCD_CAP_WB_EN; 1051 hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE; 1052 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND; 1053 1054 if (host->hw_ver.major >= 0x2) { 1055 host->caps = UFS_QCOM_CAP_QUNIPRO | 1056 UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE; 1057 } 1058 } 1059 1060 /** 1061 * ufs_qcom_setup_clocks - enables/disable clocks 1062 * @hba: host controller instance 1063 * @on: If true, enable clocks else disable them. 1064 * @status: PRE_CHANGE or POST_CHANGE notify 1065 * 1066 * Return: 0 on success, non-zero on failure. 1067 */ 1068 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, 1069 enum ufs_notify_change_status status) 1070 { 1071 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1072 1073 /* 1074 * In case ufs_qcom_init() is not yet done, simply ignore. 1075 * This ufs_qcom_setup_clocks() shall be called from 1076 * ufs_qcom_init() after init is done. 1077 */ 1078 if (!host) 1079 return 0; 1080 1081 switch (status) { 1082 case PRE_CHANGE: 1083 if (on) { 1084 ufs_qcom_icc_update_bw(host); 1085 } else { 1086 if (!ufs_qcom_is_link_active(hba)) { 1087 /* disable device ref_clk */ 1088 ufs_qcom_dev_ref_clk_ctrl(host, false); 1089 } 1090 } 1091 break; 1092 case POST_CHANGE: 1093 if (on) { 1094 /* enable the device ref clock for HS mode*/ 1095 if (ufshcd_is_hs_mode(&hba->pwr_info)) 1096 ufs_qcom_dev_ref_clk_ctrl(host, true); 1097 } else { 1098 ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MIN][0][0].mem_bw, 1099 ufs_qcom_bw_table[MODE_MIN][0][0].cfg_bw); 1100 } 1101 break; 1102 } 1103 1104 return 0; 1105 } 1106 1107 static int 1108 ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) 1109 { 1110 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); 1111 1112 ufs_qcom_assert_reset(host->hba); 1113 /* provide 1ms delay to let the reset pulse propagate. */ 1114 usleep_range(1000, 1100); 1115 return 0; 1116 } 1117 1118 static int 1119 ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) 1120 { 1121 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); 1122 1123 ufs_qcom_deassert_reset(host->hba); 1124 1125 /* 1126 * after reset deassertion, phy will need all ref clocks, 1127 * voltage, current to settle down before starting serdes. 1128 */ 1129 usleep_range(1000, 1100); 1130 return 0; 1131 } 1132 1133 static const struct reset_control_ops ufs_qcom_reset_ops = { 1134 .assert = ufs_qcom_reset_assert, 1135 .deassert = ufs_qcom_reset_deassert, 1136 }; 1137 1138 static int ufs_qcom_icc_init(struct ufs_qcom_host *host) 1139 { 1140 struct device *dev = host->hba->dev; 1141 int ret; 1142 1143 host->icc_ddr = devm_of_icc_get(dev, "ufs-ddr"); 1144 if (IS_ERR(host->icc_ddr)) 1145 return dev_err_probe(dev, PTR_ERR(host->icc_ddr), 1146 "failed to acquire interconnect path\n"); 1147 1148 host->icc_cpu = devm_of_icc_get(dev, "cpu-ufs"); 1149 if (IS_ERR(host->icc_cpu)) 1150 return dev_err_probe(dev, PTR_ERR(host->icc_cpu), 1151 "failed to acquire interconnect path\n"); 1152 1153 /* 1154 * Set Maximum bandwidth vote before initializing the UFS controller and 1155 * device. Ideally, a minimal interconnect vote would suffice for the 1156 * initialization, but a max vote would allow faster initialization. 1157 */ 1158 ret = ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MAX][0][0].mem_bw, 1159 ufs_qcom_bw_table[MODE_MAX][0][0].cfg_bw); 1160 if (ret < 0) 1161 return dev_err_probe(dev, ret, "failed to set bandwidth request\n"); 1162 1163 return 0; 1164 } 1165 1166 /** 1167 * ufs_qcom_init - bind phy with controller 1168 * @hba: host controller instance 1169 * 1170 * Binds PHY with controller and powers up PHY enabling clocks 1171 * and regulators. 1172 * 1173 * Return: -EPROBE_DEFER if binding fails, returns negative error 1174 * on phy power up failure and returns zero on success. 1175 */ 1176 static int ufs_qcom_init(struct ufs_hba *hba) 1177 { 1178 int err; 1179 struct device *dev = hba->dev; 1180 struct platform_device *pdev = to_platform_device(dev); 1181 struct ufs_qcom_host *host; 1182 struct resource *res; 1183 struct ufs_clk_info *clki; 1184 1185 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); 1186 if (!host) { 1187 dev_err(dev, "%s: no memory for qcom ufs host\n", __func__); 1188 return -ENOMEM; 1189 } 1190 1191 /* Make a two way bind between the qcom host and the hba */ 1192 host->hba = hba; 1193 ufshcd_set_variant(hba, host); 1194 1195 /* Setup the optional reset control of HCI */ 1196 host->core_reset = devm_reset_control_get_optional(hba->dev, "rst"); 1197 if (IS_ERR(host->core_reset)) { 1198 err = dev_err_probe(dev, PTR_ERR(host->core_reset), 1199 "Failed to get reset control\n"); 1200 goto out_variant_clear; 1201 } 1202 1203 /* Fire up the reset controller. Failure here is non-fatal. */ 1204 host->rcdev.of_node = dev->of_node; 1205 host->rcdev.ops = &ufs_qcom_reset_ops; 1206 host->rcdev.owner = dev->driver->owner; 1207 host->rcdev.nr_resets = 1; 1208 err = devm_reset_controller_register(dev, &host->rcdev); 1209 if (err) 1210 dev_warn(dev, "Failed to register reset controller\n"); 1211 1212 if (!has_acpi_companion(dev)) { 1213 host->generic_phy = devm_phy_get(dev, "ufsphy"); 1214 if (IS_ERR(host->generic_phy)) { 1215 err = dev_err_probe(dev, PTR_ERR(host->generic_phy), "Failed to get PHY\n"); 1216 goto out_variant_clear; 1217 } 1218 } 1219 1220 err = ufs_qcom_icc_init(host); 1221 if (err) 1222 goto out_variant_clear; 1223 1224 host->device_reset = devm_gpiod_get_optional(dev, "reset", 1225 GPIOD_OUT_HIGH); 1226 if (IS_ERR(host->device_reset)) { 1227 err = PTR_ERR(host->device_reset); 1228 if (err != -EPROBE_DEFER) 1229 dev_err(dev, "failed to acquire reset gpio: %d\n", err); 1230 goto out_variant_clear; 1231 } 1232 1233 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major, 1234 &host->hw_ver.minor, &host->hw_ver.step); 1235 1236 /* 1237 * for newer controllers, device reference clock control bit has 1238 * moved inside UFS controller register address space itself. 1239 */ 1240 if (host->hw_ver.major >= 0x02) { 1241 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1; 1242 host->dev_ref_clk_en_mask = BIT(26); 1243 } else { 1244 /* "dev_ref_clk_ctrl_mem" is optional resource */ 1245 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1246 "dev_ref_clk_ctrl_mem"); 1247 if (res) { 1248 host->dev_ref_clk_ctrl_mmio = 1249 devm_ioremap_resource(dev, res); 1250 if (IS_ERR(host->dev_ref_clk_ctrl_mmio)) 1251 host->dev_ref_clk_ctrl_mmio = NULL; 1252 host->dev_ref_clk_en_mask = BIT(5); 1253 } 1254 } 1255 1256 list_for_each_entry(clki, &hba->clk_list_head, list) { 1257 if (!strcmp(clki->name, "core_clk_unipro")) 1258 clki->keep_link_active = true; 1259 } 1260 1261 err = ufs_qcom_init_lane_clks(host); 1262 if (err) 1263 goto out_variant_clear; 1264 1265 ufs_qcom_set_caps(hba); 1266 ufs_qcom_advertise_quirks(hba); 1267 1268 err = ufs_qcom_ice_init(host); 1269 if (err) 1270 goto out_variant_clear; 1271 1272 ufs_qcom_setup_clocks(hba, true, POST_CHANGE); 1273 1274 if (hba->dev->id < MAX_UFS_QCOM_HOSTS) 1275 ufs_qcom_hosts[hba->dev->id] = host; 1276 1277 ufs_qcom_get_default_testbus_cfg(host); 1278 err = ufs_qcom_testbus_config(host); 1279 if (err) 1280 /* Failure is non-fatal */ 1281 dev_warn(dev, "%s: failed to configure the testbus %d\n", 1282 __func__, err); 1283 1284 /* 1285 * Power up the PHY using the minimum supported gear (UFS_HS_G2). 1286 * Switching to max gear will be performed during reinit if supported. 1287 */ 1288 host->hs_gear = UFS_HS_G2; 1289 1290 return 0; 1291 1292 out_variant_clear: 1293 ufshcd_set_variant(hba, NULL); 1294 1295 return err; 1296 } 1297 1298 static void ufs_qcom_exit(struct ufs_hba *hba) 1299 { 1300 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1301 1302 ufs_qcom_disable_lane_clks(host); 1303 phy_power_off(host->generic_phy); 1304 phy_exit(host->generic_phy); 1305 } 1306 1307 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba, 1308 u32 clk_cycles) 1309 { 1310 int err; 1311 u32 core_clk_ctrl_reg; 1312 1313 if (clk_cycles > DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK) 1314 return -EINVAL; 1315 1316 err = ufshcd_dme_get(hba, 1317 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1318 &core_clk_ctrl_reg); 1319 if (err) 1320 return err; 1321 1322 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK; 1323 core_clk_ctrl_reg |= clk_cycles; 1324 1325 /* Clear CORE_CLK_DIV_EN */ 1326 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; 1327 1328 return ufshcd_dme_set(hba, 1329 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1330 core_clk_ctrl_reg); 1331 } 1332 1333 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba) 1334 { 1335 /* nothing to do as of now */ 1336 return 0; 1337 } 1338 1339 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba) 1340 { 1341 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1342 1343 if (!ufs_qcom_cap_qunipro(host)) 1344 return 0; 1345 1346 /* set unipro core clock cycles to 150 and clear clock divider */ 1347 return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150); 1348 } 1349 1350 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba) 1351 { 1352 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1353 int err; 1354 u32 core_clk_ctrl_reg; 1355 1356 if (!ufs_qcom_cap_qunipro(host)) 1357 return 0; 1358 1359 err = ufshcd_dme_get(hba, 1360 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1361 &core_clk_ctrl_reg); 1362 1363 /* make sure CORE_CLK_DIV_EN is cleared */ 1364 if (!err && 1365 (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) { 1366 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; 1367 err = ufshcd_dme_set(hba, 1368 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1369 core_clk_ctrl_reg); 1370 } 1371 1372 return err; 1373 } 1374 1375 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba) 1376 { 1377 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1378 1379 if (!ufs_qcom_cap_qunipro(host)) 1380 return 0; 1381 1382 /* set unipro core clock cycles to 75 and clear clock divider */ 1383 return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 75); 1384 } 1385 1386 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, 1387 bool scale_up, enum ufs_notify_change_status status) 1388 { 1389 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1390 struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params; 1391 int err = 0; 1392 1393 /* check the host controller state before sending hibern8 cmd */ 1394 if (!ufshcd_is_hba_active(hba)) 1395 return 0; 1396 1397 if (status == PRE_CHANGE) { 1398 err = ufshcd_uic_hibern8_enter(hba); 1399 if (err) 1400 return err; 1401 if (scale_up) 1402 err = ufs_qcom_clk_scale_up_pre_change(hba); 1403 else 1404 err = ufs_qcom_clk_scale_down_pre_change(hba); 1405 1406 if (err) { 1407 ufshcd_uic_hibern8_exit(hba); 1408 return err; 1409 } 1410 } else { 1411 if (scale_up) 1412 err = ufs_qcom_clk_scale_up_post_change(hba); 1413 else 1414 err = ufs_qcom_clk_scale_down_post_change(hba); 1415 1416 1417 if (err) { 1418 ufshcd_uic_hibern8_exit(hba); 1419 return err; 1420 } 1421 1422 ufs_qcom_cfg_timers(hba, 1423 dev_req_params->gear_rx, 1424 dev_req_params->pwr_rx, 1425 dev_req_params->hs_rate, 1426 false); 1427 ufs_qcom_icc_update_bw(host); 1428 ufshcd_uic_hibern8_exit(hba); 1429 } 1430 1431 return 0; 1432 } 1433 1434 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host) 1435 { 1436 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 1437 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1); 1438 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1); 1439 } 1440 1441 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host) 1442 { 1443 /* provide a legal default configuration */ 1444 host->testbus.select_major = TSTBUS_UNIPRO; 1445 host->testbus.select_minor = 37; 1446 } 1447 1448 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host) 1449 { 1450 if (host->testbus.select_major >= TSTBUS_MAX) { 1451 dev_err(host->hba->dev, 1452 "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n", 1453 __func__, host->testbus.select_major); 1454 return false; 1455 } 1456 1457 return true; 1458 } 1459 1460 int ufs_qcom_testbus_config(struct ufs_qcom_host *host) 1461 { 1462 int reg; 1463 int offset; 1464 u32 mask = TEST_BUS_SUB_SEL_MASK; 1465 1466 if (!host) 1467 return -EINVAL; 1468 1469 if (!ufs_qcom_testbus_cfg_is_ok(host)) 1470 return -EPERM; 1471 1472 switch (host->testbus.select_major) { 1473 case TSTBUS_UAWM: 1474 reg = UFS_TEST_BUS_CTRL_0; 1475 offset = 24; 1476 break; 1477 case TSTBUS_UARM: 1478 reg = UFS_TEST_BUS_CTRL_0; 1479 offset = 16; 1480 break; 1481 case TSTBUS_TXUC: 1482 reg = UFS_TEST_BUS_CTRL_0; 1483 offset = 8; 1484 break; 1485 case TSTBUS_RXUC: 1486 reg = UFS_TEST_BUS_CTRL_0; 1487 offset = 0; 1488 break; 1489 case TSTBUS_DFC: 1490 reg = UFS_TEST_BUS_CTRL_1; 1491 offset = 24; 1492 break; 1493 case TSTBUS_TRLUT: 1494 reg = UFS_TEST_BUS_CTRL_1; 1495 offset = 16; 1496 break; 1497 case TSTBUS_TMRLUT: 1498 reg = UFS_TEST_BUS_CTRL_1; 1499 offset = 8; 1500 break; 1501 case TSTBUS_OCSC: 1502 reg = UFS_TEST_BUS_CTRL_1; 1503 offset = 0; 1504 break; 1505 case TSTBUS_WRAPPER: 1506 reg = UFS_TEST_BUS_CTRL_2; 1507 offset = 16; 1508 break; 1509 case TSTBUS_COMBINED: 1510 reg = UFS_TEST_BUS_CTRL_2; 1511 offset = 8; 1512 break; 1513 case TSTBUS_UTP_HCI: 1514 reg = UFS_TEST_BUS_CTRL_2; 1515 offset = 0; 1516 break; 1517 case TSTBUS_UNIPRO: 1518 reg = UFS_UNIPRO_CFG; 1519 offset = 20; 1520 mask = 0xFFF; 1521 break; 1522 /* 1523 * No need for a default case, since 1524 * ufs_qcom_testbus_cfg_is_ok() checks that the configuration 1525 * is legal 1526 */ 1527 } 1528 mask <<= offset; 1529 ufshcd_rmwl(host->hba, TEST_BUS_SEL, 1530 (u32)host->testbus.select_major << 19, 1531 REG_UFS_CFG1); 1532 ufshcd_rmwl(host->hba, mask, 1533 (u32)host->testbus.select_minor << offset, 1534 reg); 1535 ufs_qcom_enable_test_bus(host); 1536 /* 1537 * Make sure the test bus configuration is 1538 * committed before returning. 1539 */ 1540 mb(); 1541 1542 return 0; 1543 } 1544 1545 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba) 1546 { 1547 u32 reg; 1548 struct ufs_qcom_host *host; 1549 1550 host = ufshcd_get_variant(hba); 1551 1552 ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4, 1553 "HCI Vendor Specific Registers "); 1554 1555 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC); 1556 ufshcd_dump_regs(hba, reg, 44 * 4, "UFS_UFS_DBG_RD_REG_OCSC "); 1557 1558 reg = ufshcd_readl(hba, REG_UFS_CFG1); 1559 reg |= UTP_DBG_RAMS_EN; 1560 ufshcd_writel(hba, reg, REG_UFS_CFG1); 1561 1562 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM); 1563 ufshcd_dump_regs(hba, reg, 32 * 4, "UFS_UFS_DBG_RD_EDTL_RAM "); 1564 1565 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM); 1566 ufshcd_dump_regs(hba, reg, 128 * 4, "UFS_UFS_DBG_RD_DESC_RAM "); 1567 1568 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM); 1569 ufshcd_dump_regs(hba, reg, 64 * 4, "UFS_UFS_DBG_RD_PRDT_RAM "); 1570 1571 /* clear bit 17 - UTP_DBG_RAMS_EN */ 1572 ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1); 1573 1574 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM); 1575 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UAWM "); 1576 1577 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM); 1578 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UARM "); 1579 1580 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC); 1581 ufshcd_dump_regs(hba, reg, 48 * 4, "UFS_DBG_RD_REG_TXUC "); 1582 1583 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC); 1584 ufshcd_dump_regs(hba, reg, 27 * 4, "UFS_DBG_RD_REG_RXUC "); 1585 1586 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC); 1587 ufshcd_dump_regs(hba, reg, 19 * 4, "UFS_DBG_RD_REG_DFC "); 1588 1589 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT); 1590 ufshcd_dump_regs(hba, reg, 34 * 4, "UFS_DBG_RD_REG_TRLUT "); 1591 1592 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT); 1593 ufshcd_dump_regs(hba, reg, 9 * 4, "UFS_DBG_RD_REG_TMRLUT "); 1594 } 1595 1596 /** 1597 * ufs_qcom_device_reset() - toggle the (optional) device reset line 1598 * @hba: per-adapter instance 1599 * 1600 * Toggles the (optional) reset line to reset the attached device. 1601 */ 1602 static int ufs_qcom_device_reset(struct ufs_hba *hba) 1603 { 1604 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1605 1606 /* reset gpio is optional */ 1607 if (!host->device_reset) 1608 return -EOPNOTSUPP; 1609 1610 /* 1611 * The UFS device shall detect reset pulses of 1us, sleep for 10us to 1612 * be on the safe side. 1613 */ 1614 ufs_qcom_device_reset_ctrl(hba, true); 1615 usleep_range(10, 15); 1616 1617 ufs_qcom_device_reset_ctrl(hba, false); 1618 usleep_range(10, 15); 1619 1620 return 0; 1621 } 1622 1623 #if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND) 1624 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba, 1625 struct devfreq_dev_profile *p, 1626 struct devfreq_simple_ondemand_data *d) 1627 { 1628 p->polling_ms = 60; 1629 p->timer = DEVFREQ_TIMER_DELAYED; 1630 d->upthreshold = 70; 1631 d->downdifferential = 5; 1632 } 1633 #else 1634 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba, 1635 struct devfreq_dev_profile *p, 1636 struct devfreq_simple_ondemand_data *data) 1637 { 1638 } 1639 #endif 1640 1641 static void ufs_qcom_reinit_notify(struct ufs_hba *hba) 1642 { 1643 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1644 1645 phy_power_off(host->generic_phy); 1646 } 1647 1648 /* Resources */ 1649 static const struct ufshcd_res_info ufs_res_info[RES_MAX] = { 1650 {.name = "ufs_mem",}, 1651 {.name = "mcq",}, 1652 /* Submission Queue DAO */ 1653 {.name = "mcq_sqd",}, 1654 /* Submission Queue Interrupt Status */ 1655 {.name = "mcq_sqis",}, 1656 /* Completion Queue DAO */ 1657 {.name = "mcq_cqd",}, 1658 /* Completion Queue Interrupt Status */ 1659 {.name = "mcq_cqis",}, 1660 /* MCQ vendor specific */ 1661 {.name = "mcq_vs",}, 1662 }; 1663 1664 static int ufs_qcom_mcq_config_resource(struct ufs_hba *hba) 1665 { 1666 struct platform_device *pdev = to_platform_device(hba->dev); 1667 struct ufshcd_res_info *res; 1668 struct resource *res_mem, *res_mcq; 1669 int i, ret = 0; 1670 1671 memcpy(hba->res, ufs_res_info, sizeof(ufs_res_info)); 1672 1673 for (i = 0; i < RES_MAX; i++) { 1674 res = &hba->res[i]; 1675 res->resource = platform_get_resource_byname(pdev, 1676 IORESOURCE_MEM, 1677 res->name); 1678 if (!res->resource) { 1679 dev_info(hba->dev, "Resource %s not provided\n", res->name); 1680 if (i == RES_UFS) 1681 return -ENODEV; 1682 continue; 1683 } else if (i == RES_UFS) { 1684 res_mem = res->resource; 1685 res->base = hba->mmio_base; 1686 continue; 1687 } 1688 1689 res->base = devm_ioremap_resource(hba->dev, res->resource); 1690 if (IS_ERR(res->base)) { 1691 dev_err(hba->dev, "Failed to map res %s, err=%d\n", 1692 res->name, (int)PTR_ERR(res->base)); 1693 ret = PTR_ERR(res->base); 1694 res->base = NULL; 1695 return ret; 1696 } 1697 } 1698 1699 /* MCQ resource provided in DT */ 1700 res = &hba->res[RES_MCQ]; 1701 /* Bail if MCQ resource is provided */ 1702 if (res->base) 1703 goto out; 1704 1705 /* Explicitly allocate MCQ resource from ufs_mem */ 1706 res_mcq = devm_kzalloc(hba->dev, sizeof(*res_mcq), GFP_KERNEL); 1707 if (!res_mcq) 1708 return -ENOMEM; 1709 1710 res_mcq->start = res_mem->start + 1711 MCQ_SQATTR_OFFSET(hba->mcq_capabilities); 1712 res_mcq->end = res_mcq->start + hba->nr_hw_queues * MCQ_QCFG_SIZE - 1; 1713 res_mcq->flags = res_mem->flags; 1714 res_mcq->name = "mcq"; 1715 1716 ret = insert_resource(&iomem_resource, res_mcq); 1717 if (ret) { 1718 dev_err(hba->dev, "Failed to insert MCQ resource, err=%d\n", 1719 ret); 1720 return ret; 1721 } 1722 1723 res->base = devm_ioremap_resource(hba->dev, res_mcq); 1724 if (IS_ERR(res->base)) { 1725 dev_err(hba->dev, "MCQ registers mapping failed, err=%d\n", 1726 (int)PTR_ERR(res->base)); 1727 ret = PTR_ERR(res->base); 1728 goto ioremap_err; 1729 } 1730 1731 out: 1732 hba->mcq_base = res->base; 1733 return 0; 1734 ioremap_err: 1735 res->base = NULL; 1736 remove_resource(res_mcq); 1737 return ret; 1738 } 1739 1740 static int ufs_qcom_op_runtime_config(struct ufs_hba *hba) 1741 { 1742 struct ufshcd_res_info *mem_res, *sqdao_res; 1743 struct ufshcd_mcq_opr_info_t *opr; 1744 int i; 1745 1746 mem_res = &hba->res[RES_UFS]; 1747 sqdao_res = &hba->res[RES_MCQ_SQD]; 1748 1749 if (!mem_res->base || !sqdao_res->base) 1750 return -EINVAL; 1751 1752 for (i = 0; i < OPR_MAX; i++) { 1753 opr = &hba->mcq_opr[i]; 1754 opr->offset = sqdao_res->resource->start - 1755 mem_res->resource->start + 0x40 * i; 1756 opr->stride = 0x100; 1757 opr->base = sqdao_res->base + 0x40 * i; 1758 } 1759 1760 return 0; 1761 } 1762 1763 static int ufs_qcom_get_hba_mac(struct ufs_hba *hba) 1764 { 1765 /* Qualcomm HC supports up to 64 */ 1766 return MAX_SUPP_MAC; 1767 } 1768 1769 static int ufs_qcom_get_outstanding_cqs(struct ufs_hba *hba, 1770 unsigned long *ocqs) 1771 { 1772 struct ufshcd_res_info *mcq_vs_res = &hba->res[RES_MCQ_VS]; 1773 1774 if (!mcq_vs_res->base) 1775 return -EINVAL; 1776 1777 *ocqs = readl(mcq_vs_res->base + UFS_MEM_CQIS_VS); 1778 1779 return 0; 1780 } 1781 1782 static void ufs_qcom_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg) 1783 { 1784 struct device *dev = msi_desc_to_dev(desc); 1785 struct ufs_hba *hba = dev_get_drvdata(dev); 1786 1787 ufshcd_mcq_config_esi(hba, msg); 1788 } 1789 1790 static irqreturn_t ufs_qcom_mcq_esi_handler(int irq, void *data) 1791 { 1792 struct msi_desc *desc = data; 1793 struct device *dev = msi_desc_to_dev(desc); 1794 struct ufs_hba *hba = dev_get_drvdata(dev); 1795 u32 id = desc->msi_index; 1796 struct ufs_hw_queue *hwq = &hba->uhq[id]; 1797 1798 ufshcd_mcq_write_cqis(hba, 0x1, id); 1799 ufshcd_mcq_poll_cqe_lock(hba, hwq); 1800 1801 return IRQ_HANDLED; 1802 } 1803 1804 static int ufs_qcom_config_esi(struct ufs_hba *hba) 1805 { 1806 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1807 struct msi_desc *desc; 1808 struct msi_desc *failed_desc = NULL; 1809 int nr_irqs, ret; 1810 1811 if (host->esi_enabled) 1812 return 0; 1813 1814 /* 1815 * 1. We only handle CQs as of now. 1816 * 2. Poll queues do not need ESI. 1817 */ 1818 nr_irqs = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; 1819 ret = platform_msi_domain_alloc_irqs(hba->dev, nr_irqs, 1820 ufs_qcom_write_msi_msg); 1821 if (ret) { 1822 dev_err(hba->dev, "Failed to request Platform MSI %d\n", ret); 1823 goto out; 1824 } 1825 1826 msi_lock_descs(hba->dev); 1827 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { 1828 ret = devm_request_irq(hba->dev, desc->irq, 1829 ufs_qcom_mcq_esi_handler, 1830 IRQF_SHARED, "qcom-mcq-esi", desc); 1831 if (ret) { 1832 dev_err(hba->dev, "%s: Fail to request IRQ for %d, err = %d\n", 1833 __func__, desc->irq, ret); 1834 failed_desc = desc; 1835 break; 1836 } 1837 } 1838 msi_unlock_descs(hba->dev); 1839 1840 if (ret) { 1841 /* Rewind */ 1842 msi_lock_descs(hba->dev); 1843 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { 1844 if (desc == failed_desc) 1845 break; 1846 devm_free_irq(hba->dev, desc->irq, hba); 1847 } 1848 msi_unlock_descs(hba->dev); 1849 platform_msi_domain_free_irqs(hba->dev); 1850 } else { 1851 if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 && 1852 host->hw_ver.step == 0) { 1853 ufshcd_writel(hba, 1854 ufshcd_readl(hba, REG_UFS_CFG3) | 0x1F000, 1855 REG_UFS_CFG3); 1856 } 1857 ufshcd_mcq_enable_esi(hba); 1858 } 1859 1860 out: 1861 if (!ret) 1862 host->esi_enabled = true; 1863 1864 return ret; 1865 } 1866 1867 /* 1868 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations 1869 * 1870 * The variant operations configure the necessary controller and PHY 1871 * handshake during initialization. 1872 */ 1873 static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = { 1874 .name = "qcom", 1875 .init = ufs_qcom_init, 1876 .exit = ufs_qcom_exit, 1877 .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version, 1878 .clk_scale_notify = ufs_qcom_clk_scale_notify, 1879 .setup_clocks = ufs_qcom_setup_clocks, 1880 .hce_enable_notify = ufs_qcom_hce_enable_notify, 1881 .link_startup_notify = ufs_qcom_link_startup_notify, 1882 .pwr_change_notify = ufs_qcom_pwr_change_notify, 1883 .apply_dev_quirks = ufs_qcom_apply_dev_quirks, 1884 .suspend = ufs_qcom_suspend, 1885 .resume = ufs_qcom_resume, 1886 .dbg_register_dump = ufs_qcom_dump_dbg_regs, 1887 .device_reset = ufs_qcom_device_reset, 1888 .config_scaling_param = ufs_qcom_config_scaling_param, 1889 .program_key = ufs_qcom_ice_program_key, 1890 .reinit_notify = ufs_qcom_reinit_notify, 1891 .mcq_config_resource = ufs_qcom_mcq_config_resource, 1892 .get_hba_mac = ufs_qcom_get_hba_mac, 1893 .op_runtime_config = ufs_qcom_op_runtime_config, 1894 .get_outstanding_cqs = ufs_qcom_get_outstanding_cqs, 1895 .config_esi = ufs_qcom_config_esi, 1896 }; 1897 1898 /** 1899 * ufs_qcom_probe - probe routine of the driver 1900 * @pdev: pointer to Platform device handle 1901 * 1902 * Return: zero for success and non-zero for failure. 1903 */ 1904 static int ufs_qcom_probe(struct platform_device *pdev) 1905 { 1906 int err; 1907 struct device *dev = &pdev->dev; 1908 1909 /* Perform generic probe */ 1910 err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops); 1911 if (err) 1912 return dev_err_probe(dev, err, "ufshcd_pltfrm_init() failed\n"); 1913 1914 return 0; 1915 } 1916 1917 /** 1918 * ufs_qcom_remove - set driver_data of the device to NULL 1919 * @pdev: pointer to platform device handle 1920 * 1921 * Always returns 0 1922 */ 1923 static int ufs_qcom_remove(struct platform_device *pdev) 1924 { 1925 struct ufs_hba *hba = platform_get_drvdata(pdev); 1926 1927 pm_runtime_get_sync(&(pdev)->dev); 1928 ufshcd_remove(hba); 1929 platform_msi_domain_free_irqs(hba->dev); 1930 return 0; 1931 } 1932 1933 static const struct of_device_id ufs_qcom_of_match[] __maybe_unused = { 1934 { .compatible = "qcom,ufshc"}, 1935 {}, 1936 }; 1937 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match); 1938 1939 #ifdef CONFIG_ACPI 1940 static const struct acpi_device_id ufs_qcom_acpi_match[] = { 1941 { "QCOM24A5" }, 1942 { }, 1943 }; 1944 MODULE_DEVICE_TABLE(acpi, ufs_qcom_acpi_match); 1945 #endif 1946 1947 static const struct dev_pm_ops ufs_qcom_pm_ops = { 1948 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL) 1949 .prepare = ufshcd_suspend_prepare, 1950 .complete = ufshcd_resume_complete, 1951 #ifdef CONFIG_PM_SLEEP 1952 .suspend = ufshcd_system_suspend, 1953 .resume = ufshcd_system_resume, 1954 .freeze = ufshcd_system_freeze, 1955 .restore = ufshcd_system_restore, 1956 .thaw = ufshcd_system_thaw, 1957 #endif 1958 }; 1959 1960 static struct platform_driver ufs_qcom_pltform = { 1961 .probe = ufs_qcom_probe, 1962 .remove = ufs_qcom_remove, 1963 .driver = { 1964 .name = "ufshcd-qcom", 1965 .pm = &ufs_qcom_pm_ops, 1966 .of_match_table = of_match_ptr(ufs_qcom_of_match), 1967 .acpi_match_table = ACPI_PTR(ufs_qcom_acpi_match), 1968 }, 1969 }; 1970 module_platform_driver(ufs_qcom_pltform); 1971 1972 MODULE_LICENSE("GPL v2"); 1973