1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/acpi.h> 7 #include <linux/time.h> 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/interconnect.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/platform_device.h> 14 #include <linux/phy/phy.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/reset-controller.h> 17 #include <linux/devfreq.h> 18 19 #include <soc/qcom/ice.h> 20 21 #include <ufs/ufshcd.h> 22 #include "ufshcd-pltfrm.h" 23 #include <ufs/unipro.h> 24 #include "ufs-qcom.h" 25 #include <ufs/ufshci.h> 26 #include <ufs/ufs_quirks.h> 27 28 #define MCQ_QCFGPTR_MASK GENMASK(7, 0) 29 #define MCQ_QCFGPTR_UNIT 0x200 30 #define MCQ_SQATTR_OFFSET(c) \ 31 ((((c) >> 16) & MCQ_QCFGPTR_MASK) * MCQ_QCFGPTR_UNIT) 32 #define MCQ_QCFG_SIZE 0x40 33 34 enum { 35 TSTBUS_UAWM, 36 TSTBUS_UARM, 37 TSTBUS_TXUC, 38 TSTBUS_RXUC, 39 TSTBUS_DFC, 40 TSTBUS_TRLUT, 41 TSTBUS_TMRLUT, 42 TSTBUS_OCSC, 43 TSTBUS_UTP_HCI, 44 TSTBUS_COMBINED, 45 TSTBUS_WRAPPER, 46 TSTBUS_UNIPRO, 47 TSTBUS_MAX, 48 }; 49 50 #define QCOM_UFS_MAX_GEAR 4 51 #define QCOM_UFS_MAX_LANE 2 52 53 enum { 54 MODE_MIN, 55 MODE_PWM, 56 MODE_HS_RA, 57 MODE_HS_RB, 58 MODE_MAX, 59 }; 60 61 static const struct __ufs_qcom_bw_table { 62 u32 mem_bw; 63 u32 cfg_bw; 64 } ufs_qcom_bw_table[MODE_MAX + 1][QCOM_UFS_MAX_GEAR + 1][QCOM_UFS_MAX_LANE + 1] = { 65 [MODE_MIN][0][0] = { 0, 0 }, /* Bandwidth values in KB/s */ 66 [MODE_PWM][UFS_PWM_G1][UFS_LANE_1] = { 922, 1000 }, 67 [MODE_PWM][UFS_PWM_G2][UFS_LANE_1] = { 1844, 1000 }, 68 [MODE_PWM][UFS_PWM_G3][UFS_LANE_1] = { 3688, 1000 }, 69 [MODE_PWM][UFS_PWM_G4][UFS_LANE_1] = { 7376, 1000 }, 70 [MODE_PWM][UFS_PWM_G1][UFS_LANE_2] = { 1844, 1000 }, 71 [MODE_PWM][UFS_PWM_G2][UFS_LANE_2] = { 3688, 1000 }, 72 [MODE_PWM][UFS_PWM_G3][UFS_LANE_2] = { 7376, 1000 }, 73 [MODE_PWM][UFS_PWM_G4][UFS_LANE_2] = { 14752, 1000 }, 74 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_1] = { 127796, 1000 }, 75 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_1] = { 255591, 1000 }, 76 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 }, 77 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 }, 78 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_2] = { 255591, 1000 }, 79 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_2] = { 511181, 1000 }, 80 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 }, 81 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 }, 82 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_1] = { 149422, 1000 }, 83 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_1] = { 298189, 1000 }, 84 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 }, 85 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 }, 86 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_2] = { 298189, 1000 }, 87 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_2] = { 596378, 1000 }, 88 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 }, 89 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 }, 90 [MODE_MAX][0][0] = { 7643136, 307200 }, 91 }; 92 93 static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS]; 94 95 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host); 96 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba, 97 u32 clk_cycles); 98 99 static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd) 100 { 101 return container_of(rcd, struct ufs_qcom_host, rcdev); 102 } 103 104 #ifdef CONFIG_SCSI_UFS_CRYPTO 105 106 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host) 107 { 108 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 109 qcom_ice_enable(host->ice); 110 } 111 112 static int ufs_qcom_ice_init(struct ufs_qcom_host *host) 113 { 114 struct ufs_hba *hba = host->hba; 115 struct device *dev = hba->dev; 116 struct qcom_ice *ice; 117 118 ice = of_qcom_ice_get(dev); 119 if (ice == ERR_PTR(-EOPNOTSUPP)) { 120 dev_warn(dev, "Disabling inline encryption support\n"); 121 ice = NULL; 122 } 123 124 if (IS_ERR_OR_NULL(ice)) 125 return PTR_ERR_OR_ZERO(ice); 126 127 host->ice = ice; 128 hba->caps |= UFSHCD_CAP_CRYPTO; 129 130 return 0; 131 } 132 133 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host) 134 { 135 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 136 return qcom_ice_resume(host->ice); 137 138 return 0; 139 } 140 141 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host) 142 { 143 if (host->hba->caps & UFSHCD_CAP_CRYPTO) 144 return qcom_ice_suspend(host->ice); 145 146 return 0; 147 } 148 149 static int ufs_qcom_ice_program_key(struct ufs_hba *hba, 150 const union ufs_crypto_cfg_entry *cfg, 151 int slot) 152 { 153 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 154 union ufs_crypto_cap_entry cap; 155 bool config_enable = 156 cfg->config_enable & UFS_CRYPTO_CONFIGURATION_ENABLE; 157 158 /* Only AES-256-XTS has been tested so far. */ 159 cap = hba->crypto_cap_array[cfg->crypto_cap_idx]; 160 if (cap.algorithm_id != UFS_CRYPTO_ALG_AES_XTS || 161 cap.key_size != UFS_CRYPTO_KEY_SIZE_256) 162 return -EINVAL; 163 164 if (config_enable) 165 return qcom_ice_program_key(host->ice, 166 QCOM_ICE_CRYPTO_ALG_AES_XTS, 167 QCOM_ICE_CRYPTO_KEY_SIZE_256, 168 cfg->crypto_key, 169 cfg->data_unit_size, slot); 170 else 171 return qcom_ice_evict_key(host->ice, slot); 172 } 173 174 #else 175 176 #define ufs_qcom_ice_program_key NULL 177 178 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host) 179 { 180 } 181 182 static int ufs_qcom_ice_init(struct ufs_qcom_host *host) 183 { 184 return 0; 185 } 186 187 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host) 188 { 189 return 0; 190 } 191 192 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host) 193 { 194 return 0; 195 } 196 #endif 197 198 static int ufs_qcom_host_clk_get(struct device *dev, 199 const char *name, struct clk **clk_out, bool optional) 200 { 201 struct clk *clk; 202 int err = 0; 203 204 clk = devm_clk_get(dev, name); 205 if (!IS_ERR(clk)) { 206 *clk_out = clk; 207 return 0; 208 } 209 210 err = PTR_ERR(clk); 211 212 if (optional && err == -ENOENT) { 213 *clk_out = NULL; 214 return 0; 215 } 216 217 if (err != -EPROBE_DEFER) 218 dev_err(dev, "failed to get %s err %d\n", name, err); 219 220 return err; 221 } 222 223 static int ufs_qcom_host_clk_enable(struct device *dev, 224 const char *name, struct clk *clk) 225 { 226 int err = 0; 227 228 err = clk_prepare_enable(clk); 229 if (err) 230 dev_err(dev, "%s: %s enable failed %d\n", __func__, name, err); 231 232 return err; 233 } 234 235 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host) 236 { 237 if (!host->is_lane_clks_enabled) 238 return; 239 240 clk_disable_unprepare(host->tx_l1_sync_clk); 241 clk_disable_unprepare(host->tx_l0_sync_clk); 242 clk_disable_unprepare(host->rx_l1_sync_clk); 243 clk_disable_unprepare(host->rx_l0_sync_clk); 244 245 host->is_lane_clks_enabled = false; 246 } 247 248 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host) 249 { 250 int err; 251 struct device *dev = host->hba->dev; 252 253 if (host->is_lane_clks_enabled) 254 return 0; 255 256 err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk", 257 host->rx_l0_sync_clk); 258 if (err) 259 return err; 260 261 err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk", 262 host->tx_l0_sync_clk); 263 if (err) 264 goto disable_rx_l0; 265 266 err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk", 267 host->rx_l1_sync_clk); 268 if (err) 269 goto disable_tx_l0; 270 271 err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk", 272 host->tx_l1_sync_clk); 273 if (err) 274 goto disable_rx_l1; 275 276 host->is_lane_clks_enabled = true; 277 278 return 0; 279 280 disable_rx_l1: 281 clk_disable_unprepare(host->rx_l1_sync_clk); 282 disable_tx_l0: 283 clk_disable_unprepare(host->tx_l0_sync_clk); 284 disable_rx_l0: 285 clk_disable_unprepare(host->rx_l0_sync_clk); 286 287 return err; 288 } 289 290 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host) 291 { 292 int err = 0; 293 struct device *dev = host->hba->dev; 294 295 if (has_acpi_companion(dev)) 296 return 0; 297 298 err = ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk", 299 &host->rx_l0_sync_clk, false); 300 if (err) 301 return err; 302 303 err = ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk", 304 &host->tx_l0_sync_clk, false); 305 if (err) 306 return err; 307 308 /* In case of single lane per direction, don't read lane1 clocks */ 309 if (host->hba->lanes_per_direction > 1) { 310 err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk", 311 &host->rx_l1_sync_clk, false); 312 if (err) 313 return err; 314 315 err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk", 316 &host->tx_l1_sync_clk, true); 317 } 318 319 return 0; 320 } 321 322 static int ufs_qcom_check_hibern8(struct ufs_hba *hba) 323 { 324 int err; 325 u32 tx_fsm_val = 0; 326 unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS); 327 328 do { 329 err = ufshcd_dme_get(hba, 330 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 331 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 332 &tx_fsm_val); 333 if (err || tx_fsm_val == TX_FSM_HIBERN8) 334 break; 335 336 /* sleep for max. 200us */ 337 usleep_range(100, 200); 338 } while (time_before(jiffies, timeout)); 339 340 /* 341 * we might have scheduled out for long during polling so 342 * check the state again. 343 */ 344 if (time_after(jiffies, timeout)) 345 err = ufshcd_dme_get(hba, 346 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 347 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 348 &tx_fsm_val); 349 350 if (err) { 351 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n", 352 __func__, err); 353 } else if (tx_fsm_val != TX_FSM_HIBERN8) { 354 err = tx_fsm_val; 355 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n", 356 __func__, err); 357 } 358 359 return err; 360 } 361 362 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host) 363 { 364 ufshcd_rmwl(host->hba, QUNIPRO_SEL, 365 ufs_qcom_cap_qunipro(host) ? QUNIPRO_SEL : 0, 366 REG_UFS_CFG1); 367 368 if (host->hw_ver.major >= 0x05) 369 ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0); 370 371 /* make sure above configuration is applied before we return */ 372 mb(); 373 } 374 375 /* 376 * ufs_qcom_host_reset - reset host controller and PHY 377 */ 378 static int ufs_qcom_host_reset(struct ufs_hba *hba) 379 { 380 int ret = 0; 381 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 382 bool reenable_intr = false; 383 384 if (!host->core_reset) { 385 dev_warn(hba->dev, "%s: reset control not set\n", __func__); 386 return 0; 387 } 388 389 reenable_intr = hba->is_irq_enabled; 390 disable_irq(hba->irq); 391 hba->is_irq_enabled = false; 392 393 ret = reset_control_assert(host->core_reset); 394 if (ret) { 395 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n", 396 __func__, ret); 397 return ret; 398 } 399 400 /* 401 * The hardware requirement for delay between assert/deassert 402 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to 403 * ~125us (4/32768). To be on the safe side add 200us delay. 404 */ 405 usleep_range(200, 210); 406 407 ret = reset_control_deassert(host->core_reset); 408 if (ret) 409 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n", 410 __func__, ret); 411 412 usleep_range(1000, 1100); 413 414 if (reenable_intr) { 415 enable_irq(hba->irq); 416 hba->is_irq_enabled = true; 417 } 418 419 return 0; 420 } 421 422 static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) 423 { 424 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 425 426 if (host->hw_ver.major == 0x1) { 427 /* 428 * HS-G3 operations may not reliably work on legacy QCOM 429 * UFS host controller hardware even though capability 430 * exchange during link startup phase may end up 431 * negotiating maximum supported gear as G3. 432 * Hence downgrade the maximum supported gear to HS-G2. 433 */ 434 return UFS_HS_G2; 435 } else if (host->hw_ver.major >= 0x4) { 436 return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0)); 437 } 438 439 /* Default is HS-G3 */ 440 return UFS_HS_G3; 441 } 442 443 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) 444 { 445 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 446 struct phy *phy = host->generic_phy; 447 int ret; 448 449 /* Reset UFS Host Controller and PHY */ 450 ret = ufs_qcom_host_reset(hba); 451 if (ret) 452 dev_warn(hba->dev, "%s: host reset returned %d\n", 453 __func__, ret); 454 455 /* phy initialization - calibrate the phy */ 456 ret = phy_init(phy); 457 if (ret) { 458 dev_err(hba->dev, "%s: phy init failed, ret = %d\n", 459 __func__, ret); 460 return ret; 461 } 462 463 phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->hs_gear); 464 465 /* power on phy - start serdes and phy's power and clocks */ 466 ret = phy_power_on(phy); 467 if (ret) { 468 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n", 469 __func__, ret); 470 goto out_disable_phy; 471 } 472 473 ufs_qcom_select_unipro_mode(host); 474 475 return 0; 476 477 out_disable_phy: 478 phy_exit(phy); 479 480 return ret; 481 } 482 483 /* 484 * The UTP controller has a number of internal clock gating cells (CGCs). 485 * Internal hardware sub-modules within the UTP controller control the CGCs. 486 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved 487 * in a specific operation, UTP controller CGCs are by default disabled and 488 * this function enables them (after every UFS link startup) to save some power 489 * leakage. 490 */ 491 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba) 492 { 493 ufshcd_writel(hba, 494 ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL, 495 REG_UFS_CFG2); 496 497 /* Ensure that HW clock gating is enabled before next operations */ 498 mb(); 499 } 500 501 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba, 502 enum ufs_notify_change_status status) 503 { 504 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 505 int err = 0; 506 507 switch (status) { 508 case PRE_CHANGE: 509 ufs_qcom_power_up_sequence(hba); 510 /* 511 * The PHY PLL output is the source of tx/rx lane symbol 512 * clocks, hence, enable the lane clocks only after PHY 513 * is initialized. 514 */ 515 err = ufs_qcom_enable_lane_clks(host); 516 break; 517 case POST_CHANGE: 518 /* check if UFS PHY moved from DISABLED to HIBERN8 */ 519 err = ufs_qcom_check_hibern8(hba); 520 ufs_qcom_enable_hw_clk_gating(hba); 521 ufs_qcom_ice_enable(host); 522 break; 523 default: 524 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status); 525 err = -EINVAL; 526 break; 527 } 528 return err; 529 } 530 531 /* 532 * Return: zero for success and non-zero in case of a failure. 533 */ 534 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, 535 u32 hs, u32 rate, bool update_link_startup_timer) 536 { 537 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 538 struct ufs_clk_info *clki; 539 u32 core_clk_period_in_ns; 540 u32 tx_clk_cycles_per_us = 0; 541 unsigned long core_clk_rate = 0; 542 u32 core_clk_cycles_per_us = 0; 543 544 static u32 pwm_fr_table[][2] = { 545 {UFS_PWM_G1, 0x1}, 546 {UFS_PWM_G2, 0x1}, 547 {UFS_PWM_G3, 0x1}, 548 {UFS_PWM_G4, 0x1}, 549 }; 550 551 static u32 hs_fr_table_rA[][2] = { 552 {UFS_HS_G1, 0x1F}, 553 {UFS_HS_G2, 0x3e}, 554 {UFS_HS_G3, 0x7D}, 555 }; 556 557 static u32 hs_fr_table_rB[][2] = { 558 {UFS_HS_G1, 0x24}, 559 {UFS_HS_G2, 0x49}, 560 {UFS_HS_G3, 0x92}, 561 }; 562 563 /* 564 * The Qunipro controller does not use following registers: 565 * SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG & 566 * UFS_REG_PA_LINK_STARTUP_TIMER 567 * But UTP controller uses SYS1CLK_1US_REG register for Interrupt 568 * Aggregation logic. 569 */ 570 if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba)) 571 return 0; 572 573 if (gear == 0) { 574 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear); 575 return -EINVAL; 576 } 577 578 list_for_each_entry(clki, &hba->clk_list_head, list) { 579 if (!strcmp(clki->name, "core_clk")) 580 core_clk_rate = clk_get_rate(clki->clk); 581 } 582 583 /* If frequency is smaller than 1MHz, set to 1MHz */ 584 if (core_clk_rate < DEFAULT_CLK_RATE_HZ) 585 core_clk_rate = DEFAULT_CLK_RATE_HZ; 586 587 core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC; 588 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) { 589 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US); 590 /* 591 * make sure above write gets applied before we return from 592 * this function. 593 */ 594 mb(); 595 } 596 597 if (ufs_qcom_cap_qunipro(host)) 598 return 0; 599 600 core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate; 601 core_clk_period_in_ns <<= OFFSET_CLK_NS_REG; 602 core_clk_period_in_ns &= MASK_CLK_NS_REG; 603 604 switch (hs) { 605 case FASTAUTO_MODE: 606 case FAST_MODE: 607 if (rate == PA_HS_MODE_A) { 608 if (gear > ARRAY_SIZE(hs_fr_table_rA)) { 609 dev_err(hba->dev, 610 "%s: index %d exceeds table size %zu\n", 611 __func__, gear, 612 ARRAY_SIZE(hs_fr_table_rA)); 613 return -EINVAL; 614 } 615 tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1]; 616 } else if (rate == PA_HS_MODE_B) { 617 if (gear > ARRAY_SIZE(hs_fr_table_rB)) { 618 dev_err(hba->dev, 619 "%s: index %d exceeds table size %zu\n", 620 __func__, gear, 621 ARRAY_SIZE(hs_fr_table_rB)); 622 return -EINVAL; 623 } 624 tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1]; 625 } else { 626 dev_err(hba->dev, "%s: invalid rate = %d\n", 627 __func__, rate); 628 return -EINVAL; 629 } 630 break; 631 case SLOWAUTO_MODE: 632 case SLOW_MODE: 633 if (gear > ARRAY_SIZE(pwm_fr_table)) { 634 dev_err(hba->dev, 635 "%s: index %d exceeds table size %zu\n", 636 __func__, gear, 637 ARRAY_SIZE(pwm_fr_table)); 638 return -EINVAL; 639 } 640 tx_clk_cycles_per_us = pwm_fr_table[gear-1][1]; 641 break; 642 case UNCHANGED: 643 default: 644 dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs); 645 return -EINVAL; 646 } 647 648 if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) != 649 (core_clk_period_in_ns | tx_clk_cycles_per_us)) { 650 /* this register 2 fields shall be written at once */ 651 ufshcd_writel(hba, core_clk_period_in_ns | tx_clk_cycles_per_us, 652 REG_UFS_TX_SYMBOL_CLK_NS_US); 653 /* 654 * make sure above write gets applied before we return from 655 * this function. 656 */ 657 mb(); 658 } 659 660 if (update_link_startup_timer && host->hw_ver.major != 0x5) { 661 ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100), 662 REG_UFS_CFG0); 663 /* 664 * make sure that this configuration is applied before 665 * we return 666 */ 667 mb(); 668 } 669 670 return 0; 671 } 672 673 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, 674 enum ufs_notify_change_status status) 675 { 676 int err = 0; 677 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 678 679 switch (status) { 680 case PRE_CHANGE: 681 if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE, 682 0, true)) { 683 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", 684 __func__); 685 return -EINVAL; 686 } 687 688 if (ufs_qcom_cap_qunipro(host)) 689 /* 690 * set unipro core clock cycles to 150 & clear clock 691 * divider 692 */ 693 err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 694 150); 695 696 /* 697 * Some UFS devices (and may be host) have issues if LCC is 698 * enabled. So we are setting PA_Local_TX_LCC_Enable to 0 699 * before link startup which will make sure that both host 700 * and device TX LCC are disabled once link startup is 701 * completed. 702 */ 703 if (ufshcd_get_local_unipro_ver(hba) != UFS_UNIPRO_VER_1_41) 704 err = ufshcd_disable_host_tx_lcc(hba); 705 706 break; 707 default: 708 break; 709 } 710 711 return err; 712 } 713 714 static void ufs_qcom_device_reset_ctrl(struct ufs_hba *hba, bool asserted) 715 { 716 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 717 718 /* reset gpio is optional */ 719 if (!host->device_reset) 720 return; 721 722 gpiod_set_value_cansleep(host->device_reset, asserted); 723 } 724 725 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, 726 enum ufs_notify_change_status status) 727 { 728 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 729 struct phy *phy = host->generic_phy; 730 731 if (status == PRE_CHANGE) 732 return 0; 733 734 if (ufs_qcom_is_link_off(hba)) { 735 /* 736 * Disable the tx/rx lane symbol clocks before PHY is 737 * powered down as the PLL source should be disabled 738 * after downstream clocks are disabled. 739 */ 740 ufs_qcom_disable_lane_clks(host); 741 phy_power_off(phy); 742 743 /* reset the connected UFS device during power down */ 744 ufs_qcom_device_reset_ctrl(hba, true); 745 746 } else if (!ufs_qcom_is_link_active(hba)) { 747 ufs_qcom_disable_lane_clks(host); 748 } 749 750 return ufs_qcom_ice_suspend(host); 751 } 752 753 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) 754 { 755 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 756 struct phy *phy = host->generic_phy; 757 int err; 758 759 if (ufs_qcom_is_link_off(hba)) { 760 err = phy_power_on(phy); 761 if (err) { 762 dev_err(hba->dev, "%s: failed PHY power on: %d\n", 763 __func__, err); 764 return err; 765 } 766 767 err = ufs_qcom_enable_lane_clks(host); 768 if (err) 769 return err; 770 771 } else if (!ufs_qcom_is_link_active(hba)) { 772 err = ufs_qcom_enable_lane_clks(host); 773 if (err) 774 return err; 775 } 776 777 return ufs_qcom_ice_resume(host); 778 } 779 780 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable) 781 { 782 if (host->dev_ref_clk_ctrl_mmio && 783 (enable ^ host->is_dev_ref_clk_enabled)) { 784 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio); 785 786 if (enable) 787 temp |= host->dev_ref_clk_en_mask; 788 else 789 temp &= ~host->dev_ref_clk_en_mask; 790 791 /* 792 * If we are here to disable this clock it might be immediately 793 * after entering into hibern8 in which case we need to make 794 * sure that device ref_clk is active for specific time after 795 * hibern8 enter. 796 */ 797 if (!enable) { 798 unsigned long gating_wait; 799 800 gating_wait = host->hba->dev_info.clk_gating_wait_us; 801 if (!gating_wait) { 802 udelay(1); 803 } else { 804 /* 805 * bRefClkGatingWaitTime defines the minimum 806 * time for which the reference clock is 807 * required by device during transition from 808 * HS-MODE to LS-MODE or HIBERN8 state. Give it 809 * more delay to be on the safe side. 810 */ 811 gating_wait += 10; 812 usleep_range(gating_wait, gating_wait + 10); 813 } 814 } 815 816 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio); 817 818 /* 819 * Make sure the write to ref_clk reaches the destination and 820 * not stored in a Write Buffer (WB). 821 */ 822 readl(host->dev_ref_clk_ctrl_mmio); 823 824 /* 825 * If we call hibern8 exit after this, we need to make sure that 826 * device ref_clk is stable for at least 1us before the hibern8 827 * exit command. 828 */ 829 if (enable) 830 udelay(1); 831 832 host->is_dev_ref_clk_enabled = enable; 833 } 834 } 835 836 static int ufs_qcom_icc_set_bw(struct ufs_qcom_host *host, u32 mem_bw, u32 cfg_bw) 837 { 838 struct device *dev = host->hba->dev; 839 int ret; 840 841 ret = icc_set_bw(host->icc_ddr, 0, mem_bw); 842 if (ret < 0) { 843 dev_err(dev, "failed to set bandwidth request: %d\n", ret); 844 return ret; 845 } 846 847 ret = icc_set_bw(host->icc_cpu, 0, cfg_bw); 848 if (ret < 0) { 849 dev_err(dev, "failed to set bandwidth request: %d\n", ret); 850 return ret; 851 } 852 853 return 0; 854 } 855 856 static struct __ufs_qcom_bw_table ufs_qcom_get_bw_table(struct ufs_qcom_host *host) 857 { 858 struct ufs_pa_layer_attr *p = &host->dev_req_params; 859 int gear = max_t(u32, p->gear_rx, p->gear_tx); 860 int lane = max_t(u32, p->lane_rx, p->lane_tx); 861 862 if (ufshcd_is_hs_mode(p)) { 863 if (p->hs_rate == PA_HS_MODE_B) 864 return ufs_qcom_bw_table[MODE_HS_RB][gear][lane]; 865 else 866 return ufs_qcom_bw_table[MODE_HS_RA][gear][lane]; 867 } else { 868 return ufs_qcom_bw_table[MODE_PWM][gear][lane]; 869 } 870 } 871 872 static int ufs_qcom_icc_update_bw(struct ufs_qcom_host *host) 873 { 874 struct __ufs_qcom_bw_table bw_table; 875 876 bw_table = ufs_qcom_get_bw_table(host); 877 878 return ufs_qcom_icc_set_bw(host, bw_table.mem_bw, bw_table.cfg_bw); 879 } 880 881 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, 882 enum ufs_notify_change_status status, 883 struct ufs_pa_layer_attr *dev_max_params, 884 struct ufs_pa_layer_attr *dev_req_params) 885 { 886 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 887 struct ufs_dev_params ufs_qcom_cap; 888 int ret = 0; 889 890 if (!dev_req_params) { 891 pr_err("%s: incoming dev_req_params is NULL\n", __func__); 892 return -EINVAL; 893 } 894 895 switch (status) { 896 case PRE_CHANGE: 897 ufshcd_init_pwr_dev_param(&ufs_qcom_cap); 898 ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE; 899 900 /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */ 901 ufs_qcom_cap.hs_tx_gear = ufs_qcom_cap.hs_rx_gear = ufs_qcom_get_hs_gear(hba); 902 903 ret = ufshcd_get_pwr_dev_param(&ufs_qcom_cap, 904 dev_max_params, 905 dev_req_params); 906 if (ret) { 907 dev_err(hba->dev, "%s: failed to determine capabilities\n", 908 __func__); 909 return ret; 910 } 911 912 /* 913 * Update hs_gear only when the gears are scaled to a higher value. This is because, 914 * the PHY gear settings are backwards compatible and we only need to change the PHY 915 * settings while scaling to higher gears. 916 */ 917 if (dev_req_params->gear_tx > host->hs_gear) 918 host->hs_gear = dev_req_params->gear_tx; 919 920 /* enable the device ref clock before changing to HS mode */ 921 if (!ufshcd_is_hs_mode(&hba->pwr_info) && 922 ufshcd_is_hs_mode(dev_req_params)) 923 ufs_qcom_dev_ref_clk_ctrl(host, true); 924 925 if (host->hw_ver.major >= 0x4) { 926 ufshcd_dme_configure_adapt(hba, 927 dev_req_params->gear_tx, 928 PA_INITIAL_ADAPT); 929 } 930 break; 931 case POST_CHANGE: 932 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx, 933 dev_req_params->pwr_rx, 934 dev_req_params->hs_rate, false)) { 935 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", 936 __func__); 937 /* 938 * we return error code at the end of the routine, 939 * but continue to configure UFS_PHY_TX_LANE_ENABLE 940 * and bus voting as usual 941 */ 942 ret = -EINVAL; 943 } 944 945 /* cache the power mode parameters to use internally */ 946 memcpy(&host->dev_req_params, 947 dev_req_params, sizeof(*dev_req_params)); 948 949 ufs_qcom_icc_update_bw(host); 950 951 /* disable the device ref clock if entered PWM mode */ 952 if (ufshcd_is_hs_mode(&hba->pwr_info) && 953 !ufshcd_is_hs_mode(dev_req_params)) 954 ufs_qcom_dev_ref_clk_ctrl(host, false); 955 break; 956 default: 957 ret = -EINVAL; 958 break; 959 } 960 961 return ret; 962 } 963 964 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba) 965 { 966 int err; 967 u32 pa_vs_config_reg1; 968 969 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), 970 &pa_vs_config_reg1); 971 if (err) 972 return err; 973 974 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */ 975 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), 976 (pa_vs_config_reg1 | (1 << 12))); 977 } 978 979 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba) 980 { 981 int err = 0; 982 983 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME) 984 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba); 985 986 if (hba->dev_info.wmanufacturerid == UFS_VENDOR_WDC) 987 hba->dev_quirks |= UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE; 988 989 return err; 990 } 991 992 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba) 993 { 994 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 995 996 if (host->hw_ver.major == 0x1) 997 return ufshci_version(1, 1); 998 else 999 return ufshci_version(2, 0); 1000 } 1001 1002 /** 1003 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks 1004 * @hba: host controller instance 1005 * 1006 * QCOM UFS host controller might have some non standard behaviours (quirks) 1007 * than what is specified by UFSHCI specification. Advertise all such 1008 * quirks to standard UFS host controller driver so standard takes them into 1009 * account. 1010 */ 1011 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba) 1012 { 1013 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1014 1015 if (host->hw_ver.major == 0x01) { 1016 hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS 1017 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP 1018 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE; 1019 1020 if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001) 1021 hba->quirks |= UFSHCD_QUIRK_BROKEN_INTR_AGGR; 1022 1023 hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC; 1024 } 1025 1026 if (host->hw_ver.major == 0x2) { 1027 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION; 1028 1029 if (!ufs_qcom_cap_qunipro(host)) 1030 /* Legacy UniPro mode still need following quirks */ 1031 hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS 1032 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE 1033 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP); 1034 } 1035 1036 if (host->hw_ver.major > 0x3) 1037 hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; 1038 } 1039 1040 static void ufs_qcom_set_caps(struct ufs_hba *hba) 1041 { 1042 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1043 1044 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; 1045 hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING; 1046 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND; 1047 hba->caps |= UFSHCD_CAP_WB_EN; 1048 hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE; 1049 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND; 1050 1051 if (host->hw_ver.major >= 0x2) { 1052 host->caps = UFS_QCOM_CAP_QUNIPRO | 1053 UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE; 1054 } 1055 } 1056 1057 /** 1058 * ufs_qcom_setup_clocks - enables/disable clocks 1059 * @hba: host controller instance 1060 * @on: If true, enable clocks else disable them. 1061 * @status: PRE_CHANGE or POST_CHANGE notify 1062 * 1063 * Return: 0 on success, non-zero on failure. 1064 */ 1065 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, 1066 enum ufs_notify_change_status status) 1067 { 1068 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1069 1070 /* 1071 * In case ufs_qcom_init() is not yet done, simply ignore. 1072 * This ufs_qcom_setup_clocks() shall be called from 1073 * ufs_qcom_init() after init is done. 1074 */ 1075 if (!host) 1076 return 0; 1077 1078 switch (status) { 1079 case PRE_CHANGE: 1080 if (on) { 1081 ufs_qcom_icc_update_bw(host); 1082 } else { 1083 if (!ufs_qcom_is_link_active(hba)) { 1084 /* disable device ref_clk */ 1085 ufs_qcom_dev_ref_clk_ctrl(host, false); 1086 } 1087 } 1088 break; 1089 case POST_CHANGE: 1090 if (on) { 1091 /* enable the device ref clock for HS mode*/ 1092 if (ufshcd_is_hs_mode(&hba->pwr_info)) 1093 ufs_qcom_dev_ref_clk_ctrl(host, true); 1094 } else { 1095 ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MIN][0][0].mem_bw, 1096 ufs_qcom_bw_table[MODE_MIN][0][0].cfg_bw); 1097 } 1098 break; 1099 } 1100 1101 return 0; 1102 } 1103 1104 static int 1105 ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) 1106 { 1107 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); 1108 1109 ufs_qcom_assert_reset(host->hba); 1110 /* provide 1ms delay to let the reset pulse propagate. */ 1111 usleep_range(1000, 1100); 1112 return 0; 1113 } 1114 1115 static int 1116 ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) 1117 { 1118 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); 1119 1120 ufs_qcom_deassert_reset(host->hba); 1121 1122 /* 1123 * after reset deassertion, phy will need all ref clocks, 1124 * voltage, current to settle down before starting serdes. 1125 */ 1126 usleep_range(1000, 1100); 1127 return 0; 1128 } 1129 1130 static const struct reset_control_ops ufs_qcom_reset_ops = { 1131 .assert = ufs_qcom_reset_assert, 1132 .deassert = ufs_qcom_reset_deassert, 1133 }; 1134 1135 static int ufs_qcom_icc_init(struct ufs_qcom_host *host) 1136 { 1137 struct device *dev = host->hba->dev; 1138 int ret; 1139 1140 host->icc_ddr = devm_of_icc_get(dev, "ufs-ddr"); 1141 if (IS_ERR(host->icc_ddr)) 1142 return dev_err_probe(dev, PTR_ERR(host->icc_ddr), 1143 "failed to acquire interconnect path\n"); 1144 1145 host->icc_cpu = devm_of_icc_get(dev, "cpu-ufs"); 1146 if (IS_ERR(host->icc_cpu)) 1147 return dev_err_probe(dev, PTR_ERR(host->icc_cpu), 1148 "failed to acquire interconnect path\n"); 1149 1150 /* 1151 * Set Maximum bandwidth vote before initializing the UFS controller and 1152 * device. Ideally, a minimal interconnect vote would suffice for the 1153 * initialization, but a max vote would allow faster initialization. 1154 */ 1155 ret = ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MAX][0][0].mem_bw, 1156 ufs_qcom_bw_table[MODE_MAX][0][0].cfg_bw); 1157 if (ret < 0) 1158 return dev_err_probe(dev, ret, "failed to set bandwidth request\n"); 1159 1160 return 0; 1161 } 1162 1163 /** 1164 * ufs_qcom_init - bind phy with controller 1165 * @hba: host controller instance 1166 * 1167 * Binds PHY with controller and powers up PHY enabling clocks 1168 * and regulators. 1169 * 1170 * Return: -EPROBE_DEFER if binding fails, returns negative error 1171 * on phy power up failure and returns zero on success. 1172 */ 1173 static int ufs_qcom_init(struct ufs_hba *hba) 1174 { 1175 int err; 1176 struct device *dev = hba->dev; 1177 struct platform_device *pdev = to_platform_device(dev); 1178 struct ufs_qcom_host *host; 1179 struct resource *res; 1180 struct ufs_clk_info *clki; 1181 1182 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); 1183 if (!host) { 1184 dev_err(dev, "%s: no memory for qcom ufs host\n", __func__); 1185 return -ENOMEM; 1186 } 1187 1188 /* Make a two way bind between the qcom host and the hba */ 1189 host->hba = hba; 1190 ufshcd_set_variant(hba, host); 1191 1192 /* Setup the optional reset control of HCI */ 1193 host->core_reset = devm_reset_control_get_optional(hba->dev, "rst"); 1194 if (IS_ERR(host->core_reset)) { 1195 err = dev_err_probe(dev, PTR_ERR(host->core_reset), 1196 "Failed to get reset control\n"); 1197 goto out_variant_clear; 1198 } 1199 1200 /* Fire up the reset controller. Failure here is non-fatal. */ 1201 host->rcdev.of_node = dev->of_node; 1202 host->rcdev.ops = &ufs_qcom_reset_ops; 1203 host->rcdev.owner = dev->driver->owner; 1204 host->rcdev.nr_resets = 1; 1205 err = devm_reset_controller_register(dev, &host->rcdev); 1206 if (err) 1207 dev_warn(dev, "Failed to register reset controller\n"); 1208 1209 if (!has_acpi_companion(dev)) { 1210 host->generic_phy = devm_phy_get(dev, "ufsphy"); 1211 if (IS_ERR(host->generic_phy)) { 1212 err = dev_err_probe(dev, PTR_ERR(host->generic_phy), "Failed to get PHY\n"); 1213 goto out_variant_clear; 1214 } 1215 } 1216 1217 err = ufs_qcom_icc_init(host); 1218 if (err) 1219 goto out_variant_clear; 1220 1221 host->device_reset = devm_gpiod_get_optional(dev, "reset", 1222 GPIOD_OUT_HIGH); 1223 if (IS_ERR(host->device_reset)) { 1224 err = PTR_ERR(host->device_reset); 1225 if (err != -EPROBE_DEFER) 1226 dev_err(dev, "failed to acquire reset gpio: %d\n", err); 1227 goto out_variant_clear; 1228 } 1229 1230 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major, 1231 &host->hw_ver.minor, &host->hw_ver.step); 1232 1233 /* 1234 * for newer controllers, device reference clock control bit has 1235 * moved inside UFS controller register address space itself. 1236 */ 1237 if (host->hw_ver.major >= 0x02) { 1238 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1; 1239 host->dev_ref_clk_en_mask = BIT(26); 1240 } else { 1241 /* "dev_ref_clk_ctrl_mem" is optional resource */ 1242 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1243 "dev_ref_clk_ctrl_mem"); 1244 if (res) { 1245 host->dev_ref_clk_ctrl_mmio = 1246 devm_ioremap_resource(dev, res); 1247 if (IS_ERR(host->dev_ref_clk_ctrl_mmio)) 1248 host->dev_ref_clk_ctrl_mmio = NULL; 1249 host->dev_ref_clk_en_mask = BIT(5); 1250 } 1251 } 1252 1253 list_for_each_entry(clki, &hba->clk_list_head, list) { 1254 if (!strcmp(clki->name, "core_clk_unipro")) 1255 clki->keep_link_active = true; 1256 } 1257 1258 err = ufs_qcom_init_lane_clks(host); 1259 if (err) 1260 goto out_variant_clear; 1261 1262 ufs_qcom_set_caps(hba); 1263 ufs_qcom_advertise_quirks(hba); 1264 1265 err = ufs_qcom_ice_init(host); 1266 if (err) 1267 goto out_variant_clear; 1268 1269 ufs_qcom_setup_clocks(hba, true, POST_CHANGE); 1270 1271 if (hba->dev->id < MAX_UFS_QCOM_HOSTS) 1272 ufs_qcom_hosts[hba->dev->id] = host; 1273 1274 ufs_qcom_get_default_testbus_cfg(host); 1275 err = ufs_qcom_testbus_config(host); 1276 if (err) 1277 /* Failure is non-fatal */ 1278 dev_warn(dev, "%s: failed to configure the testbus %d\n", 1279 __func__, err); 1280 1281 /* 1282 * Power up the PHY using the minimum supported gear (UFS_HS_G2). 1283 * Switching to max gear will be performed during reinit if supported. 1284 */ 1285 host->hs_gear = UFS_HS_G2; 1286 1287 return 0; 1288 1289 out_variant_clear: 1290 ufshcd_set_variant(hba, NULL); 1291 1292 return err; 1293 } 1294 1295 static void ufs_qcom_exit(struct ufs_hba *hba) 1296 { 1297 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1298 1299 ufs_qcom_disable_lane_clks(host); 1300 phy_power_off(host->generic_phy); 1301 phy_exit(host->generic_phy); 1302 } 1303 1304 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba, 1305 u32 clk_cycles) 1306 { 1307 int err; 1308 u32 core_clk_ctrl_reg; 1309 1310 if (clk_cycles > DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK) 1311 return -EINVAL; 1312 1313 err = ufshcd_dme_get(hba, 1314 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1315 &core_clk_ctrl_reg); 1316 if (err) 1317 return err; 1318 1319 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK; 1320 core_clk_ctrl_reg |= clk_cycles; 1321 1322 /* Clear CORE_CLK_DIV_EN */ 1323 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; 1324 1325 return ufshcd_dme_set(hba, 1326 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1327 core_clk_ctrl_reg); 1328 } 1329 1330 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba) 1331 { 1332 /* nothing to do as of now */ 1333 return 0; 1334 } 1335 1336 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba) 1337 { 1338 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1339 1340 if (!ufs_qcom_cap_qunipro(host)) 1341 return 0; 1342 1343 /* set unipro core clock cycles to 150 and clear clock divider */ 1344 return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150); 1345 } 1346 1347 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba) 1348 { 1349 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1350 int err; 1351 u32 core_clk_ctrl_reg; 1352 1353 if (!ufs_qcom_cap_qunipro(host)) 1354 return 0; 1355 1356 err = ufshcd_dme_get(hba, 1357 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1358 &core_clk_ctrl_reg); 1359 1360 /* make sure CORE_CLK_DIV_EN is cleared */ 1361 if (!err && 1362 (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) { 1363 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; 1364 err = ufshcd_dme_set(hba, 1365 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), 1366 core_clk_ctrl_reg); 1367 } 1368 1369 return err; 1370 } 1371 1372 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba) 1373 { 1374 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1375 1376 if (!ufs_qcom_cap_qunipro(host)) 1377 return 0; 1378 1379 /* set unipro core clock cycles to 75 and clear clock divider */ 1380 return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 75); 1381 } 1382 1383 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, 1384 bool scale_up, enum ufs_notify_change_status status) 1385 { 1386 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1387 struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params; 1388 int err = 0; 1389 1390 /* check the host controller state before sending hibern8 cmd */ 1391 if (!ufshcd_is_hba_active(hba)) 1392 return 0; 1393 1394 if (status == PRE_CHANGE) { 1395 err = ufshcd_uic_hibern8_enter(hba); 1396 if (err) 1397 return err; 1398 if (scale_up) 1399 err = ufs_qcom_clk_scale_up_pre_change(hba); 1400 else 1401 err = ufs_qcom_clk_scale_down_pre_change(hba); 1402 if (err) 1403 ufshcd_uic_hibern8_exit(hba); 1404 1405 } else { 1406 if (scale_up) 1407 err = ufs_qcom_clk_scale_up_post_change(hba); 1408 else 1409 err = ufs_qcom_clk_scale_down_post_change(hba); 1410 1411 1412 if (err) { 1413 ufshcd_uic_hibern8_exit(hba); 1414 return err; 1415 } 1416 1417 ufs_qcom_cfg_timers(hba, 1418 dev_req_params->gear_rx, 1419 dev_req_params->pwr_rx, 1420 dev_req_params->hs_rate, 1421 false); 1422 ufs_qcom_icc_update_bw(host); 1423 ufshcd_uic_hibern8_exit(hba); 1424 } 1425 1426 return 0; 1427 } 1428 1429 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host) 1430 { 1431 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 1432 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1); 1433 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1); 1434 } 1435 1436 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host) 1437 { 1438 /* provide a legal default configuration */ 1439 host->testbus.select_major = TSTBUS_UNIPRO; 1440 host->testbus.select_minor = 37; 1441 } 1442 1443 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host) 1444 { 1445 if (host->testbus.select_major >= TSTBUS_MAX) { 1446 dev_err(host->hba->dev, 1447 "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n", 1448 __func__, host->testbus.select_major); 1449 return false; 1450 } 1451 1452 return true; 1453 } 1454 1455 int ufs_qcom_testbus_config(struct ufs_qcom_host *host) 1456 { 1457 int reg; 1458 int offset; 1459 u32 mask = TEST_BUS_SUB_SEL_MASK; 1460 1461 if (!host) 1462 return -EINVAL; 1463 1464 if (!ufs_qcom_testbus_cfg_is_ok(host)) 1465 return -EPERM; 1466 1467 switch (host->testbus.select_major) { 1468 case TSTBUS_UAWM: 1469 reg = UFS_TEST_BUS_CTRL_0; 1470 offset = 24; 1471 break; 1472 case TSTBUS_UARM: 1473 reg = UFS_TEST_BUS_CTRL_0; 1474 offset = 16; 1475 break; 1476 case TSTBUS_TXUC: 1477 reg = UFS_TEST_BUS_CTRL_0; 1478 offset = 8; 1479 break; 1480 case TSTBUS_RXUC: 1481 reg = UFS_TEST_BUS_CTRL_0; 1482 offset = 0; 1483 break; 1484 case TSTBUS_DFC: 1485 reg = UFS_TEST_BUS_CTRL_1; 1486 offset = 24; 1487 break; 1488 case TSTBUS_TRLUT: 1489 reg = UFS_TEST_BUS_CTRL_1; 1490 offset = 16; 1491 break; 1492 case TSTBUS_TMRLUT: 1493 reg = UFS_TEST_BUS_CTRL_1; 1494 offset = 8; 1495 break; 1496 case TSTBUS_OCSC: 1497 reg = UFS_TEST_BUS_CTRL_1; 1498 offset = 0; 1499 break; 1500 case TSTBUS_WRAPPER: 1501 reg = UFS_TEST_BUS_CTRL_2; 1502 offset = 16; 1503 break; 1504 case TSTBUS_COMBINED: 1505 reg = UFS_TEST_BUS_CTRL_2; 1506 offset = 8; 1507 break; 1508 case TSTBUS_UTP_HCI: 1509 reg = UFS_TEST_BUS_CTRL_2; 1510 offset = 0; 1511 break; 1512 case TSTBUS_UNIPRO: 1513 reg = UFS_UNIPRO_CFG; 1514 offset = 20; 1515 mask = 0xFFF; 1516 break; 1517 /* 1518 * No need for a default case, since 1519 * ufs_qcom_testbus_cfg_is_ok() checks that the configuration 1520 * is legal 1521 */ 1522 } 1523 mask <<= offset; 1524 ufshcd_rmwl(host->hba, TEST_BUS_SEL, 1525 (u32)host->testbus.select_major << 19, 1526 REG_UFS_CFG1); 1527 ufshcd_rmwl(host->hba, mask, 1528 (u32)host->testbus.select_minor << offset, 1529 reg); 1530 ufs_qcom_enable_test_bus(host); 1531 /* 1532 * Make sure the test bus configuration is 1533 * committed before returning. 1534 */ 1535 mb(); 1536 1537 return 0; 1538 } 1539 1540 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba) 1541 { 1542 u32 reg; 1543 struct ufs_qcom_host *host; 1544 1545 host = ufshcd_get_variant(hba); 1546 1547 ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4, 1548 "HCI Vendor Specific Registers "); 1549 1550 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC); 1551 ufshcd_dump_regs(hba, reg, 44 * 4, "UFS_UFS_DBG_RD_REG_OCSC "); 1552 1553 reg = ufshcd_readl(hba, REG_UFS_CFG1); 1554 reg |= UTP_DBG_RAMS_EN; 1555 ufshcd_writel(hba, reg, REG_UFS_CFG1); 1556 1557 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM); 1558 ufshcd_dump_regs(hba, reg, 32 * 4, "UFS_UFS_DBG_RD_EDTL_RAM "); 1559 1560 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM); 1561 ufshcd_dump_regs(hba, reg, 128 * 4, "UFS_UFS_DBG_RD_DESC_RAM "); 1562 1563 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM); 1564 ufshcd_dump_regs(hba, reg, 64 * 4, "UFS_UFS_DBG_RD_PRDT_RAM "); 1565 1566 /* clear bit 17 - UTP_DBG_RAMS_EN */ 1567 ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1); 1568 1569 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM); 1570 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UAWM "); 1571 1572 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM); 1573 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UARM "); 1574 1575 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC); 1576 ufshcd_dump_regs(hba, reg, 48 * 4, "UFS_DBG_RD_REG_TXUC "); 1577 1578 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC); 1579 ufshcd_dump_regs(hba, reg, 27 * 4, "UFS_DBG_RD_REG_RXUC "); 1580 1581 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC); 1582 ufshcd_dump_regs(hba, reg, 19 * 4, "UFS_DBG_RD_REG_DFC "); 1583 1584 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT); 1585 ufshcd_dump_regs(hba, reg, 34 * 4, "UFS_DBG_RD_REG_TRLUT "); 1586 1587 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT); 1588 ufshcd_dump_regs(hba, reg, 9 * 4, "UFS_DBG_RD_REG_TMRLUT "); 1589 } 1590 1591 /** 1592 * ufs_qcom_device_reset() - toggle the (optional) device reset line 1593 * @hba: per-adapter instance 1594 * 1595 * Toggles the (optional) reset line to reset the attached device. 1596 */ 1597 static int ufs_qcom_device_reset(struct ufs_hba *hba) 1598 { 1599 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1600 1601 /* reset gpio is optional */ 1602 if (!host->device_reset) 1603 return -EOPNOTSUPP; 1604 1605 /* 1606 * The UFS device shall detect reset pulses of 1us, sleep for 10us to 1607 * be on the safe side. 1608 */ 1609 ufs_qcom_device_reset_ctrl(hba, true); 1610 usleep_range(10, 15); 1611 1612 ufs_qcom_device_reset_ctrl(hba, false); 1613 usleep_range(10, 15); 1614 1615 return 0; 1616 } 1617 1618 #if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND) 1619 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba, 1620 struct devfreq_dev_profile *p, 1621 struct devfreq_simple_ondemand_data *d) 1622 { 1623 p->polling_ms = 60; 1624 p->timer = DEVFREQ_TIMER_DELAYED; 1625 d->upthreshold = 70; 1626 d->downdifferential = 5; 1627 } 1628 #else 1629 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba, 1630 struct devfreq_dev_profile *p, 1631 struct devfreq_simple_ondemand_data *data) 1632 { 1633 } 1634 #endif 1635 1636 static void ufs_qcom_reinit_notify(struct ufs_hba *hba) 1637 { 1638 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1639 1640 phy_power_off(host->generic_phy); 1641 } 1642 1643 /* Resources */ 1644 static const struct ufshcd_res_info ufs_res_info[RES_MAX] = { 1645 {.name = "ufs_mem",}, 1646 {.name = "mcq",}, 1647 /* Submission Queue DAO */ 1648 {.name = "mcq_sqd",}, 1649 /* Submission Queue Interrupt Status */ 1650 {.name = "mcq_sqis",}, 1651 /* Completion Queue DAO */ 1652 {.name = "mcq_cqd",}, 1653 /* Completion Queue Interrupt Status */ 1654 {.name = "mcq_cqis",}, 1655 /* MCQ vendor specific */ 1656 {.name = "mcq_vs",}, 1657 }; 1658 1659 static int ufs_qcom_mcq_config_resource(struct ufs_hba *hba) 1660 { 1661 struct platform_device *pdev = to_platform_device(hba->dev); 1662 struct ufshcd_res_info *res; 1663 struct resource *res_mem, *res_mcq; 1664 int i, ret = 0; 1665 1666 memcpy(hba->res, ufs_res_info, sizeof(ufs_res_info)); 1667 1668 for (i = 0; i < RES_MAX; i++) { 1669 res = &hba->res[i]; 1670 res->resource = platform_get_resource_byname(pdev, 1671 IORESOURCE_MEM, 1672 res->name); 1673 if (!res->resource) { 1674 dev_info(hba->dev, "Resource %s not provided\n", res->name); 1675 if (i == RES_UFS) 1676 return -ENOMEM; 1677 continue; 1678 } else if (i == RES_UFS) { 1679 res_mem = res->resource; 1680 res->base = hba->mmio_base; 1681 continue; 1682 } 1683 1684 res->base = devm_ioremap_resource(hba->dev, res->resource); 1685 if (IS_ERR(res->base)) { 1686 dev_err(hba->dev, "Failed to map res %s, err=%d\n", 1687 res->name, (int)PTR_ERR(res->base)); 1688 ret = PTR_ERR(res->base); 1689 res->base = NULL; 1690 return ret; 1691 } 1692 } 1693 1694 /* MCQ resource provided in DT */ 1695 res = &hba->res[RES_MCQ]; 1696 /* Bail if MCQ resource is provided */ 1697 if (res->base) 1698 goto out; 1699 1700 /* Explicitly allocate MCQ resource from ufs_mem */ 1701 res_mcq = devm_kzalloc(hba->dev, sizeof(*res_mcq), GFP_KERNEL); 1702 if (!res_mcq) 1703 return -ENOMEM; 1704 1705 res_mcq->start = res_mem->start + 1706 MCQ_SQATTR_OFFSET(hba->mcq_capabilities); 1707 res_mcq->end = res_mcq->start + hba->nr_hw_queues * MCQ_QCFG_SIZE - 1; 1708 res_mcq->flags = res_mem->flags; 1709 res_mcq->name = "mcq"; 1710 1711 ret = insert_resource(&iomem_resource, res_mcq); 1712 if (ret) { 1713 dev_err(hba->dev, "Failed to insert MCQ resource, err=%d\n", 1714 ret); 1715 return ret; 1716 } 1717 1718 res->base = devm_ioremap_resource(hba->dev, res_mcq); 1719 if (IS_ERR(res->base)) { 1720 dev_err(hba->dev, "MCQ registers mapping failed, err=%d\n", 1721 (int)PTR_ERR(res->base)); 1722 ret = PTR_ERR(res->base); 1723 goto ioremap_err; 1724 } 1725 1726 out: 1727 hba->mcq_base = res->base; 1728 return 0; 1729 ioremap_err: 1730 res->base = NULL; 1731 remove_resource(res_mcq); 1732 return ret; 1733 } 1734 1735 static int ufs_qcom_op_runtime_config(struct ufs_hba *hba) 1736 { 1737 struct ufshcd_res_info *mem_res, *sqdao_res; 1738 struct ufshcd_mcq_opr_info_t *opr; 1739 int i; 1740 1741 mem_res = &hba->res[RES_UFS]; 1742 sqdao_res = &hba->res[RES_MCQ_SQD]; 1743 1744 if (!mem_res->base || !sqdao_res->base) 1745 return -EINVAL; 1746 1747 for (i = 0; i < OPR_MAX; i++) { 1748 opr = &hba->mcq_opr[i]; 1749 opr->offset = sqdao_res->resource->start - 1750 mem_res->resource->start + 0x40 * i; 1751 opr->stride = 0x100; 1752 opr->base = sqdao_res->base + 0x40 * i; 1753 } 1754 1755 return 0; 1756 } 1757 1758 static int ufs_qcom_get_hba_mac(struct ufs_hba *hba) 1759 { 1760 /* Qualcomm HC supports up to 64 */ 1761 return MAX_SUPP_MAC; 1762 } 1763 1764 static int ufs_qcom_get_outstanding_cqs(struct ufs_hba *hba, 1765 unsigned long *ocqs) 1766 { 1767 struct ufshcd_res_info *mcq_vs_res = &hba->res[RES_MCQ_VS]; 1768 1769 if (!mcq_vs_res->base) 1770 return -EINVAL; 1771 1772 *ocqs = readl(mcq_vs_res->base + UFS_MEM_CQIS_VS); 1773 1774 return 0; 1775 } 1776 1777 static void ufs_qcom_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg) 1778 { 1779 struct device *dev = msi_desc_to_dev(desc); 1780 struct ufs_hba *hba = dev_get_drvdata(dev); 1781 1782 ufshcd_mcq_config_esi(hba, msg); 1783 } 1784 1785 static irqreturn_t ufs_qcom_mcq_esi_handler(int irq, void *data) 1786 { 1787 struct msi_desc *desc = data; 1788 struct device *dev = msi_desc_to_dev(desc); 1789 struct ufs_hba *hba = dev_get_drvdata(dev); 1790 u32 id = desc->msi_index; 1791 struct ufs_hw_queue *hwq = &hba->uhq[id]; 1792 1793 ufshcd_mcq_write_cqis(hba, 0x1, id); 1794 ufshcd_mcq_poll_cqe_lock(hba, hwq); 1795 1796 return IRQ_HANDLED; 1797 } 1798 1799 static int ufs_qcom_config_esi(struct ufs_hba *hba) 1800 { 1801 struct ufs_qcom_host *host = ufshcd_get_variant(hba); 1802 struct msi_desc *desc; 1803 struct msi_desc *failed_desc = NULL; 1804 int nr_irqs, ret; 1805 1806 if (host->esi_enabled) 1807 return 0; 1808 1809 /* 1810 * 1. We only handle CQs as of now. 1811 * 2. Poll queues do not need ESI. 1812 */ 1813 nr_irqs = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; 1814 ret = platform_msi_domain_alloc_irqs(hba->dev, nr_irqs, 1815 ufs_qcom_write_msi_msg); 1816 if (ret) { 1817 dev_err(hba->dev, "Failed to request Platform MSI %d\n", ret); 1818 goto out; 1819 } 1820 1821 msi_lock_descs(hba->dev); 1822 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { 1823 ret = devm_request_irq(hba->dev, desc->irq, 1824 ufs_qcom_mcq_esi_handler, 1825 IRQF_SHARED, "qcom-mcq-esi", desc); 1826 if (ret) { 1827 dev_err(hba->dev, "%s: Fail to request IRQ for %d, err = %d\n", 1828 __func__, desc->irq, ret); 1829 failed_desc = desc; 1830 break; 1831 } 1832 } 1833 msi_unlock_descs(hba->dev); 1834 1835 if (ret) { 1836 /* Rewind */ 1837 msi_lock_descs(hba->dev); 1838 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { 1839 if (desc == failed_desc) 1840 break; 1841 devm_free_irq(hba->dev, desc->irq, hba); 1842 } 1843 msi_unlock_descs(hba->dev); 1844 platform_msi_domain_free_irqs(hba->dev); 1845 } else { 1846 if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 && 1847 host->hw_ver.step == 0) { 1848 ufshcd_writel(hba, 1849 ufshcd_readl(hba, REG_UFS_CFG3) | 0x1F000, 1850 REG_UFS_CFG3); 1851 } 1852 ufshcd_mcq_enable_esi(hba); 1853 } 1854 1855 out: 1856 if (!ret) 1857 host->esi_enabled = true; 1858 1859 return ret; 1860 } 1861 1862 /* 1863 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations 1864 * 1865 * The variant operations configure the necessary controller and PHY 1866 * handshake during initialization. 1867 */ 1868 static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = { 1869 .name = "qcom", 1870 .init = ufs_qcom_init, 1871 .exit = ufs_qcom_exit, 1872 .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version, 1873 .clk_scale_notify = ufs_qcom_clk_scale_notify, 1874 .setup_clocks = ufs_qcom_setup_clocks, 1875 .hce_enable_notify = ufs_qcom_hce_enable_notify, 1876 .link_startup_notify = ufs_qcom_link_startup_notify, 1877 .pwr_change_notify = ufs_qcom_pwr_change_notify, 1878 .apply_dev_quirks = ufs_qcom_apply_dev_quirks, 1879 .suspend = ufs_qcom_suspend, 1880 .resume = ufs_qcom_resume, 1881 .dbg_register_dump = ufs_qcom_dump_dbg_regs, 1882 .device_reset = ufs_qcom_device_reset, 1883 .config_scaling_param = ufs_qcom_config_scaling_param, 1884 .program_key = ufs_qcom_ice_program_key, 1885 .reinit_notify = ufs_qcom_reinit_notify, 1886 .mcq_config_resource = ufs_qcom_mcq_config_resource, 1887 .get_hba_mac = ufs_qcom_get_hba_mac, 1888 .op_runtime_config = ufs_qcom_op_runtime_config, 1889 .get_outstanding_cqs = ufs_qcom_get_outstanding_cqs, 1890 .config_esi = ufs_qcom_config_esi, 1891 }; 1892 1893 /** 1894 * ufs_qcom_probe - probe routine of the driver 1895 * @pdev: pointer to Platform device handle 1896 * 1897 * Return: zero for success and non-zero for failure. 1898 */ 1899 static int ufs_qcom_probe(struct platform_device *pdev) 1900 { 1901 int err; 1902 struct device *dev = &pdev->dev; 1903 1904 /* Perform generic probe */ 1905 err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops); 1906 if (err) 1907 return dev_err_probe(dev, err, "ufshcd_pltfrm_init() failed\n"); 1908 1909 return 0; 1910 } 1911 1912 /** 1913 * ufs_qcom_remove - set driver_data of the device to NULL 1914 * @pdev: pointer to platform device handle 1915 * 1916 * Always returns 0 1917 */ 1918 static int ufs_qcom_remove(struct platform_device *pdev) 1919 { 1920 struct ufs_hba *hba = platform_get_drvdata(pdev); 1921 1922 pm_runtime_get_sync(&(pdev)->dev); 1923 ufshcd_remove(hba); 1924 platform_msi_domain_free_irqs(hba->dev); 1925 return 0; 1926 } 1927 1928 static const struct of_device_id ufs_qcom_of_match[] __maybe_unused = { 1929 { .compatible = "qcom,ufshc"}, 1930 {}, 1931 }; 1932 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match); 1933 1934 #ifdef CONFIG_ACPI 1935 static const struct acpi_device_id ufs_qcom_acpi_match[] = { 1936 { "QCOM24A5" }, 1937 { }, 1938 }; 1939 MODULE_DEVICE_TABLE(acpi, ufs_qcom_acpi_match); 1940 #endif 1941 1942 static const struct dev_pm_ops ufs_qcom_pm_ops = { 1943 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL) 1944 .prepare = ufshcd_suspend_prepare, 1945 .complete = ufshcd_resume_complete, 1946 #ifdef CONFIG_PM_SLEEP 1947 .suspend = ufshcd_system_suspend, 1948 .resume = ufshcd_system_resume, 1949 .freeze = ufshcd_system_freeze, 1950 .restore = ufshcd_system_restore, 1951 .thaw = ufshcd_system_thaw, 1952 #endif 1953 }; 1954 1955 static struct platform_driver ufs_qcom_pltform = { 1956 .probe = ufs_qcom_probe, 1957 .remove = ufs_qcom_remove, 1958 .driver = { 1959 .name = "ufshcd-qcom", 1960 .pm = &ufs_qcom_pm_ops, 1961 .of_match_table = of_match_ptr(ufs_qcom_of_match), 1962 .acpi_match_table = ACPI_PTR(ufs_qcom_acpi_match), 1963 }, 1964 }; 1965 module_platform_driver(ufs_qcom_pltform); 1966 1967 MODULE_LICENSE("GPL v2"); 1968